KR102196341B1 - Printed circuit board for integrated LED drivers - Google Patents

Abstract

A multilayer metal core printed circuit board (MCPCB) has mounted thereon at least one or more heat generating LEDs and one or more devices configured to provide current to the one or more LEDs. The one or more devices may include devices that carry steep voltage waveforms. Since there is typically a very thin dielectric between the patterned copper layer and the metal substrate, steep voltage waveforms can generate current in the metal substrate due to AC coupling through the parasitic capacitance. These AC-coupled currents can generate electromagnetic interference (EMI). To reduce EMI, a local shielding zone may be formed between the metal substrate and the device carrying the steep voltage waveform. The local shielding zone may be conductive and may be electrically connected to a DC voltage node adjacent to one or more devices.

Description

Printed circuit board for integrated LED drivers

Cross-reference to related applications

This application claims the benefit of U.S. Provisional Application No. 62/359,112 filed July 6, 2016 and European Patent Application No. 1616190841 filed September 27, 2016, the contents of which are hereby incorporated by reference. Included.

Light emitting diodes (LEDs) can generate a large amount of heat in some applications. One such application may be an array of high power LEDs used to form a light source for luminaires. The heat generated must be removed.

To achieve this, LEDs are typically on a metal core printed circuit board (MCPCB) rather than using a conventional printed circuit board consisting of a dielectric substrate, such as glass reinforced epoxy laminate PCBs. It is implemented in

The MCPCB may include a metal substrate, such as aluminum, a dielectric layer over the metal substrate and a patterned metal layer over the dielectric layer. The patterned metal layer may be composed of copper. The patterned metal layer can connect the LEDs to the power source. The metal substrate may then be thermally and/or electrically coupled to a grounded metal heat sink or it may be floating.

MCPCB can have better thermal performance than other PCBs due to the relative thickness of the metal substrate, which can improve lateral heat diffusion and heat dissipation for the heat sink.

A light emitting diode (LED) module and a method of forming the LED module are disclosed. The LED module may include one or more LED components and one or more other circuits. The LED module can include a first dielectric layer on the base metal substrate. The first patterned metal layer may be formed on the first dielectric layer. The first patterned metal layer can provide electrical interconnections. The local shielding region can be formed within the first patterned metal layer. The local shielding zone can be a substantially continuous zone of conductive material. The second dielectric layer may be formed on the first patterned metal layer. The second patterned metal layer may be formed on the second dielectric layer. The second patterned metal layer can provide electrical interconnections. The second metal layer can be electrically insulated from the base metal substrate by at least some of the first and second dielectric layers.

One or more LEDs may be mounted on the second patterned metal layer and may be thermally coupled to the base metal substrate. One or more devices can be formed on the second patterned metal layer and can be configured to provide a target current to the one or more LEDs. The one or more devices may include devices that carry steep voltage waveforms. The device carrying the steep voltage waveform may be over at least a portion of the local shielding area. The DC voltage node may be mounted on the second patterned metal layer. The DC voltage node can be electrically connected to the local shielding area.

A more detailed understanding may be obtained from the following description, which is given by way of example in conjunction with the accompanying drawings.
1 is a cross-sectional view of a Driver On Board (DOB) module using a single layer metal core printed circuit board (MCPCB).
2A-2C are cross-sectional views of a DOB module on a multilayer MCPCB with various configurations of localized shielding.
3 is a circuit diagram illustrating an example of a DOB module using a single stage boost converter as a shielded switch-mode power supply (SMPS).
4 is a second patterned metal layer of a shielded DOB module and overhead transparency of a local shielding region.

In the following description, a number of specific details are set forth, such as specific structures, components, materials, dimensions, processing steps, and techniques, to provide a thorough understanding of the invention. However, it will be understood by one of ordinary skill in the art that the invention may be practiced without these specific details. In other instances, well-known structures or processing steps have not been described in detail in order to avoid obscuring the invention. When an element such as a layer, region, or substrate is referred to as being “on” or “on” another element, it will be understood that it may be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly" or "directly" above another element, there are no intervening elements. It will also be understood that when an element is referred to as being “below”, “below”, or “under” another element, it may be directly below or under another element, or that intervening elements may be present. In contrast, when an element is referred to as being “immediately below” or “below” another element, there are no intervening elements.

To clarify the presentation of embodiments of the present invention, in the detailed description that follows, some processing steps or actions known in the art may be combined together for presentation and for illustrative purposes, and in some instances in detail. Could not be explained. In other instances, some processing steps or operations known in the art may not be described at all. It should be understood that the following description is rather focused on the distinct features or elements of the various embodiments of the present invention.

The following description relates to light emitting diodes (LEDs) and switching power supply drivers mounted on the same metal core printed circuit board (MCPCB), and in particular, to reduce unwanted electromagnetic interference (EMI) from the module. It's about technology.

When one or more light emitting diodes (LEDs) are mounted on a metal core printed circuit board (MCPCB), one or more devices configured to provide current to the one or more LEDs may also be mounted on the MCPCB. One or more devices may include an LED driver to control the current. This arrangement can be referred to as a driver on board (DOB) module and can be used in a compact LED module. The LED driver may be a switched mode power supply (SMPS) that receives an unregulated voltage from an external power supply and supplies a regulated current to the LEDs to achieve a target luminance level.

Referring to FIG. 1, a cross-sectional view of a driver on board (DOB) module 100 using a single layer MCPCB 102 is shown. As described above, the MCPCB 102 comprises a base metal substrate 104, a dielectric layer 106 on the base metal substrate 104, a patterned metal layer 108 on the dielectric layer 106, and a device layer ( 110) may be included.

Base metal substrate 104 may be composed of one or more thermally conductive metals, such as aluminum, copper, steel, or alloys thereof, for example. The base metal substrate 104 may be several hundred microns thick, but is not limited thereto. For example, the base metal substrate 104 may have a thickness ranging from approximately 0.5 mm to approximately 1.5 mm.

The base metal substrate 104 may have a dielectric layer 106 formed thereon. Dielectric layer 106 may include any thermally conductive dielectric materials, such as a dielectric polymer, a ceramic with high thermal conductivity, and combinations thereof. Dielectric layer 106 may include a single layer of dielectric material or multiple layers of dielectric materials. Dielectric layer 106 may be formed using a conventional deposition or lamination process. The dielectric layer 106 may have a thickness ranging from approximately 30 μm to approximately 150 μm.

The dielectric layer 106 may have a patterned metal layer 108 formed thereon. Patterned metal layer 108 may provide one or more interconnections for circuitry on device layer 110. The patterned metal layer 108 may be composed of a conductive material such as polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide, or combinations thereof. Preferably, the conductive material may be a conductive metal, such as Cu, W, or Al. The conductive material can be formed using conventional deposition or lamination processes.

Although shown as a single layer, one of ordinary skill in the art is using a conductive material, in which the patterned metal layer 108 is insulated by one or more types of dielectric material, for more complex circuits requiring crossover conductors. It will be appreciated that it may include multiple regions and/or layers of. Dielectric materials may be similar to the material within dielectric layer 106 and may be formed using similar techniques prior to being patterned by one or more conventional lithographic techniques. The patterned metal layer can have a thickness ranging from approximately 9 μm to approximately 70 μm.

As described above, the MCPCB 102 may also include a device layer 110 on the patterned metal layer 108. Device layer 110 may include one or more devices and circuitry to provide a target current to one or more LEDs 112. One or more devices may include devices that carry steep voltage waveforms, such as switching transistor 118 of SMPS 114. The device layer may include one or more LEDs 112, SMPS 114, and neighbor circuits 116. One or more of the LEDs 112 may be two-lead semiconductor light sources, each of which may be a p-n junction diode that emits light when activated. When an appropriate voltage is applied to the leads, electrons can recombine with electron holes in the device, releasing energy in the form of photons.

SMPS 114 may be any type of converter that receives an input voltage and outputs a regulated current to drive one or more LEDs 112, such as a step-up or step-down converter. The SMPS 114 may be a buck regulator, a boost regulator, or other type of switching regulator capable of providing a constant voltage to one or more LEDs 112.

The SMPS 114 may include a switching transistor 118 that switches on and off at a relatively high frequency, such as approximately 10 kHz to approximately 1 MHz. For example, switching transistor 118 may couple an inductor between ground or positive voltage at high frequencies, depending on the type of SMPS 114, to generate a boosted or reduced output voltage. Switching transistor 118 is a metal-oxide-semiconductor field-effect transistor (MOSFET) or bipolar that carries a steep voltage waveform, which can be a square wave voltage 132, at a switching frequency. It can be a transistor.

It should be noted that the term "square wave", as used herein, does not require the waveform to have rectangular pulses. It does not require that the waveform has a 50% duty cycle (ie, has equal durations of high and low levels). In some applications, non-instantaneous switching and parasitic effects can cause non-rectangular waveforms. Thus, the term “square wave” refers to a switched voltage that swings between high and low levels as a result of the switching transistor being turned on and off from time to time to achieve a target output voltage or current from SMPS 114.

Accordingly, the high frequency square wave voltage 132 may be generated with a relatively high voltage (eg, up to 500 V), and a relatively larger average current (eg, up to 1 Amp). A small on-board capacitor can be used to slightly filter out the ripple to supply the regulated DC current to one or more LEDs 112. In one example, the square wave voltage 132 may quickly transition between ground and about 500 V to drive a series of one or more LEDs 112 connected in series.

There may be one or more devices adjacent to the switching transistor 118, such as the controller 120 for example. Controller 120 may use one or more known techniques to generate a target drive current for one or more LEDs 112. In addition, the device layer 110 may include one or more additional devices 116. Although shown very close to the switching transistor 118, the controller 120 may be located farther away from the other devices 116.

The device layer 110 may be powered by a power supply 122 connected to an electromagnetic interference (EMI) measurement network 124, which may include one or more measurement devices known in the art. The EMI measurement network 124 can also be connected to the heat sink 126 via a physical earth (PE) connection 128, and the physical ground connection can serve as a ground for the DOB module 100. have. Due to the high frequency switching of potentially large currents and voltages, there is a potential for EMI. In some cases, the DOB module 100 may undergo a test to ensure that the EMI is below a threshold for electromagnetic compatibility (EMC) with other systems. If the measured AC-coupled current to the heat sink 126 is above a threshold level, the DOB module 100 may fail an electromagnetic compatibility (EMC) test, which may be an industrial or legal requirement.

As shown in FIG. 1, one or more parasitic capacitors may be formed in the DOB module 100. The first parasitic capacitor C1 is a terminal of the switching transistor 118 carrying a square wave voltage 132 and/or under the switching transistor 118 and one capacitor terminal which is a patterned metal layer 108 just below the terminal. The base metal substrate 104 in the region of may be formed with another capacitor terminal. The dielectric layer 106 can serve as a capacitor dielectric. The first parasitic capacitor C1 may be charged and discharged every switching cycle. A large current rapidly increases at the beginning and end of the square wave voltage 132 pulse, and the result of charging and discharging various capacitances may generate EMI.

The capacitance value of the first parasitic capacitor C1 is proportional to the terminal area and inversely proportional to the dielectric thickness. Thus, the capacitance value of the first parasitic capacitor C1 can be high (e.g., tens of pF) due to the thin dielectric layer 106 used for good thermal performance, and the large conductive area at both terminals. have. It should be noted that the first parasitic capacitor C1 is simplified in FIG. 1. The first parasitic capacitor C1 may be the sum of all related parasitic capacitances that diffuse through the entire DOB module 100.

The current 130 from the first parasitic capacitor C1 may be conducted to the heat sink 126 through the base metal substrate 104. From the heat sink 126, the current 130 can be detected by the EMI measurement network 124 via the PE connection 128 and can be coupled to other systems that are connected to the same ground. Current 130 can be detected and measured. If the current 130 is above the threshold, then the DOB module 100 may fail the EMC test.

In addition to the first parasitic capacitor C1, the second parasitic capacitor C2 is formed under the controller 120 due to the high frequency current in the base metal substrate 104 due to the parasitic AC coupling of the square wave voltage 132. I can. The second parasitic capacitor C2 may cause internal disturbance in the controller 120. It should be noted that the second parasitic capacitor C2 is simplified in FIG. 1. The second parasitic capacitor C2 can occur in any device within the device layer 110.

Disturbances caused by the second parasitic capacitor C2 may be greatly improved if the base metal substrate 104 is floating rather than being grounded through the heat sink 126. However, even when the base metal substrate 104 is grounded, the parasitic capacitive coupling from the switching transistor 118 to the controller 120 can be non-zero and cause problems. This is because the impedance of the long ground path at high frequencies may be non-zero, and the base metal substrate 104 is at this time a first parasitic capacitor C1 capable of being coupled to the controller 120 via a second parasitic capacitor C2. This may be because a portion of the square wave voltage 132 of the switching transistor 118 can still be carried through ).

As the power input 122 to the DOB module 100 increases, the EMC problem may also increase. Increasing the thickness of the dielectric layer 106 may reduce the capacitance of the first parasitic capacitor C1 and the second parasitic capacitor C2, but may undesirably increase the thermal resistance. Therefore, it may be desirable to reduce EMI to more easily meet EMC standards.

Referring now to FIG. 2A, a cross-sectional view of a DOB module 200 on a multilayer MCPCB 202 with localized shielding is shown. The multilayer MCPCB 202 includes a base metal substrate 204, a first dielectric layer 206 on the base metal substrate 204, a first patterned metal layer 208 on the first dielectric layer 206, and a first pattern. A second dielectric layer 210 on the oxidized metal layer 208, a second patterned metal layer 212 on the second dielectric layer 210, and a device layer 214.

The base metal substrate 204 may be composed of one or more thermally conductive metals, such as aluminum, copper, steel, and alloys thereof, for example. The base metal substrate 204 may be several hundred microns thick, but is not limited thereto. For example, the base metal substrate 204 may have a thickness ranging from approximately 0.5 mm to approximately 1.5 mm.

The base metal substrate 204 may have a first dielectric layer 206 formed thereon. The first dielectric layer 206 may include any thermally conductive dielectric materials, such as a dielectric polymer, a ceramic with high thermal conductivity, and combinations thereof. The first dielectric layer 206 may comprise a single layer of dielectric material or multiple layers of dielectric materials. The first dielectric layer 206 can be formed using a conventional deposition or lamination process. The first dielectric layer 206 may have a thickness ranging from approximately 30 μm to approximately 150 μm.

The first dielectric layer 206 can have a first patterned metal layer 208 formed thereon. The first patterned metal layer 208 may provide one or more interconnections for circuitry in higher layers. The first patterned metal layer 208 may be composed of a conductive material, such as polySi, a conductive metal, an alloy comprising at least one conductive metal, a conductive metal silicide, or combinations thereof. Preferably, the conductive material may be a conductive metal, such as Cu, W, or Al. The conductive material can be formed using conventional deposition or lamination processes.

Although shown as a single layer, one of ordinary skill in the art would appreciate that the first patterned metal layer 208 is insulated by one or more types of dielectric material, for more complex circuits requiring crossover conductors. It will be appreciated that it may include multiple regions and/or layers of conductive material. The dielectric materials may be similar to the material in the first dielectric layer 206 and may be formed using similar techniques prior to being patterned by one or more conventional lithographic techniques. The first patterned metal layer 208 may have a thickness ranging from approximately 9 μm to approximately 70 μm.

The first patterned metal layer 208 may have a second dielectric layer 210 formed thereon. The second dielectric layer 210 may be composed of materials similar to the first dielectric layer 206 and may be formed using similar techniques. The second dielectric layer 210 may have a thickness ranging from approximately 30 μm to approximately 150 μm.

The second dielectric layer 210 may have a second patterned metal layer 212 formed thereon. The second patterned metal layer 212 may be composed of materials similar to the first patterned metal layer 208 and may be formed using similar techniques. The second patterned metal layer 212 may have a thickness ranging from approximately 9 μm to approximately 70 μm.

Device layer 214 may include devices similar to those described above with respect to device layer 110 in FIG. 1, including one or more LEDs 112 and other devices 112. The device layer may include a shielded SMPS 216 comprising a DC voltage node 218 and a switching transistor 118 carrying a square wave voltage 132.

The DC voltage node 218 may be connected to the localized shield region 220 in the first patterned metal layer 208 by a conductive via 222. The local shielding zone 220 may be located under any device that directly or indirectly carries the steep voltage waveform. As shown in FIG. 2A, a local shielding region 220 may be located below the switching transistor 118, which carries a square wave voltage 132. The local shielding region 220 can be a substantially continuous region of conductive material within the first patterned metal layer 208. The shielding zone can be a conductive metal, such as Cu, W, or Al, for example.

The shielding region 220 may be formed concurrently with the formation of the first patterned metal layer 208. In one example, the first portion 224 of the first patterned metal layer 208 may be deposited on the first dielectric layer 206. The first portion 224 may be composed of a dielectric material similar to the dielectric material of the first dielectric layer 206. The first portion 224 may be patterned and etched using a conventional lithographic process to form the opening. The openings can be filled with a conductive material using conventional deposition processes, such as, but not limited to, CVD, PECVD, sputtering, chemical solution deposition, or plating. After the conductive material is deposited, it can be planarized by a conventional process such as chemical mechanical planarization (CMP), so that the top surface of the conductive material can be substantially flush with the top surface of the first part. have. A second portion 226 of the first patterned metal layer 208 may be deposited on the first portion 224 to complete the first patterned metal layer 208. The second portion 226 is made of a material similar to that of the first portion and can be formed using similar techniques.

The shielding zone 220 may have a thickness ranging from approximately 9 μm to approximately 70 μm. Shielding region 220 may have a cross-sectional area that is at least larger than that of switching transistor 118 and DC voltage node 218. Portions of the shielding region 220 may extend beyond the outer edge of the switching transistor 118 by a distance that may be several micrometers or up to the full width of the DOB module 200. Portions of the local shield region 220 may extend beyond the outer edge of the DC voltage node 218 by a distance that may be several micrometers or up to the full width of the DOB module 200.

As described above, the local shielding region 220 may be physically and electrically connected to the DC voltage node 218 by a conductive via 222. The conductive via 222 may be formed by patterning and etching the second portion 226, the second dielectric layer 210, and the second patterned metal layer 212 using conventional lithographic techniques. Patterning and etching can occur while each of the layers is being formed. The openings formed by patterning and etching may be filled with a conductive metal, for example Cu, W, or Al, using conventional deposition processes such as those described above with reference to shielding region 220. I can. It should be noted that although the local shield region 220 and the DC voltage node 218 are shown as connected by a conductive via 222, they may be connected by other means, such as a shunt or an external conductor.

The DC voltage node 218 can be a ground node, an input voltage node, or any other relatively stable node capable of sinking current. The DC voltage within DC voltage node 218 may be taken from any node or device within DOB module 200. The DC voltage can be any voltage ranging from internal ground (0 volts) or hundreds of volts. The voltage can be generated in any manner and at any DC level not related to the square wave voltage 132 level. The DC voltage node 218 may supply a DC voltage and may be connected to a local shielded region 220 having a low AC impedance in the high frequency range of the square wave voltage 132. If these conditions are met, the DC voltage node 218 and the local shield region 220 can cut off the parasitic capacitive coupling between the switching transistor 118 and other devices.

The shielding effect can be generated because the conductive via 222 is relatively short and its high frequency impedance is minimal. Thus, the voltage within the local shielding region 220 may be essentially equal to the DC voltage potential of the DC voltage node 218 in the high frequency domain. This can effectively cut off the capacitive AC coupling to the heat sink 126 and the base metal substrate 204 under the switching transistor 118.

As shown in FIG. 2A, there may be a third parasitic capacitance C3 between the switching transistor 118 and the local shielding region 220. The third parasitic capacitance C3 is the terminal of the switching transistor 118 carrying the square wave voltage 132 and/or the second patterned metal layer 212 immediately below the terminal, one capacitor terminal and switching transistor 118 ) May be the result of another capacitor terminal, which is the local shielding area 220 in the area below. The second dielectric layer 210 may serve as a capacitor dielectric.

The third parasitic capacitance C3 may be separated from the fourth parasitic capacitance C4 between the local shielding region 220 and the base metal substrate 204. The fourth parasitic capacitance C4 may be the result of one capacitor terminal, which is the local shield area 220 carrying DC voltage, and the other capacitor terminal, which is the base metal substrate 204. The first dielectric layer 210 may serve as a capacitor dielectric. Thus, at this time, the switching transistor 118 and the base metal substrate 204, which are moved to the EMI measurement network 124 through the physical ground (PE) connection 128, or ultimately the switching transistor 118 and the heat sink 126. There may be no parasitic capacitance current flowing in between.

If the local shield zone 220 is large enough, the parasitic capacitance outside the local shield zone 220 can be very small due to the long distance between the parasitic capacitor terminals and the resulting coupling effect can be negligible. The local shielding area 220 may reduce EMC problems caused by parasitic capacitive coupling.

As shown in FIG. 2A, the local shielding region 220 may be located only under the circuit carrying the high frequency/high power square wave voltage 132 caused by the switching of the switching transistor 118.

In another example, as shown in FIG. 2B, the localized shielding region 220 may overlie the entire surface of the base metal substrate 204.

In another example, as shown in FIG. 2C, the DC voltage node 218 may not be in a suitable location that is directly connected to the local shield region 220 below the switching transistor 118 to provide local shielding. For example, the DC voltage node 218 may be located on another portion of the multilayer MCPCB 202 or may be external to the multilayer MCPCB. The intermediate metal dielectric layer 240 may be formed on the first patterned metal layer 208. Intermediate dielectric layer 240 may be similar to first dielectric layer 206 and may be formed using similar techniques. The intermediate patterned metal layer 242 may be formed on the intermediate dielectric layer 240. The intermediate patterned metal layer 242 may be similar to the first patterned metal layer 208 and may be formed using similar techniques. Then, the second dielectric layer 210 may be formed on the intermediate patterned metal layer 242.

The DC voltage node 218 may be connected to a first portion of 220A of the localized shielding region in the first patterned metal layer 208 by a first conductive via 222A. The first portion 220A can convey a DC voltage laterally across the first patterned metal layer 208 to the second conductive via 222B. The second conductive via 222B may extend through the intermediate dielectric layer 240 and may be electrically connected to the second portion 220B of the local shielding region. As a result, a multi-layered local shielding zone can be formed.

Referring now to FIG. 3, a circuit diagram illustrating an example of a DOB module 200 using a single stage boost converter as shielded SMPS 216 is shown. The schematic depicts a high power lighting module that can have an AC main input and can drive one or more (eg, 158) LEDs 302A-302N connected in series. Each of the one or more LEDs 302A-302N may be a blue emitting GaN-based LED and may drop about 3 volts. Therefore, the boost circuit must boost the rectified AC mains voltage to at least 474 V. The phosphor can convert blue LED light into white light for overall illumination.

The AC mains voltage may be applied to the EMI filter 306 through the fuse 304, and the EMI filter may or may not be on the MCPCB 202 illustrated in FIG. 2. The full diode bridge 308 may rectify the AC voltage and the input capacitor 310 may at least partially filter the rectified AC voltage. The controller 312 can turn on the switching transistor 118 and the right end of the inductor 314 can be pulled to ground for charging the inductor 314. At certain times within the switching cycle, switching transistor 118 may be turned off to generate a target current through one or more LEDs 302A-302N. This can cause a voltage at the right end of the inductor 314 to rise to forward bias the diode 316. This can recharge the output capacitor 318, which can smooth the waveform and supply a DC voltage at an essentially regulated current to one or more LEDs 302A-302N. Thus, the square wave voltage 132 goes between ground and the voltage forward biasing the diode 316 in this case. The drain node 320 of the switching transistor 118 may carry a square wave voltage 132. Any high-frequency ripple in the current supplied to one or more LEDs 302A-302N may be acceptable as any high-frequency ripple may not be recognized as long as the peak current remains within the current rating of one or more LEDs 302A-302N. .

Current conducted by one or more LEDs 302A-302N may flow through a low value resistor R1. The voltage across resistor R1 can be compared to the voltage generated by the controllable voltage source 322 serving as a dimmer control circuit. Resistor R2 and capacitor 324 may filter the output of the differential amplifier 326, which may serve as an error amplifier. The feedback network may control the duty cycle or switching frequency of the switching transistor 118 so that voltages applied to the inputs of the differential amplifier 326 match. The voltage divider (resistors R3 and R4) may apply the divided voltage to the controller 312 using an error signal to control the switching of the switching transistor 118.

The controller 312 may cause self-oscillation triggered by the zero current conducted by the inductor 314. Alternatively, or in addition, the controller 312 may be a pulse width modulation (PWM) controller that uses a fixed oscillator frequency to turn on the switching transistor 118 again during each cycle. . Alternatively, or in addition, controller 312 may use other known techniques to generate a target drive current for one or more LEDs 302A-302N. The SMPS 216 may also be a current mode or voltage mode regulator.

In this example, DC voltage node 218 may be an internal ground in full diode bridge 308 that is electrically coupled to local shield region 220 to provide local shielding.

Referring now to FIG. 4, the overhead transparency of the second patterned metal layer 212 and the local shield region 220 of the shielded DOB module 200 is shown. As shown in FIG. 4, a second patterned metal layer 212 is overlaid over the local shielding region 220. The drain node 402 of the switching transistor 118 is shown. The drain node 402 may electrically connect the switching transistor 118 to the basic second patterned metal layer 212. The drain node 402 may be a copper pad connecting the drain of the switching transistor 118 or a bonded wire. A drain node 402 is shown that is connected to other portions of the DOB module 200 through an interconnect pattern in the patterned metal layer 212. The interconnection pattern may be composed of a conductive material, such as Cu, W, or Al. As described above, the interconnect pattern may be formed by one or more conventional etching and deposition processes. The interconnection pattern may carry a square wave voltage 132. The local shielding region 220 is a portion of the second patterned metal layer 212 that carries the square wave voltage 132 to shield the underlying base metal substrate 204 from reducing any significant AC coupling. It can extend beyond the footprint.

The various electrical components shown in FIG. 3 are lead?? It may be mounted on the second patterned metal layer 212 through a conventional method, such as a process. In this example, the DC voltage node 218 for biasing the local shield region may be the internal ground shown in FIG. 3. Two examples of conductive vias 222 connecting DC voltage node 218 to local shielding region 220 are shown.

As described above, various other DC nodes in the second patterned metal layer 212 may also be used for electrical connection to the local shielding region 220. The local shielding region 220 extends beyond the regions of the second patterned metal layer 212 carrying the square wave voltage to be located below the appropriate DC voltage node for connection to such a node by a vertical conductive via 222. It can be extended considerably.

In the example shown in FIG. 4, the local shielding zone 220 has one or more LEDs 302A through 302N capable of conducting substantial DC current due to smoothing by the output capacitor 318, thereby generating heat. To 302N) is not located below. Thus, there may be good thermal coupling between one or more of the LEDs 302A-302N and the base metal substrate 204. There may be only one thin dielectric layer between the LEDs 302A-302N and the base metal substrate 204 to improve thermal conductance.

Certain portions of the SMPS 216 may be external to the MCPCB 202, such as large capacitors and inductors and current setting components. In addition to the control circuitry, one or more switching transistors 118 will typically be mounted on the MCPCB to achieve the gains of the on-board driver.

While the examples provided above show a multilayer MCPCB 202 used to sink heat from the LEDs, the multilayer MCPCB 202 is mounted on the same multilayer MCPCB 202 as the SMPS 216, such as a microprocessor. It can be used to sink heat from other heat generating components.

While it is known to provide 3D printed circuits for complex circuits, multiple insulated levels of copper are required for crossovers, and those copper patterns below the top copper pattern are suitable for AC shielding of high frequency/high power square waves. It may not be and is not biased by the DC voltage from the node in the top copper layer to achieve the AC shielding function.

While features and elements are described above in specific combinations, one of ordinary skill in the art will understand that each feature or element may be used alone or in any combination with other features and elements. In addition, the methods described herein may be implemented as a computer program, software, or firmware included in a computer-readable medium for execution by a computer or processor. Examples of computer-readable media include electronic signals (transmitted over wired or wireless connections) and computer-readable storage media. Examples of computer readable storage media include read only memory (ROM), random access memory (RAM), registers, cache memory, semiconductor memory devices, magnetic media such as internal hard disks. And removable disks, magnetic optical media, and optical media such as CD-ROM disks, and digital versatile disks (DVDs).

Claims (35)

delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete As a module,
A light emitting diode (LED) driver circuit including a switching transistor and a voltage node;
Multilayer electronic device board-the multilayer electronic device board,
A first patterned metal layer disposed below the LED driver circuit and electrically coupled to the switching transistor and the voltage node,
A second patterned metal layer disposed below the first patterned metal layer and comprising a local shielding region,
A base metal layer disposed under the second patterned metal layer, and
Comprising one or more dielectric layers; And
A plated via extending from the local shielding region to the voltage node through at least a first dielectric layer of the first patterned metal layer and the one or more dielectric layers
A module containing.
22. The module of claim 21, wherein the localized shielding region comprises a continuous region of conductive metal. 22. The module of claim 21, wherein the voltage node is configured to provide an internal ground during operation of the LED driver circuit. 22. The module of claim 21, wherein the base metal layer provides an attachment zone to the heat sink. 22. The module of claim 21, wherein the switching transistor comprises a single stage boost converter circuit. 22. The module of claim 21, wherein the local shielding area extends under at least a portion of the LED driver circuit in both lateral directions. 22. The module of claim 21, wherein the switching transistor is configured to provide a square wave voltage signal to the LED array. 22. The module of claim 21, further comprising an LED array, wherein the LED array is electrically coupled to the LED driver circuit. As a method,
Forming a light emitting diode (LED) driver circuit including a switching transistor and a voltage node;
A first patterned metal layer disposed below the LED driver circuit and electrically coupled to the switching transistor and the voltage node, a second patterned metal layer disposed below the first patterned metal layer and including a local shielding region Forming a multilayer electronic device board comprising a formed metal layer, a base metal layer disposed below the second patterned metal layer, and one or more dielectric layers; And
Forming a plated via through at least a first dielectric layer of the first patterned metal layer and the one or more dielectric layers, the plated via electrically coupling the voltage node and the local shielding region-
How to include. 30. The method of claim 29, wherein the localized shielding region comprises a continuous region of conductive metal. 30. The method of claim 29, wherein the voltage node is configured to provide an internal ground during operation of the LED driver circuit. 30. The method of claim 29, wherein the base metal layer provides an attachment zone to the heat sink. 30. The method of claim 29, wherein the switching transistor comprises a single stage boost converter circuit. 30. The method of claim 29, wherein the localized shield region extends under at least a portion of the LED driver circuit in both lateral directions. 30. The method of claim 29, wherein the switching transistor is configured to provide a square wave voltage signal to the LED array on the first patterned metal layer.

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