KR102188644B1 - Semiconductor package having extanded bandwidth - Google Patents

Semiconductor package having extanded bandwidth Download PDF

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Publication number
KR102188644B1
KR102188644B1 KR1020140157710A KR20140157710A KR102188644B1 KR 102188644 B1 KR102188644 B1 KR 102188644B1 KR 1020140157710 A KR1020140157710 A KR 1020140157710A KR 20140157710 A KR20140157710 A KR 20140157710A KR 102188644 B1 KR102188644 B1 KR 102188644B1
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South Korea
Prior art keywords
semiconductor chip
pad
semiconductor
normal
dummy
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KR1020140157710A
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Korean (ko)
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KR20160057061A (en
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전선광
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에스케이하이닉스 주식회사
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Priority to KR1020140157710A priority Critical patent/KR102188644B1/en
Priority to US14/635,640 priority patent/US9177906B1/en
Publication of KR20160057061A publication Critical patent/KR20160057061A/en
Application granted granted Critical
Publication of KR102188644B1 publication Critical patent/KR102188644B1/en

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Abstract

확장된 대역폭을 갖는 반도체 패키지가 개시되어 있다. 개시된 반도체 패키지는, 상호 스택되며 각각 하부면에 제1 입출력 회로가 연결된 제1 노멀 패드 및 상기 제1 입출력 회로가 연결되지 않은 제1 더미 패드를 구비하는 제1,제2 반도체 칩과, 상기 제1 반도체 칩을 관통하여 상기 제1 반도체 칩의 상기 제1 더미 패드와 상기 제2 반도체 칩의 상기 제1 노멀 패드를 전기적으로 연결하는 제1 관통 전극과, 상기 제1 반도체 칩의 하부면을 지지하며 상기 제1 반도체 칩의 상기 제1 노멀 패드 및 상기 제1 더미 패드에 각각 전기적으로 연결된 제1 접속 패드들을 갖는 기판을 포함할 수 있다.A semiconductor package with an extended bandwidth is disclosed. The disclosed semiconductor package includes first and second semiconductor chips each having a first normal pad to which a first input/output circuit is connected to a lower surface thereof and a first dummy pad to which the first input/output circuit is not connected, and the first 1 A first through electrode electrically connecting the first dummy pad of the first semiconductor chip and the first normal pad of the second semiconductor chip through a semiconductor chip, and a lower surface of the first semiconductor chip are supported. And a substrate having first connection pads electrically connected to the first normal pad and the first dummy pad of the first semiconductor chip, respectively.

Description

확장된 대역폭을 갖는 반도체 패키지{SEMICONDUCTOR PACKAGE HAVING EXTANDED BANDWIDTH}Semiconductor package with extended bandwidth {SEMICONDUCTOR PACKAGE HAVING EXTANDED BANDWIDTH}

본 발명은 반도체 기술에 관한 것으로, 보다 상세하게는 확장된 대역폭을 갖는 반도체 패키지에 관한 것이다.The present invention relates to semiconductor technology, and more particularly, to a semiconductor package having an extended bandwidth.

반도체 소자에 대한 패키징 기술은 소형화 및 고용량화의 요구에 따라서 지속적으로 발전하고 있으며 최근에는 소형화, 고용량화 및 실장 효율성을 만족시킬 수 있는 적층 반도체 패키지(stacked semiconductor package)에 대한 다양한 기술들이 개발되고 있다.BACKGROUND OF THE INVENTION [0002] The packaging technology for semiconductor devices has been continuously developed in accordance with the demand for miniaturization and high capacity. Recently, various technologies for stacked semiconductor packages that can satisfy miniaturization, high capacity, and mounting efficiency have been developed.

반도체 산업에서 말하는 "적층"이란 적어도 2개 이상의 반도체 칩 또는 패키지를 수직으로 쌓아 올리는 기술로서, 메모리 소자의 경우 반도체 집적 공정에서 구현 가능한 메모리 용량보다 큰 메모리 용량을 갖는 제품을 구현할 수 있고 실장 면적 사용의 효율성을 높일 수 있다.In the semiconductor industry, "stacking" is a technology that vertically stacks at least two semiconductor chips or packages. In the case of a memory device, a product having a memory capacity that is larger than the memory capacity that can be implemented in the semiconductor integration process can be implemented and the mounting area is used. Can increase the efficiency of

적층 반도체 패키지 중 관통 전극(Through Silicon Via, TSV)을 이용한 적층 반도체 패키지는 반도체 칩에 관통 전극을 형성하고, 관통 전극에 의해 수직으로 반도체 칩들간 물리적 및 전기적 연결이 이루어지도록 한 구조를 갖는다. Among the stacked semiconductor packages, a stacked semiconductor package using a through electrode (TSV) has a structure in which a through electrode is formed on a semiconductor chip, and physical and electrical connections are made vertically between the semiconductor chips by the through electrode.

관통 전극을 이용한 적층 반도체 패키지에서는 반도체 칩들을 수직으로 관통하는 관통 전극들이 공통 접속 노드를 제공하기 때문에 반도체 칩들에 동시에 신호 입력은 가능하지만 동시에 신호 출력이 불가능하다. 따라서, 적층되는 반도체 칩의 개수가 증가하더라도 고정적인 대역폭(bandwidth)을 가질 수 밖에 없었다.In a multilayer semiconductor package using through electrodes, since through electrodes vertically penetrating the semiconductor chips provide a common connection node, signals can be simultaneously input to semiconductor chips, but signal output is not possible at the same time. Therefore, even if the number of stacked semiconductor chips increases, it has no choice but to have a fixed bandwidth.

본 발명의 실시예들은 확장된 대역폭을 갖는 반도체 패키지를 제공한다.Embodiments of the present invention provide a semiconductor package having an extended bandwidth.

본 발명의 일 실시예에 따른 반도체 패키지는, 상호 스택되며 각각 하부면에 제1 입출력 회로가 연결된 제1 노멀 패드 및 상기 제1 입출력 회로가 연결되지 않은 제1 더미 패드를 구비하는 제1,제2 반도체 칩과, 상기 제1 반도체 칩을 관통하여 상기 제1 반도체 칩의 상기 제1 더미 패드와 상기 제2 반도체 칩의 상기 제1 노멀 패드를 전기적으로 연결하는 제1 관통 전극과, 상기 제1 반도체 칩의 하부면을 지지하며 상기 제1 반도체 칩의 상기 제1 노멀 패드 및 상기 제1 더미 패드에 각각 전기적으로 연결된 제1 접속 패드들을 갖는 기판을 포함할 수 있다.The semiconductor package according to an exemplary embodiment of the present invention includes first and second normal pads stacked with each other and having a first normal pad connected to a first input/output circuit and a first dummy pad to which the first input/output circuit is not connected. 2 A semiconductor chip, a first through electrode penetrating the first semiconductor chip to electrically connect the first dummy pad of the first semiconductor chip to the first normal pad of the second semiconductor chip, and the first A substrate supporting a lower surface of a semiconductor chip and having first connection pads electrically connected to the first normal pad and the first dummy pad of the first semiconductor chip, respectively.

본 기술에 따르면, 스택된 반도체 칩들로/로부터 동시에 신호를 입력 및 동시에 신호를 출력할 수 있으므로 대역폭을 확장시킬 수 있다. 또한, 더미 패드가 특별한 위치적 제약 없이 노멀 패드가 형성되고 남은 여분 공간에 배치되므로 기존의 패드 배치 구조를 변경하지 않아도 되므로 패드 설계 변경에 따른 시간 및 비용 추가로 인한 어려움을 줄일 수 있다. According to the present technology, a signal can be simultaneously input to/from the stacked semiconductor chips and a signal can be output simultaneously, thereby extending the bandwidth. In addition, since the dummy pad is disposed in the remaining space after the normal pad is formed without any special positional restrictions, it is not necessary to change the existing pad arrangement structure, so that difficulties due to time and cost added to the pad design change can be reduced.

도 1은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 2는 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 3은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 4는 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 5는 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 6은 본 발명의 일 실시예에 따른 반도체 패키지를 도시한 단면도이다.
도 7는 본 발명에 따른 반도체 패키지를 구비한 전자 시스템의 블록도이다.
도 8은 본 발명에 따른 반도체 패키지를 포함하는 메모리 카드의 블럭도이다. 1 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
4 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
5 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
6 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention.
7 is a block diagram of an electronic system including a semiconductor package according to the present invention.
8 is a block diagram of a memory card including a semiconductor package according to the present invention.

이하, 첨부된 도면들을 참조하여 본 발명의 바람직한 실시예들을 상세히 설명하도록 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

도 1을 참조하면, 본 발명의 일실시예에 따른 반도체 패키지는 기판(10), 제1,제2 반도체 칩(20,22) 및 제1 관통 전극(30)들을 포함할 수 있다. Referring to FIG. 1, a semiconductor package according to an embodiment of the present invention may include a substrate 10, first and second semiconductor chips 20 and 22, and first through electrodes 30.

기판(10)은 인쇄회로기판(Printed Circuit Board, PCB)일 수 있다. 기판(10)의 상부면에는 복수개의 제1 접속 패드(11)들이 형성될 수 있고, 기판(10)의 하부면에는 복수개의 전극 패드(12)들이 형성될 수 있다. 그리고, 전극 패드(12)들 상에는 솔더볼(solder ball)과 같은 외부연결전극(13)들이 형성될 수 있다. 도시하지 않았지만, 기판(10)은 상부면에 형성된 제1 접속 패드(11)들과 하부면에 형성된 전극 패드(12)들간을 전기적으로 연결하는 회로 배선(미도시)을 포함할 수 있다. 한편, 기판(10)은 리드 프레임(leadframe), 플렉서블 기판(flexible substrate) 및 인터포저(interposer) 중 어느 하나로 구성될 수도 있다. The substrate 10 may be a printed circuit board (PCB). A plurality of first connection pads 11 may be formed on the upper surface of the substrate 10, and a plurality of electrode pads 12 may be formed on the lower surface of the substrate 10. In addition, external connection electrodes 13 such as solder balls may be formed on the electrode pads 12. Although not shown, the substrate 10 may include circuit wiring (not shown) electrically connecting the first connection pads 11 formed on the upper surface and the electrode pads 12 formed on the lower surface. Meanwhile, the substrate 10 may be formed of any one of a lead frame, a flexible substrate, and an interposer.

제1 반도체 칩(20) 및 제2 반도체 칩(22)은 기판(10) 상에 차례로 스택될 수 있다. The first semiconductor chip 20 and the second semiconductor chip 22 may be sequentially stacked on the substrate 10.

제1,제2 반도체 칩(20,22)은 단일 웨이퍼 상에서 제조된 후에 개별화된 것일 수 있으며, 실질적으로 동일한 구조를 가질 수 있다. The first and second semiconductor chips 20 and 22 may be individualized after being manufactured on a single wafer, and may have substantially the same structure.

제1,제2 반도체 칩(20,22)은 각각 웨이퍼 기판(100) 및 웨이퍼 기판(100) 상에 형성된 액티브층(200)을 포함할 수 있다. 웨이퍼 기판(100)은 실리콘 웨이퍼일 수 있고, 액티브층(200)에는 집적 회로(미도시)가 형성될 수 있다. 집적 회로는 반도체 기억 소자 또는/및 반도체 로직 소자를 포함할 수 있으며, 칩 동작에 필요한 트랜지스터, 저항, 캐패시터 및 퓨즈 등의 개별 소자들이 상호 전기적으로 접속된 구조를 가질 수 있다. The first and second semiconductor chips 20 and 22 may each include a wafer substrate 100 and an active layer 200 formed on the wafer substrate 100. The wafer substrate 100 may be a silicon wafer, and an integrated circuit (not shown) may be formed on the active layer 200. The integrated circuit may include a semiconductor memory device or/and a semiconductor logic device, and may have a structure in which individual devices such as transistors, resistors, capacitors, and fuses required for chip operation are electrically connected to each other.

제1,제2 반도체 칩(20, 22)은 액티브층(200)이 기판(10) 쪽을 향하고, 웨이퍼 기판(100)이 기판(10)의 반대쪽을 향하도록 스택될 수 있다. The first and second semiconductor chips 20 and 22 may be stacked so that the active layer 200 faces the substrate 10 and the wafer substrate 100 faces the opposite side of the substrate 10.

액티브층(200)에 의해 제공되는 제1,제2 반도체 칩(20, 22)의 하부면에는 제1 입출력 회로(500)가 연결된 제1 노멀 패드(first normal pad, 300)들 및 제1 입출력 회로(500)가 연결되지 않은 제1 더미 패드(first dummy pad, 400)들이 형성될 수 있다. 제1 노멀 패드(300)들은 외부 장치와의 전기적인 연결을 위한 집적 회로의 외부 단자로서, 집적 회로에 다층 배선 구조(미도시)를 거쳐 전기적으로 접속될 수 있다. 제1 노멀 패드(300)들은 기존의 칩 설계 규칙에 따른 패드 배치 구조를 가질 수 있고, 제1 더미 패드(400)들은 제1 노멀 패드(300)들이 배치되고 남은 여분 공간에 배치될 수 있다. 본 실시예에서, 제1 더미 패드(400)들은 제1 노멀 패드(300)들에 일대일로 대응될 수 있으며, 각각 대응하는 제1 노멀 패드(300)의 주변에 배치될 수 있다. First normal pads 300 connected to the first input/output circuit 500 and first input/output are provided on the lower surfaces of the first and second semiconductor chips 20 and 22 provided by the active layer 200. First dummy pads 400 to which the circuit 500 is not connected may be formed. The first normal pads 300 are external terminals of an integrated circuit for electrical connection with an external device, and may be electrically connected to the integrated circuit through a multilayer wiring structure (not shown). The first normal pads 300 may have a pad arrangement structure according to an existing chip design rule, and the first dummy pads 400 may be disposed in an extra space remaining after the first normal pads 300 are disposed. In this embodiment, the first dummy pads 400 may correspond to the first normal pads 300 on a one-to-one basis, and may be disposed around the corresponding first normal pads 300, respectively.

제1 입출력 회로(500)는 액티브층(200)에 형성되며 입력 버퍼(input buffer) 및 출력 드라이버(output driver) 등을 포함할 수 있다. 제1 입출력 회로(500)는 제1 노멀 패드(300)를 통해 외부로부터 입력되는 신호를 집적 회로로 전달하거나, 집적 회로로부터 출력되는 신호를 제1 노멀 패드(300)를 통해서 외부로 전달할 수 있다. The first input/output circuit 500 is formed on the active layer 200 and may include an input buffer and an output driver. The first input/output circuit 500 may transmit a signal input from the outside through the first normal pad 300 to the integrated circuit, or may transmit a signal output from the integrated circuit to the outside through the first normal pad 300. .

제1 관통 전극(30)들은 제1 반도체 칩(20)을 관통하여 제1 반도체 칩(20)의 제1 더미 패드(400)들과 제2 반도체 칩(22)의 제1 노멀 패드(300)들을 전기적으로 연결할 수 있다. 본 실시예에서, 각각의 제1 관통 전극(30)들은 제1 반도체 칩(20)의 웨이퍼 기판(100)을 관통하는 전도성 필라(conductive pillar, 31) 및 제1 반도체 칩(20)의 액티브층(200)에 형성되며 전도성 필라(31)와 제1 반도체 칩(20)의 제1 더미 패드(400)를 전기적으로 연결하는 회로 패턴(circuit pattern, 32)을 포함할 수 있다. The first through electrodes 30 pass through the first semiconductor chip 20 and the first dummy pads 400 of the first semiconductor chip 20 and the first normal pad 300 of the second semiconductor chip 22. Can be connected electrically. In this embodiment, each of the first through electrodes 30 is a conductive pillar 31 penetrating the wafer substrate 100 of the first semiconductor chip 20 and an active layer of the first semiconductor chip 20. A circuit pattern 32 formed on 200 and electrically connecting the conductive pillar 31 and the first dummy pad 400 of the first semiconductor chip 20 may be included.

전도성 필라(31)는 제1 반도체 칩(20)의 웨이퍼 기판(100)에 비아홀을 형성하고 비아홀에 구리, 알루미늄, 알루미늄 합금, SnAg, Au 등의 도전성 물질을 충진하여 형성될 수 있다. 비아홀에 도전성 물질을 충진하기 전에 전도성 필라(31)와 웨이퍼 기판(100)간을 절연 분리시키기 위하여 비아홀의 표면에 산화막, 질화막 및 유기막 등으로 절연 스페이서를 형성할 수도 있다. The conductive pillar 31 may be formed by forming a via hole in the wafer substrate 100 of the first semiconductor chip 20 and filling the via hole with a conductive material such as copper, aluminum, aluminum alloy, SnAg, or Au. Before filling the via hole with a conductive material, an insulating spacer may be formed of an oxide film, a nitride film, an organic film, or the like on the surface of the via hole in order to insulate and separate the conductive pillar 31 and the wafer substrate 100.

본 실시예에서, 전도성 필라(31)는 제1 노멀 패드(300)와 동일 선상에서 제1 반도체 칩(20)의 웨이퍼 기판(100)을 관통할 수 있다. 그리고, 제2 반도체 칩(22)은 자신의 제1 노멀 패드(300)들이 제1 반도체 칩(20)의 제1 노멀 패드(300)들과 동일 선상에 배치되도록 제1 반도체 칩(20) 상에 수직하게 스택될 수 있다. In this embodiment, the conductive pillar 31 may penetrate the wafer substrate 100 of the first semiconductor chip 20 on the same line as the first normal pad 300. Further, the second semiconductor chip 22 is formed on the first semiconductor chip 20 so that its first normal pads 300 are disposed on the same line as the first normal pads 300 of the first semiconductor chip 20. Can be stacked vertically.

제1 반도체 칩(20, 22)의 제1 노멀 패드(300)들 및 제1 더미 패드(400)들 상에는 범프(bump) 등으로 이루어진 전도성 연결부재(600, 620)들이 형성될 수 있다. Conductive connecting members 600 and 620 made of bumps may be formed on the first normal pads 300 and the first dummy pads 400 of the first semiconductor chips 20 and 22.

제1 반도체 칩(20)의 제1 노멀 패드(300)들 및 제1 더미 패드(400)는 전도성 연결부재(600)들을 매개로 기판(10)의 제1 접속 패드(11)들과 전기적으로 연결될 수 있고, 제2 반도체 칩(22)의 제1 노멀 패드(300)들은 전도성 연결부재(620)들을 매개로 제1 관통 전극(30)들에 전기적으로 연결될 수 있다. The first normal pads 300 and the first dummy pad 400 of the first semiconductor chip 20 are electrically connected to the first connection pads 11 of the substrate 10 through the conductive connection member 600. The first normal pads 300 of the second semiconductor chip 22 may be connected to each other, and the first normal pads 300 of the second semiconductor chip 22 may be electrically connected to the first through electrodes 30 through the conductive connection members 620.

본 실시예에서는 제1 관통 전극(30)들을 통하여 데이터 버스가 형성될 수 있고, 제2 반도체 칩(22)에 형성된 집적 회로는 제1 관통 전극(30)들을 통하여 제1 반도체 칩(20)과 별개로 데이터를 입력받거나 데이터를 출력할 수 있다.In this embodiment, a data bus may be formed through the first through electrodes 30, and the integrated circuit formed on the second semiconductor chip 22 is connected to the first semiconductor chip 20 through the first through electrodes 30. Separately, data can be input or data can be output.

그리고, 제1,제2 반도체 칩(20,22)을 외부 환경으로부터 보호하기 위하여 기판(10)의 상부면 상에는 제1,제2 반도체 칩(20,22)을 몰딩하는 몰드부(40)가 형성될 수 있다. In addition, in order to protect the first and second semiconductor chips 20 and 22 from the external environment, a mold part 40 for molding the first and second semiconductor chips 20 and 22 is formed on the upper surface of the substrate 10. Can be formed.

도 1을 참조로 하여 설명된 실시예에서는 제1 관통 전극(30)의 전도성 필라(31)가 제1 반도체 칩(20)의 제1 노멀 패드(300)와 동일선 상에서 제1 반도체 칩(20)의 실리콘 기판(100)을 관통하고, 제2 반도체 칩(22)이 제1 반도체 칩(20) 상에 수직하게 스택된 경우를 나타내었으나, 본 발명의 기술적 사상은 이에 한정되지 않는다. In the embodiment described with reference to FIG. 1, the conductive pillar 31 of the first through electrode 30 is on the same line as the first normal pad 300 of the first semiconductor chip 20. Although the second semiconductor chip 22 penetrates through the silicon substrate 100 and is vertically stacked on the first semiconductor chip 20, the technical idea of the present invention is not limited thereto.

예컨대, 도 2를 참조하면 제1 관통 전극(30)의 전도성 필라(31)는 제1 반도체 칩(20)의 제1 더미 패드(400)와 동일선상에서 제1 반도체 칩(20)의 실리콘 기판(100)을 관통할 수 있다. 그리고, 제2 반도체 칩(22)은 자신의 제1 노멀 패드(300)들이 제1 반도체 칩(20)의 제1 더미 패드(400)들과 동일선 상에 위치되도록 제1 반도체 칩(20)과 어긋나게 스택될 수 있다.For example, referring to FIG. 2, the conductive pillar 31 of the first through electrode 30 is on the same line as the first dummy pad 400 of the first semiconductor chip 20 and the silicon substrate of the first semiconductor chip 20 ( 100) can be penetrated. In addition, the second semiconductor chip 22 includes the first semiconductor chip 20 so that its first normal pads 300 are positioned on the same line as the first dummy pads 400 of the first semiconductor chip 20. Can be stacked misaligned.

한편, 도 1 및 도 2를 참조로 하여 설명된 실시예에서는 제1 관통 전극(30)이 전도성 필라(31) 및 회로 패턴(32)으로 구성된 경우를 나타내었으나, 본 발명은 이에 한정되지 않는다. 예컨대, 도 3을 참조하면 제1 관통 전극(30)은 제1 반도체 칩(20)의 실리콘 기판(100) 및 액티브층(200)을 관통하여 제1 더미 패드(400)에 전기적으로 접속된 전도성 필라로 구성될 수도 있다. Meanwhile, in the embodiment described with reference to FIGS. 1 and 2, a case in which the first through electrode 30 is formed of a conductive pillar 31 and a circuit pattern 32 is illustrated, but the present invention is not limited thereto. For example, referring to FIG. 3, the first through electrode 30 passes through the silicon substrate 100 and the active layer 200 of the first semiconductor chip 20 and is electrically connected to the first dummy pad 400. It can also be composed of pillars.

한편, 도 1 내지 도 3을 참조로 한 실시예에서는 기판상에 2개의 반도체 칩이 스택된 경우를 나타내었으나, 본 발명의 기술적 사상은 이에 한정되지 않고 스택되는 반도체 칩의 개수는 2개보다 많을 수 있다. 이러한 실시예들은 도 4 내지 도 6을 참조로 한 이하의 설명을 통해 보다 명백해질 것이다. Meanwhile, in the embodiment with reference to FIGS. 1 to 3, two semiconductor chips are stacked on a substrate, but the technical idea of the present invention is not limited thereto, and the number of stacked semiconductor chips may be greater than two. I can. These embodiments will become more apparent through the following description with reference to FIGS. 4 to 6.

도 4를 참조하면, 본 발명의 일실시예에 따른 반도체 패키지는 기판(10), 제1,제2 반도체 칩(20,22), 제1 관통 전극(30), 제3,제4 반도체 칩(50,52) 및 제2 관통 전극(60)을 포함할 수 있다. Referring to FIG. 4, a semiconductor package according to an embodiment of the present invention includes a substrate 10, first and second semiconductor chips 20 and 22, a first through electrode 30, and a third and fourth semiconductor chip. (50, 52) and a second through electrode 60 may be included.

기판(10)은 인쇄회로기판(PCB)일 수 있다. 기판(10)의 상부면 중심에는 복수개의 제1 접속 패드(11)들이 형성되고, 기판(10)의 상부면 가장자리에는 복수개의 제2 접속 패드(11A)들이 형성될 수 있다. 그리고, 기판(10)의 하부면에는 복수개의 전극 패드(12)들이 형성될 수 있고, 전극 패드(12)들 상에는 솔더볼과 같은 외부연결전극(13)들이 형성될 수 있다. 도시하지 않았지만, 기판(10)은 상부면에 형성된 제1,제2 접속 패드(11,11A)들과 하부면에 형성된 전극 패드(12)들간을 전기적으로 연결하는 회로 배선(미도시)을 포함할 수 있다. 한편, 기판(10)은 리드 프레임, 플렉서블 기판 및 인터포저 중 어느 하나로 구성될 수도 있다. The substrate 10 may be a printed circuit board (PCB). A plurality of first connection pads 11 may be formed at the center of the upper surface of the substrate 10, and a plurality of second connection pads 11A may be formed at the edge of the upper surface of the substrate 10. Further, a plurality of electrode pads 12 may be formed on the lower surface of the substrate 10, and external connection electrodes 13 such as solder balls may be formed on the electrode pads 12. Although not shown, the substrate 10 includes a circuit wiring (not shown) electrically connecting the first and second connection pads 11 and 11A formed on the upper surface and the electrode pads 12 formed on the lower surface. can do. Meanwhile, the substrate 10 may be composed of any one of a lead frame, a flexible substrate, and an interposer.

제1 반도체 칩(20) 및 제2 반도체 칩(22)은 기판(10) 상에 차례로 스택될 수 있다. The first semiconductor chip 20 and the second semiconductor chip 22 may be sequentially stacked on the substrate 10.

제1,제2 반도체 칩(20,22)은 단일 웨이퍼 상에서 제조된 후에 개별화된 것일 수 있으며, 실질적으로 동일한 구조를 가질 수 있다. The first and second semiconductor chips 20 and 22 may be individualized after being manufactured on a single wafer, and may have substantially the same structure.

제1,제2 반도체 칩(20,22)은 각각 웨이퍼 기판(100) 및 웨이퍼 기판(100) 상에 형성된 액티브층(200)을 포함할 수 있다. 웨이퍼 기판(100)은 실리콘 웨이퍼일 수 있고, 액티브층(200)에는 집적 회로(미도시)가 형성될 수 있다. 집적 회로는 반도체 기억 소자 또는/및 반도체 로직 소자를 포함할 수 있으며, 칩 동작에 필요한 트랜지스터, 저항, 캐패시터 및 퓨즈 등의 개별 소자들이 상호 전기적으로 접속된 구조를 가질 수 있다. The first and second semiconductor chips 20 and 22 may each include a wafer substrate 100 and an active layer 200 formed on the wafer substrate 100. The wafer substrate 100 may be a silicon wafer, and an integrated circuit (not shown) may be formed on the active layer 200. The integrated circuit may include a semiconductor memory device or/and a semiconductor logic device, and may have a structure in which individual devices such as transistors, resistors, capacitors, and fuses required for chip operation are electrically connected to each other.

제1,제2 반도체 칩(20, 22)은 액티브층(200)이 기판(10) 쪽을 향하고, 웨이퍼 기판(100)이 기판(10)의 반대쪽을 향하도록 스택될 수 있다. The first and second semiconductor chips 20 and 22 may be stacked so that the active layer 200 faces the substrate 10 and the wafer substrate 100 faces the opposite side of the substrate 10.

액티브층(200)에 의해 제공되는 제1,제2 반도체 칩(20, 22)의 하부면에는 제1 입출력 회로(500)가 연결된 제1 노멀 패드(300)들 및 제1 입출력 회로(500)가 연결되지 않은 제1 더미 패드(400)들이 형성될 수 있다. 제1 노멀 패드(300)들은 외부 장치와의 전기적인 연결을 위한 집적 회로의 외부 단자로서, 집적 회로에 다층 배선 구조(미도시)를 거쳐 전기적으로 접속될 수 있다. 제1 노멀 패드(300)들은 기존의 칩 설계 규칙에 따른 패드 배치 구조를 가질 수 있고, 제1 더미 패드(400)들은 제1 노멀 패드(300)들이 배치되고 남은 여분 공간에 배치될 수 있다. 본 실시예에서, 제1 더미 패드(400)들은 제1 노멀 패드(300)들에 일대일로 대응될 수 있으며, 각각 대응하는 제1 노멀 패드(300)의 주변에 배치될 수 있다.The first normal pads 300 and the first input/output circuit 500 to which the first input/output circuit 500 is connected to the lower surfaces of the first and second semiconductor chips 20 and 22 provided by the active layer 200 First dummy pads 400 to which are not connected may be formed. The first normal pads 300 are external terminals of an integrated circuit for electrical connection with an external device, and may be electrically connected to the integrated circuit through a multilayer wiring structure (not shown). The first normal pads 300 may have a pad arrangement structure according to an existing chip design rule, and the first dummy pads 400 may be disposed in an extra space remaining after the first normal pads 300 are disposed. In this embodiment, the first dummy pads 400 may correspond to the first normal pads 300 on a one-to-one basis, and may be disposed around the corresponding first normal pads 300, respectively.

제1 입출력 회로(500)는 액티브층(200)에 형성되며 입력 버퍼 및 출력 드라이버 등을 포함할 수 있다. 제1 입출력 회로(500)는 제1 노멀 패드(300)를 통해 외부로부터 입력되는 신호를 집적 회로로 전달하거나, 집적 회로로부터 출력되는 신호를 제1 노멀 패드(300)를 통해서 외부로 전달할 수 있다. The first input/output circuit 500 is formed on the active layer 200 and may include an input buffer and an output driver. The first input/output circuit 500 may transmit a signal input from the outside through the first normal pad 300 to the integrated circuit, or may transmit a signal output from the integrated circuit to the outside through the first normal pad 300. .

제1 관통 전극(30)들은 제1 반도체 칩(20)을 관통하여 제1 반도체 칩(20)의 제1 더미 패드(400)들과 제2 반도체 칩(22)의 제1 노멀 패드(300)들을 전기적으로 연결할 수 있다. 따라서, 제1 관통 전극(30)들을 통하여 데이터 버스가 형성될 수 있고, 제2 반도체 칩(22)에 형성된 집적 회로는 제1 관통 전극(30)들을 통하여 제1 반도체 칩(20)과 별개로 데이터를 입력받거나 데이터를 출력할 수 있다.The first through electrodes 30 pass through the first semiconductor chip 20 and the first dummy pads 400 of the first semiconductor chip 20 and the first normal pad 300 of the second semiconductor chip 22. Can be connected electrically. Accordingly, a data bus may be formed through the first through electrodes 30, and the integrated circuit formed in the second semiconductor chip 22 is separated from the first semiconductor chip 20 through the first through electrodes 30. You can receive data or output data.

본 실시예에서, 각각의 제1 관통 전극(30)들은 제1 반도체 칩(20)의 웨이퍼 기판(100)을 관통하는 전도성 필라(31) 및 제1 반도체 칩(20)의 액티브층(200)에 형성되며 전도성 필라(31)와 제1 반도체 칩(20)의 제1 더미 패드(400)를 전기적으로 연결하는 회로 패턴(32)을 포함할 수 있다. In this embodiment, each of the first through electrodes 30 is a conductive pillar 31 penetrating the wafer substrate 100 of the first semiconductor chip 20 and the active layer 200 of the first semiconductor chip 20. And a circuit pattern 32 that is formed in the conductive pillar 31 and electrically connects the first dummy pad 400 of the first semiconductor chip 20 to each other.

비록, 본 실시예에서는 제1 관통 전극(30)이 전도성 필라(31) 및 회로 패턴(32)으로 구성된 경우를 나타내었으나, 본 발명의 기술적 사상은 이에 한정되지 않으며, 앞서 도 3을 참조로 설명한 바와 같이 제1 관통 전극(30)은 제1 반도체 칩(20)의 실리콘 기판(100) 및 액티브층(200)을 관통하여 제1 더미 패드(400)에 전기적으로 접속된 전도성 필라만으로 구성될 수도 있다. Although, in the present embodiment, a case in which the first through electrode 30 is composed of the conductive pillar 31 and the circuit pattern 32 is shown, the technical idea of the present invention is not limited thereto, and described above with reference to FIG. 3. As shown, the first through electrode 30 may be formed of only conductive pillars electrically connected to the first dummy pad 400 through the silicon substrate 100 and the active layer 200 of the first semiconductor chip 20. have.

도 4를 다시 참조하면, 전도성 필라(31)는 제1 반도체 칩(20)의 웨이퍼 기판(100)에 비아홀을 형성하고 비아홀에 구리, 알루미늄, 알루미늄 합금, SnAg, Au 등의 도전성 물질을 충진하여 형성될 수 있다. 비아홀에 도전성 물질을 충진하기 전에 전도성 필라(31)와 웨이퍼 기판(100)간을 절연 분리시키기 위하여 비아홀의 표면에 산화막, 질화막 및 유기막 등으로 절연 스페이서를 형성할 수도 있다. Referring again to FIG. 4, the conductive pillar 31 forms a via hole in the wafer substrate 100 of the first semiconductor chip 20 and fills the via hole with a conductive material such as copper, aluminum, aluminum alloy, SnAg, and Au. Can be formed. Before filling the via hole with a conductive material, an insulating spacer may be formed of an oxide film, a nitride film, an organic film, or the like on the surface of the via hole in order to insulate and separate the conductive pillar 31 and the wafer substrate 100.

본 실시예에서, 전도성 필라(31)는 제1 노멀 패드(300)와 동일 선상에서 제1 반도체 칩(20)의 웨이퍼 기판(100)을 관통할 수 있다. 그리고, 제2 반도체 칩(22)은 자신의 제1 노멀 패드(300)들이 제1 반도체 칩(20)의 제1 노멀 패드(300)들과 동일 선상에 배치되도록 제1 반도체 칩(20) 상에 수직하게 스택될 수 있다. In this embodiment, the conductive pillar 31 may penetrate the wafer substrate 100 of the first semiconductor chip 20 on the same line as the first normal pad 300. Further, the second semiconductor chip 22 is formed on the first semiconductor chip 20 so that its first normal pads 300 are disposed on the same line as the first normal pads 300 of the first semiconductor chip 20. Can be stacked vertically.

비록, 본 실시예에서는 제1 관통 전극(30)의 전도성 필라(31)가 제1 반도체 칩(20)의 제1 노멀 패드(300)와 동일선 상에서 제1 반도체 칩(20)의 실리콘 기판(100)을 관통하고, 제2 반도체 칩(22)이 제1 반도체 칩(20) 상에 수직하게 스택된 경우를 나타내었으나, 본 발명의 기술적 사상은 이에 한정되지 않는다. 예컨대, 앞서 도 2를 참조로 하여 설명한 바와 같이 제1 관통 전극(30)의 전도성 필라(31)는 제1 반도체 칩(20)의 제1 더미 패드(400)와 동일선상에서 제1 반도체 칩(20)의 실리콘 기판(100)을 관통할 수 있고, 제2 반도체 칩(22)은 자신의 제1 노멀 패드(300)들이 제1 반도체 칩(20)의 제1 더미 패드(400)들과 동일선 상에 위치되도록 제1 반도체 칩(20)과 어긋나게 스택될 수 있다.Although, in this embodiment, the conductive pillar 31 of the first through electrode 30 is on the same line as the first normal pad 300 of the first semiconductor chip 20 and the silicon substrate 100 of the first semiconductor chip 20 ), and the second semiconductor chip 22 is vertically stacked on the first semiconductor chip 20, but the technical idea of the present invention is not limited thereto. For example, as described above with reference to FIG. 2, the conductive pillar 31 of the first through electrode 30 is on the same line as the first dummy pad 400 of the first semiconductor chip 20. ), and the second semiconductor chip 22 has its first normal pads 300 on the same line as the first dummy pads 400 of the first semiconductor chip 20. It may be stacked so as to be positioned at the first semiconductor chip 20 so as to be shifted from the first semiconductor chip 20.

제1,제2 반도체 칩(20, 22)의 제1 노멀 패드(300)들 및 제1 더미 패드(400)들 상에는 범프와 같은 전도성 연결부재(600, 620)들이 형성될 수 있다. 제1 반도체 칩(20)의 제1 노멀 패드(300)들 및 제1 더미 패드(400)는 전도성 연결부재(600)들을 매개로 기판(10)의 제1 접속 패드(11)들에 전기적으로 연결될 수 있고, 제2 반도체 칩(22)의 제1 노멀 패드(300)들은 전도성 연결부재(620)들을 매개로 제1 관통 전극(30)들에 전기적으로 연결될 수 있다.Conductive connecting members 600 and 620 such as bumps may be formed on the first normal pads 300 and the first dummy pads 400 of the first and second semiconductor chips 20 and 22. The first normal pads 300 and the first dummy pad 400 of the first semiconductor chip 20 are electrically connected to the first connection pads 11 of the substrate 10 through the conductive connection members 600. The first normal pads 300 of the second semiconductor chip 22 may be connected to each other, and the first normal pads 300 of the second semiconductor chip 22 may be electrically connected to the first through electrodes 30 through the conductive connection members 620.

제3,제4 반도체 칩(50,52)은 제1,제2 반도체 칩(20,22)보다 큰 평면적을 가지며, 제1,제2 반도체 칩(20,22)의 개재하에 기판(10) 상에 차례로 스택될 수 있다. The third and fourth semiconductor chips 50 and 52 have a larger planar area than the first and second semiconductor chips 20 and 22, and the substrate 10 is interposed by the first and second semiconductor chips 20 and 22. Can be stacked one after the other.

제3,제4 반도체 칩(50,52)은 단일 웨이퍼 상에서 제조된 후에 개별화된 것일 수 있으며, 실질적으로 동일한 구조를 가질 수 있다. The third and fourth semiconductor chips 50 and 52 may be individualized after being manufactured on a single wafer, and may have substantially the same structure.

제3,제4 반도체 칩(50,52)은 각각 웨이퍼 기판(110) 및 웨이퍼 기판(110) 상에 형성된 액티브층(210)을 포함할 수 있다. 웨이퍼 기판(110)은 실리콘 웨이퍼일 수 있고, 액티브층(210)에는 집적 회로(미도시)가 형성될 수 있다. 집적 회로는 반도체 기억 소자 또는/및 반도체 로직 소자를 포함할 수 있으며, 칩 동작에 필요한 트랜지스터, 저항, 캐패시터 및 퓨즈 등의 개별 소자들이 상호 전기적으로 접속된 구조를 가질 수 있다. The third and fourth semiconductor chips 50 and 52 may include a wafer substrate 110 and an active layer 210 formed on the wafer substrate 110, respectively. The wafer substrate 110 may be a silicon wafer, and an integrated circuit (not shown) may be formed on the active layer 210. The integrated circuit may include a semiconductor memory device or/and a semiconductor logic device, and may have a structure in which individual devices such as transistors, resistors, capacitors, and fuses required for chip operation are electrically connected to each other.

제3,제4 반도체 칩(50, 52)은 액티브층(210)이 기판(10) 쪽을 향하고, 웨이퍼 기판(110)이 기판(10)의 반대쪽을 향하도록 스택될 수 있다. The third and fourth semiconductor chips 50 and 52 may be stacked so that the active layer 210 faces the substrate 10 and the wafer substrate 110 faces the opposite side of the substrate 10.

액티브층(210)에 의해 제공되는 제3,제4 반도체 칩(50, 52)의 하부면에는 제2 입출력 회로(510)가 연결된 제2 노멀 패드(second normal pad, 310)들 및 제2 입출력 회로(510)가 연결되지 않은 제2 더미 패드(second dummy pad, 410)들이 형성될 수 있다. 제2 노멀 패드(310)들은 외부 장치와의 전기적인 연결을 위한 집적 회로의 외부 단자로서, 다층 배선 구조(미도시)를 통해 집적 회로에 전기적으로 접속될 수 있다. 제2 노멀 패드(310)들은 기존의 칩 설계 규칙에 따른 패드 배치 구조를 가질 수 있고, 제2 더미 패드(410)들은 제2 노멀 패드(310)들이 배치되고 남은 여분 공간에 배치될 수 있다. 본 실시예에서, 제2 더미 패드(410)들은 제2 노멀 패드(310)들에 일대일로 대응될 수 있으며, 각각 대응하는 제2 노멀 패드(310)의 주변에 배치될 수 있다.Second normal pads 310 to which a second input/output circuit 510 is connected and a second input/output are provided on the lower surfaces of the third and fourth semiconductor chips 50 and 52 provided by the active layer 210. Second dummy pads 410 to which the circuit 510 is not connected may be formed. The second normal pads 310 are external terminals of an integrated circuit for electrical connection with an external device, and may be electrically connected to the integrated circuit through a multilayer wiring structure (not shown). The second normal pads 310 may have a pad arrangement structure according to an existing chip design rule, and the second dummy pads 410 may be disposed in an extra space remaining after the second normal pads 310 are disposed. In the present embodiment, the second dummy pads 410 may correspond to the second normal pads 310 on a one-to-one basis, and may be disposed around the corresponding second normal pads 310, respectively.

제2 입출력 회로(510)는 액티브층(210)에 형성되며 입력 버퍼 및 출력 드라이버 등을 포함할 수 있다. 제2 입출력 회로(510)는 제2 노멀 패드(310)를 통해 외부로부터 입력되는 신호를 집적 회로로 전달하거나, 집적 회로로부터 출력되는 신호를 제2 노멀 패드(310)를 통해서 외부로 전달할 수 있다. The second input/output circuit 510 is formed on the active layer 210 and may include an input buffer and an output driver. The second input/output circuit 510 may transmit a signal input from the outside through the second normal pad 310 to the integrated circuit, or may transmit a signal output from the integrated circuit to the outside through the second normal pad 310. .

제2 관통 전극(60)들은 제3 반도체 칩(50)을 관통하여 제3 반도체 칩(50)의 제2 더미 패드(410)들과 제4 반도체 칩(52)의 제2 노멀 패드(310)들을 전기적으로 연결할 수 있다. 본 실시예에서, 제2 관통 전극(60)들은 각각 제3 반도체 칩(50)의 웨이퍼 기판(110)을 관통하는 전도성 필라(61) 및 제3 반도체 칩(50)의 액티브층(210)에 형성되며 전도성 필라(61)와 제3 반도체 칩(50)의 제2 더미 패드(410)를 전기적으로 연결하는 회로 패턴(62)을 포함할 수 있다. The second through electrodes 60 pass through the third semiconductor chip 50 and the second dummy pads 410 of the third semiconductor chip 50 and the second normal pad 310 of the fourth semiconductor chip 52. Can be connected electrically. In this embodiment, the second through electrodes 60 are respectively formed on the conductive pillar 61 penetrating the wafer substrate 110 of the third semiconductor chip 50 and the active layer 210 of the third semiconductor chip 50. It is formed and may include a circuit pattern 62 electrically connecting the conductive pillar 61 and the second dummy pad 410 of the third semiconductor chip 50.

전도성 필라(61)는 제3 반도체 칩(50)의 웨이퍼 기판(110)에 비아홀을 형성하고 비아홀에 구리, 알루미늄, 알루미늄 합금, SnAg, Au 등의 도전성 물질을 충진하여 형성될 수 있다. 비아홀에 도전성 물질을 충진하기 전에 전도성 필라(61)와 웨이퍼 기판(110)간을 절연 분리시키기 위하여 비아홀의 표면에 산화막, 질화막 및 유기막 등으로 절연 스페이서를 형성할 수도 있다. The conductive pillar 61 may be formed by forming a via hole in the wafer substrate 110 of the third semiconductor chip 50 and filling the via hole with a conductive material such as copper, aluminum, aluminum alloy, SnAg, or Au. Before filling the via hole with a conductive material, an insulating spacer may be formed of an oxide film, a nitride film, an organic film, or the like on the surface of the via hole in order to insulate the conductive pillar 61 and the wafer substrate 110.

본 실시예에서, 전도성 필라(61)는 제2 노멀 패드(310)와 동일 선상에서 제3 반도체 칩(50)의 웨이퍼 기판(110)을 관통할 수 있다. 그리고, 제4 반도체 칩(52)은 자신의 제2 노멀 패드(310)들이 제3 반도체 칩(50)의 제2 노멀 패드(310)들과 동일 선상에 배치되도록 제3 반도체 칩(50) 상에 수직하게 스택될 수 있다. In this embodiment, the conductive pillar 61 may penetrate the wafer substrate 110 of the third semiconductor chip 50 on the same line as the second normal pad 310. In addition, the fourth semiconductor chip 52 is formed on the third semiconductor chip 50 so that its second normal pads 310 are disposed on the same line as the second normal pads 310 of the third semiconductor chip 50. Can be stacked vertically.

제3,제4 반도체 칩(50, 52)의 제2 노멀 패드(310)들 및 제2 더미 패드(410)들 상에는 범프와 같은 전도성 연결부재(700, 720)들이 형성될 수 있다. 제3 반도체 칩(50)의 제2 노멀 패드(310)들 및 제2 더미 패드(410)는 전도성 연결부재(700)들을 매개로 기판(10)의 제2 접속 패드(11A)들에 전기적으로 연결될 수 있고, 제4 반도체 칩(52)의 제2 노멀 패드(310)들은 전도성 연결부재(720)들을 매개로 제2 관통 전극(60)들에 전기적으로 연결될 수 있다.Conductive connection members 700 and 720 such as bumps may be formed on the second normal pads 310 and the second dummy pads 410 of the third and fourth semiconductor chips 50 and 52. The second normal pads 310 and the second dummy pad 410 of the third semiconductor chip 50 are electrically connected to the second connection pads 11A of the substrate 10 via the conductive connection members 700. The second normal pads 310 of the fourth semiconductor chip 52 may be connected to each other, and the second normal pads 310 of the fourth semiconductor chip 52 may be electrically connected to the second through electrodes 60 through the conductive connection members 720.

그리고, 제1 내지 제4 반도체 칩들(20,22,50,52)을 외부 환경으로부터 보호하기 위하여 기판(10)의 상부면 상에는 제1 내지 제4 반도체 칩들(20,22,50,52)을 몰딩하는 몰드부(40)가 형성될 수 있다. 몰드부(40)는 에폭시 몰드 컴파운드(EMC)를 포함할 수 있다. In addition, in order to protect the first to fourth semiconductor chips 20, 22, 50, and 52 from an external environment, first to fourth semiconductor chips 20, 22, 50, and 52 are disposed on the upper surface of the substrate 10. A mold part 40 to be molded may be formed. The mold part 40 may include an epoxy mold compound (EMC).

비록, 도 4을 참조로 하여 설명된 실시예에서는 제2 관통 전극(60)의 전도성 필라(61)가 제3 반도체 칩(50)의 제2 노멀 패드(310)와 동일선 상에서 제3 반도체 칩(50)의 실리콘 기판(110)을 관통하고, 제4 반도체 칩(52)이 제3 반도체 칩(50) 상에 수직하게 스택된 경우를 나타내었으나, 본 발명의 기술적 사상은 이에 한정되지 않는다. Although, in the embodiment described with reference to FIG. 4, the conductive pillar 61 of the second through electrode 60 is on the same line as the second normal pad 310 of the third semiconductor chip 50. Although a case where the fourth semiconductor chip 52 is vertically stacked on the third semiconductor chip 50 after passing through the silicon substrate 110 of 50) is illustrated, the technical concept of the present invention is not limited thereto.

예컨대, 도 5를 참조하면 제3 관통 전극(60)의 전도성 필라(61)는 제3 반도체 칩(50)의 제2 더미 패드(410)와 동일선상에서 제3 반도체 칩(50)의 실리콘 기판(110)을 관통할 수 있다. 그리고, 제4 반도체 칩(52)은 자신의 제2 노멀 패드(310)들이 제3 반도체 칩(50)의 제2 더미 패드(410)들과 동일선 상에 위치되도록 제3 반도체 칩(50)과 어긋나게 스택될 수 있다.For example, referring to FIG. 5, the conductive pillar 61 of the third through electrode 60 is on the same line as the second dummy pad 410 of the third semiconductor chip 50 and the silicon substrate of the third semiconductor chip 50 ( 110). In addition, the fourth semiconductor chip 52 includes the third semiconductor chip 50 so that its second normal pads 310 are positioned on the same line as the second dummy pads 410 of the third semiconductor chip 50. Can be stacked misaligned.

한편, 도 4 및 도 5를 참조로 하여 설명된 실시예에서는 제2 관통 전극(60)이 전도성 필라(61) 및 회로 패턴(62)으로 구성된 경우를 나타내었으나, 본 발명은 이에 한정되지 않는다. 예컨대, 도 6을 참조하면 제2 관통 전극(60)은 제3 반도체 칩(50)의 실리콘 기판(110) 및 액티브층(210)을 관통하여 제3 반도체 칩(50)의 제2 더미 패드(410)에 접속된 전도성 필라로 구성될 수도 있다. Meanwhile, in the embodiment described with reference to FIGS. 4 and 5, a case in which the second through electrode 60 is formed of the conductive pillar 61 and the circuit pattern 62 is illustrated, but the present invention is not limited thereto. For example, referring to FIG. 6, the second through-electrode 60 penetrates the silicon substrate 110 and the active layer 210 of the third semiconductor chip 50 and passes through the second dummy pad of the third semiconductor chip 50. It may be composed of a conductive pillar connected to 410).

본 실시예들에 따르면, 스택된 반도체 칩들로/로부터 동시에 신호를 입력 및 동시에 신호를 출력할 수 있으므로 대역폭을 확장시킬 수 있다. 또한, 더미 패드가 특별한 위치적 제약 없이 노멀 패드가 형성되고 남은 여분 공간에 배치되므로 기존의 패드 배치 구조를 변경하지 않아도 되므로 패드 설계 변경에 따른 시간 및 스택된 반도체 칩들로/로부터 동시에 신호를 입력 및 동시에 신호를 출력할 수 있으므로 대역폭을 확장시킬 수 있다. 또한, 더미 패드가 특별한 위치적 제약 없이 노멀 패드가 형성되고 남은 여분 공간에 배치되므로 기존의 패드 배치 구조를 변경하지 않아도 되므로 패드 설계 변경에 따른 시간 및 비용 추가로 인한 어려움을 줄일 수 있다. 비용 추가로 인한 어려움을 줄일 수 있다. According to the present embodiments, a signal can be simultaneously input to/from the stacked semiconductor chips and a signal can be simultaneously output, so that a bandwidth can be extended. In addition, since the dummy pad is placed in the remaining space after the normal pad is formed without any special positional restrictions, it is not necessary to change the existing pad arrangement structure, so the time according to the pad design change and the signal to/from the stacked semiconductor chips are simultaneously input and Since signals can be output at the same time, the bandwidth can be expanded. In addition, since the dummy pad is disposed in the remaining space after the normal pad is formed without any special positional restrictions, it is not necessary to change the existing pad arrangement structure, so that difficulties due to time and cost added to the pad design change can be reduced. Difficulties caused by additional costs can be reduced.

전술한 반도체 패키지는 다양한 반도체 패키지들에 적용될 수 있다.The above-described semiconductor package can be applied to various semiconductor packages.

도 7을 참조하면, 본 발명의 실시예들에 따른 반도체 패키지는 전자 시스템(710)에 적용될 수 있다. 전자 시스템(710)은 컨트롤러(711), 입출력부(712) 및 메모리(713)를 포함할 수 있다. 컨트롤러(711), 입출력부(712) 및 메모리(713)는 데이터 이동하는 경로를 제공하는 버스(718)를 통해서 상호 커플링될 수 있다. Referring to FIG. 7, a semiconductor package according to embodiments of the present invention may be applied to an electronic system 710. The electronic system 710 may include a controller 711, an input/output unit 712, and a memory 713. The controller 711, the input/output unit 712, and the memory 713 may be coupled to each other through a bus 718 providing a path for moving data.

예컨데, 컨트롤러(711)는 적어도 하나의 마이크로 프로세서, 적어도 하나의 디지털 시그날 프로세서, 적어도 하나의 마이크로 컨트롤러 및 이러한 컴포넌트들과 동일한 기능을 수행할 수 있는 로직 회로 중 적어도 하나 이상을 포함할 수 있다. 메모리(713)는 본 발명의 실시예들에 따른 반도체 패키지 중 적어도 하나 이상을 포함할 수 있다. 입출력부(712)는 키패드, 키보드, 디스플레이 장치, 터치 스크린 등으로부터 선택된 적어도 하나 이상을 포함할 수 있다. 메모리(713)는 데이터 저장을 위한 장치로, 데이터 또는/및 컨트롤러(711) 등에 의해 실행된 커멘드(command)를 저장할 수 있다. For example, the controller 711 may include at least one microprocessor, at least one digital signal processor, at least one microcontroller, and at least one of a logic circuit capable of performing the same function as these components. The memory 713 may include at least one or more of the semiconductor packages according to embodiments of the present invention. The input/output unit 712 may include at least one selected from a keypad, a keyboard, a display device, and a touch screen. The memory 713 is a device for storing data, and may store data or/and a command executed by the controller 711 or the like.

메모리(713)는 DRAM과 같은 휘발성 메모리 장치 또는/및 플래시 메모리와 같은 비휘발성 메모리 장치를 포함할 수 있다. 예컨데, 플래시 메모리는 이동 단말기 또는 데스크 탑 컴퓨터와 같은 정보 처리 시스템에 장착될 수 있다. 플래시 메모리는 SSD(Solid State Disk)로 구성될 수 있다. 이 경우, 전자 시스템(710)은 플래시 메모리 시스템에 많은 양의 데이터를 안정적으로 저장할 수 있다. The memory 713 may include a volatile memory device such as DRAM or/and a nonvolatile memory device such as flash memory. For example, the flash memory can be mounted in an information processing system such as a mobile terminal or a desktop computer. The flash memory may be composed of a solid state disk (SSD). In this case, the electronic system 710 may stably store a large amount of data in the flash memory system.

전자 시스템(710)은 통신망과 데이터를 송수신할 수 있도록 설정된 인터페이스(714)를 더 포함할 수 있다. 인터페이스(714)는 유선 또는 무선 형태를 가질 수 있다. 예컨데, 인터페이스(714)는 인테나, 유선 트랜시버(transceiver) 또는 무선 트랜시버를 포함할 수 있다. The electronic system 710 may further include an interface 714 configured to transmit and receive data to and from a communication network. The interface 714 may have a wired or wireless form. For example, the interface 714 may include an antenna, a wired transceiver, or a wireless transceiver.

전자 시스템(710)은 모바일 시스템, 퍼스널 컴퓨터, 산업용 컴퓨터 또는 다양한 기능들을 수행하는 로직 시스템으로 이해될 수 있다. 예컨데, 모바일 시스템은 PDA(Personal Digital Assistant), 포터블 컴퓨터(portable computer), 테블릿 컴퓨터(tablet computer), 모바일 폰(mobile phone), 스마트 폰(smart phone), 무선 전화, 랩탑 컴퓨터(laptop computer), 메모리 카드(memory card), 디지털 음악 시스템, 정보 송수신 시스템 중 어느 하나일 수 있다.The electronic system 710 may be understood as a mobile system, a personal computer, an industrial computer, or a logic system that performs various functions. For example, the mobile system is a PDA (Personal Digital Assistant), a portable computer, a tablet computer, a mobile phone, a smart phone, a wireless phone, a laptop computer. , A memory card, a digital music system, and an information transmission/reception system.

전자 시스템(710)이 무선 통신을 수행할 수 있는 장치인 경우, 전자 시스템(710)은 CDMA(Code Division Multiple access), GSM(global system for mobile communications), NADC(north American digital cellular), E-TDMA(enhanced-time division multiple access), WCDAM(wideband code division multiple access), CDMA2000, LTE(long term evolution) and Wibro(wireless broadband Internet)와 같은 통신 시스템에 사용될 수 있다. When the electronic system 710 is a device capable of performing wireless communication, the electronic system 710 is a code division multiple access (CDMA), global system for mobile communications (GSM), north American digital cellular (NADC), E- It can be used in communication systems such as enhanced-time division multiple access (TDMA), wideband code division multiple access (WCDAM), CDMA2000, long term evolution (LTE), and wireless broadband Internet (Wibro).

도 8을 참조하면, 본 발명의 실시예들에 따른 반도체 패키지는 메모리 카드(800)의 형태로 제공될 수 있다. 예컨데, 메모리 카드(800)는 비휘발성 메모리 장치와 같은 메모리(810) 및 메모리 컨트롤러(820)를 포함할 수 있다. 메모리(810) 및 메모리 컨트롤러(820)은 데이터를 저장하거나 저장된 데이터를 독출할 수 있다.Referring to FIG. 8, a semiconductor package according to embodiments of the present invention may be provided in the form of a memory card 800. For example, the memory card 800 may include a memory 810 and a memory controller 820 such as a nonvolatile memory device. The memory 810 and the memory controller 820 may store data or read stored data.

메모리(810)는 본 발명의 실시예들에 따른 반도체 패키지가 적용된 비휘발성 메모리 장치들 중 어느 하나 이상을 포함할 수 있고, 메모리 컨트롤러(820)는 호스트(830)로부터의 기입/독출 요청에 응답하여 저장된 데이터를 독출해내거나 데이터를 저장하도록 메모리(810)를 컨트롤한다.The memory 810 may include any one or more of nonvolatile memory devices to which a semiconductor package according to embodiments of the present invention is applied, and the memory controller 820 responds to a write/read request from the host 830 Thus, the memory 810 is controlled to read out the stored data or to store the data.

앞서 설명한 본 발명의 상세한 설명에서는 본 발명의 실시예를 참조하여 설명하였지만, 해당 기술분야의 숙련된 당업자 또는 해당 기술분야에 통상의 지식을 갖는 자라면 후술 될 특허청구범위에 기재된 본 발명의 사상 및 기술 영역으로부터 벗어나지 않는 범위 내에서 본 발명을 다양하게 수정 및 변경시킬 수 있음을 이해할 수 있을 것이다.In the detailed description of the present invention described above, it has been described with reference to embodiments of the present invention, but those skilled in the art or those of ordinary skill in the relevant technical field have the spirit and spirit of the present invention described in the claims to be described later. It will be appreciated that various modifications and changes can be made to the present invention without departing from the technical field.

10: 기판
20,22,50.52: 제1 내지 제4 반도체 칩
30, 60: 제1,제2 관통 전극
500, 510: 제1,제2 입출력 회로10: substrate
20,22,50.52: first to fourth semiconductor chips
30, 60: first and second through electrodes
500, 510: first and second input/output circuits

Claims (16)

상호 스택되며, 각각 제1 데이터 입출력 패드를 구비하며 각각의 하부면에 제1 데이터 입출력 회로가 연결된 제1 노멀 패드 및 상기 제1 데이터 입출력 회로가 연결되지 않은 제1 더미 패드를 구비하는 제1,제2 반도체 칩;
상기 제1 반도체 칩을 관통하여 상기 제1 반도체 칩의 상기 제1 더미 패드와 상기 제2 반도체 칩의 상기 제1 노멀 패드를 전기적으로 연결하는 제1 관통 전극;및
상기 제1 반도체 칩의 하부면을 지지하며 상기 제1 반도체 칩의 상기 제1 노멀 패드 및 상기 제1 더미 패드에 각각 전기적으로 연결된 제1 접속 패드들을 갖는 기판;을 포함하며,
상기 제2 반도체 칩의 상기 제1 노멀 패드, 상기 제1 관통 전극 및 상기 제1 반도체 칩의 상기 제1 더미 패드는 상기 제2 반도체 칩의 상기 제1 데이터 입출력 회로와 상기 제1 접속 패드들의 하나를 연결하는 제1 데이터 입출력 경로를 구성하고,
상기 제1 반도체 칩의 제1 노멀 패드는 상기 제1 반도체 칩의 상기 제1 데이터 입출력 회로와 상기 제1 접속 패드들의 다른 하나를 연결하는 제2 데이터 입출력 경로를 구성하는 것을 특징으로 하는 반도체 패키지.A first normal pad stacked with each other, each having a first data input/output pad and having a first data input/output circuit connected to each lower surface thereof, and a first dummy pad to which the first data input/output circuit is not connected, A second semiconductor chip;
A first through electrode penetrating the first semiconductor chip and electrically connecting the first dummy pad of the first semiconductor chip and the first normal pad of the second semiconductor chip; and
A substrate supporting a lower surface of the first semiconductor chip and having first connection pads electrically connected to the first normal pad and the first dummy pad of the first semiconductor chip, respectively, and
The first normal pad of the second semiconductor chip, the first through electrode, and the first dummy pad of the first semiconductor chip are one of the first data input/output circuit and the first connection pads of the second semiconductor chip Configure a first data input/output path connecting
Wherein the first normal pad of the first semiconductor chip constitutes a second data input/output path connecting the first data input/output circuit of the first semiconductor chip and the other one of the first connection pads. 제1 항에 있어서, 상기 제1,제2 반도체 칩은 각각 웨이퍼 기판;및
상기 웨이퍼 기판상에 형성되며 상기 하부면 및 상기 제1 데이터 입출력 회로를 제공하는 액티브층;을 포함하는 반도체 패키지.The semiconductor device of claim 1, wherein each of the first and second semiconductor chips comprises a wafer substrate; and
And an active layer formed on the wafer substrate and providing the lower surface and the first data input/output circuit. 제2 항에 있어서, 상기 제1 관통 전극은 상기 제1 반도체 칩의 상기 웨이퍼 기판을 관통하는 전도성 필라; 및
상기 제1 반도체 칩의 상기 액티브층에 형성되며 상기 전도성 필라와 상기 제1 반도체 칩의 상기 제1 더미 패드를 전기적으로 연결하는 회로 패턴;을 포함하는 반도체 패키지.The semiconductor device of claim 2, wherein the first through electrode comprises: a conductive pillar penetrating the wafer substrate of the first semiconductor chip; And
And a circuit pattern formed on the active layer of the first semiconductor chip and electrically connecting the conductive pillar and the first dummy pad of the first semiconductor chip. 제3 항에 있어서, 상기 전도성 필라는 상기 제1 반도체 칩의 상기 제1 노멀 패드와 동일 선상에 형성된 반도체 패키지. The semiconductor package of claim 3, wherein the conductive pillar is formed on the same line as the first normal pad of the first semiconductor chip. 제4 항에 있어서, 상기 제2 반도체 칩은 자신의 상기 제1 노멀 패드가 상기 제1 반도체 칩의 상기 제1 노멀 패드와 동일선상에 배치되도록 상기 제1 반도체 칩 상에 수직하게 스택된 반도체 패키지.The semiconductor package of claim 4, wherein the second semiconductor chip is vertically stacked on the first semiconductor chip such that its first normal pad is disposed on the same line with the first normal pad of the first semiconductor chip. . 제3 항에 있어서, 상기 전도성 필라는 상기 제1 반도체 칩의 상기 제1 더미 패드와 동일 선상에 형성된 반도체 패키지. The semiconductor package of claim 3, wherein the conductive pillar is formed on the same line as the first dummy pad of the first semiconductor chip. 제6 항에 있어서, 상기 제2 반도체 칩은 자신의 상기 제1 노멀 패드가 상기 제1 반도체 칩의 제1 더미 패드와 동일선상에 배치되도록 상기 제1 반도체 칩과 어긋나게 스택된 반도체 패키지.The semiconductor package of claim 6, wherein the second semiconductor chip is stacked to shift from the first semiconductor chip such that its first normal pad is disposed on the same line as the first dummy pad of the first semiconductor chip. 제2 항에 있어서, 상기 제1 관통 전극은 상기 제1 반도체 칩의 상기 제1 더미 패드와 동일선 상에서 상기 웨이퍼 기판 및 상기 액티브층을 관통하여 상기 제1 반도체 칩의 상기 제1 더미 패드에 접속된 전도성 필라를 포함하는 반도체 패키지. The method of claim 2, wherein the first through electrode is connected to the first dummy pad of the first semiconductor chip through the wafer substrate and the active layer on the same line as the first dummy pad of the first semiconductor chip. A semiconductor package including a conductive pillar. 제1항에 있어서, 상기 제1,제2 반도체 칩의 개재하에 상기 기판상에 스택되며, 각각의 하부면에 제2 데이터 입출력 회로가 연결된 제2 노멀 패드 및 상기 제2 데이터 입출력 회로가 연결되지 않은 제2 더미 패드를 구비하는 제3,제4 반도체 칩;
상기 제3 반도체 칩을 관통하여 상기 제3 반도체 칩의 제2 더미 패드와 상기 제4 반도체 칩의 상기 제2 노멀 패드를 전기적으로 연결하는 제2 관통 전극;을 더 포함하고,
상기 기판은 상기 제3 반도체 칩의 상기 제2 노멀 패드 및 상기 제2 더미 패드에 각각 전기적으로 연결된 제2 접속 패드들을 더 포함하며,
상기 제4 반도체 칩의 상기 제2 노멀 패드, 상기 제2 관통 전극 및 상기 제3 반도체 칩의 상기 제2 더미 패드는 상기 제4 반도체 칩의 상기 제2 데이터 입출력 회로와 상기 제2 접속 패드들의 하나를 연결하는 제3 데이터 입출력 경로를 구성하고,
상기 제3 반도체 칩의 제2 노멀 패드는 상기 제3 반도체 칩의 상기 제2 데이터 입출력 회로와 상기 제2 접속 패드들의 다른 하나를 연결하는 제4 데이터 입출력 경로를 구성하는 것을 특징으로 하는 반도체 패키지.The method of claim 1, wherein the second normal pad and the second data input/output circuit are stacked on the substrate with the first and second semiconductor chips interposed therebetween, and the second data input/output circuit is connected to each lower surface. Third and fourth semiconductor chips having second dummy pads that are not;
A second through electrode penetrating the third semiconductor chip and electrically connecting the second dummy pad of the third semiconductor chip and the second normal pad of the fourth semiconductor chip; and
The substrate further includes second connection pads electrically connected to each of the second normal pad and the second dummy pad of the third semiconductor chip,
The second normal pad of the fourth semiconductor chip, the second through electrode, and the second dummy pad of the third semiconductor chip are one of the second data input/output circuit and the second connection pads of the fourth semiconductor chip Configure a third data input/output path to connect,
And a second normal pad of the third semiconductor chip constitutes a fourth data input/output path connecting the second data input/output circuit of the third semiconductor chip and the other one of the second connection pads. 제9 항에 있어서, 상기 제3,제4 반도체 칩은 각각 상기 하부면 및 상기 제2 데이터 입출력 회로를 제공하는 액티브층;및
상기 액티브층 상에 형성된 웨이퍼 기판;을 포함하는 반도체 패키지.The semiconductor device of claim 9, wherein the third and fourth semiconductor chips include an active layer providing the lower surface and the second data input/output circuit, respectively; And
A semiconductor package including a wafer substrate formed on the active layer. 제10 항에 있어서, 상기 제2 관통 전극은 상기 제3 반도체 칩의 상기 웨이퍼 기판을 관통하는 전도성 필라; 및
상기 제3 반도체 칩의 상기 액티브층에 형성되며 전도성 필라와 상기 제3 반도체 칩의 상기 제2 더미 패드를 전기적으로 연결하는 회로 패턴;을 포함하는 반도체 패키지.11. The display device of claim 10, wherein the second through electrode comprises: a conductive pillar penetrating the wafer substrate of the third semiconductor chip; And
And a circuit pattern formed on the active layer of the third semiconductor chip and electrically connecting a conductive pillar and the second dummy pad of the third semiconductor chip. 제11 항에 있어서, 상기 전도성 필라는 상기 제3 반도체 칩의 상기 제2 노멀 패드와 동일 선상에 형성된 반도체 패키지. The semiconductor package of claim 11, wherein the conductive pillar is formed on the same line as the second normal pad of the third semiconductor chip. 제12 항에 있어서, 상기 제4 반도체 칩은 자신의 상기 제2 노멀 패드가 상기 제3 반도체 칩의 제2 노멀 패드와 동일선상에 배치되도록 상기 제4 반도체 칩 상에 수직하게 스택된 반도체 패키지.The semiconductor package of claim 12, wherein the fourth semiconductor chip is vertically stacked on the fourth semiconductor chip such that its second normal pad is disposed on the same line as the second normal pad of the third semiconductor chip. 제11 항에 있어서, 상기 전도성 필라는 상기 제3 반도체 칩의 상기 제2 더미 패드와 동일 선상에 형성된 반도체 패키지. The semiconductor package of claim 11, wherein the conductive pillar is formed on the same line as the second dummy pad of the third semiconductor chip. 제14 항에 있어서, 상기 제4 반도체 칩은 자신의 상기 제2 노멀 패드가 상기 제3 반도체 칩의 제2 더미 패드와 동일선상에 배치되도록 상기 제3 반도체 칩과 어긋나게 스택된 반도체 패키지.The semiconductor package of claim 14, wherein the fourth semiconductor chip is stacked so that its second normal pad is disposed on the same line as the second dummy pad of the third semiconductor chip. 제10 항에 있어서, 상기 제2 관통 전극은 상기 제3 반도체 칩의 상기 제2 더미 패드와 동일선 상에서 상기 웨이퍼 기판 및 상기 액티브층을 관통하여 상기 제3 반도체 칩의 상기 제2 더미 패드에 접속된 전도성 필라를 포함하는 반도체 패키지. The method of claim 10, wherein the second through electrode is connected to the second dummy pad of the third semiconductor chip through the wafer substrate and the active layer on the same line as the second dummy pad of the third semiconductor chip. A semiconductor package including a conductive pillar.
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