KR102168175B1 - Re-configurable processor, method and apparatus for optimizing use of configuration memory thereof - Google Patents

Abstract

A method and apparatus for optimizing the use of the configuration memory of a reconfigurable processor is provided by analyzing the parallelism of a loop in the program code, and scheduling groups of functional units to be activated in each cycle of the loop according to the analyzed parallelism. It generates configuration data for a cycle and maps the generated configuration data for groups scheduled in adjacent cycles to a configuration memory.

Description

Reconfigurable processor, method and apparatus for optimizing the use of configuration memory of the reconfigurable processor TECHNICAL FIELD OF THE INVENTION

A reconfigurable processor, and a method and apparatus for optimizing the use of configuration memory of the reconfigurable processor.

The re-configurable architecture refers to an architecture capable of changing a hardware configuration of a computing device to be optimized to a work situation of a specific task in order to perform a specific task.

If a specific task is processed only with fixed hardware of a computing device, if there is a slight change in work contents of a specific task, it is difficult to efficiently process the changed work contents due to fixed functions of the fixed hardware. On the other hand, if a specific task is processed only with software, the operation of the software can be changed to suit the changed work contents in a specific task, but the processing speed may be slower than using hardware.

The reconfigurable architecture can be implemented to satisfy both the usability when using hardware and the usability when using software. In particular, in the field of digital signal processing (DSP) in which the same specific task is repeatedly performed, such a reconfigurable architecture is attracting much attention.

There are several types of reconfigurable architectures, of which the Coarse-Grained Array (CGA) is a representative. Meanwhile, recently, a reconfigurable architecture has emerged that can utilize part of a coarse grain array as a very long instruction word (VLIW) machine.

This reconfigurable architecture can have two execution modes: CGA mode and VLIW mode. In general, a reconfigurable architecture having a CGA mode and a VLIW mode can be implemented to handle a loop operation in the CGA mode and a general operation in addition to the loop operation in the VLIW mode.

It is to provide a reconfigurable processor, a method and apparatus for optimizing the use of configuration memory of a reconfigurable processor. Further, it is to provide a computer-readable recording medium in which a program for executing the method on a computer is recorded. The technical problem to be solved by this embodiment is not limited to the technical problems as described above, and other technical problems may exist.

According to an aspect, a method of optimizing the use of a configuration memory of a reconfigurable processor includes: analyzing a parallelism of a loop in a program code based on an architecture of a reconfigurable processor and a specification of the configuration memory; Generating configuration data for each cycle by scheduling groups of functional units to be activated in each cycle of the loop according to the analyzed parallelism; And sequentially mapping the generated configuration data for the scheduled groups in adjacent cycles to at least one row of the configuration memory.

In addition, the generating step generates the configuration data by scheduling the functional units of the same type to be activated in each cycle.

In addition, in the generating step, the configuration data is generated by scheduling some of the entire functional units included in the reconfigurable processor to be repeatedly activated every the cycle.

In addition, in the mapping step, the generated configuration data is mapped to the configuration memory using regular encoding.

In the mapping step, the configuration data corresponding to each of the groups is mapped by dividing fields of the configuration memory into equal sizes.

In addition, the analyzing may include the parallelism based on information on the number of functional units included in the reconfigurable processor, a connection relationship between the functional units, and a multiplexing relationship between the functional units and the configuration memory. Analyze.

Also, determining whether regular encoding of the configuration data is possible based on the architecture and specifications of the configuration memory; And when the regular encoding is possible, determining whether the groups are the same in the adjacent cycles, and the mapping step further comprises determining whether the regular encoding is possible and the groups are the same, the adjacent The generated configuration data for each of the cycles is mapped to the configuration memory.

According to another aspect, there is provided a computer-readable recording medium storing a program for executing a method for optimizing use of the configuration memory of the reconfigurable processor in a computer.

According to another aspect, an apparatus for optimizing use of a configuration memory of a reconfigurable processor includes an analysis unit that analyzes parallelism of a loop of a program code based on an architecture of a reconfigurable processor and a specification of the configuration memory. ; A scheduling unit generating configuration data for each cycle by scheduling groups of functional units to be activated in every cycle of the loop according to the analyzed parallelism; And a determination unit sequentially mapping the generated configuration data for the scheduled groups in adjacent cycles to at least one row of the configuration memory.

In addition, the scheduling unit generates the configuration data by scheduling the functional units of the same type to be activated in each cycle.

In addition, the scheduling unit generates the configuration data by scheduling some of all functional units included in the reconfigurable processor to be repeatedly activated every the cycle.

Also, the determination unit maps the generated configuration data to the configuration memory using regular encoding.

Further, the determination unit maps the configuration data corresponding to each of the groups by dividing the fields of the configuration memory into equal sizes.

In addition, the analysis unit analyzes the parallelism based on information on the number of functional units included in the reconfigurable processor, a connection relationship between the functional units, and a multiplexing relationship between the functional units and the configuration memory. .

In addition, the determination unit determines whether regular encoding of the configuration data is possible based on the architecture and specifications of the configuration memory, and if the regular encoding is possible, the groups are included in the adjacent cycles. It is determined whether or not they are the same, and when the determination result is that the regular encoding is possible and the groups are the same, the generated configuration data for each of the adjacent cycles is mapped to the configuration memory.

As described above, based on the architecture of a re-configurable processor, by compiling a schedule of functional units optimized for a given loop, various memory mapping schemes for a configuration memory are flexible ( flexible) and more efficient use of the memory space of the configuration memory.

1 is a configuration diagram of computing devices 10 and 20 according to an embodiment of the present invention.
2 is a detailed configuration diagram of a compiler 200 according to an embodiment of the present invention.
3 is a diagram for explaining a basic concept for optimizing the use of the configuration memory 130 according to an embodiment of the present invention.
4 is a flowchart of a method of optimizing the use of configuration memory of the reconfigurable processor 100 according to an embodiment of the present invention.
5 is a diagram illustrating configuration data generated by the scheduling unit 220 of the compiler 200 according to an embodiment of the present invention.
6 is a flowchart illustrating a process of determining a memory mapping method by the determiner 230 of the compiler 200 according to an embodiment of the present invention.
7 is a diagram for describing a first memory mapping method according to an embodiment of the present invention.
FIG. 8 is a diagram for describing an architecture of a reconfigurable processor 100 for applying a first memory mapping method according to an embodiment of the present invention.
9 is a diagram for explaining a second memory mapping method for a 4x1 CGRA mode according to an embodiment of the present invention.
10 is a diagram for explaining a second memory mapping method for a 2x1 CGRA mode according to an embodiment of the present invention.
11 is a diagram for describing a third memory mapping method according to an embodiment of the present invention.
12 is a diagram for describing a fourth memory mapping method according to an embodiment of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the drawings.

1 is a configuration diagram of computing devices 10 and 20 according to an embodiment of the present invention.

Referring to FIG. 1, the computing device 10 includes a re-configurable processor 100, and the reconfigurable processor 100 includes a plurality of function units (FUs) 113 and It includes a processor core 110 with register files, a main memory 120 and a configuration memory 130.

The computing device 20 includes a compiler 200.

Meanwhile, for the computing devices 10 and 20 illustrated in FIG. 1, only components related to the present embodiment are shown in order to prevent the features of the present embodiment from being blurred. Therefore, it can be understood by those of ordinary skill in the art related to the present embodiment that other general-purpose components may be further included in addition to the components shown in FIG. 1.

2 is a detailed configuration diagram of a compiler 200 according to an embodiment of the present invention.

Referring to FIG. 2, the compiler 200 includes an analysis unit 210, a scheduling unit 220, and a determination unit 230. However, with respect to the compiler 200 shown in FIG. 2, only components related to the present embodiment are shown in order to prevent the features of the present embodiment from being blurred. Therefore, it can be understood by those of ordinary skill in the art related to the present embodiment that other general-purpose components may be further included in addition to the components shown in FIG. 2.

Hereinafter, operations and functions of the computing devices 10 and 20 will be described in conjunction with FIGS. 1 and 2.

The reconfigurable processor 100 refers to hardware that can be reconfigured to optimize the operation of the processor core 110 in order to perform a specific task, instruction, or operation. Here, the configuration of the functional units 113 that perform processing in the reconfigurable processor 100 may be determined by compilation by the compiler 200.

The processor core 110 includes an array of a plurality of functional units 113. The functional units 113 of the processor core 110 may correspond to an arithmetic logic unit (ALU), a multiplier, or a load/store unit, and the like, and functional units ( 113) A number of input/output paths may be provided. Further, the processor core 110 may include various types of register files such as a local register file.

The processor core 110 may support a coarse grained re-configurable array (CGRA) mode or a very long instruction word (VLIW) mode. For example, the processor core 110 may be hardware supporting only CGRA mode, hardware supporting only VLIW mode, or hardware supporting both CGRA mode and VLIW mode. That is, the processor core 110 may support only one mode or various modes.

The processor core 110 may process a loop operation in parallel using various functional units 113 included in the processor core 110 according to the CGRA mode. That is, when the processor core 110 is operated according to the CGRA mode, the processor core 110 may execute Loop Level Parallelism (LLP).

The processor core 110 may process a general serial operation rather than a loop operation using some of the functional units 113 included in the processor core 110 according to the VLIW mode. However, the processor core 110 may be capable of performing a simple or low repetition number of loop operations under the VLIW mode. That is, when the processor core 110 is operated according to the VLIW mode, the processor core 110 may execute Instruction Level Parallelism (ILP).

The main memory 120 is hardware that stores configuration data and other data transmitted from the compiler 200, and may be implemented as a dynamic random access memory (DRAM), but is not limited thereto.

The configuration data is data including the operation code (OP code) of the functional units 113 of the processor core 110 or connection information between the functional units 113 scheduled (compiled) by the compiler 200 , Including information on a processing schedule of overall operations to be performed by the reconfigurable processor 100.

The configuration memory 130 is hardware that loads and stores configuration data from the main memory 120, and may be implemented as a static random access memory (SRAM), which is faster than DRAM, but is not limited thereto.

The compiler 200 converts the given program code into a low-level language. For example, the compiler 200 converts a program code written in a high-level language into an assembly language or a machine language. The compiler 200 schedules the operation of the functional units 113 by using instructions of the converted assembly language or machine language language. The compiler 200 may use information stored in a memory (not shown) of the computing device 20 to compile the created program code.

The computing device 20 includes information on given program code information, the architecture of the reconfigurable processor 100 to execute the program code, specifications of the functional units 113, and interconnections between the functional units 113. ), information on the specifications of the configuration memory 130, the number of register files, the connection relationship between the functional units 113 and the register file, and the like may be stored in advance.

As described above, the compiler 200 may schedule a non-loop operation to be processed in the VLIW mode of the reconfigurable processor 100, and schedule a loop-in operation to be processed in the CGRA mode of the reconfigurable processor 100. .

Meanwhile, the computing devices 10 and 20 may correspond to separate and independent devices, or may be implemented as separate modules in one device. For example, the computing device 20 is a personal computer (PC) that compiles program code including a loop, and the actually compiled instructions are reconfiguration of another computing device 10 such as a smartphone or a tablet device. It may be executed by the capable processor 100.

And, the computing devices 10 and 20 are Personal computer (PC), Server computer, Smart phone, PDA, PMP, Navigation, TV, content playback device, Communication system, Image processing system, Graphics processing system, laptop, tablet PC It may be implemented as or included therein.

3 is a diagram for explaining a basic concept for optimizing the use of the configuration memory 130 according to an embodiment of the present invention.

Referring to FIG. 3, compared to a case 310 compiled so that all 16 functional units 113 are activated in the reconfigurable processor 100, when the four functional units 113 are compiled to be activated At 320, the usage of the configuration memory 130 may be reduced. For example, when comparing the two cases 310 and 320, there may be a difference in data size of the connection relationship between the functional units 113.

In the case where the four functional units 113 are compiled to be activated (320), since only some of the 16 functional units 113 are activated, when the 16 functional units 113 are compiled to be activated, (310) can handle longer schedules. That is, in the case of software pipelining, for example, when the four functional units 113 are compiled to be activated (320), the initiation interval (II) of the loop operation may be increased.

Accordingly, the compiler 200 according to the present embodiment can optimize the use of the configuration memory 130 by scheduling so that only some of the functional units 113 included in the processor core 110 are activated and processed. .

4 is a flowchart of a method of optimizing the use of configuration memory of the reconfigurable processor 100 according to an embodiment of the present invention. Referring to FIG. 4, the method for optimizing the use of the configuration memory 130 of the reconfigurable processor 100 according to the present embodiment is processed in a time series by the computing devices 10 and 20 described in FIGS. 1 and 2. It's a process. Therefore, even if omitted below, the descriptions of the computing devices 10 and 20 may also be applied to a method of optimizing the use of the configuration memory 130 of the reconfigurable processor 100 according to the present embodiment.

In step 410, the analysis unit 210 of the compiler 200 determines the parallelism of the loops of the given program code based on the architecture of the reconfigurable processor 100 and the specifications of the configuration memory 130. Analyze.

The architecture of the reconfigurable processor 100 includes the number of functional units 113 included in the reconfigurable processor 100, the connection relationship between the functional units 113, the multiplexing between the functional units 113 and the configuration memory ( It contains information about multiplexing) relationships.

In particular, the analysis unit 210 is based on the architecture of the reconfigurable processor 100 and the specifications of the configuration memory 130, such as instruction level parallelism (ILP) or data level parallelism (DLP) of a loop of a given program code. By analyzing the parallelism, it is possible to determine the number of functional units 113 required in each cycle of the loop.

In step 420, the scheduling unit 220 of the compiler 200 generates configuration data for each cycle by scheduling groups of functional units 113 to be activated in every cycle of the loop according to the analyzed parallelism.

Here, the configuration data is data about an operation code (OP code) of the functional units 113, connection information between the functional units 113, and the like. Meanwhile, the configuration data generated by the scheduling unit 220 will be described in more detail in FIG. 5 below.

In step 430, the determination unit 230 of the compiler 200 determines a memory mapping method for storing the generated configuration data in the regions of the configuration memory 130 based on the scheduling result.

Here, the memory mapping method determined by the determination unit 230 may be a method for storing the configuration data to be processed in at least one or more cycles in at least one row of the configuration memory 130. For example, the determiner 230 may determine a memory mapping method such that configuration data to be processed in one cycle is stored in each of all rows of the configuration memory 130. Alternatively, the determiner 230 may determine a memory mapping method such that configuration data to be processed in at least two cycles are stored in each of all rows of the configuration memory 130. Furthermore, the determination unit 230 may determine a memory mapping method such that configuration data to be processed in one cycle is stored in each of some rows of the configuration memory 130 and configuration data to be processed in two or more cycles are stored in each of the remaining rows. have. That is, the memory mapping method determined by the determination unit 230 is not limited to any one case.

In particular, when some of the entire functional units 113 included in the reconfigurable processor 100 are activated in adjacent cycles of the loop, the determiner 230 may determine any one memory mapping method.

According to the present embodiment, the determination unit 230 determines any one of the first memory mapping method to the fourth memory mapping method for each cycle in order to store the configuration data for each cycle in the configuration memory 130 do.

5 is a diagram illustrating configuration data generated by the scheduling unit 220 of the compiler 200 according to an embodiment of the present invention.

As a result of the scheduling, the scheduling unit 220 generates configuration data bits to be processed in each of the groups of the functional units 113 scheduled in every cycle.

For example, in the configuration data bits for the functional units 113 of group A, bits of the operation code (OP code), intraconnections related to the interconnections of the functional units 113 of group A Bits for intra group connections, dedicated register bits for a dedicated register file for group A, and connection relations between group A and functional units 113 of other groups Bits related to inter group connections may be included, but are not limited thereto.

In addition, among all the configuration data bits generated by the scheduling unit 220, the last bits may include globally shared bits regarding a global register file shared by a plurality of groups.

In order to apply the memory mapping method according to the present embodiment, the scheduling unit 220 reconstructs the configuration data so that the bits of the global register file are included in the configuration data for each of the configuration data bits as described above. (reorganize).

Hereinafter, a process of determining a memory mapping method and types of memory mapping methods will be described in more detail.

6 is a flowchart illustrating a process of determining a memory mapping method by the determiner 230 of the compiler 200 according to an embodiment of the present invention.

In step 610, the determination unit 230 determines whether regular encoding of the configuration data is possible based on the architecture of the reconfigurable processor 100 and the specifications of the configuration memory 130.

In step 620, when it is determined that regular encoding is possible in step 610, the determination unit 230 determines whether groups of the functional units 113 scheduled in adjacent cycles of the loop are the same based on the scheduling result. .

In step 630, based on the architecture of the reconfigurable processor 100 and the specifications of the configuration memory 130, the determination unit 230 determines whether buffering by the buffers provided in the functional units 113 is available. Judge.

In step 640, if buffering is not available, the determination unit 230 determines a first memory mapping method.

In step 650, when buffering is available, the determination unit 230 determines a first memory mapping method and a fourth memory mapping method together.

In step 660, when it is determined that the groups of the functional units 113 scheduled in step 620 are not the same, the determination unit 230 determines a second memory mapping method.

In step 670, if it is determined in step 610 that regular encoding is not possible, the determination unit 230 determines whether buffering by buffers provided in the functional units 113 can be used.

In step 680, if it is determined that buffering is not available in step 670, the determination unit 230 determines a third memory mapping method.

In step 690, if it is determined in step 670 that buffering is available, the determination unit 230 determines a third memory mapping method and a fourth memory mapping method together.

7 is a diagram for describing a first memory mapping method according to an embodiment of the present invention.

Referring to FIG. 7, the first memory mapping method is a memory mapping method determined in operation 640 or 650 of FIG. 6.

When one group of scheduled functional units 113 corresponds to the 4x2 CGRA 710, the configuration data of cycle 0 for the functional unit 1 (FU1) to the functional unit 8 (FU8) is Each of the eight fields may be evenly mapped. That is, the configuration data of cycle 0 may be mapped to eight fields of the configuration memory 130 through regular encoding in the same encoding format.

However, if there are 8 fields of the configuration memory 130, the memory mapping method for the 4x2 CGRA 710 is a configuration for one cycle (cycle 0) in one row of the configuration memory 130. Data can only be mapped.

However, when one group of the scheduled functional units 113 corresponds to the 4x1 CGRA 720 and the 2x1 CGRA 730, processing in one row of the configuration memory 130 in at least two cycles The configuration data to be made can be mapped. However, according to another embodiment, configuration data to be processed in one cycle may be mapped to one row of the configuration memory 130.

When one group of the scheduled functional units 113 corresponds to the 4x1 CGRA 720, the configuration data of cycle 0 for the functional unit 1 (FU1) to the functional unit 4 (FU4) is Each of the first four fields can be evenly mapped. Also, the configuration data of cycle 1 for the functional unit 1 (FU1) to the functional unit 4 (FU4) may be equally mapped to the remaining four fields of the configuration memory 130, respectively.

If one group of the scheduled functional units 113 corresponds to the 2x1 CGRA 730, the configuration data of cycle 0 for the functional unit 1 (FU1) and the functional unit 2 (FU2) is the configuration data of the configuration memory 130. The first two fields are mapped evenly, respectively, the configuration data of cycle 1 is mapped evenly to the next two fields of the configuration memory 130, and the configuration data of cycle 2 is mapped to the next of the configuration memory 130. Each of the two fields is evenly mapped, and the configuration data of cycle 3 may be evenly mapped to the last two fields of the configuration memory 130, respectively.

Accordingly, according to the first memory mapping method, as a result of the scheduling of the scheduling unit 220 for the CGRA mode, when only some of the functional units 113 are activated in the CGRA mode, one row of the configuration memory 130 is , Since the configuration data to be processed in at least one or more cycles may be mapped together, the use of the configuration memory 130 may be optimized.

FIG. 8 is a diagram for describing an architecture of a reconfigurable processor 100 for applying a first memory mapping method according to an embodiment of the present invention.

The first memory mapping method may be applied to an architecture such as the configuration memory 810, multiplexers 820, and functional units 830 illustrated in FIG. 8. That is, if only one group of functional units 113 is scheduled to be repeatedly activated, according to the multiplexing relationship between the configuration memory 810 and the functional units 830 by the multiplexers 820, the functional unit The s 830 are architectures capable of loading configuration data from several columns existing in one row of the configuration memory 810 at the same time, and thus a first memory mapping method may be applied.

9 is a diagram for explaining a second memory mapping method for a 4x1 CGRA mode according to an embodiment of the present invention.

Referring to FIG. 9, the second memory mapping method is the memory mapping method determined in step 660 of FIG. 6. The second memory mapping method may be applied when the groups (4x1 CGRA) of different functional units 113 are scheduled to be activated by interleaving.

According to the second memory mapping method, a flag bit for identifying a current cycle is inserted between configuration data for each cycle to be mapped to the configuration memory 810. For example, S in FIG. 9 is a stop bit, and the stop bit S is a bit for identifying that the immediately preceding field and the immediately following field are configuration data for different cycles. In addition, C of 9 is a continuation bit, and the continuation bit C is a bit that identifies that the immediately preceding field and the immediately following field are configuration data for the same cycle.

That is, when one row of the configuration memory 810 is loaded into the functional units 113, the functional units 113 may identify and process configuration data in each cycle through a flag bit.

In cycle 0 910, functional units 113 may be scheduled such that functional units 1 to 4 are activated. And, in cycle 1 920, the functional units 113 may be scheduled so that the functional units 5 to 8 are activated. Also, in cycle 2 930, the functional units 113 may be scheduled so that the functional units 1 to 4 are activated again.

The configuration data for cycle 0 910 may be mapped to the first four fields in one row of configuration memory 130. That is, the scheduling unit 220 inserts the contour view bit into the last bit of the second field (or the first bit of the third field) of the configuration memory 130, and the last bit of the fourth field (or the fifth field) By inserting a stop bit in the first bit), configuration data can be generated.

The configuration data for cycle 1 920 may be mapped to the following four fields in one row of configuration memory 130. That is, the scheduling unit 220 inserts the continuation bit into the last bit of the 6th field (or the first bit of the 7th field) of the configuration memory 130, and inserts the stop bit into the last bit of the 8th field. , Can generate configuration data.

Meanwhile, the configuration data for the cycle 2 930 may also be mapped to the configuration memory 130 in a manner similar to the configuration data for the cycle 0 910 or the cycle 1 920.

That is, when the groups of different functional units 113 are scheduled to be activated by interleaving, the determination unit 230 may determine the second memory mapping method as described above.

10 is a diagram for explaining a second memory mapping method for a 2x1 CGRA mode according to an embodiment of the present invention.

Referring to FIG. 10, since the second memory mapping method for the 2x1 CGRA mode is similar to the memory mapping method for the 4x1 CGRA mode of FIG. 9, a detailed description will be omitted. The second memory mapping method may be applied when the groups (2x1 CGRA) of different functional units 113 are scheduled to be activated by interleaving.

However, in the second memory mapping method for the 2x1 CGRA mode shown in FIG. 10, cycles 0 to 3 (1010, 1020, 1030, and 1040) are divided in units of two fields in one row of the configuration memory 130. Therefore, the continuation bits are not used, and only the stop bits can be used.

11 is a diagram for describing a third memory mapping method according to an embodiment of the present invention.

Referring to FIG. 11, the third memory mapping method is the memory mapping method determined in step 680 of FIG. 6. The third memory mapping method may be applied when the size of each field of the configuration memory 1110 is different from each other. In other words, the third memory mapping method can be applied in the case of irregular encoding.

For example, assume that field 1 1120 has 15 bits and field 2 1130 has 19 bits. In the field 1 (1120), 4 bits are allocated to the bits op related to the operation code, 3 bits are allocated to each of the bits s0 and s1 related to the register file, respectively, and the connection relationship between the functional units 113 is allocated. It is assumed that 2 bits and 3 bits are respectively allocated to the bits trn0 and trn1, respectively.

In the field 2 1130, 4 bits are allocated to bits op related to the operation code, 3 bits, 4 bits, and 3 bits are respectively allocated to bits s0, s1 and s2 related to the register file, respectively, and functional units ( 113) It is assumed that 1 bit and 4 bits are respectively allocated to the bits trn0 and trn1 related to the connection relationship between them.

In cycle 0 (1140), functional unit 1 (FU1) is mapped to field 1 (1120), functional unit 2 (FU2) is mapped to field 2 (1130), so functional unit 1 (FU1) and functional unit 2 ( The configuration data for cycle 0 1140 of FU2) may be mapped to the configuration memory 1110 without a lost bit.

In contrast, in cycle 1 1150, functional unit 1 (FU1) is mapped to field 2 (1130), and functional unit 2 (FU2) will have to be mapped to field 1 (1120).

Since field 2 (1130) is 19 bits, all 15 bits of configuration data of field 1 (1120) can be mapped.

However, since field 1 (1120) is 15 bits, all 19 bits of configuration data of field 2 (1130) may be mapped.

Therefore, in the third memory mapping scheme, for example, only some of the configuration data of bits s1 and s2 in the 19 bits of the configuration data of the field 2 1130 are mapped to the field 1 1120, and the bit trn1 is not mapped. The configuration data of cycle 1 1150 can be mapped to configuration memory 1110 using random encoding.

As another example, in the third memory mapping method, for example, in the field 1 (1120), the bit s2 in the 19-bit configuration data of the field 2 (1130) is not mapped, and some configurations of bits s1 and trn1 The configuration data of cycle 1 1150 may be mapped to the configuration memory 1110 using irregular encoding in which only data is mapped.

In other words, the third memory mapping method maps the configuration data with irregular encoding when the sizes of the fields of the configuration memory 1110 to which the configuration data is to be mapped are different or when the sizes of the configuration data in each cycle are different. This is the way.

12 is a diagram for describing a fourth memory mapping method according to an embodiment of the present invention.

Referring to FIG. 12, the fourth memory mapping method is a memory mapping method determined in operation 650 or 690 of FIG. 6. The fourth memory mapping method may be applied when buffering by the buffers 1225 provided in the functional units 113 of the processor core 1220 is available. In particular, the fourth memory mapping method can be applied together with other memory mapping methods.

The configuration data mapped to the configuration memory 1210 may be buffered by 19-bit buffers 1225 provided in each of the functional units 1 (FU1) to 4 (FU4).

When buffering is available, the 15-bit configuration data for the functional unit 1 (FU1) will be buffered in the 19-bit buffer 1225 provided in the functional unit 1 (FU1). However, the size of the buffer 1225 is larger than the size of the configuration data for the functional unit 1 (FU1). Accordingly, according to the fourth memory mapping method, the configuration data for the functional unit 1 (FU1) is mapped so that 4 bits of padding bits are inserted with respect to the configuration data for the functional unit 1 (FU1).

Similarly, when buffering is available, 7 bits of padding bits and 2 bits for each of the configuration data for the functional unit 3 (FU3) and the configuration data for the functional unit 4 (FU4) according to the fourth memory mapping method. The configuration data for the functional unit 3 (FU3) and the configuration data for the functional unit 4 (FU4) are mapped so that the padding bits of are respectively inserted.

However, since the configuration data for the functional unit 2 (FU2) is 19 bits and is the same as the size of the buffer 1225, the configuration data for the functional unit 4 (FU4) is mapped without a padding bit.

So far, the first to fourth memory mapping methods have been described as memory mapping methods according to the present embodiment. However, there may be various other memory mapping methods to which the present embodiment can be applied, and the determination unit 230 uses the first memory mapping method to the fourth memory mapping method, and various other memory mapping methods. May be mapped to the configuration memory (130 in FIG. 1).

That is, according to the method of optimizing the use of the configuration memory 130 of the reconfigurable processor 100, based on the architecture of the reconfigurable processor 100 and the specifications of the configuration memory 130, one of the configuration memories 130 By flexibly determining various memory mapping schemes for mapping the configuration data to be processed in at least one or more cycles to the row of, the memory space of the configuration memory 130 may be more efficiently used.

Meanwhile, the above-described embodiments of the present invention can be written as a program that can be executed on a computer, and can be implemented in a general-purpose digital computer that operates the program using a computer-readable recording medium. In addition, the data structure used in the above-described embodiment of the present invention can be recorded on a computer-readable recording medium through various means. The computer-readable recording medium includes a storage medium such as a magnetic storage medium (eg, ROM, floppy disk, hard disk, etc.), and an optical reading medium (eg, CD-ROM, DVD, etc.).

So far, the present invention has been looked at around its preferred embodiments. Those of ordinary skill in the art to which the present invention pertains will be able to understand that the present invention can be implemented in a modified form without departing from the essential characteristics of the present invention. Therefore, the disclosed embodiments should be considered from an illustrative point of view rather than a limiting point of view. The scope of the present invention is shown in the claims rather than the foregoing description, and all differences within the scope equivalent thereto should be construed as being included in the present invention.

10: computing device 20: computing device
100: reconfigurable processor 110: processor core
113: functional units (FUs) 120: main memory
130: configuration memory 200: compiler
210: analysis unit 220: scheduling unit
230: decision part

Claims (15)

In the method of optimizing the use of configuration memory of a reconfigurable processor,
Analyzing a parallelism of a loop of a program code based on an architecture of a reconfigurable processor and a specification of the configuration memory;
Generating configuration data for each cycle by scheduling groups of functional units to be activated in each cycle of the loop according to the analyzed parallelism;
Determining whether regular encoding of the configuration data is possible and whether the groups are the same in adjacent cycles based on the architecture and specifications of the configuration memory; And
Sequentially mapping the generated configuration data for the scheduled groups in adjacent cycles to at least one row of the configuration memory; includes,
The mapping step,
When the determination result is that the regular encoding is possible and the groups are the same, mapping the generated configuration data for each of the adjacent cycles to the configuration memory. The method of claim 1,
The generating step
Generating the configuration data by scheduling the functional units of the same type to be activated every the cycle. The method of claim 1,
The generating step
Generating the configuration data by scheduling some of the entire functional units included in the reconfigurable processor to be repeatedly activated every the cycle. The method of claim 1,
The mapping step
Mapping the generated configuration data to the configuration memory using regular encoding. The method of claim 4,
The mapping step
And mapping the configuration data corresponding to each of the groups by dividing fields of the configuration memory into equal sizes. The method of claim 1,
The analyzing step
The method of analyzing the parallelism based on information on the number of functional units included in the reconfigurable processor, a connection relationship between the functional units, and a multiplexing relationship between the functional units and the configuration memory. delete A computer-readable recording medium storing a program for executing the method of any one of claims 1 to 6 on a computer. In the apparatus for optimizing the use of configuration memory of a reconfigurable processor,
An analysis unit that analyzes parallelism of loops in the program code based on the architecture of the reconfigurable processor and the specifications of the configuration memory;
A scheduling unit generating configuration data for each cycle by scheduling groups of functional units to be activated in every cycle of the loop according to the analyzed parallelism; And
A determining unit sequentially mapping the generated configuration data for the scheduled groups in adjacent cycles to at least one row of the configuration memory,
Wherein the determining unit uniformly maps the configuration data to be processed in a plurality of cycles to the plurality of fields of the configuration memory through regular encoding using the same encoding format. delete delete delete delete delete delete

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