KR102166123B1 - Multi-bank type semiconductor memory device for reducing current consumption in data line - Google Patents

Abstract

A semiconductor memory device having a multi-bank structure that reduces current consumption of a data line is disclosed. In the semiconductor memory device of the present invention, a data line between each memory bank and an input/output buffer is divided into a horizontal data line and a vertical data line. Further, the high-impedance driver is provided to drive horizontal local data of the horizontal data line and provide vertical local data of the vertical data line. Accordingly, in the semiconductor memory device of the present invention, even if the horizontal local data and the vertical local data are controlled by a low power supply voltage, a decrease in the overall operation speed hardly occurs. Further, according to the semiconductor memory device of the present invention, the current consumption of the data line is significantly reduced.

Description

A semiconductor memory device with a multi-bank structure that reduces the current consumption of data lines {MULTI-BANK TYPE SEMICONDUCTOR MEMORY DEVICE FOR REDUCING CURRENT CONSUMPTION IN DATA LINE}

The present invention relates to a semiconductor memory device having a multi-bank structure, and more particularly, to a semiconductor memory device having a multi-bank structure that reduces current consumption of a data line.

In general, a semiconductor memory device is implemented in a multi-bank structure including a plurality of memory banks therein. In the semiconductor memory device of such a multi-bank structure, while a data read operation is performed on one bank, a precharge operation or the like required before the data read operation is performed in the other bank. Accordingly, a semiconductor memory device having a multi-bank structure has a great advantage in realizing high speed.

However, in a conventional semiconductor memory device having a multi-bank structure, data read from each memory bank is connected to the outside of the chip through the same data input/output line called a “global data line”.

Accordingly, in a semiconductor memory device having a conventional multi-bank structure, the data input/output line is lengthened, and a large load is formed on the data input/output line. Such a large load acts as a factor that limits the data transmission speed.

Of course, in order to compensate for the decrease in data transmission speed due to such a load, a high-level power supply voltage is sometimes used in a semiconductor memory device having a multi-bank structure.

However, in this case, there is a problem in that the current consumption in the data line of the semiconductor memory device becomes large.

An object of the present invention is to provide a semiconductor memory device having a multi-bank structure that reduces current consumption of a data line while maintaining an appropriate data transfer rate.

One aspect of the present invention for achieving the above object relates to a semiconductor memory device having a multi-bank structure. The semiconductor memory device of the present invention is a bank set including first to fourth memory banks each outputting its own bank data, wherein the second memory bank is disposed below the first memory bank, and the third A memory bank is disposed on the right side of the first memory bank, and the fourth memory bank is disposed below the third memory bank; Horizontal data lines extending in the left and right directions between the first and second memory banks and between the third and fourth memory banks; Vertical data lines extending in a vertical direction between the first and third memory banks and between the second and fourth memory banks; As first to fourth bank read amplifiers disposed to correspond to the first to fourth memory banks, the corresponding banks of the first to fourth memory banks are selected according to the selection of the corresponding first to fourth memory banks The first to fourth bank read amplifiers amplifying data and outputting their read data; A first read driver that drives read data of the first bank read amplifier and the second bank read amplifier as the horizontal local data of the horizontal data line according to the selection of the first memory bank and the second memory bank ; As the third memory bank and the fourth memory bank are selected, a second read that drives read data of the third bank read amplifier and the fourth bank read amplifier to provide the horizontal local data of the horizontal data line driver; A high impedance driver for driving the horizontal local data and outputting the vertical local data of the vertical data line according to the selection of any one of the first to fourth memory banks; And a global amplifier that amplifies the vertical local data to provide global data of a global data line, wherein the global data line includes the global amplifier electrically connected to an input/output buffer. The bank data and the global data of each of the first to fourth memory banks are driven with a high power voltage when pulled up, and the horizontal local data and the vertical local data are controlled with a low power voltage lower than the high power voltage when pulled up. .

In the semiconductor memory device of the present invention having the above configuration, the data lines between each memory bank and the input/output buffer are separated into horizontal data lines and vertical data lines. Further, the high-impedance driver is provided to drive horizontal local data of the horizontal data line and provide vertical local data of the vertical data line. Accordingly, in the semiconductor memory device of the present invention, even if the horizontal local data and the vertical local data are controlled by a low power supply voltage, a decrease in the overall operation speed hardly occurs. Further, according to the semiconductor memory device of the present invention, the current consumption of the data line is significantly reduced.

A brief description of each drawing used in the present invention is provided.
1 is a diagram illustrating a semiconductor memory device having a multi-bank structure according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating the bank read amplifier of FIG. 1.
3A is a diagram illustrating in detail the first read driver of FIG. 1.
3B is a diagram illustrating in detail the second read driver of FIG. 1.
4 is a diagram illustrating in detail the high impedance driver of FIG. 1.
5 is a diagram illustrating in detail the global amplifier of FIG. 1.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the implementation of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided so that the disclosed content may be thorough and complete, and the spirit of the present invention may be sufficiently conveyed to those skilled in the art.

And, in understanding each drawing, it should be noted that the same members are intended to be shown with the same reference numerals as much as possible. Further, detailed descriptions of known functions and configurations that are determined to unnecessarily obscure the subject matter of the present invention are omitted.

Meanwhile, in the present specification, reference numerals are added to <> together with the same reference numerals for elements performing the same configuration and operation. In this case, these components are collectively referred to by reference numerals. And, if it is necessary to distinguish them individually,'< >'is added after the reference sign.

In describing the contents of the present invention throughout the specification, the meanings of the terms'electrically connected','connected', and'connected' between individual constituent elements are not only direct connection, but also attributes more than a certain degree. It includes everything that is maintained and connected through an intermediate medium. Terms such as'transmitted' and'derived' of individual signals also include both direct meaning as well as indirect meaning through intermediate media while maintaining the properties of the signal to a certain extent. In addition, terms such as'applied,'applied', and'input' to a voltage or signal are also used in the same meaning throughout the specification.

Also, a plurality of expressions for each component may be omitted. For example, even if a configuration consisting of a plurality of switches or a plurality of signal lines may be expressed as'switches' and'signal lines', it may be expressed in a singular number such as'switches' and'signal lines'. This is because the switches may operate complementary to each other, and in some cases, operate independently. In the case of multiple signal lines having the same properties, for example, data signals, the number of switches is It is also because there is no need to separate them into plural. In this respect, this description is valid. Therefore, similar expressions should also be interpreted in the same meaning throughout the specification.

Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

1 is a diagram illustrating a semiconductor memory device having a multi-bank structure according to an embodiment of the present invention. Note that in the semiconductor memory device of the present invention, transmitted data is pulled up to a high power voltage (HVDD) or a low power voltage (LVDD) when pulled up according to a transmission location. Here, the high power voltage HVDD is at a relatively high level, and the low power voltage LVDD is at a relatively low level.

Referring to FIG. 1, a semiconductor memory device of the present invention includes a bank set STBANK including first to fourth memory banks MBANK<1> to MBANK<1>. In this case, the first to fourth memory banks MBANK<1> to MBANK<1> are non-redundantly selected. Further, each of the first to fourth memory banks MBANK<1> to MBANK<1> outputs their own bank data BDAT.

The first memory bank MBANK<1> outputs its own bank data BDAT<1> to the lower side. The second memory bank MBANK<2> is disposed under the first memory bank MBANK<1>, and outputs its own bank data BDAT<2> to the upper side. The third memory bank MBANK<3> is disposed on the right side of the first memory bank MBANK<1>, and outputs its own bank data BDAT<3> to the lower side. Further, the fourth memory bank MBANK<4> is disposed under the second memory bank MBANK<2>, and outputs its own bank data BDAT<4> to the upper side.

At this time, the bank data BDAT output from each of the first to fourth memory banks MBANK<1> to MBANK<1> is controlled by the high power voltage HVDD during pull-up. Accordingly, data loss due to voltage drop or the like is minimized in the output bank data BDAT.

For reference, in this specification, for the sake of simplicity of description, one bank set (SRBANK) is representatively shown and described. However, the number of bank sets STBANK may be extended to two or more.

In addition, the semiconductor memory device of the present invention includes a horizontal data line (LHDAT), a vertical data line (LVDAT), first to fourth bank read amplifiers 100<1> to 100<4>, and a first read driver 200< 1>), a second read driver 200<2>, a high impedance 300, and a global amplifier 400 are also provided.

In this specification, the horizontal data line (LHDAT), the vertical data line (LVDAT), the first to fourth bank read amplifiers (100<1> to 100<4>), the first read driver (200<1>), Each of the two read driver 200<2>, the high impedance 300, the global amplifier 400, and the input/output buffer 500 is shown. However, this is only for the sake of simplification and clarity of description, and in practice, it is generally implemented in plural according to the number of data read out from each memory bank MBANK.

For example, if 128 pieces of data are read out to each memory bank (MBANK) at once, the horizontal data line (LHDAT), the vertical data line (LVDAT), the first to fourth bank read amplifiers 100<1> to 100 <4>), the first read driver 200<1>, the second read driver 200<2>, the high impedance 300, and the global amplifier 400 may be implemented in 128 units each. In addition, when the burst length is 8, the number of input/output buffers 500 may be 16.

The horizontal data line (LHDAT) is between the first memory bank (MBANK<1>) and the second memory bank (MBANK<2>), and the third memory bank (MBANK<3>) and the fourth memory bank It extends long in the left and right directions between (MBANK<4>).

The vertical data line LVDAT is between the first memory bank MBANK<1> and the third memory bank MBANK<3>, and the second memory bank MBANK<2> and the fourth memory bank Between (MBANK<4>), it extends long in the vertical direction.

The first to fourth bank read amplifiers 100<1> to 100<4> are arranged to correspond to the first to fourth memory banks MBANK<1> to MBANK<4>.

Specifically, the first bank read amplifier 100<1> is disposed corresponding to the first memory bank MBANK<1>. In addition, as the first bank read amplifier 100<1> is selected for the corresponding first memory bank MBANK<1>, the bank data of the corresponding first memory bank MBANK<1> ( BDAT<1>) is amplified and output as its own read data (RDAT<1>). Preferably, the read data RDAT<1> of the first memory bank MBANK<1> is controlled by the high power voltage HVDD during pull-up.

The second bank read amplifier 100<2> is disposed corresponding to the second memory bank MBANK<2>. In addition, as the second bank read amplifier 100<2> is selected from the corresponding second memory bank MBANK<2>, the bank data of the corresponding second memory bank MBANK<2> ( BDAT<2>) is amplified and output as its own read data (RDAT<2>). Preferably, the read data RDAT<2> of the second memory bank MBANK<2> is controlled by the high power voltage HVDD during pull-up.

The third bank read amplifier 100<3> is disposed corresponding to the third memory bank MBANK<3>. In addition, as the third bank read amplifier 100<3> is selected from the corresponding third memory bank MBANK<3>, the bank data of the corresponding third memory bank MBANK<3> ( BDAT<3>) is amplified and output as its own read data (RDAT<3>). Preferably, the read data RDAT<3> of the third memory bank MBANK<3> is controlled by the high power voltage HVDD during pull-up.

Also, the fourth bank read amplifier 100<4> is disposed corresponding to the fourth memory bank MBANK<4>. In addition, as the fourth bank read amplifier 100<4> is selected from the corresponding fourth memory bank MBANK<4>, the bank data of the corresponding fourth memory bank MBANK<4> ( BDAT<4>) is amplified and output as its own read data (RDAT<4>). Preferably, the read data RDAT<4> of the fourth memory bank MBANK<4> is controlled by the high power voltage HVDD during pull-up.

Subsequently, the configurations of the first to fourth bank read amplifiers 100<1> to 100<4> of FIG. 1 will be described in detail. In this case, the first to fourth bank read amplifiers 100<1> to 100<4> may be implemented in the same form.

FIG. 2 is a diagram illustrating the bank read amplifier 100<i> of FIG. 1, where i is a natural number greater than or equal to 1 and less than or equal to 4;

Referring to FIG. 2, the bank read amplifier 100<i> includes a bank read amplification unit 110 and a bank read disable unit 120.

The bank read amplification unit 110 uses the high power voltage HVDD as a pull-up voltage, and is activated when the corresponding memory bank MBANK<i> is selected, the i-th bank read amplifier enable signal ( BRDEN<i>). In addition, the bank read amplification unit 110 differentially amplifies the bank data (BDAT<i>) and the inverted bank data (/BDAT<i>) of the corresponding memory bank (MBANK<i>) to read its own. It is driven to output data RDAT<i> and reverse read data/RADT<i>. In this case, the read data RDAT<i> and the inverted read data /RADT<i> of the memory bank MBANK<i> are controlled by the high power voltage HVDD during pull-up.

The bank read disable unit 120 is deactivated as the memory bank MBANK<i> is not selected, in response to the i-th bank read amplifier enable signal BRDEN<i>, and the memory bank MBANK <i>) read data (RDAT<i>) and inverted read data (/RADT<i>) are both controlled to be deactivated by the ground voltage (VSS).

Referring back to FIG. 1, the first read driver 200<1> is selected from among the first memory bank MBANK<1> and the second memory bank MBANK<2>. It is enabled.

That is, as the first read driver 200<1> is selected from the first memory bank MBANK<1>, the read data RDAT<1> of the first bank read amplifier 100<1> ) Is provided as horizontal local data DATH of the horizontal data line LHDAT.

In addition, as the second memory bank MBANK<2> is selected, the first read driver 200<1> is read data RDAT<2> of the second bank read amplifier 100<2>. ) Is provided as the horizontal local data DATH of the horizontal data line LHDAT.

3A is a diagram illustrating in detail the first read driver 200<1> of FIG. 1. Referring to FIG. 3A, the first lead driver 200<1> includes a first pull-up control unit 210, a first pull-down control unit 220, and a first lead driving unit 230.

The first pull-up control unit 210 includes read data (RDAT<1>) of the first bank read amplifier (100<1>) and read data (RDAT<2>) of the second bank read amplifier (100<2>). >) to generate a first pull-up control signal (/XPU1). At this time, the first pull-up control signal (/XPU1) is read data (RDAT<1>) of the first bank read amplifier (100<1>) and read data of the second bank read amplifier (100<2>). Either of (RDAT<2>) is activated with "L" as it activates with "H".

The first pull-down controller 220 includes inverted read data (/RDAT<1>) of the first bank read amplifier 100<1> and inverted read data of the second bank read amplifier 100<2> ( /RDAT<2>) to generate a first pull-down control signal XPD1. At this time, the first pull-down control signal XPD1 is read data (RDAT<1>) of the first bank read amplifier 100<1> and read data of the second bank read amplifier 100<2> ( RDAT<2>) deactivated with "L" as all activated with "H".
Here, the operation of the first pull-up control unit 210 and the first pull-down control unit 220 will be described in more detail.
First, it is assumed that the first memory bank MBANK<1> is selected. At this time, since the second memory bank MBANK<2> cannot be selected to overlap with the first memory bank MBANK<1>, it is not selected. Therefore, the read data RDAT<2> and the inverted read data /RDAT<2> of the second memory bank MBANK<2> are both ground voltage VSS, that is, "L", as described above. Is controlled by the logical state of.
As a result, according to the read data (RDAT<1>) and inverted read data (/RDAT<1>) of the first memory bank MBANK<1>, the first pull-up control signal (/XPU1) and the first Any one of the pull-down control signals XPD1 is activated.
Next, it is assumed that the second memory bank MBANK<2> is selected. At this time, since the first memory bank MBANK<1> cannot be selected to overlap with the second memory bank MBANK<2>, it is not selected. Therefore, the read data RDAT<1> and the inverted read data /RDAT<1> of the first memory bank MBANK<1> are both controlled to the ground voltage VSS, that is, a logic state of “L”. .
As a result, according to the read data (RDAT<2>) and inverted read data (/RDAT<2>) of the second memory bank MBANK<2>, the first pull-up control signal (/XPU1) and the first Any one of the pull-down control signals XPD1 is activated.

The first read driving unit 230 pulls up the horizontal data line LHDAT to the low power voltage LVDD in response to activation of the first pull-up control signal /XPU1 to "L". In addition, the first read driving unit 230 pulls down the horizontal data line LHDAT in response to activation of the first pull-down control signal XPD1 to “H”.

In the first read driver 200<1> having the above-described configuration, horizontal local data DATH is selected as any one of the first and second memory banks MBANK<1> and MBANK<2> is selected. Will have a valid value. At this time, the horizontal local data DATH is controlled by the low power supply voltage LVDD during pull-up.

If both the first and second memory banks (MBANK<1> and MBANK<2>) are unselected, the first pull-up control signal (/XPU1) and the first pull-down control signal (XPD1) are all It is deactivated. In this case, the horizontal local data DATH depends on the operation of the second read driver 200<2>.

Referring back to FIG. 1, the second read driver 200<2> is selected from one of the third memory bank MBANK<3> and the fourth memory bank MBANK<4>. It is enabled.

That is, as the second read driver 200<2> is selected from the third memory bank MBANK<3>, the read data RDAT<3> of the third bank read amplifier 100<3> is ) Is provided as horizontal local data DATH of the horizontal data line LHDAT.

In addition, as the fourth memory bank MBANK<4> is selected, the second read driver 200<2> reads the read data RDAT<4> of the fourth bank read amplifier 100<4>. ) Is provided as the horizontal local data DATH of the horizontal data line LHDAT.

3B is a diagram illustrating in detail the second read driver 200<2> of FIG. 1. Referring to FIG. 3B, the second lead driver 200<2> includes a second pull-up control unit 260, a second pull-down control unit 270, and a second lead driving unit 280.

The second pull-up control unit 260 includes read data (RDAT<3>) of the third bank read amplifier (100<3>) and read data (RDAT<4>) of the fourth bank read amplifier (100<4>). >) to generate a second pull-up control signal (/XPU2). At this time, the second pull-up control signal (/XPU2) is read data (RDAT<3>) of the third bank read amplifier (100<3>) and read data of the fourth bank read amplifier (100<4>). Either of (RDAT<4>) is activated with "L" as it activates with "H".

The second pull-down controller 270 includes inverted read data (/RDAT<3>) of the third bank read amplifier 100<3> and inverted read data (/RDAT<3>) of the fourth bank read amplifier 100<4>. /RDAT<4>) is received, and a second pull-down control signal XPD2 is generated. At this time, the second pull-down control signal XPD2 is read data (RDAT<3>) of the third bank read amplifier (100<3>) and read data of the fourth bank read amplifier (100<4>) ( RDAT<4>) deactivated with "L" as all activate with "H".
Here, the operation of the second pull-up control unit 260 and the second pull-down control unit 270 will be described in more detail.
First, it is assumed that the third memory bank MBANK<3> is selected. At this time, since the fourth memory bank MBANK<4> cannot be selected to overlap with the third memory bank MBANK<1>, it is not selected. Therefore, the read data RDAT<4> and the inverted read data /RDAT<4> of the fourth memory bank MBANK<4> are both controlled to the ground voltage VSS, that is, a logic state of "L". .
As a result, according to the read data (RDAT<3>) and inverted read data (/RDAT<3>) of the third memory bank (MBANK<1>), the second pull-up control signal (/XPU2) and the second Any one of the pull-down control signals XPD2 is activated.
Next, it is assumed that the fourth memory bank MBANK<4> is selected. At this time, since the third memory bank MBANK<3> cannot be selected to overlap with the fourth memory bank MBANK<4>, it is not selected. Therefore, the read data RDAT<3> and the inverted read data /RDAT<3> of the third memory bank MBANK<3> are both controlled to the ground voltage VSS, that is, a logic state of “L”. .
As a result, according to the read data (RDAT<4>) and inverted read data (/RDAT<4>) of the fourth memory bank (MBANK<4>), the second pull-up control signal (/XPU2) and the second Any one of the pull-down control signals XPD2 is activated.

The second read driving unit 280 pulls up the horizontal data line LHDAT to the low power voltage LVDD in response to activation of the second pull-up control signal /XPU2 to “L”. In addition, the second read driving unit 280 pulls down the horizontal data line LHDAT in response to activation of the second pull-down control signal XPD2 to “H”.

In the second read driver 200<2> having the above-described configuration, horizontal local data DATH is selected as any one of the third and fourth memory banks MBANK<3> and MBANK<4> is selected. Will have a valid value. At this time, the horizontal local data DATH is controlled by the low power supply voltage LVDD during pull-up.

If both the third and fourth memory banks (MBANK<1> and MBANK<2>) are unselected, the second pull-up control signal (/XPU2) and the second pull-down control signal (XPD2) are all It is deactivated. In this case, the horizontal local data DATH depends on the operation of the first read driver 200<1>.

Referring again to Fig. 1, the high impedance driver 300 is enabled when any one of the first to fourth memory banks MBANK<1> to (MBANK<4>) is selected. The impedance driver 300 drives the horizontal local data DATH and outputs it as vertical local data DATV of the vertical data line LVDAT, where the vertical local data DATV is pulled up with a low power supply voltage. It is controlled by (LVDD).

4 is a diagram illustrating the high impedance driver 300 of FIG. 1 in detail. Referring to FIG. 4, the high impedance driver 300 specifically includes a horizontal local latch unit 310 and a high impedance driving unit 330.

The horizontal local latch unit 310 latches the horizontal local data DATH provided by the first read driver 200<1> and the second read driver 200<2>.

The high-impedance driving unit 330 responds to a high-impedance enable signal HIZEN activated with "H" when any one of the first to fourth memory banks MBANK<1> to MBANK<4> is selected. In response, it is enabled.

In this case, the high impedance driving unit 330 receives the low power voltage LVDD, drives the horizontal local data DATH, and outputs the vertical local data DATV of the vertical data line LVDAT. Here, the horizontal local data DATH is controlled to a low power supply voltage LVDD during pull-up.

Referring back to FIG. 1, the global amplifier 400 amplifies the vertical local data DATV and provides it as global data DATG of the global data line GDL. Here, the global data line is electrically connected to the input/output buffer 500. At this time, the global data DATG is controlled by the high power voltage HVDD during pull-up.

As a result, data output from the semiconductor memory device of the present invention is sufficiently developed to facilitate communication with an external device.

5 is a diagram illustrating in detail the global amplifier 400 of FIG. 1. Referring to FIG. 5, in detail, the global amplifier 400 includes a global reference voltage generator 410, a global amplifier 420, a global driving unit 430, a global repeating unit 440, and a global disable unit. It has 450.

The global reference voltage generation unit 410 is enabled in response to a preliminary enable signal PRAMEN activated as "H" in a read operation to generate a global reference voltage VGRF.

The global amplification unit 420 is enabled in response to a global enable signal GAMEN activated with "H" in a read operation. In this case, the global amplifying unit 420 senses and amplifies the voltage level of the vertical local data DATV with respect to the global reference voltage VGRF to generate global preliminary data DPG.

Here, the activation of the global enable signal GAMEN is performed after the preliminary enable signal PRAMEN is activated.

The global driving unit 430 generates global driving data DAGD according to the global preliminary data DPG.

The global repeating unit 440 latches and amplifies the global driving data DAGD to generate the global data DATG. At this time, the global data DATG is controlled by the low power supply voltage LVDD during pull-up.

When disabled, the global disable unit 450 is driven to control the global preliminary data DPG and the inverted data /DPG of the global preliminary data DPG with a high power voltage HVDD. Accordingly, the global driving data DAGD maintains the value latched by the global repeating unit 440 as it is.

In the semiconductor memory device of the present invention as described above, the bank data (BDAT<1> to BDAT<4>) of the first to fourth memory banks (MBANK<1> to (MBANK<4>) and the global data The DATG is controlled by the high power voltage HVDD during pull-up, thereby minimizing the loss of data output from the memory bank MBANK, and the global data provided to the input/output buffer 500. DATG) is also controlled by the high power voltage (HVDD) during pull-up, so that communication with external devices can be performed smoothly.

On the other hand, in the semiconductor memory device of the present invention, a data line between each memory bank MBANK and the input/output buffer 500 is divided into a horizontal data line LHDAT and a vertical data line LHDAT. In addition, the high-impedance driver 300 is provided to drive horizontal local data DATH of the horizontal data line LHDAT and provide vertical local data DATV of the vertical data line LHDAT.

Accordingly, in the semiconductor memory device of the present invention, the load on the data line is significantly reduced compared to the semiconductor memory device in which each memory bank MBANK and the input/output buffer 500 are connected by one data line.

Therefore, in the semiconductor memory device of the present invention, even if the horizontal local data DATH and the vertical local data DATV are controlled by the low power supply voltage LVDD, the overall operation speed hardly decreases.

Further, in the semiconductor memory device of the present invention, since the horizontal local data DATH and the vertical local data DATV are controlled by the low power supply voltage LVDD during pull-up, current consumption of a data line is reduced.

In addition, in the semiconductor memory device of the present invention, the first read driver 200<1> is shared by the first memory bank MBANK<1> and the second memory bank MBANK<2>, and the second The read driver 200<2> is implemented in a structure in which the third memory bank MBANK<3> and the fourth memory bank MBANK<4> share.

Therefore, according to the semiconductor memory device of the present invention, the overall layout area is greatly reduced.

As described above, although the embodiments have been described by the limited embodiments and drawings, various modifications and variations are possible from the above description by those of ordinary skill in the art. For example, the described techniques are performed in a different order from the described method, and/or components such as a system, structure, device, circuit, etc. described are combined or combined in a form different from the described method, or other components Alternatively, even if substituted or substituted by an equivalent, an appropriate result can be achieved.

Therefore, the true technical protection scope of the present invention should be determined by the technical idea of the attached registration claims.

Claims (7)

In the semiconductor memory device of a multi-bank structure,
A bank set including first to fourth memory banks each outputting its own bank data, wherein the second memory bank is disposed under the first memory bank, and the third memory bank is the first memory bank. The bank set is disposed on the right side of the bank, and the fourth memory bank is disposed below the third memory bank;
Horizontal data lines extending in the left and right directions between the first and second memory banks and between the third and fourth memory banks;
Vertical data lines extending in a vertical direction between the first and third memory banks and between the second and fourth memory banks;
As first to fourth bank read amplifiers disposed to correspond to the first to fourth memory banks, the corresponding banks of the first to fourth memory banks are selected according to the selection of the corresponding first to fourth memory banks The first to fourth bank read amplifiers amplifying data and outputting their read data;
A first read driver that drives read data of the first bank read amplifier and the second bank read amplifier as the horizontal local data of the horizontal data line according to the selection of the first memory bank and the second memory bank ;
As the third memory bank and the fourth memory bank are selected, a second read that drives read data of the third bank read amplifier and the fourth bank read amplifier to provide the horizontal local data of the horizontal data line driver;
A high impedance driver for driving the horizontal local data and outputting the vertical local data of the vertical data line according to the selection of any one of the first to fourth memory banks; And
A global amplifier that amplifies the vertical local data and provides it as global data of a global data line, wherein the global data line includes the global amplifier electrically connected to an input/output buffer,
The bank data and the global data of each of the first to fourth memory banks are
When pulled up, it is driven by high power voltage
The horizontal local data and the vertical local data are
It is controlled by a low power supply voltage lower than the high power voltage when pulling up,
The high impedance driver is
A horizontal local latch unit for latching the horizontal local data; And
And a high-impedance driving unit configured to drive the horizontal local data and output the vertical local data of the vertical data line according to the selection of any one of the first to fourth memory banks. Memory device.
The method of claim 1, wherein each of the first to fourth bank lead amplifiers
A bank read amplification unit that is enabled according to the selection of the corresponding first to fourth memory banks, and is driven to amplify the bank data of the corresponding first to fourth memory banks and output them as the read data; And
And a bank read disable unit that controls to deactivate the read data of the corresponding first to fourth memory banks when the corresponding first to fourth memory banks are deselected.
delete delete delete The method of claim 1, wherein the global amplifier is
A global reference voltage generator that generates a global reference voltage;
A global amplifier configured to sense and amplify a voltage level of the vertical local data with respect to the global reference voltage to generate global preliminary data;
A global driving unit that is driven according to the global preliminary data to generate global driving data; And
And a global repeating unit configured to latch and amplify the global driving data to generate the global data.
The method of claim 6, wherein the global amplifier is
And a global disable unit for controlling the global preliminary data so as to hold the global driving data latched by the global repeating unit when disabled.

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