KR102164793B1 - Printed circuit board with embedded passive component - Google Patents

Abstract

The present disclosure relates to a first insulating layer, a first core layer disposed on the first insulating layer and having at least one first through hole, at least one first passive component disposed in the first through hole, and the first passive component And a second insulating layer covering at least a part of the first through hole, a second core layer disposed on the second insulating layer, and a third insulating layer disposed on the second core layer, the One surface of the first core layer in contact with the first insulating layer and one surface of the first passive component in contact with the first insulating layer are coplanar with each other, and the other surface of the first passive component covered with the second insulating layer A core structure spaced apart from the second core layer by a predetermined distance; A first build-up structure disposed on one side of the core structure and including a plurality of first build-up layers and a plurality of first wiring layers; And a second build-up structure disposed on the other side of the core structure and including a plurality of second build-up layers and a plurality of second wiring layers. And the first passive component is electrically connected to at least one of the plurality of first and second wiring layers, and relates to a passive component embedded substrate.

Description

PASSIVE COMPONENT WITH EMBEDDED PASSIVE COMPONENT{PRINTED CIRCUIT BOARD WITH EMBEDDED PASSIVE COMPONENT}

The present disclosure relates to a passive component embedded substrate, more specifically, to a passive component embedded substrate on which a semiconductor package can be mounted.

In recent years, high-performance packages are required to process exponentially increased data, and with this change, substrates and passive components within the package are also required to improve performance. For example, capacitors among passive components are required to have high reliability at high temperatures, miniaturization, high capacity, and low ESL performance. Among them, the ESL value is closely related to noise and power consumption, and the ESL reduction effect can be further maximized by bringing this value closer to the semiconductor rather than simply improving the performance of the capacitor.

In the existing high-performance package, a capacitor is placed around a semiconductor (DSC: Die Side Capacitor) or a substrate solder ball side under the semiconductor region (LSC: Land Side Capacitor) to reduce the distance. However, this also has a distance of several to tens of mm, and the parasitic inductance is generated due to this, which has a bad influence in terms of power noise and power integrity.

One of the various objectives of the present disclosure is to minimize the distance between the semiconductor chip and the passive component, thereby reducing the substrate parasitic inductance and impedance, thereby improving power integrity. Nevertheless, it is possible to minimize defects such as voids and undulation to improve reliability. In particular, it is to provide a passive component embedded substrate capable of having excellent via processing and plating quality even if the thickness of the component is different when a plurality of passive components are embedded.

One of the various solutions proposed through the present disclosure is to form a core structure by alternately stacking a plurality of core layers and a plurality of insulating layers, but forming a passive component to be embedded in the core structure, and at this time, the core in which the passive component is embedded. In the case of layers, one side of the core layer and one side of the passive component are arranged to be coplanar, and then stacked after up/down inversion during the lamination process, so that the flat side of the coplanar is intentionally directed to the outside. It is to implement a printed circuit board by forming a build-up layer above and below it.

For example, the passive component embedded substrate according to an example of the present disclosure may include a first insulating layer, a first core layer disposed on the first insulating layer and having at least one first through hole, and disposed in the first through hole. At least one first passive component, a second insulating layer covering the first passive component and filling at least a portion of the first through hole, a second core layer disposed on the second insulating layer, and the second core layer A third insulating layer disposed thereon, and one surface of the first core layer in contact with the first insulating layer and one surface of the first passive component in contact with the first insulating layer are coplanar with each other, and the first A core structure in which the other surface of the passive component covered with the second insulating layer is spaced apart from the second core layer by a predetermined distance; A first build-up structure disposed on one side of the core structure and including a plurality of first build-up layers and a plurality of first wiring layers; And a second build-up structure disposed on the other side of the core structure and including a plurality of second build-up layers and a plurality of second wiring layers. And the first passive component may be electrically connected to at least one of the plurality of first and second wiring layers.

As one of the effects of the present disclosure, the distance between the semiconductor chip and the passive component can be minimized to reduce substrate parasitic inductance and impedance to improve power integrity. Nevertheless, reliability by minimizing defects such as voids and undulations In particular, it is possible to provide a passive component embedded substrate capable of having excellent via processing and plating quality even if the thickness of the component is different when a plurality of passive components are embedded.

1 is a block diagram schematically showing an example of an electronic device system.
2 is a perspective view schematically showing an example of an electronic device.
3 is a schematic cross-sectional view showing an example of a passive component embedded substrate.
4 to 9 are process diagrams schematically showing an example of manufacturing the passive component embedded substrate of FIG. 3.
10 is a cross-sectional view schematically showing another example of a passive component embedded substrate.
11 is a cross-sectional view schematically showing another example of a passive component embedded substrate.
12 is a schematic cross-sectional view of another example of a passive component embedded substrate.
13 is a schematic cross-sectional view illustrating an example in which a semiconductor package is disposed on a substrate with an embedded passive component.
14 is a schematic cross-sectional view illustrating an example in which a semiconductor chip is disposed on a substrate with an embedded passive component.
15 schematically shows one effect of the passive component embedded substrate.

Hereinafter, the present disclosure will be described with reference to the accompanying drawings. In the drawings, the shapes and sizes of elements may be exaggerated or reduced for clearer explanation.

Electronics

1 is a block diagram schematically showing an example of an electronic device system.

Referring to the drawings, the electronic device 1000 accommodates a main board 1010. A chip-related part 1020, a network-related part 1030, and other parts 1040 are physically and/or electrically connected to the main board 1010. These are also combined with other components to be described later to form various signal lines 1090.

The chip-related parts 1020 include memory chips such as volatile memory (eg, DRAM), non-volatile memory (eg, ROM), and flash memory; Application processor chips such as a central processor (eg, a CPU), a graphics processor (eg, a GPU), a digital signal processor, an encryption processor, a microprocessor, and a microcontroller; Logic chips such as analog-to-digital converters and application-specific ICs (ASICs) are included, but are not limited thereto, and other types of chip-related components may be included in addition to this. Also, of course, these parts 1020 may be combined with each other.

Network-related parts 1030 include Wi-Fi (IEEE 802.11 family, etc.), WiMAX (IEEE 802.16 family, etc.), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM , GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, 5G and any other wireless and wired protocols designated as such and beyond, including, but not limited to, many other wireless or wired protocols. Any of the standards or protocols may be included. In addition, it goes without saying that the network-related component 1030 may be combined with the chip-related component 1020 with each other.

Other components 1040 include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, LTCC (low temperature co-firing ceramics), EMI (Electro Magnetic Interference) filters, and MLCC (Multi-Layer Ceramic Condenser). , It is not limited thereto, and in addition, passive components used for various other purposes may be included. In addition, it goes without saying that the other components 1040 may be combined with each other along with the chip-related component 1020 and/or the network-related component 1030.

Depending on the type of the electronic device 1000, the electronic device 1000 may include other components that may or may not be physically and/or electrically connected to the main board 1010. For example, the camera 1050, antenna 1060, display 1070, battery 1080, audio codec (not shown), video codec (not shown), power amplifier (not shown), compass ( Not shown), accelerometer (not shown), gyroscope (not shown), speaker (not shown), mass storage device (eg, hard disk drive) (not shown), compact disk (CD) (not shown), and DVD There are (digital versatile disk) (not shown), but are not limited thereto, and other parts used for various purposes may be included depending on the type of the electronic device 1000.

The electronic device 1000 includes a smart phone, a personal digital assistant, a digital video camera, a digital still camera, a network system, and a computer ( computer), a monitor, a tablet, a laptop, a netbook, a television, a video game, a smart watch, an automotive, and the like. However, the present invention is not limited thereto, and, of course, it may be any other electronic device that processes data in addition to these.

2 is a perspective view schematically showing an example of an electronic device.

Referring to the drawings, the electronic device may be a smart phone 1100. For example, the motherboard 1110 is accommodated in the body 1101 of the smart phone 1100, and various components 1120 are physically and/or electrically connected to the motherboard 1110. In addition, other components that may or may not be physically and/or electrically connected to the motherboard 1110, such as the camera 1130, are accommodated in the body 1101. Some of the components 1120 may be chip-related components, and some of them may be the semiconductor package 1121. The semiconductor package 1121 may include an organic interposer. In addition, in order to be mounted on a main board, etc., although not shown in the drawings, it may be mounted on a printed circuit board such as a ball grid array substrate. On the other hand, the electronic device is not necessarily limited to the smart phone 1100, and of course, other electronic devices may be used.

Passive parts built-in board

In the following, the distance between the semiconductor chip and the passive component can be minimized to reduce the substrate parasitic inductance and impedance to improve power integrity. Nevertheless, the reliability can be improved by minimizing defects such as voids and undulation. Particularly, when a plurality of passive components are embedded, a passive component embedded substrate capable of having excellent via processing and plating quality even if the components have different thicknesses will be described with reference to the drawings.

3 is a schematic cross-sectional view showing an example of a passive component embedded substrate.

Referring to the drawings, a passive component embedded substrate 100A according to an example includes a core structure 110A and first and second build-up structures 120 and 130 disposed on both sides of the core structure 110A. The core structure 110A includes a plurality of core layers 111a1 and 111a2 and a plurality of insulating layers 111b1, 111b2, 111b3, and 111b4. More specifically, the core structure 110A is disposed on the first insulating layer 111b1 and the first insulating layer 111b1 and has one or more through holes 111a1h, and one or more through holes. A second insulating layer 111b2 covering at least one of the passive components 112a, 112b, 112c, and passive components 112a, 112b, and 112c respectively disposed on 111a1h and filling at least a portion of each of the through holes 111a1h , The second core layer 111a2 disposed on the second insulating layer 111b2, the third insulating layer 111b3 disposed on the second core layer 111a2, and the second insulating layer 111b2 and the second And a fourth insulating layer 111b4 disposed between the core layers 111a2. In addition, the core structure 110A includes the first core wiring layer 116a and the third insulating layer 111b3 disposed on the opposite side of the first insulating layer 111b1 to the side on which the first core layer 111a1 is disposed. And a second core wiring layer 116b disposed on a side opposite to the side on which the two core layers 111a2 are disposed. The first and second core wiring layers 116a and 116b are through vias 114 penetrating all of the first and second core layers 111a1 and 111a2 and the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4. ) Through the electrical connection. The passive components 112a, 112b, and 112c are electrically connected to the first core wiring layer 116a through connection vias 115a, 115b, and 115c passing through the first insulating layer 111b1, respectively. The first and second build-up structures 120 and 130 include a plurality of first and second build-up layers 121 and 131, a plurality of first and second wiring layers 122 and 132, and a plurality of first and second build-up layers, respectively. Includes two wiring via layers 123 and 133, and each of the passive components 112a, 112b, and 112c passes through the first core wiring layer 116a to each of the first and/or second buildup structures 120 and 130. It is electrically connected to the plurality of first and/or second wiring layers 122 and 132.

On the other hand, conventional high-performance packages have attempted to reduce the electrical distance by placing the capacitor around the semiconductor on the substrate (DSC) or on the solder ball side of the substrate under the semiconductor region (LSC). Since it is a millimeter, there is a problem that it is difficult to expect excellent effects in terms of power noise and power integrity due to the occurrence of parasitic inductance. As a solution to this problem, it may be considered to embed a passive component such as a capacitor into a substrate under the semiconductor region. For example, it is possible to consider embedding passive components in the core layer of the substrate. Specifically, it may be considered to form a cavity in the core layer, place the passive component in the cavity, and cover it with an insulating material. However, in this case, small-sized passive components are arranged to be biased on one side of the thick core layer, and in this case, it is difficult to fill the remaining cavity space with an insulating material, and defects such as voids and undulation are likely to occur. Alternatively, it is possible to consider embedding passive components in the build-up layer of the substrate, but in this case, the build-up layer is thinner than the passive component to be embedded, and even if it is stacked in multiple layers, it is difficult to manage the depth of the embedding cavity due to the accumulated thickness accumulation tolerance. There is a problem that it is difficult.

On the other hand, the passive component embedded substrate 100A according to an example comprises a core structure 110A of a plurality of core layers 111a1 and 111a2 and a plurality of insulating layers 111b1, 111b2, 111b3, and 111b4, wherein at least one A through hole 111a1h is formed in the core layer 111a, and passive components 112a, 112b, 112c are disposed in the through hole 111a1h, and covered with an insulating material to be embedded. That is, a through hole 111a1h is formed in one core layer 111a having a thickness similar to that of the passive components 112a, 112b, and 112c, for example having a thickness difference of several to tens of microns or less, and the passive components 112a, 112b, and 112c After that, in order to increase the thickness, core layers 111b and 111c and insulating layers 111b1, 111b2, 111b3, and 111b4 are alternately stacked to form a core structure 110A. Therefore, the small-sized passive components 112a, 112b, and 112c are disposed in the through holes 111a1h formed in the core layer 111a of similar thickness and covered with an insulating material, such as voids or undulations described above. In addition, the core layer 111b, 111c and insulating layers 111b1, 111b2, 111b3, and 111b4 are used to form a symmetrical thick core structure 110A. Similar to the introduction of the core layer of, it can have excellent rigidity maintenance and warpage control effect as it is.

In particular, the passive component embedded substrate 100A according to an example has one surface in contact with the first insulating layer 111b1 of the first core layer 111a1 and the first insulating layer 111b1 of each of the passive components 112a, 112b, and 112c. One surface in contact with, for example, one surface of the electrode in contact with the first insulating layer 111b1 of each of the passive components 112a, 112b, and 112c and one surface in contact with the first insulating layer 111b1 of the second insulating layer 111b2 are each Coplanar, and at the same time, the other surface covered with the second insulating layer 111b2 of each of the passive components 112a, 112b, and 112c is spaced apart from the second core layer 111a2 by a predetermined distance. This, as can be seen in the process to be described later, in the manufacturing process of the core structure (110A), the passive components (122a, 122b, 122c) are arranged such that the first core layer (111a1) and one side are coplanar with each other, the After that, the first core layer 111a1 in which they are embedded can be stacked upside down and stacked so that the flat surface faces upward. In this case, the first core layer 111a1 and the coplanar flat surface may be provided regardless of the thickness of each of the passive components 112a, 112b, and 112c, and the electrodes of each of the passive components 112a, 112b, and 112c The insulation distance of can be made constant. Accordingly, the heights of the connection vias 115a, 115b, and 115c may be the same. In this case, in the process of forming the first insulating layer 111b1, the connection vias 115a, 115b, and 115c, and the first core wiring layer 116a, there is no problem of defects such as voids or undulation, and better via processing and plating quality Can have

Hereinafter, the configuration of the passive component embedded substrate 100A will be described in more detail with reference to the drawings.

The core structure 110A contains the passive components 112a, 112b, and 112c and serves to add rigidity to the substrate. The core structure 110A is disposed on the first insulating layer 111b1 and the first insulating layer 111b1, and has at least one through hole 111a1h, and has at least one through hole 111a1h. A second insulating layer 111b2 covering at least a portion of each of the through holes 111a1h, covering each of the one or more passive components 112a, 112b, and 112c, and the passive components 112a, 112b, and 112c disposed respectively, and the second insulating layer. The second core layer 111a2 disposed on the layer 111b2, the third insulating layer 111b3 disposed on the second core layer 111a2, and the second insulating layer 111b2 and the second core layer 111a2 ) And a fourth insulating layer 111b4 disposed between them. In addition, the core structure 110A includes the first core wiring layer 116a and the third insulating layer 111b3 disposed on the opposite side of the first insulating layer 111b1 to the side on which the first core layer 111a1 is disposed. And a second core wiring layer 116b disposed on a side opposite to the side on which the two core layers 111a2 are disposed. The first and second core wiring layers 116a and 116b are through vias 114 penetrating all of the first and second core layers 111a1 and 111a2 and the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4. ) Through the electrical connection. The passive components 112a, 112b, and 112c are electrically connected to the first core wiring layer 116a through connection vias 115a, 115b, and 115c passing through the first insulating layer 111b1, respectively.

Each of the first and second core layers 111a1 and 111a2 may impart rigidity to the core structure 110A. An insulating material may be used as the material of the first and second core layers 111a1 and 111a2. In this case, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler. Or a material containing a resin impregnated with a core material such as glass fiber (Glass Fiber, Glass Cloth, Glass Fabric) together with an inorganic filler, for example, a copper clad laminate (CCL) or an unclad copper clad laminate ( Unclad CCL) can be used. However, the present invention is not limited thereto, and at least one of the first and second core layers 111a1 and 111a2 may be formed of another type of rigid material such as a glass substrate or a ceramic substrate. Each of the through holes 111a1h formed in the first core layer 111a1 may be one hole formed to continuously surround the passive components 112a, 112b, and 112c respectively accommodated in the plan view.

Each of the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4 may function as a bonding layer bonding layers and layers in the core structure 110A. An insulating material may also be used as the material of the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4. In this case, as the insulating material, a thermosetting resin such as epoxy resin, a thermoplastic resin such as polyimide, or these resins A resin mixed with an inorganic filler or impregnated with a core material such as glass fiber together with an inorganic filler, for example, a prepreg (PPG), or the like may be used. It may be preferable in terms of warpage control that the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4 are introduced in an uncured state, bonded, and then cured at once. The boundaries of the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4 may be separated from each other, or the boundaries may be unclear. The fourth insulating layer 111b4 may be omitted if necessary.

The thicknesses of the first and second core layers 111a1 and 111a2 may be substantially the same. The thicknesses of the first and third insulating layers 113a and 113c may be substantially the same as each other. Each of the first and second core layers 111a1 and 111a2 may have a thickness greater than that of each of the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4. Here, the thickness of the second insulating layer 111b2 excludes the thickness filling the through hole 111a1h. That is, the thickness of the second insulating layer 111b2 means the thickness between the first core layer 111a1 and the fourth insulating layer 111b4. The core structure 110A is configured in a symmetrical shape as described above, and thus may be effective for warpage control.

There may be a plurality of passive components 112a, 112b, and 112c, and a plurality of passive components 112a, 112b, and 112c may be disposed in each of the through holes 111a1h. The passive components 112a, 112b, and 112c may be the same or different from each other. The passive components 112a, 112b, and 112c may be known passive components such as capacitors and inductors. Each of the passive components 112a, 112b, and 112c may have the same thickness or may be different from each other. One surface of each of the passive components 112a, 112b, and 112c in contact with the first insulating layer 111b1 may be coplanar with each other, and the other surface covered with each of the second insulating layers 111b2 is a second core layer 111a2. ) And can be physically separated by a predetermined distance. Each electrode of the passive components 112a, 112b, and 112c may be electrically connected to the first core wiring layer 116a through connection vias 115a, 115b, and 115c. These connection vias 115a, 115b, and 115c may also have the same height. The thickness of each of the passive components 112a, 112b, and 112c may be smaller than the thickness of the first core layer 111a1. That is, the thickness of the first core layer 111a1 may be thicker than the thickness of each of the passive components 112a, 112b, and 112c, but the difference may be about several to tens of micrometers or less.

The first and second core wiring layers 116a and 116b perform various functions within the core structure 110A according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. In addition, various pads may be included. Materials for forming the first and second core wiring layers 116a and 116b are copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), and lead ( A conductive material such as Pb), titanium (Ti), or an alloy thereof, specifically, a metal material may be used.

A mark pattern 116c may be disposed on the other surface of the first core layer 111a1 covered by the second insulating layer 111b2. The mark pattern 116c may be an alignment mark for arranging the passive components 112a, 112b, and 112c in the through hole 111a1h. At least one of the mark patterns 116c may be electrically insulated from the plurality of first and second wiring layers 122 and 132. As a material for forming the mark pattern 116c, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), Alternatively, a conductive material such as an alloy thereof, specifically a metal material may be used.

The through via 114 electrically connects the first and second core wiring layers 116a and 116b. The through via 114 may include a ground via, a power via, a signal via, or the like. The through-via 114 is formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), respectively. , Or a conductive material such as an alloy thereof, specifically, a metal material may be used. The through via 114 may have a cylindrical shape. The through via 114 may have a shape penetrating through the core structure 110A. This is because the core wiring layer may be omitted inside the core structure 110A. That is, the core wiring layer may be omitted inside the core structure 110A, and other pattern layers may be minimized. This is to minimize the occurrence of interlayer lifting by interfering with the movement of moisture absorbed by metal. Here, the minimum pattern layer may be the aforementioned mark pattern 116c, such as a facility target design for processing the through-hole 111a1h and embedding the passive components 112a, 112b, and 112c. The through-via 114 is formed of metal in a conformal form along the wall of the through-via hole penetrating all of the first and second core layers 111a1 and 111a2 and the first to fourth insulating layers 111b1, 111b2, 111b3, and 111b4. The material 114a may be a plated through hole (PHT) formed by plating. In this case, the space of the through-via hole between the metal materials 114a may be filled with the plugging material 114b. As the plugging material 114b, a known plugging material such as an insulating material or conductive ink may be employed.

The connection vias 115a, 115b, and 115c electrically connect each of the passive components 112a, 112b, and 112c to the first core wiring layer 116a. In this way, each of the passive components 112a, 112b, and 112c may be electrically connected to the first core wiring layer 116a in the core structure 110A through the connection vias 115a, 115b, and 115c only upward. The connection vias 115a, 115b, and 115c may also include a ground via, a power via, and a signal via, respectively. In addition, as a forming material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their Conductive materials such as alloys, specifically metal materials, can be used. The connection vias 115a, 115b, and 115c may have a tapered shape in the same direction as the wiring via of the wiring via layer 123 of the first build-up structure 120.

The first build-up structure 120 substantially provides various wiring designs so that the passive component-embedded substrate 100A can function as a printed circuit board. The first build-up structure 120 includes a plurality of first build-up layers 121, a plurality of first wiring layers 122 and a plurality of first wiring via layers 123. A first passivation layer 124 may be disposed on the uppermost side of the first build-up structure 120. The first passivation layer 124 may each have a plurality of openings 124h exposing at least a portion of the uppermost first wiring layer 122, and each of the plurality of openings 124h has a first electrical connection structure 140 Can be placed.

The first build-up layer 121 may include an insulating material, and as an insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler, or in the core material of the inorganic filler. Impregnated resin, for example, ABF (Ajinomoto Build-up Film) may be used, but is not limited thereto. The number of layers of the first build-up layer 121 is not particularly limited, and may be variously changed according to design. They may have clear boundaries or unclear boundaries. The thickness of each of the first build-up layers 121 may be thinner than the thickness of each of the core layers 111a1 and 111a2. In addition, the elastic modulus of each of the first build-up layers 121 may be smaller than that of each of the core layers 111a1 and 111a2. That is, the build-up layer 121 may be designed to introduce a plurality of first wiring layers 122 as thin as possible.

The first wiring layer 122 performs various functions according to the design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. In addition, various pads may be included. The first wiring layer 122 is formed of copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti ), or a conductive material such as an alloy thereof, specifically a metal material.

The first wiring via layer 123 electrically connects each of the first wiring layers 122 to each other. In addition, the first core wiring layer 116a and the first wiring layer 122 are electrically connected. The first wiring via layer 123 may also include a ground via, a power via, a signal via, or the like. In addition, as a forming material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their Conductive materials such as alloys, specifically metal materials, can be used. Each wiring via of the first wiring via layer 123 may have a tapered shape in the same direction as the connection vias 115a, 115b, and 115c.

The first passivation layer 124 may protect the first build-up layer 121, the first wiring layer 122, and the first wiring via layer 123. The material of the first passivation layer 124 is not particularly limited. For example, an insulating material may be used. In this case, a solder resist may be used as the insulating material. However, the present invention is not limited thereto, and the aforementioned prepreg, ABF (Ajinomoto Build-up Film), or the like may be used.

The electrical connection structure 140 is used as an external connection terminal for mounting a semiconductor chip or a semiconductor package on the passive component embedded substrate 100A. Each of the electrical connection structures 140 may be formed of a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), etc., but this is only an example and the material is It is not particularly limited thereto. The electrical connection structure 140 may be a land, a ball, a pin, or the like. The electrical connection structure 140 may be formed in multiple layers or a single layer. When formed as a multilayer, copper pillars and solder may be included, and when formed as a single layer, tin-silver solder or copper may be included, but this is also only an example and is not limited thereto. .

The second build-up structure 130 also provides various wiring designs so that the passive component-embedded substrate 100A can function as a printed circuit board. The second build-up structure 130 also includes a plurality of second build-up layers 131, a plurality of second wiring layers 132, and a plurality of second wiring via layers 133. A second passivation layer 134 may be disposed on the lowermost side of the second build-up structure 130. The second passivation layer 134 may each have a plurality of openings 134h exposing at least a portion of the lowermost second wiring layer 132. A second electrical connection structure 150 may be disposed in each of the plurality of openings 124h. The second build-up structure 130 may be formed as symmetrical as possible with the first build-up structure 120. That is, the number of layers of the build-up layers 121 and 131 and the number of layers of the wiring layers 122 and 132 may be the same, and the thickness may also be substantially the same. That is, they may be simultaneously formed in a double-sided build-up process based on the core structure 110A.

The second build-up layer 131 may include an insulating material, and as an insulating material, a thermosetting resin such as an epoxy resin, a thermoplastic resin such as polyimide, or these resins are mixed with an inorganic filler, or in the core material of the inorganic filler. Impregnated resin, for example, ABF (Ajinomoto Build-up Film) may be used, but is not limited thereto. The number of layers of the second build-up layer 131 is not particularly limited, and may be variously changed according to design. They may have clear boundaries or unclear boundaries. The thickness of each second build-up layer 131 may be thinner than that of each of the core layers 111a1 and 111a2. In addition, the elastic modulus of each of the second build-up layers 131 may be smaller than that of each of the core layers 111a1 and 111a2. That is, the second build-up layer 131 may also be designed to introduce a plurality of second wiring layers 132 as thin as possible.

The second wiring layer 132 also performs various functions according to the design design of the corresponding layer. For example, a ground (GrouND: GND) pattern, a power (PoWeR: PWR) pattern, a signal (S) pattern, and the like may be included. Here, the signal S pattern includes various signals, for example, data signals, excluding the ground (GND) pattern, the power (PWR) pattern, and the like. In addition, various pads may be included. Materials for forming the second wiring layer 132 include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), and titanium (Ti). ), or a conductive material such as an alloy thereof, specifically a metal material.

The second wiring via layer 133 electrically connects each of the second wiring layers 132 to each other. In addition, the second core wiring layer 116b and the second wiring layer 132 are electrically connected. The second wiring via layer 133 may also include a ground via, a power via, and a signal via, respectively. In addition, as a forming material, copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), or their Conductive materials such as alloys, specifically metal materials, can be used. Each wiring via of the second wiring via layer 133 may have a tapered shape in a direction opposite to that of the connection vias 115a, 115b, and 115c and each of the first wiring via layer 123.

The second passivation layer 134 may protect the second build-up layer 131, the second wiring layer 132, and the second wiring via layer 133. The material of the second passivation layer 134 is also not particularly limited. For example, an insulating material may be used. In this case, a solder resist may be used as the insulating material. However, the present invention is not limited thereto, and the aforementioned prepreg, ABF (Ajinomoto Build-up Film), or the like may be used.

The electrical connection structure 150 is used as an external connection terminal for mounting the passive component embedded substrate 100A on a main board of an electronic device. The electrical connection structure 150 may also be formed of a low melting point metal, for example, a solder such as tin (Sn)-aluminum (Al)-copper (Cu), etc., but this is only an example and the material is It is not particularly limited thereto. The electrical connection structure 150 may be a land, a ball, a pin, or the like. The electrical connection structure 150 may be formed in multiple layers or a single layer. When formed as a multilayer, copper pillars and solder may be included, and when formed as a single layer, tin-silver solder or copper may be included, but this is also only an example and is not limited thereto. .

4 to 10 are process diagrams schematically showing an example of manufacturing the passive component embedded substrate of FIG. 3.

Referring to FIG. 4, first, a first core layer 111a is prepared using a copper clad laminate or the like. In this case, a mark pattern 116c may be formed on at least one surface of the first core layer 111A. Next, one or more through holes 111a1h are formed in the first core layer 111a with a laser drill and/or a mechanical drill. Next, a tape 210 is attached to one side of the first core layer 111a, and at least one passive component (respectively) in one or more through holes 111a1h of the first core layer 111a using the tape 210 112a, 112b, 112c).

Referring to FIG. 5, next, a second insulating layer 111b2 is covered on the tape 210 using a copper foil 220 to cover each of the first core layer 111a1 and the passive components 112a, 112b, and 112c. And lamination to fill at least a part of each of the through holes 111a1h, and then curing. Next, the tape 210 is peeled off. After peeling off the tape 210, one surface of the first core layer 111a1, one surface of the second insulating layer 111b2, and one surface of each of the passive components 112a, 112b, and 112c are coplanar with each other. Next, the copper foil 220 is removed by etching.

Referring to FIG. 6, next, the first copper foil 116b1, the first insulating layer 111b1, and the passive components 112a, 112b, 112c are embedded and the first core layer covered with the second insulating layer 111b2 ( 111a1), the fourth insulating layer 111b4, the third insulating layer 111b3, and the second copper foil 116b2 are collectively stacked in this order to form the basic structure of the core structure 110A described above. The first insulating layer 111b1, the third insulating layer 111b3, and the fourth insulating layer 111b4 are introduced through an uncured prepreg, and the second core layer 111a2 is introduced through an unclad copper clad laminate. I can.

Referring to FIG. 7, next, a through via hole 114h penetrating the basic structure of the core structure 110A prepared by using a mechanical drill and/or a laser drill is formed. In addition, via holes 115ah, 115bh, and 115ch are formed through the first insulating layer 111b1 and exposing the electrodes of each of the passive components 112a, 112b, and 112c. Next, using the first and second copper foils 116as and 116bs as seed layers, the through vias 114 and the connection vias 115a, 115b and 115c and the first and second core wiring layers ( 116a, 116b) is formed. The core structure 110A is manufactured through a series of processes.

Referring to FIG. 8, next, first and second build-up layers 121 and 131 are formed on both sides of the core structure 110A. These can be formed by laminating ABF or the like and then curing them. Next, via holes 123h and 133h are formed in each of the first and second buildup layers 121 and 131 using a laser drill and/or a mechanical drill. Next, first and second wiring via layers 123 and 133 and first and second wiring layers 122 and 132 are formed by a plating process or the like.

Referring to FIG. 9, next, by repeating the above-described series of processes, the first and second build-up layers 121 and 131, the first and second wiring layers 122 and 132, and the first and second build-up layers as needed are repeated. The wiring via layers 123 and 133 are formed. Next, if necessary, the first and second build-up structures 120 and 130 are formed by forming the first and second passivation layers 124 and 134 by laminating ABF or the like and then curing them. When the first and second electrical connection metals 140 and 150 are formed and then subjected to a reflow process, the passive component embedded substrate 100A according to the above-described example may be obtained.

10 is a cross-sectional view schematically showing another example of a passive component embedded substrate.

Referring to the drawings, the passive component embedded substrate 100B according to another example is a through hole 111a1h of the first core layer 111a1 of the core structure 110B in the passive component embedded substrate 100A according to the above-described example. Passive parts 112a, 112b, and 112c having different thicknesses are disposed and built in. In this way, even when the passive components 112a, 112b, and 112c have different thicknesses, one surface of the passive components 112a, 112b, and 112c in contact with the first insulating layer 111b1 is coplanar with each other, and the first Each of the core layer 111a1 and the second insulating layer 111b2 is a coplanar with one surface in contact with the first insulating layer 111a1, but the passive components 112a, 112b, and 112c are each of the second insulating layers 111b2. The other side covered can be located at different levels. In this way, even if the thicknesses of the passive components 112a, 112b, and 112c are different, there is no problem in providing a flat surface. Therefore, the first insulating layer 111b1, the connection vias 115a, 115b, 115c, and the first core wiring layer ( In the process of forming 116a), it is possible to have better via processing and plating quality without problems of defects such as voids or undulation. Other descriptions are substantially the same as those described in FIGS. 3 to 10 above, and detailed descriptions will be omitted.

11 is a cross-sectional view schematically showing another example of a passive component embedded substrate.

Referring to the drawings, a passive component embedded substrate 100C according to another example includes a third core structure 110C disposed on a third insulating layer 111b3 in the passive component embedded substrate 100A according to the above-described example. It further includes a fifth insulating layer 111b5 disposed on the core layer 111a3 and the third core layer 111a3. That is, in order to increase the thickness of the core structure 110C, the third core layer 111a3 may be introduced by attaching an unclad copper clad laminate or the like. In this case, a thicker core structure 110C may be introduced. Meanwhile, it goes without saying that the contents described in the passive component embedded substrate 100B according to another example may also be applied to the passive component embedded substrate 100C according to another example. Other descriptions are substantially the same as those described in FIGS. 3 to 10 above, and detailed descriptions will be omitted.

12 is a schematic cross-sectional view of another example of a passive component embedded substrate.

Referring to the drawings, in the passive component embedded substrate 100D according to another example, in the passive component embedded substrate 100A according to the above-described example, the second core layer 111a2 of the core structure 110D is also at least one through hole ( 111a2h), and one or more passive components 112d, 112e, and 112f are disposed in the one or more through holes 111a2h, respectively. At this time, in the core structure 110D, the fourth insulating layer 111b4 is disposed between the second insulating layer 111b2 and the second core layer 111a2, so that the second core layer 111a2 and the passive components 112d and 112e, 112f) Covers each and fills at least a portion of each of the second through holes 111a2h. If necessary, a fifth insulating layer 111b5 may be further disposed between the second and fourth insulating layers 111b2 and 111b4. Further, the core structure 110D passes through the third insulating layer 111b3, respectively, and the connection vias 115d, 115e, and 115f electrically connect the second core wiring layer 116b to each of the passive components 112d, 112e, and 112f. ). One surface of each of the passive components 112d, 112e, and 112f in contact with the third insulating layer 111b3 can also be coplanar with each other, and the third insulating layer of each of the second core layer 111a2 and the fourth insulating layer 111b4 One surface in contact with the layer 111b3 may be coplanar, and the other surface covered with the fourth insulating layer 111b4 of each of the passive components 112d, 112e, and 112f may be spaced apart from the first core layer 111a1 by a predetermined distance. I can. Also, the heights of each of the connection vias 115d, 115e, and 115f may be the same. Therefore, even in the process of forming the third insulating layer 111b3, the connection vias 115d, 115e, and 115f, and the second core wiring layer 116b, better via processing and plating quality can be achieved without problems such as voids or undulation. Can have. Each of the through holes 111a2h formed in the second core layer 111a2 may be one hole formed to continuously surround the passive components 112d, 112e, and 112f respectively accommodated in the plan view. In addition, the connection vias 115d, 115e, and 115f may be tapered in a direction opposite to the connection vias 115a, 115b, and 115c. Meanwhile, it goes without saying that the contents described in the passive component embedded substrates 100B and 100C according to another example may also be applied to the passive component embedded substrate 100D according to another example. Other descriptions are substantially the same as those described in FIGS. 3 to 11, and detailed descriptions will be omitted.

13 is a schematic cross-sectional view illustrating an example in which a semiconductor package is disposed on a substrate with an embedded passive component.

Referring to the drawings, for example, when using the passive component embedded substrate (100A) as a BGA substrate, the first to third semiconductor chips 311, 312, 313 are mounted on the interposer 314 to be electrically connected to each other semiconductor The package 300 may be mounted on the passive component embedded substrate 100A. At this time, the DSC 400 and the LSC 450 disposed on the conventional BGA substrate are included in the passive component embedded substrate 100A. 112b, 112c), the first to third semiconductor chips 311 and 312 of the semiconductor package 300 through a very short electrical path through the plurality of first wiring layers 122 of the first build-up structure 120, etc. 313) and can be electrically connected. Meanwhile, the first semiconductor chip 311 may be an Application Specific Integrated Circuit (ASIC), and the second and third semiconductor chips 312 and 313 may be High Bandwidth Memory (HBM), but are not limited thereto. On the other hand, it goes without saying that the semiconductor package 300 may be substantially identically mounted to the passive component embedded substrate 100A according to an example, as well as the passive component embedded substrate 100B, 100C, and 100D according to another example.

14 is a schematic cross-sectional view illustrating an example in which a semiconductor chip is disposed on a substrate with an embedded passive component.

Referring to the drawings, when the passive component embedded substrate 100A according to an example is used as a BGA substrate, a packaged semiconductor chip 350 may be mounted on the passive component embedded substrate 100A, and at this time, on a conventional BGA substrate. The arranged DSC 400 and LSC 450 are embedded as passive components 112a, 112b, and 112c in the passive component embedded substrate 100A, so that a plurality of first wiring layers 122 of the first build-up structure 120, etc. Through a very short electrical path, the semiconductor chip 351 in the packaged semiconductor chip 350 may be electrically connected. Meanwhile, the semiconductor chip 351 may be a CPU (Central Processing Unit), but is not limited thereto. On the other hand, it goes without saying that the packaged semiconductor chip 350 may be mounted substantially in the same manner on not only the passive component embedded substrate 100A according to the example, but also the passive component embedded substrate 100B, 100C, and 100D according to another example.

15 schematically shows one effect of the passive component embedded substrate.

Referring to the drawings, when using the passive component embedded substrate (100A, 100B, 100C, 100D) according to the present disclosure according to the present disclosure as in FIG. 13 or 14 instead of the conventional BGA substrate, the passive component embedded substrate (100A, 100B, Passive components 112a, 112b, 112c are embedded in 100C, 100D) and are electrically connected to the semiconductor chip through a very short electrical path.As compared to the case of using DSC and LSC, the distance between the chip and the capacitor is shortened and the substrate parasitic inductance and Impedance can be effectively reduced, and as a result, power integrity characteristics can be effectively improved.

In the present disclosure, the term “coplanner” refers to being positioned at substantially the same level, and is a concept including not only the exact same case, but also a minute position difference that may occur due to an error in the process. Also, that the height is the same is not only that the height is completely the same, but also includes a case where there is a slight height difference that may occur due to an error in the process, that is, the concept that the height is substantially the same.

In the present disclosure, the lower side, the lower side, the lower side, etc. are used to mean the direction toward the mounting surface of the semiconductor package including the organic interposer based on the cross section of the drawing for convenience, and the upper side, the upper side, and the upper surface are used in the opposite direction. I did. However, this defines a direction for convenience of explanation, and it is of course not to say that the scope of the claims is not specifically limited by the description of such direction.

In the present disclosure, the meaning of connection is a concept including not only direct connection but also indirect connection through an adhesive layer or the like. In addition, the meaning of being electrically connected is a concept that includes both physically connected and unconnected cases. In addition, expressions such as first and second are used to distinguish one component from another, and do not limit the order and/or importance of the corresponding components. In some cases, without departing from the scope of the rights, the first component may be referred to as the second component, and similarly, the second component may be referred to as the first component.

The expression example used in the present disclosure does not mean the same embodiment as each other, and is provided to emphasize and describe different unique features. However, the examples presented above are not excluded from being implemented in combination with other example features. For example, even if a matter described in a specific example is not described in another example, it may be understood as a description related to another example unless there is a description contradicting or contradicting the matter in another example.

The terms used in the present disclosure are used only to describe an example, and are not intended to limit the present disclosure. In this case, the singular expression includes a plural expression unless it clearly means differently in the context.

Claims (16)

A first insulating layer, a first core layer disposed on the first insulating layer and having at least one first through hole, a first surface on which a mark pattern is disposed, and a second surface opposite to the first surface, the first One or more first passive parts disposed in one through hole, a second insulating layer covering the first passive part and filling at least a part of the first through hole, a second core layer disposed on the second insulating layer, and A core structure including a third insulating layer disposed on the second core layer;
A first build-up structure disposed on one side of the core structure and including a plurality of first build-up layers and a plurality of first wiring layers; And
A second build-up structure disposed on the other side of the core structure and including a plurality of second build-up layers and a plurality of second wiring layers; Including,
The second surface of the first core layer is coplanar with a boundary surface between the first insulating layer and the second insulating layer,
The second surface of the first core layer is coplanar with one surface of the electrode in contact with the first insulating layer of the first passive component,
Substrate with built-in passive components.
The method of claim 1,
The core structure includes a first core wiring layer disposed on the second surface of the first core layer, and a first core wiring layer penetrating the first insulating layer and electrically connecting the first core wiring layer to the first passive component. It further includes a connection via,
The first core wiring layer is electrically connected to the plurality of first wiring layers,
The second surface of the first core layer is coplanar with one surface of the first connection via in contact with the electrode of the first passive component,
Substrate with built-in passive components.
The method of claim 1,
The distance from the second surface of the first core layer to the mark pattern is greater than the thickness of the first passive component,
Substrate with built-in passive components.
The method of claim 1,
At least one of the mark patterns is electrically insulated from the plurality of first and second wiring layers,
No wiring layer is disposed on the second surface of the first core layer,
Substrate with built-in passive components.
The method of claim 1,
The first passive component includes one or a plurality of passive components,
One surface of each of the one or more passive components in contact with the first insulating layer is coplanar with each other,
The other surfaces covered with the second insulating layer of each of the one or more passive components are located at different levels,
Substrate with built-in passive components.
The method of claim 1,
The core structure further includes a fourth insulating layer disposed between the second insulating layer and the second core layer,
The second insulating layer and the fourth insulating layer contain the same material,
The second insulating layer and the fourth insulating layer are in direct contact,
Substrate with built-in passive components.
The method of claim 2,
The core structure includes a second core wiring layer disposed on a side opposite to the side on which the second core layer is disposed of the third insulating layer, and the first insulating layer, the first core layer, the second insulating layer, and the Further comprising a through via passing through both the second core layer and the third insulating layer and electrically connecting the first core wiring layer and the second core wiring layer,
The second core wiring layer is electrically connected to the plurality of second wiring layers,
Substrate with passive components.
The method of claim 7,
The first build-up structure further includes a plurality of first wiring via layers passing through the plurality of first build-up layers and electrically connecting the plurality of first wiring layers, respectively,
The plurality of first wiring via layers have a maximum width greater than a maximum width of the 1-1 wiring via layer and the 1-1 wiring via layer electrically connected to the first passive component, and a first wiring via layer electrically connected to the through via. -2 comprising a wiring via layer,
Substrate with built-in passive components.
The method of claim 1,
The core structure,
A second passive component disposed in at least one second through hole of the second core layer;
A fourth insulating layer covering the second passive component and filling at least a portion of the second through hole;
A fifth insulating layer between the second insulating layer and the fourth insulating layer;
A second core wiring layer disposed on one surface of the second core layer; And
A second connection via penetrating the third insulating layer and electrically connecting the second core wiring layer to the second passive component; and
The second core wiring layer is electrically connected to the plurality of second wiring layers,
Substrate with passive components.
The method of claim 1,
The first build-up structure,
A first passivation layer disposed on the second surface of the first core layer and having a plurality of first openings exposing at least a portion of an uppermost first wiring layer among the plurality of first wiring layers; And
A first electrical connection metal disposed on the first passivation layer and electrically connected to the plurality of first wiring layers through the plurality of first openings, further comprising:
The second build-up structure,
A second passivation layer disposed on the first surface of the first core layer and having a plurality of second openings exposing at least a portion of a lowermost second wiring layer among the plurality of second wiring layers; And
A second electrical connection metal disposed on the second passivation layer and electrically connected to the plurality of second wiring layers through the plurality of second openings, further comprising:
Further comprising one or more semiconductor chips electrically connected to the first electrical connection metal on the second surface of the first core layer,
Substrate with built-in passive components.
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