KR102143952B1 - Low power adaptive equalizer and operation method thereof - Google Patents

Abstract

According to an embodiment of an application of the present invention, a low-power adaptive equalizer comprises: an extractor which generates each pulse train for each equalization coefficient by using each pair of slicer signals based on each equalization signal to be equalized; a counter for counting a normal pulse having a magnitude of a predetermined level or more for every predetermined unit time in the pulse train; and an equalization coefficient controller which determines an equalization coefficient corresponding to at least one pulse train among the equalization coefficients as an optimal equalization coefficient, based on the at least one pulse train having the maximum number of normal pulses.

Description

Low power adaptive equalizer and its operation method {LOW POWER ADAPTIVE EQUALIZER AND OPERATION METHOD THEREOF}

The present application relates to a low-power adaptive equalizer and a method of operating the same, and more particularly, to a low-power adaptive equalizer for reducing power consumption by quickly determining an optimum equalization coefficient, and a method of operating the same.

The equalizer is a circuit used to compensate for data distortion (ISI, jitter, etc.) caused by channel attenuation. In particular, the equalizer can reduce inter-symbol interference (ISI) and jitter of data, thereby minimizing the bit error rate (BER) when recovering data at the receiving end due to channel attenuation.

These equalizers include Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalizer (DFE). Specifically, a continuous-time linear equalizer can effectively remove long-tail ISI at the same time as amplifying high frequency components, and a decision feedback equalizer can remove ISI according to the number of taps without noise amplification.

Recently, as the data transmission speed increases, data distortion due to channel attenuation increases, resulting in severe data distortion, and the channel characteristics are slightly different depending on various factors even between channels of the same type, and the role of an equalizer is becoming important in high-speed transceivers. . In particular, the high-speed transceiver is the most efficient when using a continuous-time linear equalizer and a decision feedback equalizer, which have advantages and disadvantages, and it is difficult to determine the optimal equalization coefficient (EQ _OPT ) from the outside. Adaptive Equalizer).

Accordingly, in the present application, by quickly and efficiently determining the optimal equalization coefficient (EQ _OPT ), it is intended to provide a low-power adaptive equalizer that can be implemented as a digital circuit capable of microprocessing while reducing power consumption.

The purpose of this application is a low-power adaptive that can be implemented as a digital circuit capable of microprocessing while reducing power consumption by simply extracting the degree of equalization for an input signal and quickly determining the optimal equalization coefficient (EQ _OPT ). To provide an equalizer.

The low-power adaptive equalizer according to an embodiment of the present application is an extractor that generates each pulse train for each equalization coefficient using a pair of slicer signals based on each equalization signal, and a predetermined value for each unit time in the pulse train. Optimal equalization of an equalization coefficient corresponding to the at least one pulse train among the equalization coefficients, based on a counter for counting normal pulses having a level greater than or equal to a predetermined time and at least one pulse train in which the number of normal pulses is the maximum It includes an equalization coefficient controller that determines by coefficient.

In an embodiment, further comprising a frequency divider for dividing each of the pulse trains by a preset frequency ratio and providing each of the low speed pulse trains to the counter.

In an embodiment, the extractor extracts each pair of slicer signals output through a comparator for comparing each equalization signal and a reference voltage.

In an embodiment, the comparator outputs at least one pair of slicer signals corresponding to the optimal equalization coefficients according to a minimum value of a delay time that varies according to each equalization coefficient.

In an embodiment, the delay time is increased according to an equalization coefficient spaced apart from the optimal equalization coefficient.

In an embodiment, among the pair of slicer signals, the other pair of slicer signals that are abnormally output according to the delay time of the comparator include abnormal state information of equalization coefficients corresponding to the remaining pair of slicer signals.

In an embodiment, a first inverter inverting a first slicer signal of each pair of slicer signals into a first inverting signal, and inverting a second slicer signal of each pair of slicer signals into a second inverting signal And an OR gate for generating each pulse train based on the second inverter and the first and second inverting signals.

In an embodiment, when one of the first and second inverting signals is less than a reference level, the OR gate performs a logical operation on any one of the first and second inverting signals at a LOW level.

In an embodiment, an SR latch for receiving and storing each pair of slicer signals, a flip-flop for outputting an output signal by sampling the pair of slicer signals stored in the SR latch according to a preset clock CLK, According to each of the equalization coefficients, a linear equalizer that linearly equalizes an input signal transmitted from a transmitter and outputs each linear equalization signal to an adder, and a gain according to each equalization coefficient and the product of each pair of slicer signals And a decision feedback equalizer that feeds back to and outputs the equalized signal through the adder.

A method of operating a low-power adaptive equalizer according to an embodiment of the present application, comprising: extracting, by an extractor, a pair of slicer signals output through a comparator according to each equalization signal equalized for each equalization coefficient, and the extractor Generating each pulse train using a pair of slicer signals, counting normal pulses having a magnitude of a predetermined level or more for a predetermined time in each of the pulse trains by a counter, and the number of the normal pulses by an equalization coefficient controller And determining an equalization coefficient corresponding to at least one pulse train having a maximum value as an optimal equalization coefficient.

In an embodiment, the frequency divider further comprises the step of dividing each pulse train by a preset frequency ratio, and providing each low-speed pulse train to the counter.

In an embodiment, the generating of each pulse train comprises inverting a first slicer signal of each pair of slicer signals into a first inverting signal, and a second slicer signal of each pair of slicer signals And inverting to a second inverting signal, and outputting the respective pulse trains by performing an OR logic operation on the first and second inverting signals.

In an embodiment, the outputting of each pulse train includes the step of performing a logic operation on one of the first and second inverting signals at a LOW level when one of the first and second inverting signals is less than a reference level.

The low-power adaptive equalizer according to the exemplary embodiment of the present application has an effect of being able to simply extract the equalization degree for each equalization signal equalized according to each equalization coefficient without a conventional EYE data monitoring device.

In addition, by quickly and efficiently determining the optimal equalization coefficient (EQ _OPT ), it is possible to reduce power consumption and implement a digital circuit capable of fine processing.

1 is a block diagram of an adaptive equalizer according to an embodiment of the present application.
2 is a diagram illustrating a change in the number of normal pulses according to each equalization coefficient of FIG. 1.
FIG. 3 is a diagram illustrating a pair of slicer signals of FIG. 1.
4 is a diagram illustrating a delay time of a comparator according to the equalization coefficient of FIG. 1.
5 is an operation process of a low power adaptive equalizer according to an embodiment of the present application.
6 is a diagram showing in detail the extractor of FIG. 3.
7 is an operational process for the extractor of FIG. 6.
8 is a diagram showing in detail the adaptive equalizer of FIG. 1.
9 is a waveform for an input/output signal according to an embodiment of the adaptive equalizer of FIG. 8.
10 is a waveform diagram of an input/output signal according to another embodiment of the adaptive equalizer of FIG. 8.
11 is a waveform diagram of an input/output signal according to another embodiment of the adaptive equalizer of FIG. 8.
12 is a diagram illustrating in detail an adaptive equalizer according to another embodiment.
13(a) is an EYE diagram measured with a parameter of 16 Gb/s, 30-dB loss chnnel.
13(b) is an EYE diagram measured with a parameter of 16Gb/s, 15-dB loss chnnel.

Specific structural or functional descriptions of the embodiments according to the concept of the present application disclosed in the present specification are exemplified only for the purpose of describing the embodiments according to the concept of the present application, and the embodiments according to the concept of the present application are It may be implemented in various forms and is not limited to the embodiments described herein.

Since the embodiments according to the concept of the present application can apply various changes and have various forms, the embodiments will be illustrated in the drawings and described in detail in the present specification. However, this is not intended to limit the embodiments according to the concept of the present application to specific disclosed forms, and includes all changes, equivalents, or substitutes included in the spirit and scope of the present application.

Terms such as first or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are only for the purpose of distinguishing one component from other components, for example, without departing from the scope of rights according to the concept of the present application, the first component may be named as the second component, and similarly The second component may also be referred to as a first component.

When a component is referred to as being "connected" or "connected" to another component, it is understood that it is directly connected to or may be connected to the other component, but other components may exist in the middle. Should be. On the other hand, when a component is referred to as being "directly connected" or "directly connected" to another component, it should be understood that there is no other component in the middle. Other expressions describing the relationship between components, such as "between" and "just between" or "adjacent to" and "directly adjacent to" should be interpreted as well.

Terms used in the present specification are used only to describe specific embodiments, and are not intended to limit the present application. Singular expressions include plural expressions unless the context clearly indicates otherwise. In the present specification, terms such as "comprise" or "have" are intended to designate the presence of implemented features, numbers, steps, actions, components, parts, or a combination thereof, but one or more other features or numbers It is to be understood that it does not preclude the possibility of the presence or addition of, steps, actions, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person of ordinary skill in the art to which this application belongs. Terms as defined in a commonly used dictionary should be interpreted as having a meaning consistent with the meaning in the context of the related technology, and should not be interpreted as an ideal or excessively formal meaning unless explicitly defined in the present specification. Does not.

Hereinafter, the present application will be described in detail by describing a preferred embodiment of the present application with reference to the accompanying drawings.

1 is a block diagram of an adaptive equalizer 100 according to an embodiment of the present application. 2 is a diagram showing a change in the number of normal pulses according to each equalization coefficient of FIG.

Referring to FIGS. 1 and 2, the adaptive equalizer 100 may include an extractor 110, a counter 120, and an equalization coefficient controller 130.

First, the extractor 110 uses each pair of slicer signals (S _IN ) based on each equalization signal (D _EQ ), and converts each pulse train (P _TRAIN ) into equalization coefficients (e.g., EQ1 to EQN). Can be generated.

Specifically, the equalization signal D _EQ is a signal equalized by the linear equalizer 154 or the decision feedback equalizer 155 according to each of the equalization coefficients (eg, EQ1 to EQN) from the input signal D _IN . For example, D1_EQ1 to D1_EQN and D2_EQ1 to D2_EQN) may be differential input signals input to the extractor 110. Subsequently, the equalization coefficients (eg, EQ1 to EQN) may be parameters that are linearly adjusted to compensate for channel distortion that appears above the level or phase of the input signal D _IN . That is, each equalization signal (eg, D1_EQ1 to D1_EQN, D2_EQ1 to D2_EQN) may correspond to each equalization coefficient (eg, EQ1 to EQN).

In addition, the pair of slicer signals S _IN is a sawtooth-shaped pulse based on each equalization signal (e.g., D1_EQ1-D1_EQN, D2_EQ1-D2_EQN) linearly equalized for each of the equalization coefficients (e.g., EQ1-EQN). It may be a signal that occurs every time (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N). Subsequently, the pulse train P _TRAIN is a signal (eg, P _TRAIN 1 to P _TRAIN N) in which a square wave-shaped pulse is generated every unit time, and may correspond to the shape of the clock CLK. That is, each pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) may correspond to each pulse train (eg, P _TRAIN 1 to P _TRAIN N).

That is, each pulse train (e.g., P _TRAIN 1 to P _TRAIN N) is each equalization coefficient (e.g., EQ1 to EQN), each equalization signal (e.g., D1_EQ1 to D1_EQN, D2_EQ1 to D2_EQN), and each pair of slicer signals (e.g. , S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) information may be included.

Next, the counter 120 may count normal pulses in each pulse train (eg, P _TRAIN 1 to P _TRAIN N). Here, the normal pulse may be a square wave signal having a magnitude of a predetermined level or more per unit time.

Specifically, the counter 120 may count the number of normal pulses (N _PN ) having a magnitude greater than or equal to a predetermined level per unit time for a predetermined time for each pulse train (eg, P _TRAIN 1 to P _TRAIN N). In this case, the counter 120 may skip a counting operation for an abnormal pulse having a magnitude less than a predetermined level per unit time for each pulse train (eg, P _TRAIN 1 to P _TRAIN N).

Next, the equalization coefficient controller 130 is based on at least one pulse train in which the number of normal pulses (N _PN ) is the maximum among each pulse train (P _TRAIN 1 to P _TRAIN N), the equalization coefficients (e.g., EQ1 to EQN), an equalization coefficient corresponding to at least one pulse train may be determined as an optimal equalization coefficient EQ _OPT .

As illustrated in FIG. 2, the optimum equalization coefficient EQ _OPT may be an equalization coefficient corresponding to at least one pulse train having a maximum number of normal pulses N _PN among a plurality of pulse trains. Specifically, the optimal equalization coefficient (EQ _OPT ) is the corresponding equalization coefficient (e.g., EQ5 to EQ9) of at least one pulse train whose number of normal pulses (N _PN ) is the maximum among each pulse train (P _TRAIN 1 to P _TRAIN N). ) Can be. That is, the equalization coefficient controller 130 adjusts at least one equalization coefficient (e.g., EQ5 to EQ9) corresponding to at least one pulse train in which the normal pulse is the maximum among each equalization coefficient (e.g., EQ1 to EQN). EQ _OPT ) can be judged.

At this time, the equalization coefficient controller 130 may reset the counting operation of the counter 120. Specifically, the equalization coefficient controller 130 resets the counting operation of the counter 120 whenever each equalization coefficient (e.g., EQ1 to EQN) is changed, and in each pulse train (e.g., P _TRAIN 1 to P _TRAIN N). The number of counted normal pulses can be initialized.

In the technical idea according to the embodiment of the present application, the adaptive equalizer 100 includes a pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S1_N) extracted through the extractor 110 S2_N), without a conventional EYE data monitoring device, simply monitor the equalization state for each equalization signal (e.g., D1_EQ1 to D1_EQN, D2_EQ1 to D2_EQN) equalized according to each equalization coefficient (e.g., EQ1 to EQN). can do.

In addition, the adaptive equalizer 100 is each pulse train from each pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) through the extractor 110 (P _TRAIN 1 ~ P _TRAIN N) is generated, and the number of normal pulses can be counted through the counter 120. At this time, the adaptive equalizer 100 is based on at least one pulse train (e.g., P _TRAIN 5 to P _TRAIN 9) in which the number of normal pulses (N _PN ) is the maximum through the equalization coefficient controller 130 By determining the coefficient EQ _OPT quickly and efficiently, there is an effect of reducing power consumption and enabling the digital circuit to be implemented.

FIG. 3 is a diagram illustrating a pair of slicer signals of FIG. 1, and a diagram illustrating a delay time TD of the comparator 151 according to the equalization coefficient of FIG. 1.

3 and 4, the comparator 151 compares each equalization signal (e.g., D1_EQ1 to D1_EQN, D2_EQ1 to D2_EQN) and a reference voltage to be linearly equalized according to a preset clock CLK, and each pair of slicers Signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) may be output.

Here, each pair of slicer signals (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) are each first slicer signal (e.g., S1_1, S1_2, ..., S1_N) and each second slicer Signals (eg, S2_1, S2_2, ..., S2_N) may be included.

At this time, as shown in FIG. 4, the minimum value of the delay time (TD) of the comparator 151 that changes according to the equalization coefficients (e.g., EQ1 to EQN) is an optimal equalization coefficient (e.g., EQ4 to EQ5 interval). I can. In this case, the comparator 151 may normally output a pair of slicer signals corresponding to the optimal equalization coefficient (eg, EQ5 to EQ9 interval) according to the delay time of the minimum value.

Meanwhile, the delay time TD of the comparator 151 may increase as the distance from the optimum equalization coefficient (eg, EQ5 to EQ9 interval) is separated. At this time, the comparator 151 may abnormally output a pair of slicer signals corresponding to the optimal equalization coefficient (e.g., EQ5 to EQ9 interval) and the spaced equalization coefficient (e.g., EQ1) as the delay time (TD) increases. have.

According to an embodiment, the extractor 110 extracts a pair of slicer signals output through the comparator 151, and thus corresponds to the minimum value of the delay time TD of the comparator 151 among the respective equalization coefficients EQ1 to EQN. It may be possible to determine the optimal equalization coefficient (eg, EQ5 ~ EQ9 interval).

5 is an operation process of the low power adaptive equalizer 100 according to an embodiment of the present application.

1 to 5, first, in step S110, the extractor 110 outputs through the comparator 151 according to each equalization signal (D _EQ1 to D _EQN ) equalized by equalization coefficients (EQ1 to EQN). Each pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) may be extracted.

Here, each equalization coefficient (EQ1 ~ EQN) is associated with each equalized signal (D _EQ1 ~ D _EQN), each equalized signal (D _EQ1 ~ D _EQN) is (for example, each pair of slicers signal, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N). That is, each equalization coefficient EQ1 to EQN may correspond to a pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N).

Then, in step S120, the extractor 110 uses each pair of slicer signals (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N), each pulse train (e.g., P _TRAIN 1 ~ P _TRAIN N) can be created.

Next, in step S130, the counter 120 may count a normal pulse having a magnitude of a predetermined level or more for each unit time in each pulse train (eg, P _TRAIN 1 to P _TRAIN N) for a predetermined time.

Thereafter, in step S140, the equalization coefficient controller 130 optimizes at least one equalization coefficient corresponding to at least one pulse train in which the number of normal pulses is the maximum among each pulse train (eg, P _TRAIN 1 to P _TRAIN N). It can be judged by the equalization coefficient.

According to an embodiment, when there are a plurality of at least one equalization coefficient corresponding to at least one pulse train in which the number of normal pulses is the maximum, the equalization coefficient controller 130 determines the intermediate value of the at least one equalization coefficient. It can be judged as. For example, when at least one equalization coefficient is 5, 6, and 7, the equalization coefficient controller 130 may determine the intermediate value of 6 among the at least one equalization coefficient as the optimal equalization coefficient.

According to another embodiment, when the median value is at least two or more, the equalization coefficient controller 130 may determine the minimum value among the median values as the optimum equalization coefficient. For example, when at least one equalization coefficient is 5, 6, 7, and 8, the equalization coefficient controller 130 may determine a small value of 6 as an optimal equalization coefficient from 6 and 7 which are intermediate values of the equalization coefficients. .

6 is a diagram showing in detail the extractor 110 of FIG. 3.

3 and 6, the extractor 110 may include a first inverter 111, a second inverter 112 and an OR gate 113.

First, the first inverter 111 is each of a pair of slicer signals (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) output from the comparator 151, each of the first slicer signal (e.g., S1_1 ~S1_N) can be extracted. At this time, the first inverter 111 may invert each of the first slicer signals (eg, S1_1 to S1_N) to each of the first inverting signals (eg, INV1_1 to INV1_N) and output them to the OR gate 113. .

For example, the first inverter 111 extracts a first slicer signal (eg, S1_1) from among a first pair of slicer signals (eg, S1_1 and S2_1), and converts the first slicer signal (eg, S1_1) to a first The inverting signal (eg, INV1_1) may be inverted and output to the OR gate 113.

Next, the second inverter 112 is each second slicer signal (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) of each pair of slicer signals output from the comparator 151 S2_1~S2_N) can be extracted. At this time, the second inverter 112 may invert each second slicer signal (e.g., S2_1 to S2_N) to each second inverting signal (e.g., INV2_1 to INV2_N) and output to the OR gate 113 .

For example, the second inverter 112 extracts a second slicer signal (eg, S2_1) from among the first pair of slicer signals (eg, S1_1 and S2_1), and converts the second slicer signal (eg, S2_1) to a second By inverting with an inverting signal (eg, INV2_1), the OR gate 113 may be output.

Next, the OR gate 113 may generate each pulse train (eg, P _TRAIN 1 to P _TRAIN N) based on each of the first and second inverting signal signals (eg, INV1_1 and INV2_1). Here, each pulse train (eg, P _TRAIN 1 to P _TRAIN N) may include at least one of a normal pulse having a magnitude of a predetermined level or higher per unit time and an abnormal pulse having a magnitude of a predetermined level or higher per unit time.

In the present application, it is described as an OR gate 113 that adds up each of the first and second inverting signal signals (eg, INV1_1 and INV2_1), but depending on the structure of the counter 120 and the frequency divider 140, the NOR gate or It can be transformed into various other structures.

7 is an operational process for the extractor 110 of FIG. 6.

6 and 7, first, in step S121, the first inverter 111 extracts a first slicer signal from a pair of slicer signals output through the comparator 151, and transmits the first slicer signal to the first inverting signal. You can butt. In this case, in step S122, the second inverter 112 may extract the second slicer signal from each pair of slicer signals output through the comparator 151 and invert the second inverting signal.

Then, in step S123, the OR gate 113 may receive the first and second inverting signals through the first and second inverters 111 and 112. Here, since the first and second slicer signals have a level complementary to each other for each unit time, the first and second inverting signals may have a level complementary to each other for each unit time.

At this time, in step S124, when performing the R logic operation on the first and second inverting signals, when any one is less than the reference level, the OR gate 113 performs an OR logic operation at a LOW level for the first and second inverting signals. Can be done. That is, since the first and second inverting signals are at complementary levels for each unit time, when any one of the above is OR logic operated at a LOW level, the OR gate 113 is used for both the first and second inverting signals. OR logic operation can be performed at the LOW level.

Thereafter, in step S125, the OR gate 113 may output a pulse train generated through an OR logic operation for each equalization coefficient.

8 is a diagram showing in detail the adaptive equalizer 100 of FIG. 1, FIG. 9 is a waveform for an input/output signal according to an embodiment of the adaptive equalizer 100 of FIG. 8, and FIG. 8 is a waveform for an input/output signal according to another embodiment of the adaptive equalizer 100 of FIG. 8, and FIG. 11 is a waveform for an input/output signal according to another embodiment of the adaptive equalizer 100 of FIG. 8.

1 to 8, the adaptive equalizer 100 includes an extractor 110, a counter 120, an equalization coefficient controller 130, a comparator 151, an SR latch 152, and a flip-flop 153. , A linear equalizer 154 and a decision feedback equalizer 155 may be included.

Hereinafter, a redundant description of the extractor 110, the counter 120, and the equalization coefficient controller 130 of the same reference number described in FIGS. 1 to 7 will be omitted.

Next, the comparator 151 may receive each equalized signal D _EQ through the linear equalizer 154 and compare each equalized signal D _EQ with a reference voltage according to the clock CLK. .

At this time, the comparator 151 is based on the voltage difference between each equalization signal (D _EQ ) and the reference voltage, each first slicer signal (eg, S1_1 to S1_N) and each second slicer signal (eg, S2_1 to S2_N) Each pair of slicer signals including S1_1 and S2_1 (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) may be output to the SR latch 152.

As shown in FIG. 9, when a pair of slicer signals (eg, S1_1 and S2_1) output through the comparator 151 does not contain an abnormal pulse having a magnitude less than a predetermined level per unit time, the extractor 110 _May output a pulse train (eg, P _TRAIN1 ) formed of a square wave of a constant size. Here, the pulse train (eg, P _TRAIN1 ) may correspond to at least one of the equalization coefficients (eg, EQ1 to EQN) (eg, EQ5 to EQ9).

Specifically, the first and second inverters 111 and 112 invert a first slicer signal (eg, S1_1) among a pair of slicer signals (eg, S1_1 and S2_1) to a first inverting signal (eg, INV1_1). Then, the second slicer signal (eg, S2_1) may be inverted into a second inverting signal (eg, INV2_1).

Here, since the first and second slicer signals (eg, S1_1 and S2_1) correspond to differential signals that are complementary to each other for each unit time, the first and second inverting signals (eg, INV1_1 and INV2_1) may be complementary to each other. . In this case, the OR gate 113 may output a pulse train (eg, P _TRAIN ) formed of a square wave having a predetermined size based on the first and second inverting signals (eg, INV1_1 and INV2_1).

As shown in FIGS. 10 and 11, when a pair of slicer signals (eg, S1_1 and S2_1) output through the comparator 151 includes abnormal pulses having a magnitude less than a predetermined level per unit time, the extractor ( 110) may output a pulse train (eg, P _TRAIN2 ) including a square wave having an irregular size. Here, the pulse train (eg, P _TRAIN2 ) may correspond to the remaining equalization coefficients excluding at least one of the equalization coefficients (eg, EQ1 to EQN) (eg, EQ5 to EQ9).

Specifically, the extractor 110 inverts a first slicer signal (eg, S1_1) of a pair of slicer signals (eg, S1_1 and S2_1) to a first inverting signal (eg, INV1_1), and a second slicer signal ( For example, S2_1 may be inverted to a second inverting signal (eg, INV2_1). In this case, when any one of the first and second inverting signals (eg, INV1_1 and INV2_1) is at a level less than the reference level, the extractor 110 may perform a logical operation on any of the above at a LOW level.

Specifically, as illustrated in FIG. 10, the extractor 110 may perform a logical operation on a first inverting signal (eg, INV1_1) having a magnitude less than a predetermined level at a LOW level. For example, when the first inverting signal (eg, INV1_1) has a magnitude less than a predetermined level, and the second inverting signal (eg, INV2_1) complementary to the first inverting signal (eg, INV1_1) is LOW , The OR gate 113 may output a LOW signal.

In addition, as illustrated in FIG. 10, the OR gate 113 may perform a logical operation on a second inverting signal (eg, INV2_1) having a size less than a predetermined level at a LOW level. For example, when the second inverting signal (eg, INV2_1) has a magnitude less than a predetermined level, and the first inverting signal (eg, INV2_1) complementary to the second inverting signal (eg, INV2_1) is LOW , The OR gate 113 may output a LOW signal.

Next, the SR latch 152 may store each pair of slicer signals (eg, S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) output from the comparator 151.

Next, the flip-flop 153 samples each pair of slicer signals (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) stored in the SR latch 152 according to the clock CLK. , Output signal (D _OUT ) can be output.

Next, the linear equalizer 154 linearly equalizes the input signal DIN according to equalization coefficients (e.g., EQ1 to EQN), and generates each equalization signal (e.g., D1_EQ1 to D1_EQN, D2_EQ1 to D2_EQN). It can be output to the comparator 151.

Next, the decision feedback equalizer 155 may include a gain unit 155_1 and an adder 155_2.

Specifically, the gain unit 155_1 is determined through each pair of slicer signals stored in the SR latch 152 (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N) and the equalization coefficient controller 130 The product of the gain according to the optimized equalization coefficient may be fed back to the adder 155_2.

At this time, the adder 155_2 calculates an input signal (DIN) transmitted from the transmitter based on the product between the gain and each pair of slicer signals (e.g., S1_1 and S2_1, S1_2 and S2_2, ..., S1_N and S2_N). It can be optimally equalized.

12 is a diagram illustrating in detail an adaptive equalizer 100_1 according to another embodiment.

Referring to FIG. 12, the adaptive equalizer 100_1 includes an extractor 110, a counter 120, an equalization coefficient controller 130, a frequency divider 140, a comparator 151, an SR latch 152, and a flip-flop. 153, a linear equalizer 154 and a decision feedback equalizer 155 may be included.

Hereinafter, the extractor 110, the counter 120, the equalization coefficient controller 130, the comparator 151, the SR latch 152, the flip-flop 153, the linear equalization described in FIGS. 1 to 11 A redundant description of the machine 154 and the decision feedback equalizer 155 will be omitted.

The frequency divider 140 according to the embodiment divides each pulse train (e.g., P _TRAIN 1 to P _TRAIN N) by a preset frequency ratio, and each low speed pulse train (e.g., P _TRAIN 1 to P _TRAIN N) May be provided as the counter 120. Thereafter, the counter 120 may perform an asynchronous counting operation for each low-speed pulse train (eg, P _TRAIN 1 to P _TRAIN N).

Accordingly, the frequency divider 140 increases the timing margin reduced due to a delay difference between the MSB (Most Significant Bit) corresponding to the critical path delay of the counter 120 and the LSB (LSB) corresponding to the minimum delay. I can do it.

FIG. 13(a) is an EYE diagram measured with a parameter of 16 Gb/s, 30-dB loss chnnel, and FIG. 13(b) is an EYE diagram measured with a parameter of 16 Gb/s, 15-dB loss chnnel.

13(a) and 13(b), the adaptive equalizer 100 of FIGS. 1 to 12 can appropriately equalize the input signal regardless of the change in the input signal whose channel attenuation is twice. I can.

Although the present application has been described with reference to an exemplary embodiment illustrated in the drawings, this is only exemplary, and those of ordinary skill in the art will understand that various modifications and equivalent other exemplary embodiments are possible therefrom. Therefore, the true technical protection scope of the present application should be determined by the technical idea of the attached registration claims.

100: adaptive equalizer
110: extractor
120: counter
130: equalization coefficient controller
140: frequency divider

Claims (12)

An extractor for generating each pulse train for each equalization coefficient using each pair of slicer signals based on each equalization signal;
A counter for counting a normal pulse having a magnitude of a predetermined level or more for a predetermined time in the pulse train for each unit time;
An equalization coefficient controller that determines an equalization coefficient corresponding to the at least one pulse train among the equalization coefficients as an optimal equalization coefficient based on at least one pulse train having a maximum number of normal pulses;
An SR latch for receiving and storing each pair of slicer signals;
A flip-flop for sampling each pair of slicer signals stored in the SR latch according to a preset clock CLK and outputting an output signal;
A linear equalizer that linearly equalizes an input signal transmitted from a transmitter according to each equalization coefficient and outputs each linear equalization signal to an adder; And
A low power adaptive equalizer comprising a decision feedback equalizer for outputting the equalized signal through the adder by feeding back a product of the gain according to each equalization coefficient and the pair of slicer signals to the adder. The method of claim 1,
Further comprising a frequency divider for dividing each of the pulse trains by a preset frequency ratio and providing each of the low speed pulse trains to the counter. The method of claim 1,
The extractor, for extracting each pair of slicer signals output through a comparator for comparing the equalization signal and a reference voltage, low power adaptive equalizer. The method of claim 3,
The comparator outputs at least one pair of slicer signals corresponding to the optimum equalization coefficients according to a minimum value of a delay time varying according to the respective equalization coefficients. The method of claim 4,
The delay time is increased according to an equalization coefficient spaced apart from the optimal equalization coefficient. The method of claim 1,
A first inverter for inverting a first slicer signal of each of the pair of slicer signals into a first inverting signal;
A second inverter for inverting a second slicer signal of each of the pair of slicer signals into a second inverting signal; And
And an OR gate that generates each of the pulse trains based on the first and second inverting signals. The method of claim 6,
The OR gate, when any one of the first and second inverting signals is less than a reference level, performs a logical operation on the one of the first and second inverting signals at a LOW level. delete As a method of operating a low power adaptive equalizer,
Extracting, by an extractor, each pair of slicer signals output through a comparator according to each equalization signal equalized for each equalization coefficient;
Generating, by the extractor, each pulse train using the pair of slicer signals;
Counting, by a counter, a normal pulse having a magnitude of a predetermined level or more for a predetermined time per unit time in each pulse train:
An equalization coefficient controller determining an equalization coefficient corresponding to at least one pulse train having a maximum number of normal pulses as an optimal equalization coefficient,
The low-power adaptive equalizer includes: an SR latch configured to receive and store each pair of slicer signals;
A flip-flop for sampling each pair of slicer signals stored in the SR latch according to a preset clock CLK and outputting an output signal;
A linear equalizer that linearly equalizes an input signal transmitted from a transmitter according to each equalization coefficient and outputs each linear equalization signal to an adder; And
And a decision feedback equalizer for outputting the equalized signal through the adder by feeding back a product of the gain according to each equalization coefficient and the pair of slicer signals to the adder. The method of claim 9,
The method of operating a low-power adaptive equalizer, further comprising the step of: a frequency divider dividing each pulse train by a preset frequency ratio and providing each low-speed pulse train to the counter. The method of claim 9,
The generating of each pulse train may include inverting a first slicer signal of each of the pair of slicer signals into a first inverting signal;
Inverting a second slicer signal of each pair of slicer signals into a second inverting signal; And
And outputting the respective pulse trains by performing an OR logic operation on the first and second inverting signals. The method of claim 11,
The outputting of each of the pulse trains comprises the step of performing a logic operation on the one of the first and second inverting signals at a LOW level when any one of the first and second inverting signals is less than the reference level. How to operate.

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