KR102139942B1 - Semiconductor Memory Device And Method Of Fabricating The Same - Google Patents

Abstract

The present invention relates to a three-dimensional semiconductor memory device and a method of manufacturing the same, repeatedly forming a thin film structure by alternately stacking sacrificial films and insulating films on a substrate, and a channel hole through the thin film structure to expose the substrate Forming, surface treating the sacrificial films exposed in the channel hole, forming a channel structure in the channel hole, forming a trench spaced apart from the channel structure and penetrating the thin film structure, and Provided is a method of manufacturing a 3D semiconductor memory device including replacing the sacrificial layers exposed in the trenches with gate patterns.

Description

Semiconductor memory device and its manufacturing method

The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor memory device having memory cells arranged in three dimensions and a method of manufacturing the same.

In order to meet the excellent performance and low price required by consumers, it is required to increase the degree of integration of semiconductor devices. In the case of a semiconductor device, since the integration degree is an important factor determining the price of a product, an increased integration degree is particularly required. In the case of a conventional two-dimensional or planar semiconductor device, the degree of integration is largely determined by the area occupied by the unit memory cells, and thus is greatly influenced by the level of fine pattern formation technology. However, since the ultra-high-priced equipments are required for pattern miniaturization, the density of the two-dimensional semiconductor device is increasing, but it is still limited.

To overcome this limitation, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass-produce a 3D semiconductor memory device, there is a demand for a process technology capable of realizing reliable product characteristics while reducing manufacturing cost per bit than that of a 2D semiconductor device.

The problem to be solved by the present invention is to provide a three-dimensional semiconductor memory device with improved reliability.

Another problem to be solved by the present invention is to provide a method of manufacturing a 3D semiconductor memory device with improved reliability.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

A method of manufacturing a 3D semiconductor memory device according to the present invention for achieving the above object is to alternately repeatedly stack sacrificial films and insulating films on a substrate to form a thin film structure; Forming a channel hole through the thin film structure to expose the substrate; Surface-treating the sacrificial films exposed in the channel hole; Forming a channel structure in the channel hole; Forming a trench spaced apart from the channel structure and penetrating the thin film structure; And replacing the sacrificial layers exposed in the trenches with gate patterns.

According to one embodiment, surface treatment of the sacrificial films may include performing a hydrogen annealing process.

According to an embodiment, the hydrogen annealing process may be performed under a temperature of 700 to 1000°C and a pressure of 1 to 10 Torr.

According to an embodiment, prior to surface treatment of the sacrificial layers, the method may further include removing a natural oxide layer on the surfaces of the sacrificial layers exposed in the channel hole.

According to an embodiment, replacing the sacrificial layers with gate patterns may include removing the sacrificial layers exposed in the trench to form recess regions between the insulating layers; And forming a gate pattern in each of the recess regions.

According to an embodiment, the sacrificial films include a silicon film, and the sacrificial films and the insulating films may be formed of different materials.

A 3D semiconductor memory device according to the present invention for achieving the above object includes a stacked structure including gate patterns and insulating patterns alternately stacked on a substrate; A channel structure penetrating the stacked structure and connected to the substrate; And a data storage layer interposed between the stacked structure and the channel structure and conformally covering one side wall of the stacked structure, wherein the gate patterns have a greater width than the insulating patterns, but the stacked structure is The sidewalls of the gate patterns in contact with the data storage layer have a rounded shape.

According to an embodiment, a horizontal insulation pattern interposed between one side wall of the gate pattern and the data storage layer may cover a top surface and a bottom surface of the gate pattern.

According to one embodiment, the data storage layer includes a stacked charge storage layer and a tunnel insulating layer, wherein the charge storage layer conformally covers one side wall of the stacked structure and defines an empty space in the extended region, The tunnel insulating layer may be filled in the empty space.

According to an embodiment, the channel structure may have protrusions filling portions of the extended regions.

According to embodiments of the present invention, it is possible to improve the wrinkles generated on the inner wall of the channel hole through the surface treatment process for the sacrificial films exposed in the channel hole. Accordingly, surface areas of cells formed through a subsequent process may be uniform, and as a result, characteristic distribution of a 3D semiconductor memory device may be improved.

Further, according to embodiments of the present invention, a charge storage layer that vertically crosses one side walls of the gate electrodes vertically stacked on the substrate may be formed to be curved. Accordingly, charges trapped in the charge storage layer in the flash memory device can be prevented from spreading vertically. Therefore, it is possible to reduce loss of charges stored in the charge storage layer, thereby improving charge retention characteristics of the flash memory device. Therefore, reliability of the three-dimensional semiconductor memory device can be improved.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.
2 is a cross-sectional view of a 3D semiconductor memory device according to an embodiment of the present invention.
3 to 6 are enlarged cross-sectional views showing part A of FIG. 2.
7 is a flowchart illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention.
8 to 16 are cross-sectional views illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention.
17 and 19 are views showing part B of FIG. 10, and are views for comparing before and after surface treatment of the sacrificial films.
18 is a cross-sectional view taken along line AA′ in FIG. 17.
20 is a cross-sectional view taken along line BB' of FIG. 19.
21 is a schematic block diagram illustrating an example of a memory system including a three-dimensional semiconductor memory device according to embodiments of the present invention.
22 is a schematic block diagram illustrating an example of a memory card having a three-dimensional semiconductor memory device according to embodiments of the present invention.
23 is a schematic block diagram illustrating an example of an information processing system equipped with a 3D semiconductor memory device according to embodiments of the present invention.

Advantages and features of the present invention, and methods for achieving them will be clarified with reference to embodiments described below in detail together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only the present embodiments allow the disclosure of the present invention to be complete, and the common knowledge in the technical field to which the present invention pertains. It is provided to fully inform the holder of the scope of the invention, and the invention is only defined by the scope of the claims. The same reference numerals throughout the specification refer to the same components.

The terminology used herein is for describing the embodiments and is not intended to limit the present invention. In the present specification, the singular form also includes the plural form unless otherwise specified in the phrase. As used herein,'comprises' and/or'comprising' refers to the components, steps, operations and/or elements mentioned above, the presence of one or more other components, steps, operations and/or elements. Or do not exclude additions. Also, in the present specification, when it is stated that a film is on another film or substrate, it means that it may be formed directly on another film or substrate, or a third film may be interposed therebetween.

In addition, the embodiments described herein will be described with reference to cross-sectional views and/or plan views, which are ideal exemplary views of the present invention. In the drawings, the thicknesses of the films and regions are exaggerated for effective description of technical content. Therefore, the shape of the exemplary diagram may be modified by manufacturing technology and/or tolerance. Accordingly, the embodiments of the present invention are not limited to the specific shapes shown, but also include changes in shapes generated according to the manufacturing process. For example, the etched area illustrated at right angles may be rounded or have a predetermined curvature. Accordingly, the regions illustrated in the figures have schematic properties, and the shapes of the regions illustrated in the figures are intended to illustrate specific forms of regions of the device and are not intended to limit the scope of the invention.

Hereinafter, a 3D semiconductor memory device and a method of manufacturing the same according to embodiments of the present invention will be described in detail with reference to the drawings.

1 is a simplified circuit diagram illustrating a cell array of a 3D semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 1, a cell array of a 3D semiconductor memory device according to an embodiment includes a common source line CSL, a plurality of bit lines BL, and a common source line CSL and bit lines BL. It may include a plurality of cell strings (CSTR) disposed in.

The bit lines BL are two-dimensionally arranged, and a plurality of cell strings CSTR are connected to each of them in parallel. The cell strings CSTR may be commonly connected to the common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL and the common source line CSL. According to an embodiment, a plurality of common source lines CSL may be provided, and the common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the common source lines CSL, or each of the common source lines CSL may be electrically controlled.

Each of the cell strings CSTR has a ground select transistor GST connected to a common source line CSL, a string select transistor SST connected to a bit line BL, and ground and string select transistors GST and SST. ) May be formed of a plurality of memory cell transistors (MCT). In addition, the ground selection transistor GST, the string selection transistor SST, and the memory cell transistors MCT may be connected in series.

The common source line CSL may be commonly connected to the sources of the ground selection transistors GST. In addition, the ground selection line GSL, the plurality of word lines WL0-WL3 and the plurality of string selection lines SSL, which are disposed between the common source line CSL and the bit lines BL, are grounded. It may be used as gate electrodes of the selection transistor GST, the memory cell transistors MCT, and the string selection transistors SST, respectively. Also, each of the memory cell transistors MCT includes a data storage element.

2 is a cross-sectional view of a 3D semiconductor memory device according to an embodiment of the present invention. 3 to 6 are enlarged cross-sectional views showing part A of FIG. 2.

Referring to FIG. 2, a stacked structure 200 including insulating patterns 112 and gate patterns 160 alternately and repeatedly stacked is disposed on a substrate 100.

The substrate 100 may be a silicon substrate, a germanium substrate, or a silicon-germanium substrate. The substrate 100 may include a common source region 107 doped with impurities.

The stacked structure 200 may have a line shape extending in one direction from a planar viewpoint. According to an embodiment, the width of the gate patterns 160 and the insulating patterns 112 in the stacked structure 200 may be different. For example, as illustrated in FIG. 2, the width of the gate pattern 160 may be greater than the width of the insulating pattern 112. Accordingly, the stacked structure 200 may have an inner wall having a plurality of expanded regions vertically spaced from each other. In detail, as illustrated in FIGS. 3 to 6, extended regions 117 may be defined between vertically adjacent gate patterns 112. Also, as illustrated in FIGS. 3 to 6, sidewalls of the gate patterns 160 may have a rounded shape. That is, the gate patterns 160 have protrusions that extend horizontally between the vertically adjacent insulating patterns 112, but sidewalls of the protrusions may have a rounded shape.

According to an embodiment, the thickness of the insulating patterns 112 may be smaller than the thickness of the gate patterns 160. In another embodiment, the thickness of some of the insulating patterns 112 may be greater than the thickness of the gate patterns 160. In another embodiment, the thickness of the insulating patterns 112 and the thickness of the gate patterns 160 may be the same.

According to one embodiment, some of the gate patterns 160 (eg, top gate patterns and bottom gate patterns) are gates of the ground and string select transistors GST and SST described with reference to FIG. 1. It can be used as electrodes. That is, in the 3D NAND flash memory, the top gate patterns are used as the gate electrode of the string select transistor that controls the electrical connection between the bit line 175 and the channel structures 210, and the bottom gate patterns are the substrate 100 It may be used as the gate electrode of the ground selection transistor that controls the electrical connection between the impurity region 107 (ie, common source line) and the channel structures 210.

In addition to this, the lower insulating layer 105 may be provided between the substrate 100 and the stacked structure 200. For example, the lower insulating film 105 may be a silicon oxide film formed through a thermal oxidation process. Alternatively, the lower insulating film 105 may be a silicon oxide film formed using a deposition technique. The lower insulating layer 105 may have a thickness thinner than the insulating patterns 112 formed thereon.

The channel structure 210 may penetrate the stacked structure 200 and be electrically connected to the substrate 100. The channel structure 210 may penetrate a plurality of gate patterns 160 stacked on the substrate 100. In one embodiment, the channel structure 210 may be made of a semiconductor material. The channel structure 210 can have a conductive pad 137 on top of it. The conductive pad 137 may be an impurity region doped with impurities, or may be made of a conductive material. The bottom surface of the channel structure 210 may be positioned at a lower level than the top surface of the substrate 100. That is, the channel structure 210 may have a structure inserted into the substrate 100.

Furthermore, a plurality of channel structures 210 may penetrate the stacked structure 200. The channel structures 210 passing through the layered structure 200 may be arranged in one direction from a planar perspective. Alternatively, the channel structures 210 may be arranged in a zigzag form in one direction from a planar perspective.

According to an embodiment, the channel structure 210 may be a hollow pipe-shaped or a macaroni-shaped. At this time, the lower end of the channel structure 210 may be a closed state. And, the interior of the channel structure 210 may be filled by the buried insulating pattern 135.

More specifically, the channel structure 210 may include a first semiconductor pattern 131 and a second semiconductor pattern 133. The first semiconductor pattern 131 may cover the inner wall of the stacked structure 200 having extended regions (see 117 of FIGS. 3 to 6 ). The first semiconductor pattern 131 may be in the form of a pipe or a macaroni with open top and bottom ends. In addition, the first semiconductor pattern 131 may be spaced apart from contact with the substrate 100.

The second semiconductor pattern 133 may be in the form of a pipe with a closed bottom or a macaroni. The inside of the second semiconductor pattern 133 of this type may be filled with a buried insulating pattern 135. In addition, the second semiconductor pattern 133 may contact the inner wall of the first semiconductor pattern 131 and the upper surface of the substrate 100. That is, the second semiconductor pattern 133 may electrically connect the first semiconductor pattern 131 and the substrate 100.

The first and second semiconductor patterns 131 and 133 may be undoped or doped with impurities having the same conductivity type as the substrate 100. The first semiconductor pattern 131 and the second semiconductor pattern 133 may be polycrystalline or monocrystalline.

According to an embodiment, a vertical insulating pattern 121 may be interposed between the stacked structure 200 and the channel structure 210. The vertical insulation pattern 121 may be in the form of a pipe or macaroni with open top and bottom ends. According to an embodiment, the vertical insulation pattern 121 may have a bottom portion interposed between the bottom surface of the first semiconductor pattern 131 and the substrate 100. In addition to this, the vertical insulating pattern 121 is substantially perpendicular to the substrate 100, but may have a curved shape. The vertical insulation pattern 121 may conformally cover the inner wall of the stacked structure 200 having the extended regions 117. That is, the vertical insulating pattern 121 may have protrusions protruding in a horizontal direction to the upper surface of the substrate 100.

According to an embodiment, the vertical insulation pattern 121 includes a data storage layer. The data storage layer may include a charge storage layer of a flash memory device. For example, the charge storage film may be a trap insulating film or an insulating film including conductive nano dots. Data stored in the data storage layer may be changed using Fowler-Northernheim tunneling caused by a voltage difference between the channel structure 210 and the gate patterns 160. Alternatively, the data storage layer may be a thin film (for example, a thin film for a phase change memory or a thin film for a variable resistance memory) capable of storing information based on other operating principles.

In addition to this, a horizontal insulation pattern 150 may be interposed between the stacked structure 200 and the vertical insulation pattern 121. The horizontal insulating pattern 150 may extend substantially horizontally to cover the lower surface and the upper surface of the gate pattern 160. The horizontal insulating pattern 150 may be composed of one thin film or a plurality of thin films. According to an embodiment, the horizontal insulating pattern 150 may include a blocking insulating layer of a charge trap type flash memory transistor.

In addition, a bit line 175 traversing the stacked structure 200 may be disposed on the stacked structure 200. The bit line 175 may be connected to the conductive pad 137 of the channel structure 210 through the contact plug 171.

Hereinafter, the structure of the vertical insulation pattern 121 according to an embodiment of the present invention will be described in more detail with reference to FIGS. 3 to 6.

According to the embodiments illustrated in FIGS. 3 to 6, the vertical insulation pattern 121 includes a charge storage layer CTL, and the charge storage layer CTL conforms to the inner wall of the stacked structure 200. Can be covered. According to an embodiment, since the width of the insulating pattern 112 is smaller than the width of the gate pattern 160, enlarged regions 117 may be defined between the vertically adjacent gate patterns 160. . That is, the gate patterns 160 may have protrusions extending between the extension regions 117. In addition, side walls of the protruding gate patterns 160 may have a rounded shape. Accordingly, the charge storage layer CTL may conformally cover the sidewalls of the rounded gate patterns 160 and the extended regions 117 defined between the gate patterns 160. In addition, the charge storage layer CTL may have a thickness less than half of the thickness of the insulating pattern 112 (ie, the vertical distance between the gate patterns 160 ). Accordingly, the charge storage layer CTL covers the extended regions 117 conformally, but may define an empty space in the extended regions 117. That is, the charge storage layer CTL may be formed in a structure having a concave surface. As described above, since the charge storage layer CTL is formed to be curved, charges trapped in the charge storage layer CTL can be suppressed from vertically spreading. Therefore, it is possible to reduce the loss of charges stored in the data storage layer, thereby improving the charge retention characteristics of the 3D flash memory device.

More specifically, according to the embodiments illustrated in FIGS. 3 to 5, the vertical insulating pattern 121 may include a charge storage layer (CTL) and a tunnel insulating layer (TIL). The charge storage layer CTL contacts one side wall of the insulating pattern 112 between the gate patterns 160 and may extend to upper and lower surfaces of the gate patterns 160. Also, the charge storage layer CTL may extend to one side of the rounded walls of the gate patterns 160.

In FIG. 3, the tunnel insulating layer TIL may be conformally formed on the charge storage layer CTL, and fill an empty space defined by the charge storage layer CTL. That is, the tunnel insulating layer TIL may have protrusions between the vertically adjacent gate patterns 160. Accordingly, the thickness of the tunnel insulating layer TIL between the insulating pattern 112 and the channel structure 210 may be greater than the thickness of the tunnel insulating layer TIL between the gate pattern 160 and the channel structure 210. have.

In FIG. 4, the charge storage layer CTL and the tunnel insulating layer TIL may define an empty space in the extended regions 117 between the gate patterns 160. And, the empty space defined by the vertical insulation pattern 121 may be filled with the channel structure 210.

According to the embodiments illustrated in FIGS. 4, 5 and 6, the channel structure 210 may fill empty spaces of the extended regions 117 in which the charge storage layer CTL and the tunnel insulating layer TIL are formed. . That is, the channel structure 210 may have protrusions between the vertically adjacent gate patterns 160. That is, the thickness of the channel structure 210 between the insulating pattern 112 and the buried insulating film may be greater than the thickness of the channel structure 210 between the buried insulating film and the gate pattern 160.

According to the embodiments illustrated in FIGS. 3 and 4, the horizontal insulating pattern 150 may be a blocking insulating layer (BIL) of a flash memory device. In addition, the horizontal insulating pattern 150 may include first and second blocking insulating layers BIL1 and BIL2, as illustrated in FIG. 5.

According to the embodiment illustrated in FIG. 6, the vertical insulating pattern 121 may include a first blocking insulating layer BIL1, a charge storage layer CTL, and a tunnel insulating layer TIL. The first blocking insulating layer BIL1 and the charge storage layer CTL conformally cover the extended regions 117 and define an empty space in the extended regions 117. The horizontal insulating pattern 150 may include a second blocking insulating layer BIL2.

In the embodiments illustrated in FIGS. 3 to 6, the charge storage layer CTL may include a trap insulating layer or an insulating layer including conductive nano dots. As a more specific example, the charge storage layer (CTL) may be at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon-rich nitride layer, a nanocrystalline silicon layer, or a laminated trap layer. It may include.

The tunnel insulating layer TIL may be one of materials having a band gap larger than the charge storage layer CTL. For example, the tunnel insulating layer TIL may be a silicon oxide layer.

The blocking insulating layer BIL may include one of materials having a band gap smaller than the tunnel insulating layer TIL and larger than the charge storage layer CTL. For example, the blocking insulating layer (BIL) may include one of high dielectric films such as an aluminum oxide film and a hafnium oxide film. In this aspect, the dielectric constant of the blocking insulating layer BIL may be substantially greater than that of the tunnel insulating layer TIL.

In the embodiment illustrated in FIG. 5, the first and second blocking insulating layers BIL1 and BIL2 may be formed of different materials. In addition, one of the first and second blocking insulating films BIL1 and BIL2 is formed of one of materials having a band gap smaller than that of the tunnel insulating film TIL and larger than the charge storage film CTL, and the other It can be formed of materials having a small dielectric constant. For example, one of the first and second blocking insulating films BIL1 and BIL2 may include one of high dielectric films such as an aluminum oxide film and a hafnium oxide film, and the other may be a silicon oxide film. In this aspect, the effective dielectric constants of the first and second blocking insulating layers BIL1 and BIL2 may be substantially greater than that of the tunnel insulating layer TIL.

Hereinafter, a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 7 to 20. 7 is a flowchart illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention. 8 to 16 are cross-sectional views illustrating a method of manufacturing a 3D semiconductor memory device according to an embodiment of the present invention. 17 and 19 are views showing part B of FIG. 10, and are views for comparing before and after surface treatment of the sacrificial films. 18 is a cross-sectional view taken along the line A-A' in FIG. 17, and FIG. 20 is a cross-sectional view taken along the line B-B' in FIG.

Referring to FIGS. 7 and 8, the sacrificial films 111 and the insulating films 112 are alternately stacked alternately on the substrate 100 to form the thin film structure 110 (S10 ).

The substrate 100 may be one of materials having semiconductor properties, insulating materials, a semiconductor covered with an insulating material, or a conductor. For example, the substrate 100 may be a silicon wafer.

The sacrificial films 111 may be formed of a material that can be etched with etching selectivity to the insulating films 112. According to an embodiment, the sacrificial layers 111 and the insulating layers 112 may have a high etching selectivity in a wet etching process using a chemical solution, and a low etching selectivity in a dry etching process using an etching gas. have. In addition, the sacrificial layers 111 and the insulating layers 112 may have the same thickness, and the sacrificial layers 111 and the insulating layers 112 may have different thicknesses.

The sacrificial film and the insulating films 111 and 112 may include thermal CVD, plasma enhanced CVD, physical CVD or atomic layer deposition (ALD) technology. It can be deposited using.

According to an embodiment, the sacrificial layer and the insulating layers 111 and 112 are formed of an insulating material, and may have etch selectivity with each other. In addition, the sacrificial film and the insulating films 111 and 112 may be formed of a material capable of minimizing the increase in stress of the thin film structure 100 even when the number of stacked layers of the sacrificial film and the insulating films 111 and 112 increases. Can. For example, the sacrificial films 111 may be formed of a silicon film, and the insulating films 112 may be formed of a silicon oxide film.

7 and 9, channel holes 115 exposing the substrate 100 through the thin film structure 110 may be formed (S20 ).

According to an embodiment, each of the channel holes 115 may be formed in a shape whose depth is at least 5 times larger than its width. Also, the channel holes 115 may be formed in two dimensions on the upper surface (ie, xy plane) of the substrate 100. That is, each of the channel holes 115 may be an isolated area formed spaced apart from others along the x and y directions. According to another embodiment, although not shown in the drawings. The channel holes 115 may be arranged in a zig zag direction in the y-axis direction. In addition, the separation distance between the channel holes 115 adjacent in one direction may be smaller than or equal to the width of the channel hole 115.

The channel holes 115 may be formed by forming a mask pattern (not shown) on the thin film structure 110 and anisotropically etching using a mask pattern (not shown) as an etch mask. In the anisotropic etching process, the substrate 100 may be over-etched to the upper surface, and accordingly, the substrate 100 under the channel holes 115 may be recessed to a predetermined depth. In the etching process for the formation of these channel holes 115, due to the difference in the reaction between the etching gas and the sacrificial films/insulation films, and the reaction between the etching gas and the reaction by-products, the channel, as shown in FIG. Striations may be generated in the inner wall of the holes 115. Wrinkles mean the non-uniformity of the diameter of the channel holes 115. This non-uniformity may cause a problem in that the dispersion of characteristics of memory cells formed through a subsequent process becomes large.

7 and 10, portions of the insulating layers 112 exposed to the channel hole 115 are removed to form extended regions 117. These extended regions 117 may be formed as a result of a process of cleaning the surface of the sacrificial films 111 exposed to the channel hole 115 (S30). Cleaning the surface of the sacrificial films 111 is performed by applying a natural oxide film on the outer surface of the sacrificial films 111 before performing a surface treatment process on the sacrificial films 111 exposed to the channel hole 115. To remove.

The cleaning process may include a dry and/or wet etching process, and as a result of the etching process, natural oxide films or foreign substances on the surfaces of the sacrificial films 111 may be completely removed. During the etching process, portions of the insulating layers 112 may be removed. As a result, the thin film structure 110 having one side wall in which the extended regions 117 vertically spaced from each other is defined may be formed. As shown in FIG. 17, the extended regions 117 may extend from the channel hole 115 between the sacrificial films 111 and expose portions of the upper and lower surfaces of the sacrificial films 111. I can do it. That is, the extended region 117 may be defined by upper and lower surfaces of the sacrificial films 111 positioned on one side wall and upper and lower parts of the recessed insulating film 112.

Next, a process of surface-treating the sacrificial films 111 from which the natural oxide film has been removed is performed (S40). In one embodiment, the process of surface-treating the sacrificial films 111 may include performing an annealing process in a hydrogen (H ₂ ) atmosphere. This surface treatment process is a process for improving the striation of the inner wall of the channel hole 115, the migration of silicon atoms in the sacrificial films 111 in order to make the diameter of the channel hole 115 uniform ( It is a step to induce migration).

Specifically, the annealing process in a hydrogen atmosphere can be performed under a temperature of about 700 to 1000°C and a pressure of about 1 to 10 Torr. When the annealing temperature is lower than 700°C, migration of silicon atoms in the sacrificial films 111 is difficult to be effectively performed. In addition, when the annealing temperature exceeds 1000°C, the degree of migration of silicon atoms in the sacrificial films 111 is too large, and there is a fear that other device regions on the same substrate, such as an ion implantation region, may deteriorate due to high temperature. .

As a result of the surface treatment process, as shown in FIG. 20, wrinkles on the outer surface of the sacrificial film 111 are improved, so that the diameter of the channel hole 115 may be uniform. In addition, as a result of the surface treatment process, as illustrated in FIG. 19, sidewalls of the sacrificial films 111 protruding between the extended regions 117 may have a rounded shape.

7 and 11 to 13, vertical insulation patterns 121 and first and second semiconductor patterns 131 and 133 may be formed in the channel hole 115 (S50 ).

Referring to FIG. 11, a vertical insulating layer 120 and a first semiconductor layer 130 covering the inner wall of the channel hole 115 in which the extended regions 117 are formed may be sequentially formed. The sum of deposition thicknesses of the vertical insulating layer 120 and the first semiconductor layer 130 may be less than half the width of the channel hole 115. That is, the channel hole 115 may not be completely filled by the vertical insulating layer 120 and the first semiconductor layer 130. Furthermore, the vertical insulating layer 120 may cover the upper surface of the substrate 100 exposed in the channel hole 115.

The vertical insulating layer 120 may be deposited to conformally cover one side wall of the thin film structure 110 in which the extended regions 117 are formed. The vertical insulating layer 120 may be deposited using, for example, plasma enhanced CVD, physical CVD, or atomic layer deposition (ALD) technology.

The vertical insulating layer 120 may be formed of a plurality of thin films. According to an embodiment, the vertical insulating film 120 may include a charge storage film and a tunnel insulating film used as a memory element of the charge trap type flash memory device. Alternatively, the vertical insulating film 120 may include a blocking insulating film, a charge storage film, and a tunnel insulating film. The vertical insulating film 120 may be formed in various forms, as described with reference to FIGS. 3 to 6. Here, the charge storage layer may be deposited with a uniform thickness, as shown in FIGS. 3 to 6, and an empty space may be defined in the extended regions 117. The vertical insulating layer 120 formed of a plurality of thin films may completely fill the extended areas 117 or define an empty space in the extended areas 117.

The first semiconductor layer 130 may be conformally formed on the vertical insulating layer 120. According to an embodiment, the first semiconductor film 130 is a semiconductor material (eg, a polycrystalline silicon film, a monocrystalline silicon film) formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. , Or an amorphous silicon film). Alternatively, the first semiconductor film 130 may be one of organic semiconductor films and carbon nanostructures. According to an embodiment, when the extended regions 117 of the thin film structure 110 are not completely filled by the vertical insulating layer 120, the first semiconductor layer 130 may include extended regions in which the vertical insulating layer 120 is formed. The remaining space of 117 can be filled.

Referring to FIG. 12, the upper surface of the substrate 100 may be exposed by etching the first semiconductor layer 130 (see FIG. 11) and the vertical insulating layer 120 (see FIG. 11) at the bottom of the channel hole 115. have. Accordingly, the first semiconductor pattern 131 and the vertical insulating pattern 121 may be formed on the inner wall of the channel hole 115. That is, the vertical insulating pattern 121 and the first semiconductor pattern 131 may be formed in a cylindrical shape having both ends open. In addition, as a result of over-etching during the anisotropic etching of the first semiconductor layer 130 (see FIG. 11) and the vertical insulating layer 120 (see FIG. 11 ), the first semiconductor pattern 131 is exposed. The upper surface of the substrate 100 may be recessed.

Meanwhile, during anisotropic etching, a portion of the vertical insulating layer 120 (see FIG. 11) positioned under the first semiconductor pattern 131 may not be etched. In this case, the vertical insulating pattern 121 may be the first semiconductor. It may have a bottom portion interposed between the bottom surface of the pattern 131 and the top surface of the substrate 100.

In addition, as a result of anisotropic etching on the first semiconductor layer 130 (see FIG. 11) and the vertical insulating layer 120 (see FIG. 11 ), the upper surface of the thin film structure 110 may be exposed. Accordingly, each of the vertical insulating patterns 121 and the first semiconductor patterns 131 may be localized in the channel holes 115. That is, the vertical insulating patterns 121 and the first semiconductor patterns 131 may be arranged two-dimensionally on a plane.

Referring to FIG. 13, a second semiconductor pattern 133 and a buried insulation pattern 135 may be sequentially formed on a result of forming the vertical insulation pattern 121 and the first semiconductor pattern 131.

The second semiconductor pattern 133 and the buried insulating pattern 135 sequentially form a second semiconductor film and a buried insulating film in the channel hole 115 in which the vertical insulating pattern 121 and the first semiconductor pattern 131 are formed, It may be formed by flattening such that the upper surface of the thin film structure 110 is exposed.

The second semiconductor film may be a semiconductor material (eg, a polycrystalline silicon film, a monocrystalline silicon film, or an amorphous silicon film) formed using one of atomic layer deposition (ALD) or chemical vapor deposition (CVD) techniques. According to an embodiment, the second semiconductor film may be formed conformally within the channel hole 115 to a thickness that does not completely fill the channel hole 115. That is, the second semiconductor pattern 133 may be formed in a channel hole 115 in a pipe-shaped, hollow cylindrical shape, or cup shape. Meanwhile, according to another embodiment, the second semiconductor pattern 133 may be formed to fill the channel hole 115.

The buried insulating pattern 135 may be formed to fill the channel hole 115 in which the second semiconductor pattern 133 is formed, and may be one of insulating materials and silicon oxide films formed by using SOG technology. have.

After forming the second semiconductor layer and the buried insulating pattern 135, conductive pads 137 connected to the first and second semiconductor patterns 131 and 133 may be formed. The conductive pad 137 may be formed by recessing the upper regions of the first and second semiconductor patterns 131 and 133, and then filling the recessed region with a conductive material. In addition, the conductive pad 137 may be formed by doping dopants of a different conductivity type from the first and second semiconductor films positioned below it. Accordingly, the conductive pad 137 may constitute a lower region and a diode.

Referring to FIGS. 7 and 14, trenches 140 exposing the substrate 100 between adjacent channel holes 115 by patterning the thin film structure 110 may be formed (S60 ).

Specifically, forming the trenches 140 includes forming a mask pattern (not shown) that defines the planar position of the trenches 140 on the thin film structure 110 and using the mask pattern as an etch mask. It may include anisotropic etching the thin film structure 110.

The trenches 140 may be formed to be spaced apart from the first and second semiconductor patterns 131 and 133 to expose sidewalls of the sacrificial layer and the insulating layers 111 and 112. From a horizontal perspective, trenches 140 may be formed in a line shape or a rectangle, and for vertical depth, trenches 140 may be formed to expose the top surface of substrate 100. While forming the trenches 140, the substrate 100 may be used as an etch stop layer, and an upper surface of the substrate 100 exposed to the trenches 140 by over etch may have a predetermined depth. Can be set. In addition, the trenches 140 may have different widths depending on the distance from the substrate 100 by an anisotropic etching process.

As the trenches 140 are formed, the thin film structure 110 may have a line shape extending in one direction. In addition, a plurality of first and second semiconductor patterns 131 and 133 may pass through one line-type thin film structure 110.

Referring to FIGS. 7, 15 and 16, a step (S70) of replacing sacrificial films 111 of the thin film structure 110 with a conductive material film may be performed.

Referring to FIG. 15, by removing the sacrificial films 111 exposed in the trenches 140, recess regions 145 may be formed between the insulating layers 112. The recess regions 145 may be formed by removing the sacrificial layers 111 between the insulating layers 112. That is, the recess regions 145 may extend horizontally between the trenches 140 and the insulating layers 112, and expose sidewall portions of the vertical insulation pattern 121. That is, the recess regions 145 may be defined by vertically adjacent insulating layers 112 and one side wall of the vertical insulating pattern 121.

More specifically, when the vertical insulating pattern 121 includes a charge storage layer and a tunnel insulating layer, the recess regions 145 may expose a portion of the charge storage layer. When the vertical insulating pattern 121 includes a blocking insulating layer, a charge storage layer, and a tunnel insulating layer, the recessed region 145 may expose the blocking insulating layer.

Specifically, the recess regions 145 may be formed by isotropically etching the sacrificial layers 111 using an etch recipe having an etch selectivity with respect to the insulating layers 112. Here, the sacrificial films 111 may be completely removed by an isotropic etching process.

Referring to FIG. 16, a horizontal insulating pattern 150 covering the inner wall of the recess regions 145 and a gate pattern 160 filling the remaining space of the recess regions 145 may be formed. In this embodiment, the width of the gate pattern 160 may be larger than the width of the patterned insulating layer 112 positioned at the upper and lower parts.

Forming the horizontal insulating pattern 150 and the gate patterns 160 is formed by forming a horizontal insulating film and a conductive film that sequentially cover the recess regions 145, and then removing the conductive film in the trenches 140 to form a recess. It may include locally forming the gate patterns 160 in the regions 145.

The horizontal insulating pattern 150 may be composed of one thin film or a plurality of thin films, similar to the case of the vertical insulating pattern 121. According to an embodiment, the horizontal insulating pattern 150 may include a blocking insulating layer of a charge trap type flash memory transistor. The horizontal insulation pattern 150 may conformally cover the inner wall of the recess region 145.

According to an embodiment, the conductive film may be formed to conformally cover the inner wall of the trench 140. In this case, forming the gate pattern 160 is an isotropic etching of the conductive film in the trenches 140. The method may include removing. According to another embodiment, the conductive layer may be formed to fill the trenches 140, and in this case, the gate pattern 160 may be formed by anisotropically etching the conductive layer within the trenches 140. The conductive film may include at least one of doped silicon, metal materials, metal nitride films, or metal silicides. For example, the conductive film may include a tantalum nitride film or a metal material such as tungsten.

Subsequently, according to an embodiment of the present invention for a flash memory device, after forming the gate patterns 160, impurity regions 107 may be formed on the substrate 100. The impurity regions 107 may be formed through an ion implantation process, and may be formed in the substrate 100 exposed through the trenches 140.

Meanwhile, the impurity regions 107 may have a different conductivity type from the first and second semiconductor patterns 131 and 133. In addition, the impurity regions 107 may form a P-junction with the substrate 100. Alternatively, the region of the substrate 100 in contact with the second semiconductor pattern 133 may have the same conductivity type as the second semiconductor pattern 133.

According to an embodiment, each of the impurity regions may be connected to each other to be in an equipotential state. According to another embodiment, each of the impurity regions may be electrically separated to have different potentials. According to another embodiment, the impurity regions may constitute a plurality of independent source groups including a plurality of different impurity regions, and each of the source groups may be electrically separated to have different potentials.

Subsequently, referring to FIG. 16, an electrode separation pattern 165 filling the trenches 140 may be formed. The electrode separation pattern 165 may be formed of at least one of a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The contact plugs 171 may be formed of one of doped silicon or metallic materials.

Subsequently, as illustrated in FIG. 2, contact plugs 171 connecting to each of the conductive pads 137 and a bit line 175 connecting the contact plugs 171 may be formed. The bit line 175 may be electrically connected to the first and second semiconductor patterns 131 and 133 through the contact plug 171 and formed to cross the gate patterns 160 or the trenches 140. Can be.

According to embodiments of the present invention, it is possible to improve the wrinkles generated on the inner wall of the channel hole through the surface treatment process for the sacrificial films exposed in the channel hole. Accordingly, surface areas of cells formed through a subsequent process may be uniform, and as a result, characteristic distribution of a 3D semiconductor memory device may be improved.

Further, according to embodiments of the present invention, a charge storage layer that vertically crosses one side walls of the gate electrodes vertically stacked on the substrate may be formed to be curved. Accordingly, charges trapped in the charge storage layer in the flash memory device can be prevented from spreading vertically. Therefore, it is possible to reduce loss of charges stored in the charge storage layer, thereby improving charge retention characteristics of the flash memory device. Therefore, reliability of the three-dimensional semiconductor memory device can be improved.

21 is a schematic block diagram illustrating an example of a memory system including a 3D semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 21, the memory system 1100 includes a PDA, a portable computer, a web tablet, a wireless phone, a mobile phone, and a digital music player, It can be applied to a memory card or any device capable of transmitting and/or receiving information in a wireless environment.

The memory system 1100 includes an input/output device 1120 such as a controller 1110, a keypad, a keyboard and a display, a memory 1130, an interface 1140, and a bus 1150. The memory 1130 and the interface 1140 communicate with each other through the bus 1150.

The controller 1110 includes at least one microprocessor, digital signal processor, microcontroller, or other similar process devices. The memory 1130 can be used to store instructions executed by the controller. The input/output device 1120 may receive data or signals from outside the system 1100 or output data or signals from outside the system 1100. For example, the input/output device 1120 may include a keyboard, a keypad, or a display element.

The memory 1130 includes a 3D semiconductor memory device according to embodiments of the present invention. The memory 1130 may further include other types of memory, volatile memory that can be accessed at any time, and various other types of memory.

The interface 1140 transmits data to a communication network or receives data from the network.

In addition, the 3D semiconductor memory device or memory system according to the present invention may be mounted in various types of packages. For example, the three-dimensional semiconductor memory device or memory system according to the present invention includes PoP (Package on Package), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In- Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flatpack (TQFP), Small Outline(SOIC), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), Thin Quad Flatpack(TQFP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), It can be packaged and mounted in the same way as Wafer-Level Processed Stack Package (WSP).

22 is a schematic block diagram illustrating an example of a memory card having a three-dimensional semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 22, a memory card 1200 for supporting a high-capacity data storage capability is equipped with a flash memory device 1210. The flash memory device 1210 includes a 3D semiconductor memory device according to embodiments of the present invention described above. The memory card 1200 according to the present invention includes a memory controller 1220 that controls data exchange between the host and the flash memory device 1210.

SRAM 1221 is used as the working memory of processing unit 1222. The host interface 1223 includes a data exchange protocol of a host connected to the memory card 1200. The error correction block 1224 detects and corrects an error included in data read from the multi-bit flash memory device 1210. The memory interface 1225 interfaces with the flash memory device 1210 of the present invention. The processing unit 1222 performs various control operations for data exchange of the memory controller 1220. Although not shown in the drawing, it is common knowledge in the art that the memory card 1200 according to the present invention may further be provided with a ROM (not shown) for storing code data for interfacing with a host, etc. It is obvious to those who have learned it.

23 is a schematic block diagram illustrating an example of an information processing system equipped with a 3D semiconductor memory device according to embodiments of the present invention.

Referring to FIG. 23, a flash memory device 1210 is mounted in an information processing system such as a mobile device or a desktop computer. The flash memory device 1210 includes a 3D semiconductor memory device according to embodiments of the present invention described above. The information processing system 1300 according to the present invention includes a flash memory system 1310 and a modem 1320 electrically connected to a system bus 760, a central processing unit 1330, a RAM 1340, and a user interface 1350, respectively. It includes. The flash memory system 1310 will be configured substantially the same as the aforementioned memory system or flash memory system. The flash memory system 1310 stores data processed by the central processing unit 1330 or data input from outside. Here, the above-described flash memory system 1310 may be configured as a semiconductor disk device (SSD). In this case, the information processing system 1300 may stably store a large amount of data in the flash memory system 1310. In addition, as the reliability increases, the flash memory system 1310 may reduce resources required for error correction, thereby providing a high-speed data exchange function to the information processing system 1300. Although not shown, it is common knowledge in this field that the information processing system 1300 according to the present invention may further be provided with an application chipset, a camera image processor (CIS), and an input/output device. It is obvious to those who have learned it.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but those of ordinary skill in the art to which the present invention pertains can implement the present invention in other specific forms without changing its technical spirit or essential features. You will understand that there is. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

Claims (10)

Forming a thin film structure by repeatedly stacking sacrificial films and insulating films alternately on the substrate;
Forming a channel hole through the thin film structure to expose the substrate;
Surface-treating the sacrificial films exposed in the channel hole;
Forming a channel structure in the channel hole;
Forming a trench spaced apart from the channel structure and penetrating the thin film structure; And
And replacing the sacrificial layers exposed in the trenches with gate patterns. According to claim 1,
A method of manufacturing a 3D semiconductor memory device, wherein surface treating the sacrificial layers includes performing a hydrogen annealing process. According to claim 2,
The hydrogen annealing process is performed under a temperature of 700 to 1000°C and a pressure of 1 to 10 Torr. According to claim 1,
Before surface treatment of the sacrificial films,
And removing a natural oxide layer on the surface of the sacrificial layers exposed in the channel hole. According to claim 1,
Replacing the sacrificial films with gate patterns:
Removing the sacrificial films exposed in the trench to form recess regions between the insulating films; And
A method of manufacturing a 3D semiconductor memory device, comprising forming a gate pattern in each of the recess regions. According to claim 1,
The sacrificial films include a silicon film, wherein the sacrificial films and the insulating films are formed of different materials. delete delete delete delete

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