KR102112396B1 - Pseudo static random access memory and control method thereof - Google Patents

Abstract

[Objective] The present invention provides a pseudo SRAM and a control method thereof that shortens the time required for the write operation, thereby lengthening the time for executing the refresh operation.
[Solution] Pseudo SRAM and its control method. The control method includes, in the write operation, counting data input to the pseudo SRAM by the reference clock signal from the outside to generate a first count value, and in the write operation, the assembled clock signal whose initial period is smaller than the period of the reference clock signal By counting the data written to the dynamic memory array of the pseudo SRAM to generate a second count value, comparing the first count value and the second count value, the first count value is equal to the second count value To enable the write matching signal to be performed, convert the write operation from asynchronous mode to synchronous mode when receiving the validated write matching signal, and adjust the period of the input clock signal to be equal to that of the reference clock signal. , And.

Description

Pseudo SRAM and its control method {PSEUDO STATIC RANDOM ACCESS MEMORY AND CONTROL METHOD THEREOF}

The present invention relates to a method for controlling a memory, and more particularly, to a method for controlling a pseudo SRAM.

In recent years, the level of integration of semiconductor memory devices is gradually increasing, and there is a demand for higher speeds. In particular, the advantages of SRAM (Static Random Access Memory) and DRAM (Dynamic Random Access Memory) used in portable devices are simultaneously The demand for pseudo pseudo SRAM (Pseudo Static Random Access Memory) continues to increase.

The pseudo SRAM is a memory device having a unit structure of DRAM and a peripheral circuit of SRAM. Pseudo SRAM has the advantage of high capacity and low cost, but the need to regularly perform refresh operations must be taken into account. In the conventional pseudo SRAM, during the write operation, there is a problem that the time of the refresh operation is shortly limited, and the data retention time is reduced. In order not to cause an error, the refresh period can be shortened correspondingly, but the current during standby increases, thereby increasing power consumption. In order to prevent an increase in the standby current, when complicated control is required for the refresh operation and the refresh period, the control logic circuit is complicated, and there is a drawback of increasing the chip size and cost.

The present invention provides a pseudo SRAM that shortens the time required for a write operation and lengthens the time for executing the refresh operation, and a control method thereof.

The control method of the present invention is applied to a pseudo SRAM. The control method is to generate a first count value by counting data input to the pseudo SRAM by a reference clock signal from the outside in a write operation,

In the writing operation, counting the data written to the dynamic memory array of the pseudo SRAM by a joining clock signal whose initial period is smaller than that of the reference clock signal, thereby generating a second count value,

Comparing the first count value and the second count value and validating the write matching signal when the first count value is equal to the second count value,

And, upon receiving a valid write matching signal, converting the write operation from asynchronous mode to synchronous mode, and adjusting the period of the input clock signal to be equal to that of the reference clock signal.

The pseudo SRAM of the present invention includes a dynamic memory array, a controller, and input / output circuits. The controller is coupled to the dynamic memory array. Input / output circuitry is coupled to the dynamic memory array and controller. The controller includes a first counter, a second counter, a comparator, and an address strobe clock generator. In the write operation, the first counter counts data input to the pseudo SRAM by the reference clock signal from the outside, and generates a first count value. In the write operation, the second counter counts the data written to the dynamic memory array by the input clock signal whose initial period is smaller than the period of the reference clock signal, thereby generating a second count value. The comparator is coupled to the first counter and the second counter, compares the first count value and the second count value, and validates the write matching signal when the first count value is equal to the second count value. The address strobe clock generator is coupled to the comparator. Upon receiving the valid write matching signal, the write operation is switched from asynchronous mode to synchronous mode, and the period of the input clock signal is adjusted to be equal to the period of the reference clock signal.

Based on the above, the present invention performs the same write operation in asynchronous mode and synchronous mode. When the number of data started to be supplied to the input terminal buffer of the pseudo SRAM is greater than the number of data written to the memory unit of the dynamic memory array, the data is written to the dynamic memory array by a fastening clock signal shorter than the period of the reference clock signal. Then, the number of data of both is gradually made equal. When equal, the period of the input clock signal is adjusted to be the same as that of the reference clock signal. By doing so, it is possible to effectively shorten the time required for the writing operation without requiring complicated control, and to lengthen the time for performing the refresh operation, thereby reducing errors and power consumption.

In order to further clarify the above-described features and advantages of the present invention, detailed description will be given below with reference to the drawings, for example.

1 is a circuit schematic diagram for explaining a pseudo SRAM based on an embodiment of the present invention.
2 is a circuit schematic diagram for explaining an address strobe clock generator based on an embodiment of the present invention.
[Fig. 3] Fig. 3 is a schematic waveform diagram illustrating the generation of a join clock signal based on an embodiment of the present invention.
[Fig. 4] Fig. 4 is a schematic waveform diagram explaining the writing operation of the pseudo SRAM based on the embodiment of the present invention.
5 is a circuit schematic diagram for explaining a pre-charge control circuit based on an embodiment of the present invention.
[Fig. 6] Fig. 6 is a schematic waveform diagram for explaining the refresh operation during the writing operation of the pseudo SRAM based on the embodiment of the present invention.
[Fig. 7] Fig. 7 is a schematic waveform diagram explaining the refresh operation at the time of reading operation of the pseudo SRAM based on the embodiment of the present invention.
[Fig. 8] Fig. 8 is a flow chart for explaining a method for controlling pseudo SRAM based on an embodiment of the present invention.
Fig. 9 is a flow chart for explaining a method for controlling pseudo SRAM based on an embodiment of the present invention.

Referring now to Fig. 1, Fig. 1 is a circuit schematic diagram illustrating a pseudo SRAM based on an embodiment of the present invention. The pseudo SRAM 100 includes a dynamic memory array 110, a controller 120, an input / output circuit 130, and a precharge control circuit 140. The controller 120 is coupled to the dynamic memory array 110. The input / output circuit 130 is coupled to the dynamic memory array 110 and the controller 120. The controller 120 includes a first counter 121, a second counter 122, a comparator 123, an address strobe clock generator 124, and an input command decoder 125. The comparator 123 is coupled to the first counter 121 and the second counter 122. The first counter 121 receives data input from the input / output circuit 130 of the pseudo SRAM 100 by the reference clock signal CLK from the outside (for example, inputted by the data port signal ADQ). Counting is used to generate a first count value (FCV). The second counter 122 is used to count the data written to the dynamic memory array 110 from the input / output circuit 130 by the input clock signal CASP and generate the second count value SCV. Generally, data is input to the buffer of the input / output circuit 130 from the outside during a write operation, and then is written to the dynamic memory array 110 from the input / output circuit 130. However, when data starts to be input to the input / output circuit 130 from the outside, writing of data to the memory unit of the dynamic memory array 110 is not started unless some circuit or control delay has elapsed. Therefore, in this embodiment, when starting execution of the write operation, the initial period of the join clock signal CASP is made smaller than the reference clock signal CLK by the asynchronous method, and the data is transferred to the dynamic memory array 110. ) Is faster than the speed at which data is input to the input / output circuit 130 from the outside, and the number of data written to the dynamic memory array 110 is input to the pseudo SRAM 100 from the outside. Let the number gradually reach.

In FIG. 1, the comparator 123 compares the first count value FCV and the second count value SCV, and when the first count value FCV is equal to the second count value SCV, the write matching The signal WRMTC is valid. That is, when the number of data written to the dynamic memory array 110 is almost equal to the number of data input to the pseudo SRAM 100 from the outside, the comparator 123 enables the write matching signal WRMTC , It may indicate that the speed at which data is written to the dynamic memory array 110 does not need to be faster than the speed at which data is input to the input / output circuit 130 from the outside. In other words, when receiving the validated write matching signal WRMTC, the address strobe clock generator 124 converts the write operation from asynchronous mode to synchronous mode, and the cycle of the join clock signal CASP is a reference clock signal. Adjust so that it is the same as the cycle of (CLK).

In this embodiment, the first counter 121 and the second counter 122 may have a counter circuit having a known counter function (but not limited to this). The controller 120 and the precharge control circuit 140 may be logic circuits composed of a plurality of logic gates (but not limited to this). The dynamic memory array 110 may be a known DRAM, but is not limited to this. In the field of integrated circuits, the input / output circuit 130 may be implemented using a structure in which a memory circuit familiar to those skilled in the art is applied.

Hereinafter, referring to FIGS. 1 and 2 at the same time, FIG. 2 is a circuit diagram illustrating an address strobe clock generator based on an embodiment of the present invention. The address strobe clock generator 124 includes a synchronous controller 210, an asynchronous clock controller 220, a synchronous clock controller 230, a one shot pulse generator 240, and a clock regulator 250. Includes. After determining the execution of the write operation or read operation, the input command decoder 125 may generate an operation signal (MODE) and a delay preparation signal (RCDRDY) corresponding to the operation to be performed. The synchronization controller 210 can receive the operation signal MODE and the write matching signal WRMTC generated by the comparator 123, and when the write matching signal WRMTC becomes valid in the write operation, the synchronization determination signal (CLSYNC) is enabled.

The asynchronous clock controller 220 receives the delay ready signal RCDRDY, the synchronous decision signal CLSYNC, and the assembled clock signal CASP, and when the delay ready signal RCDRDY becomes valid, also the synchronous decision signal CLSYNC. When is not enabled, the asynchronous clock controller 220 may generate an asynchronous base signal (CASASP), since it indicates that it is currently in asynchronous mode. When the delay ready signal RCDRDY becomes valid, it indicates that the system operation of the row address, such as a word line and an induction amplifier, is ready for driving, and the system operation of the column address is ready. That is, during the write operation, data can be started to be written from the buffer of the input / output circuit 130 to the memory unit of the dynamic memory array 110.

The synchronous clock controller 230 receives the reference clock signal CLK and the synchronous determination signal CLSYNC. When the synchronization determination signal CLSYNC becomes valid, it indicates that it has already been converted to the synchronization mode, and the synchronization clock controller 230 can generate a corresponding synchronization base signal CASPP in response to the reference clock signal CLK. have.

The one-shot pulse generator 240 receives the asynchronous base signal (CASASP), the synchronous base signal (CASSP), and the delay preparation signal (RCDRDY) and, in an asynchronous mode, responds to the asynchronous base signal (CASASP) A built-in clock signal (CASP) can be generated, and in the synchronous mode, in response to the synchronous base signal (CASSP), a corresponding built-in clock signal (CASP) can be generated. Among them, in the one-shot pulse generator 240, for example, an asynchronous base signal (CASASP) and a synchronous base signal (CASSP) are selected by OR operation, and in response to the selected signal, the delay preparation signal (RCDRDY) is effective. After that, a one-shot pulse having a predetermined pulse width can be generated as the joining clock signal CASP. The incoming clock signal CASP is further fed back to the asynchronous clock controller 220 to adjust the subsequent asynchronous base signal CASASP.

The clock adjuster 250 receives the input clock signal CASP and generates a control signal CLP in response to the input clock signal CASP through a predetermined delay time.

Hereinafter, referring to FIG. 2 and FIG. 3 at the same time, FIG. 3 is a waveform schematic diagram illustrating generation of a join clock signal based on an embodiment of the present invention. It is related to the details of generating a join clock signal. In FIG. 3, first, when the delay ready signal RCDRDY becomes valid (goes up to a high logic level), the asynchronous clock controller 220 can start generating the asynchronous base signal CASASP. At this time, the one-shot pulse generator 240 may trigger the generation of a one-shot pulsed clock signal (CASP) in response to the rise of the asynchronous base signal (CASASP). The period of the asynchronous base signal CASASP is smaller than that of the reference clock signal CLK. The control signal CLP is generated from the clock regulator 250 in response to the input clock signal CASP through a predetermined delay time. In the present embodiment, the height of the level of the input clock signal CASP is different from that of the control signal CLP, but the present invention is not limited to this.

Subsequently, when the synchronization determination signal CLSYNC is enabled by the synchronization controller 210, it indicates that it is converted to the synchronization mode, and the synchronization clock controller 230 responds to the reference clock signal CLK, corresponding ( For example, both the period and pulse width produce a synchronous base signal (CASSP), such as the reference clock signal (CLK). At this time, the one-shot pulse generator 240 responds to the rise of the synchronous base signal CASPP, triggers the generation of a one-shot pulsed clock signal CASP, and the cycle of the clock signal CASP is a reference clock signal ( CLK).

Hereinafter, referring to FIGS. 1, 2 and 4 at the same time, FIG. 4 is a waveform schematic diagram for explaining the writing operation of the pseudo SRAM based on the embodiment of the present invention. With respect to the details of the writing operation of the pseudo SRAM 100, the input command decoder 125 of the pseudo SRAM 100 is externally provided with a reference clock signal CLK, a data port signal ADQ, and a chip enable signal CE ). The data port signal ADQ may include, for example, commands, addresses, and contents of data. When the chip enable signal CE becomes valid (down to a low logic level), before executing the write operation or read operation, the input command decoder 125 determines whether to receive a refresh request. When a refresh request is received, a refresh operation is performed. Other details of the refresh operation can be referred to below.

Subsequently, the input command decoder 125 determines execution of a write operation or a read operation based on the command of the received data port signal ADQ. In this embodiment, the chip enable signal CE is a low active signal, that is, the chip enable signal CE is at a logic low level when it is in an active state. Naturally, in other embodiments of the present invention, the chip enable signal CE may be a high active signal, and there is no specific limitation.

In FIG. 4, after the execution of the write operation is determined, data included in the data port signal ADQ (data DATA in FIG. 4) is sequentially buffered by the input / output circuit 130 by the reference clock signal CLK. Is entered in. Before the delay ready signal RCDRDY becomes valid, there is no data being written to the dynamic memory array 110.

After the delay ready signal RCDRDY becomes valid, the one-shot pulse generator 240 of the address strobe clock generator 124 is a submerged clock signal CASP in an asynchronous mode (the period of which is longer than that of the reference clock signal CLK). Small). At this time, data may be written to at least one memory unit corresponding to the address data of the dynamic memory array 110 by the join clock signal CASP in order by the control signal CLP generated as described above.

After starting the write operation, the first counter 121 can start counting data input to the input / output circuit 130 based on the count start signal LTCSTA generated from the input command decoder 125. , When the write flag signal WRFLG generated from the input command decoder 125 becomes valid, the second counter 122 may count data written to the dynamic memory array 110. When the number of both data is the same, the comparator 123 validates the write matching signal, and the synchronization controller 210 validates the synchronization determination signal CLSYNC.

In Fig. 4, when the write matching signal WRMTC and the synchronization determination signal CLSYNC become valid (up to a high logic level), it shows that the conversion from the asynchronous mode to the synchronous mode, and one shot of the address strobe clock generator 124 The pulse generator 240 may initiate generation of a synchronous mode interlocked clock signal CASP (the period being the same as that of the reference clock signal CLK). At this time, the control signal CLP generated as described above may write data to at least one memory unit corresponding to the address data of the dynamic memory array 110 by the input clock signal CASP adjusted in order. .

On the other hand, when the input command decoder 125 determines execution of the read operation based on the command of the received data port signal ADQ, the input / output circuit 130 interpolates the period equal to the period of the reference clock signal CLK. Data of the dynamic memory array 110 is read based on the clock signal CASP. Specifically, the data corresponding to the address data of the dynamic memory array 110 is controlled by the control clock CLP generated as described above, and the input clock signal CASP having the same period as the reference clock signal CLK in order of data. At least one memory unit can be read, and the read data is output. In the entire flow of the read operation, either is performed by the synchronous mode (the period of the input clock signal CASP is the same as that of the reference clock signal CLK).

Regardless of whether a write operation or a read operation is performed, a precharge operation is required after completing the operation. In FIG. 1, the precharge control circuit 140 is coupled to the input command decoder 125 and the comparator 123, and when performing a write operation or a read operation, the precharge control circuit 140 receives the chip enable signal CE ) Can be detected, and when the chip enable signal CE becomes invalid (indicating the end of external writing or reading), a precharge operation is performed.

Hereinafter, referring to FIGS. 1 and 5 at the same time, FIG. 5 is a circuit schematic diagram for explaining a pre-charge control circuit based on an embodiment of the present invention. The input command decoder 125 determines execution of a write operation or a read operation based on the command of the received data port signal ADQ, and outputs the write flag signal WRFLG and the read flag signal RDFLG in this way do. In addition, the input command decoder 125 also outputs a chip select signal CS based on the received chip enable signal CE.

In FIG. 5, the latch 510 receives the write flag signal WRFLG and the chip select signal CS. The latch 520 receives the read flag signal RDFLG and the chip select signal CS. The signal generated by the latch 510 is delayed and transmitted to the AND gate 530 and the AND gate 540. The signal generated by the latch 510 is transmitted to the AND gate 530 in synchronization with the rise of the join clock signal CASP, and the synchronized signal is further delayed and transmitted to the AND gate 540. The AND gate 530 may perform an AND operation with the write matching signal WRMTC to transmit the signal to the OR gate 550. The AND gate 540 may perform an AND operation with the write matching signal WRMTC to transmit the signal to the OR gate 560.

The signal generated by the latch 520 is transmitted to the OR gate 550 in synchronization with the rise of the join clock signal CASP, and the synchronized signal is further synchronized with the falling of the control signal CLP to OR gate 560 ). The control termination signal CLPSTP is generated by the operation of the OR gate 550. The pre-charge signal PREP is generated by the operation of the OR gate 560, and execution of the pre-charge operation is notified.

Referring now to Fig. 6, Fig. 6 is a schematic waveform diagram illustrating a refresh operation during a write operation of a pseudo SRAM based on an embodiment of the present invention. In Fig. 6, after the chip enable signal CE becomes valid, a refresh request is sent immediately, so that the refresh operation can be executed before the write operation.

In FIG. 6, the refresh request signal REF becomes valid immediately after the chip enable signal CE becomes valid. In this embodiment, the refresh request signal REF is periodically valid, for example by a counter (not shown).

In this embodiment, there is no write delay, and input data is stored in the FIFO buffer of the input / output circuit 130 before the actual write operation.

As shown in Fig. 6, in the present embodiment, after the refresh operation is finished, it is notified that the operation drive signal RRASW becomes valid and execution of the write operation can be started. That is, the refresh operation of the present embodiment can be executed other than the cycle of a plurality of write operations. In this example, the refresh operation can correspond to up to five write operations, and the time for executing the refresh operation can be lengthened.

Hereinafter, referring to FIG. 7, FIG. 7 is a schematic waveform diagram illustrating a refresh operation during a read operation of a pseudo SRAM based on an embodiment of the present invention. In Fig. 7, a refresh request is sent immediately after the chip enable signal CE is valid, so that the refresh operation can be executed before the read operation.

In Fig. 7, after the chip enable signal CE is valid, the refresh request signal REF becomes valid immediately. In this embodiment, the refresh request signal REF is periodically valid, for example by a counter (not shown).

As shown in Fig. 7, in this embodiment, after the refresh operation is finished, the operation driving signal RRASW becomes valid, and it is informed that execution of the read operation can be started. The first control signal CLP is generated after one of the first CLP clock and delay preparation signal RCDRDY in FIG. 7. In this example, the read delay is originally set to 5 clocks, but since the refresh request signal REF appears before the read operation, it is expanded to 10 clocks.

8 is a flowchart illustrating a method of controlling a pseudo SRAM based on an embodiment of the present invention. Referring to FIGS. 1 and 8 at the same time, in step S810, in the writing operation, the first counter 121 counts data input to the pseudo SRAM 100 by the reference clock signal CLK from the outside. , A first count value (FCV) is generated. In step S820, in the writing operation, the second counter 122 is driven by a joining clock signal CASP whose initial period is smaller than that of the reference clock signal CLK, and the dynamic memory array of the pseudo SRAM 100 ( The data written in 110) is counted to generate a second count value (SCV). In step S830, the comparator 123 compares the first count value FCV and the second count value SCV, and when the first count value FCV is equal to the second count value SCV, The write matching signal WRMTC is valid. In step S840, when receiving the valid write matching signal WRMTC, the address strobe clock generator 124 converts the writing operation from asynchronous mode to synchronous mode, and changes the period of the assembled clock signal CASP. Adjust so that it is equal to the period of the reference clock signal CLK. Details of the implementation of each step are all described in detail in the above-described examples and implementation methods, and are not repeated below.

9 is a flowchart illustrating a method for controlling pseudo SRAM based on an embodiment of the present invention. In FIG. 9, the flow of the judgment of the write operation and the read operation, the execution of the refresh operation, and the flow of the precharge operation will be described as an example.

Referring to FIG. 9, it is shown in step S910 whether the enabled chip enable signal CE is received and a write operation or read operation is performed. In step S920, whether or not a refresh request is transmitted is detected. When a refresh request is detected, a refresh operation is executed in step S930. In step S940, it is determined whether a writing operation or a reading operation is executed. When it is determined that the writing operation, the writing operation is executed in step S950. In step S960, it is detected whether the chip enable signal CE is invalidated. When it becomes invalid, the end of the write operation is indicated, and in step S970, the precharge operation is performed. When it is determined that the reading operation, the reading operation is executed in step S980. In step S965, it is detected whether the chip enable signal CE is invalidated. When it becomes invalid, the end of the read operation is indicated, and in step S975, a precharge operation is performed. The details of the implementation of each step are all described in detail in the above-described examples and implementation methods, and are not repeated below.

As described above, the present invention can be divided into two steps in performing a write operation, asynchronous mode and synchronous mode. In the asynchronous mode, the input clock signal shorter than the period of the reference clock signal is used to write data into the memory unit and compensate for the delay occurring in the process of inputting data. When the number of data written to the memory unit reaches the number of data written to the pseudo SRAM from the outside, the data is switched to the synchronous mode. By doing this, it is possible to effectively shorten the time required for the writing operation without requiring complicated control, lengthen the time for executing the refresh operation, and reduce errors and power consumption.

Although the text is shown as in the above embodiment, the scope of protection of the present invention is ionized because it is possible to change or modify the scope of the present invention without departing from the scope of the spirit of the present invention. It is based on what was limited in the claims.

[Industrial availability]

The present invention relates to a pseudo SRAM and a control method thereof, which allows data to be written to the dynamic memory array by an input clock signal shorter than the period of the reference clock signal in asynchronous mode, effectively reducing the time required for the write operation. It is possible to lengthen the time for executing the refresh operation.

100: pseudo SRAM
110: dynamic memory array
120: controller
121: first counter
122: second counter
123: comparator
124: address strobe clock generator
125: input command decoder
130: input and output circuit
140: pre-charge control circuit
210: synchronous controller
220: asynchronous clock controller
230: synchronous clock controller
240: one-shot pulse generator
250: clock regulator
510, 520: latch
530, 540: AND gate
550, 560: OR gate
ADQ: Data port signal
DATA: data
CASASP: Asynchronous base signal
CASP: Input clock signal
CASSP: Synchronous base signal
CE: chip enable signal
CS: Chip select signal
CLK: Reference clock signal
CLP: control signal
CLPSTP: Control end signal
CLSYNC: Synchronization decision signal
FCV: first count value
LTCSTA: count start signal
MODE: Operation signal
RASRW: Operation drive signal
RCDRDY: delay ready signal
RDFLG: Poison Flag Signal
REF: refresh request signal
SCV: second count value
PREP: Precharge signal
WRFLG: Write flag signal
WRMTC: write matching signal
S810 ~ S840, S910 ~ 980: Step

Claims (10)

In the control method applied to the pseudo SRAM,
In the writing operation, counting data input from the external to the pseudo SRAM by a reference clock signal to generate a first count value,
In the writing operation, generating a second count value by counting data written to the dynamic memory array of the pseudo SRAM by a joining clock signal whose initial period is smaller than that of the reference clock signal,
Comparing the first count value and the second count value and validating the write matching signal when the first count value is equal to the second count value,
Upon receiving the valid write matching signal, convert the write operation from asynchronous mode to synchronous mode until the write operation ends, and adjust the period of the input clock signal to be equal to the period of the reference clock signal Doing, including the control method. According to claim 1,
The control method,
Receiving a chip enable signal from the outside,
When the chip enable signal becomes valid, further comprising determining, based on the received command, execution of the write operation or read operation,
The step of determining the execution of the writing operation or the reading operation is:
Determining whether to receive a refresh request before executing the write operation or the read operation,
And receiving a refresh operation when receiving the refresh request. According to claim 2,
After the step of validating the write matching signal,
Detecting whether the chip enable signal is invalid,
And when the chip enable signal becomes invalid, performing a precharge operation. According to claim 1,
The step of converting the writing operation from the asynchronous mode to the synchronous mode until the writing operation ends, and adjusting the period of the input clock signal to be equal to the period of the reference clock signal,
Providing a delay ready signal,
Validating the synchronization determination signal when the write matching signal is valid in the writing operation,
Generating an asynchronous base signal when the delay ready signal is valid and when the synchronous determination signal is not valid,
When the synchronization determination signal becomes valid, in response to the reference clock signal, generating a corresponding synchronization base signal,
In the asynchronous mode, in response to the asynchronous base signal, generating the corresponding sub clock signal, and in the synchronous mode, in response to the synchronous base signal, generating the corresponding sub clock signal,
And receiving the input clock signal and generating a control signal in response to the input clock signal through a predetermined delay time. According to claim 2,
And in the read operation, reading data of the dynamic memory array by the input clock signal whose period is equal to the period of the reference clock signal. In the pseudo SRAM,
Dynamic memory array,
A controller coupled to the dynamic memory array,
And an input / output circuit coupled to the dynamic memory array and the controller,
The controller,
In the writing operation, a first counter for counting data input to the pseudo SRAM by a reference clock signal from the outside and generating a first count value,
A second counter for counting data written to the dynamic memory array by a joining clock signal whose initial period is smaller than a period of the reference clock signal in the writing operation, and generating a second count value;
Combined with the first counter and the second counter, and comparing the first count value and the second count value, when the first count value is equal to the second count value, the write matching signal is effective And the comparator
When receiving the write matching signal which is coupled to the comparator and becomes valid, converts the write operation from asynchronous mode to synchronous mode until the write operation ends, and the period of the assembled clock signal is the reference clock signal. An address strobe clock generator that adjusts to be equal to the period of, pseudo pseudo SRAM. The method of claim 6,
The controller,
When the dynamic memory array, the input / output circuit, and the address strobe clock generator are coupled to receive a chip enable signal from the outside and the chip enable signal becomes valid, based on the received command, the write operation or Further comprising an input command decoder for determining the execution of the read operation,
Prior to executing the write operation or the read operation, the input command decoder determines whether to receive a refresh request, and also executes a refresh operation when receiving the refresh request. The method of claim 7,
It is coupled to the input command decoder and the comparator and detects whether or not the chip enable signal is invalid when executing the write operation or the read operation, and also precharges when the chip enable signal is invalid. Further comprising a pre-charge control circuit for performing the operation,
After determining the execution of the write operation or the read operation, the input command decoder generates an operation signal and a delay preparation signal corresponding to the operation to be performed,
The address strobe clock generator,
A synchronization controller receiving the operation signal and the write matching signal, and in the write operation, when the write matching signal becomes valid, a synchronization controller for validating a synchronization determination signal,
An asynchronous clock that receives the delay ready signal, the synchronous decision signal, and the interlock clock signal, and generates an asynchronous base signal when the delay ready signal is valid and when the synchronous decision signal is not valid. With the controller,
A synchronous clock controller that receives the reference clock signal and the synchronization determination signal, and generates a corresponding synchronization base signal in response to the reference clock signal when the synchronization determination signal becomes valid;
Receiving the asynchronous base signal, the synchronous base signal, and the delay preparation signal, and in the asynchronous mode, in response to the asynchronous base signal, generating the corresponding clock signal, and in the synchronous mode, And a one-shot pulse generator for generating the corresponding clock signal in response to the synchronous base signal. The method of claim 8,
The address strobe clock generator,
A pseudo SRAM coupled to the one-shot pulse generator, further comprising a clock regulator that receives the input clock signal and generates a control signal in response to the input clock signal through a predetermined delay time. The method of claim 9,
In the read operation, the input / output circuit reads data of the dynamic memory array by the input clock signal whose period is equal to the period of the reference clock signal.

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