KR102103958B1 - Organic light emitting display apparatus and manufacturing method thereof - Google Patents

Abstract

According to an aspect of the invention, the substrate; A thin film transistor disposed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; An uneven pattern portion spaced apart from the thin film transistor and formed on the substrate and formed of an insulating layer; A pixel electrode formed on the uneven pattern portion; An intermediate layer formed on the pixel electrode and including an organic emission layer; And a counter electrode formed on the intermediate layer.

Description

Organic light emitting display device and manufacturing method thereof

The present invention relates to an organic light emitting display device and a method for manufacturing the same, and more particularly, to a back light emitting structured organic light emitting display device, an organic light emitting display device capable of preventing light leakage and improving light extraction efficiency It is about.

The organic light emitting display device is attracting attention as a next-generation display device because of its advantages of being capable of driving at a low voltage, light weight, thin shape, wide viewing angle, excellent contrast, and fast response speed.

Such an organic light emitting display device has a wide light emission wavelength, and thus, the light emission efficiency decreases and the color purity decreases. In addition, since the light emitted from the organic light emitting layer has no specific directionality, many of the photons emitted in an arbitrary direction do not reach the actual observer due to total internal reflection of the organic light emitting device, thereby reducing the light extraction efficiency of the organic light emitting device. In order to improve light extraction efficiency, a DBR (distributed brag reflector) mirror may be applied to the organic light emitting diode display, or a resonant structure that controls the thickness of the organic layer may be applied. However, this resonant structure improves the light efficiency, but there is a problem that color shift occurs according to the viewing angle.

An object of the present invention is to provide an organic light emitting display device having improved metal extraction efficiency by forming a metal partition in a pixel region, and a method for manufacturing the same.

According to an embodiment of the present invention, the substrate; A thin film transistor disposed on the substrate and including an active layer, a gate electrode, a source electrode, and a drain electrode; An uneven pattern portion spaced apart from the thin film transistor and formed on the substrate and formed of an insulating layer; A conductor partition wall formed along an outer slope of the uneven pattern portion; A pixel electrode formed on the uneven pattern portion; An intermediate layer formed on the pixel electrode and including an organic emission layer; And a counter electrode formed on the intermediate layer.

In the present invention, the uneven pattern portion may include an insulating layer formed on the same layer as the insulating layer constituting the thin film transistor.

In the present invention, a buffer layer is further provided between the substrate and the thin film transistor, and the uneven pattern portion may further include the buffer layer.

In the present invention, the uneven pattern portion may be formed such that the uneven pattern formed in the buffer layer exposes the surface of the substrate.

In the present invention, the irregular pattern portion pixel buffer layer including the buffer layer; And a pixel insulating layer formed to cover the pixel buffer layer.

In the present invention, the thin film transistor is stacked in the order of the active layer, the gate electrode, the source electrode and the drain electrode, a gate insulating layer is formed between the active layer and the gate electrode, the gate electrode and the source An interlayer insulating layer is formed between the electrode and the drain electrode, and the pixel insulating layer of the uneven pattern portion may be formed on the same layer as the gate insulating layer.

In the present invention, the interlayer insulating layer forms an opening on the substrate, and the uneven pattern portion may be formed in the opening.

In the present invention, the pixel electrode may include a transparent conductive material.

The method of claim 8, wherein the pixel electrode is indium tin oxide (indium tin oxide: ITO), indium zinc oxide (indium zinc oxide: IZO), zinc oxide (zinc oxide: ZnO), indium oxide (indium oxide: In2O3), It may include at least one selected from the group containing indium galium oxide (indium galium oxide: IGO) and aluminum zinc oxide (AZO).

In the present invention, the uneven pattern portion, at least two or more insulating layers may be laminated.

In the present invention, the two or more insulating layers may have different refractive indices.

In the present invention, the two or more insulating layers have the same outer etch surface, and the partition wall may be stacked on the outer etch surface.

In the present invention, a capacitor first electrode formed on the same layer as the active layer and a capacitor second electrode formed of the same material as the pixel electrode may be included.

In the present invention, the counter electrode may be a reflective electrode.

In the present invention, a thin film transistor covering the thin film transistor and laterally spaced apart from the thin film transistor to further include a pixel defining layer having an opening, and the pixel electrode may be disposed in an opening formed in the pixel defining film.

According to another embodiment of the present invention, a first mask process for forming a buffer layer on a substrate and patterning the buffer layer to form a pixel buffer layer having an uneven pattern; A second mask process for forming a semiconductor layer on a substrate and patterning the semiconductor layer to form an active layer of a thin film transistor; A first insulating layer GI is formed, a first conductive layer is stacked on the first insulating layer, and the first conductive layer is patterned to form a gate electrode of a thin film transistor and an etch stop in the side of the gate electrode. Forming a third mask process; Forming a second insulating layer (ILD), patterning the second insulating layer to form a first opening exposing the active layer, and patterning the first insulating layer exposed to the etch stop to form an uneven pattern portion A fourth mask process; Forming a second conductive layer and patterning the second conductive layer to form a partition wall formed along a slope of a source electrode, a drain electrode, and the uneven pattern portion; A sixth mask process of forming a third conductive layer (anode) and patterning the third conductive layer to form a pixel electrode on a portion of the uneven pattern portion; And a seventh mask process for forming a third insulating layer and forming an opening exposing the pixel electrode. A method of manufacturing an organic light emitting display device comprising:

In the present invention, the uneven pattern portion may include the buffer layer and the first insulating layer.

In the present invention, the fifth mask process may form the partition wall along the slopes of the buffer layer and the first insulating layer.

In the organic light emitting diode display and the manufacturing method according to the above-described embodiments, the light leakage phenomenon may be improved by forming a metal partition in the pixel area.

In addition, it is possible to reduce the resistance of the cathode electrode.

1 is a cross-sectional view schematically showing an organic light emitting diode display according to an exemplary embodiment of the present invention.
2A to 2F are cross-sectional views sequentially illustrating a method of manufacturing the OLED display of FIG. 1.
3 is a plan view showing an example of a partition wall shape.
4 is a cross-sectional view schematically showing an organic light emitting diode display according to another exemplary embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present invention pertains can easily practice. The present invention can be implemented in many different forms and is not limited to the embodiments described herein.

In order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar elements throughout the specification.

In addition, in various embodiments, components having the same configuration are typically described in the first embodiment by using the same reference numerals, and in other embodiments, the configuration different from the first embodiment will be mainly described. do.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, the present invention is not necessarily limited to those illustrated.

In the drawings, thicknesses are enlarged to clearly represent various layers and regions. In the drawings, thicknesses of some layers and regions are exaggerated for convenience of description. Layers, membranes, areas, plates, etc. are different parts? When it is said, this includes the case where another part is “on the right” as well as the case where there is another part in the middle.

In addition, throughout the specification, when a part “includes” a certain component, it means that the component may further include other components, not to exclude other components, unless otherwise stated. In addition, in the whole specification, "to top" means to be located above or below the target part, and does not necessarily mean to be located above the center of gravity.

1 is a cross-sectional view schematically showing an organic light emitting display device 1 according to an embodiment of the present invention.

Referring to FIG. 1, a pixel area PXL, a transistor area TR, and a capacitor area CAP are provided on the substrate 10.

The substrate 10 may be provided as a transparent substrate such as a plastic substrate including polyethylen terephthalate (PET), polyethylen naphthalate (PEN), and polyimide, as well as a glass substrate.

A buffer layer 11 may be provided on the substrate 10. The buffer layer 11 is formed to form a smooth surface on the upper portion of the substrate 10 and prevent impurity elements from penetrating, and may be formed of a single layer or multiple layers of silicon nitride and / or silicon oxide.

In this embodiment, the buffer layer 11 formed in the uneven pattern in the pixel area PXL forms first to fourth openings C1 to C4 to form an uneven pattern. In particular, the buffer layer 11 formed in the uneven pattern may include openings C1 to C4 having an oblique slope so that the metal partition 116 can be deposited obliquely. The buffer layer 11 of the pixel area forms the pixel buffer layer 111 and the first and second concavo-convex buffer layers 11a and 11b, and an organic light emitting material 119 to be described later is generated in the area on the pixel buffer layer 111.

The active layer 212 is provided on the buffer layer 11. The active layer 212 may be formed of a semiconductor including amorphous silicon or crystalline silicon. The active layer 212 may include a channel region 212d and a source region 212b and a drain region 212c doped with ion impurities on the outside of the channel region 212d.

In the transistor region TR, the gate electrode 214 is provided on the active layer 212 at a position corresponding to the channel region 212d of the active layer 212 with the first insulating layer 13 as a gate insulating layer therebetween. .

The gate electrode 214 is, for example, aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd) , Iridium (Ir), Chromium (Cr), Nickel (Li), Calcium (Ca), Molybdenum (Mo), Titanium (Ti), Tungsten (W), Copper (Cu). Can be formed.

The source electrode 216a and the drain electrode (respectively) connected to the source region 212b and the drain region 212c of the active layer 212 with the second insulating layer 15 as an interlayer insulating layer therebetween on the gate electrode 214. 216b) is provided. The source electrode 216a and the drain electrode 216b are aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd) ), Iridium (Ir), chromium (Cr), nickel (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) and includes at least one metal material selected from , It may be formed of a single layer or multiple layers.

A third insulating layer 18 is provided on the second insulating layer 15 to cover the source electrode 216a and the drain electrode 216b. The third insulating layer 18 may be provided as an organic insulating layer.

On the other hand, the buffer layer 11 and the first insulating layer 13 extending into the pixel region PXL form an uneven pattern portion 115 having the same etched surface on the outside, and a partition wall is formed at the edge of the uneven pattern portion 115. (116) is formed. In more detail, a pixel insulating layer 113 in which a portion of the first insulating layer 13 is etched is formed on the buffer layers 111, 11a, and 11b of the pixel region PXL having an uneven pattern, and the pixel buffer layer 111 , The first and second uneven buffer layers 11a and 11b and the pixel insulating layer 113 form the uneven pattern portion 115. In addition, a metal partition wall 116 is formed on the outer slope of the uneven pattern portion 115.

The buffer layers 111, 11a, and 11b forming the uneven pattern portion 115 and the pixel insulating layer 113 may be formed of a single layer or multiple layers of insulating layers, respectively. Also, the buffer layers 111, 11a, and 11b and the pixel insulating layer 113 may be formed of materials having different refractive indices. The buffer layers 111, 11a, 11b and the first insulating layer 13 are at least selected from the group comprising SiNx, SiO2, SiON, HfO2, Si3N4, ZrO2, TiO2, Ta2O4, Ta2O5, Nb2O5, Al2O3, BST and PZT. It can contain one. In addition, a partition wall 116 including a metal material is formed on the edge of the uneven pattern portion 115 to prevent light leakage.

That is, light is primarily reflected by the uneven pattern portion 115 without leaking to the outside, and secondly, the light path exiting to the side is blocked by the partition wall 116 located at the edge of the uneven pattern portion 115. As described later, the partition wall 116 may be formed of a component such as source / drain electrodes 216s / 216d.

The partition wall 116 may have various shapes.

3 is a plan view showing an example of the shape of the partition wall 116. The partition wall 116 may be located at the left and right peripheral portions of the opening C5 as shown in FIG. 3 (a), or may be located at the upper, lower, left, and right peripheral portions as shown in FIG. In another embodiment, it may not be continuously formed around FIG. 3 (c) and the opening C5, but may be cut into a plurality of parts. In addition to this, the shape of the partition wall according to the present invention can be variously manufactured in a form that is separated or connected to the upper, lower, left, and right of the pixel portion.

Referring back to FIG. 1, the pixel electrode 117 is formed according to some regions on the pixel insulating layer 113. The pixel electrode 117 may be made of a transparent conductive material. Transparent conductive materials include indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO; It may include at least one selected from the group comprising indium galium oxide (AZO), and aluminum zinc oxide (AZO).

An intermediate layer (not shown) including the organic emission layer 119 is provided on the pixel electrode 117. The organic emission layer 119 may be a low molecular organic material or a high molecular organic material. When the organic light emitting layer 119 is a low molecular organic material, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL), and electron injection are provided in the intermediate layer (not shown). A layer (electron injection layer) or the like may be laminated. In addition, various layers may be stacked as necessary. In this case, copper phthalocyanine (CuPc: copper phthalocyanine), N'-di (naphthalene-1-yl) -N (N'-Di (naphthalene-1-yl) -N), N'-diphenyl -Benzidine (N'-diphenyl-benzidine: NPB), tris-8-hydroxyquinoline aluminum (Alq3), and can be applied in various ways. Meanwhile, when the organic emission layer 119 is a polymer organic material, a hole transport layer (HTL) may be included in the intermediate layer (not shown). As the hole transport layer, polyethylene dihydroxythiophene (PEDOT: poly- (3,4) -ethylene-dihydroxy thiophene), polyaniline (PANI), or the like can be used. At this time, as an organic material that can be used, a polymer organic material such as poly-phenylenevinylene (PPV) -based and polyfluorene-based may be used. The organic emission layer 119 may form one unit pixel as sub-pixels emitting red, green, and blue light.

In the above-described embodiment, the case where the organic light emitting layer 119 is formed inside the opening C5 to form a separate light emitting material for each pixel is described as an example, but the present invention is not limited thereto. The organic emission layer 119 may be commonly formed in the entire third insulating layer 18 regardless of the pixel position. In this case, the organic light emitting layer may be formed, for example, by layering or mixing a layer including a light emitting material emitting red, green, and blue light vertically.

The counter electrode 120 is deposited as a common electrode on the organic emission layer 119. The counter electrode 21 may be formed as a common electrode. In the case of the organic light emitting diode display according to the present embodiment, the pixel electrode 117 is used as an anode electrode, and the counter electrode 120 is used as a cathode electrode. Of course, the polarity of the electrode can be applied in reverse.

The counter electrode 120 may be configured as a reflective electrode including a reflective material. The counter electrode 120 may include one or more materials selected from Ag, Al, Mg, Li, Ca, LiF / Ca and LiF / Al.

Since the counter electrode 123 is provided as a reflective electrode, light emitted from the organic light emitting layer 119 is reflected by the counter electrode 120 and transmitted through the pixel electrode 117 made of a transparent conductive material, and emitted to the substrate 10 side. do. At this time, the uneven structure 115 and the partition wall 116 of the pixel area PXL can improve the light extraction efficiency of the organic light emitting display device 1 and increase the color reproduction rate.

In the capacitor region CAP, a capacitor first electrode 312 is formed on the substrate 10 on the same layer as the active layer 212. The first insulating layer 13 is extended to form a dielectric film of the capacitor. The second electrode 317 of the capacitor formed of the same material as the pixel electrode 117 described above is formed on the first insulating layer 13. In the present embodiment according to FIG. 1, the case where the dielectric film of the capacitor corresponds only to the first insulating layer 13, but both the first insulating layer 13 and the second insulating layer 15 form a dielectric film of the capacitor It can also be assumed.

The third insulating layer 18 is disposed on the second electrode 317 of the capacitor. A third insulating layer 18 including an organic insulating material having a small dielectric constant is interposed between the counter electrode 120 and the upper electrode 317 to be formed between the counter electrode 120 and the second electrode 317 of the capacitor. By reducing the parasitic capacity that can be prevented, signal interference due to the parasitic capacity can be prevented.

2A to 2G are cross-sectional views sequentially illustrating a method of manufacturing the OLED display of FIG. 1.

Referring to FIG. 2A, FIG. 2B shows the result of the first mask process, forming the buffer layer 11 on the substrate 10, and patterning the buffer layer 11 to form the first to the pixel area PXL. The fourth openings C1 to C4 are formed. A first uneven buffer layer 11a, a second uneven buffer layer 11b, and a pixel buffer layer 111 are formed by the first to fourth openings. The first uneven buffer layer 11a and the second uneven buffer layer 11b become a part of the uneven pattern portion 115 to be described later.

The buffer layer 11 prevents the diffusion of impurity ions, prevents penetration of moisture or outside air, and may serve as a barrier layer and a blocking layer for planarizing the surface. The buffer layer 11 may be formed by various deposition methods such as plasma enhanced chemical vapor deosition (PECVD) method, atmospheric pressure CVD (APCVD) method, and low pressure CVD (LPCVD) method using SiO ₂ and / or SiN _x or the like. You can.

The first mask process by photolithography is followed by exposure to a first mask (not shown) with an exposure apparatus (not shown), followed by a series of development, etching and stripping or ashing. Proceeds through the process of Hereinafter, description of the same content in the subsequent mask process will be omitted.

Next, referring to FIG. 2B, FIG. 2B shows the result of the second mask process, and forms the active layer 212 and the first electrode 312 of the capacitor on the buffer layer 11.

Although not shown in detail in FIG. 2B, a semiconductor layer (not shown) is formed on the buffer layer 11, and a photoresist (not shown) is applied, followed by a photolithography process using a second mask (not shown). The semiconductor layer (not shown) is patterned to form the active layer 212 and the first electrode 312 of the capacitor.

The semiconductor layer (not shown) may be formed of amorphous silicon or polysilicon. The semiconductor layer may be deposited on the buffer layer 11 by various deposition methods, such as plasma enhanced chemical vapor deposition (PECVD), atomic pressure CVD (APCVD), and low pressure CVD (LPCVD).

Referring to FIG. 2C, the first insulating layer 13 is formed on the entire surface of the result of the second mask process of FIG. 2B, the gate electrode 214 on the first insulating layer 13, and etching for the uneven pattern The blocking portion 114 and the etching blocking portion 314 of the capacitor are formed.

The etch stop 114 of the pixel region PXL is formed in regions corresponding to the first insulating layer 13 on the pixel buffer layer 111 and the first and second uneven buffer layers 11a and 11b.

Ion impurities are first doped (D1) into the active layer 212 using the gate electrode 214 formed on the first insulating layer 13 as a self-align mask. A source region 212b and a drain region 212c doped with ion impurities are formed, and a channel region 212d with no ion impurities doped.

Referring to FIG. 2D, a second insulating layer 15 is formed on a result of the third mask process of FIG. 2C, and the second insulating layer 15 is patterned by a third mask (not shown) to form a pixel region The openings C6 and C7 are exposed, the openings C12 exposing the source region 212b and the drain region 212c, and the openings C13 exposing the capacitor region.

In this case, the buffer layers 111, 11a, and 11b and the first insulating layer 13 under the etch stop 114 are not etched, and the region between the etch stop 114 and the second insulating layer 15 is not etched. Only the buffer layer 11 and the first insulating layer 13 corresponding to are etched. As a result, the first insulating layer 13 located outside the first and second uneven buffer layers 11a and 11b is partially etched, and the first insulating layer 13 under the etch stop 114 is a pixel insulating layer. (113).

Therefore, the sixth opening C6 and the seventh opening C7 in which the buffer layer 11 and the first insulating layer 13 are not formed are formed in the outer regions of the uneven pattern portion 115 and the pixel insulating layer 113. Therefore, light leakage along the buffer layer 11 and the first insulating layer 13 can be prevented.

Referring to FIG. 2E, a source electrode 216a, a drain electrode 216b, and a partition wall 116 are formed on the result of the fourth mask process of FIG. 2D. The source electrode 216a, the drain electrode 216b, and the partition wall 116 may be selected from the same conductive material as the gate electrode, but are not limited thereto and may be formed of various conductive materials.

The partition 116 may be formed along one side of the sixth opening C6 and the seventh opening C7. The partition 116 is formed obliquely along the outer slopes of the first and second uneven buffer layers 11a and 11b and the pixel insulating layer 113. The partition 116 serves as a reflective film that prevents light generated from the organic emission layer 119 to be described later leaking out of the pixel area PXL.

In addition, when patterning the source electrode 216a, the drain electrode 216b, and the partition wall 116, the etch stop portion 114 for the uneven pattern and the etch stop portion 314 of the capacitor are removed. Ion impurities on the resultant product are subjected to secondary doping (D2) by targeting the first electrode 312 of the capacitor. Although not shown in the drawing, an etch stop 114 that is not removed may remain between the partition wall 116 and the pixel insulating layer 113.

Referring to FIG. 2F, a pixel electrode 117 and a second electrode 317 of a capacitor are formed on the result of the fifth mask process of FIG. 2E.

The pixel electrode 117 and the second electrode 317 of the capacitor are indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3) It may be formed of a material containing at least one transparent conductive material selected from the group containing indium oxide (IGO), indium galium oxide (IGO), and aluminum zinc oxide (AZO).

Referring to FIG. 2G, a third insulating layer 18 is formed on the result of the sixth mask process of FIG. 2F. The third insulating layer 18 is patterned to form an opening C5 exposing the pixel electrode 117.

4 is a cross-sectional view schematically showing an organic light emitting diode display according to another exemplary embodiment of the present invention.

According to the embodiment of FIG. 4, unlike FIG. 1, it can be seen that the third insulating layer 18 is etched up to the partition wall 116 so that the counter electrode 120 contacts the partition wall 116. In the embodiment illustrated in FIG. 4, light traveling in the direction of the upper third insulating layer 18 may be reflected into the pixel region PXL by the uneven pattern of the counter electrode 120, and at the same time, the counter electrode 120 The effect of decreasing the resistance of the cathode electrode by increasing the area.

Although the present invention has been described with reference to the embodiments shown in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

1: organic light emitting diode display 10: substrate
11: buffer layer 13: first insulating layer
15: second insulating layer 18: third insulating layer
111: pixel buffer layer 113: pixel insulating layer
115: uneven pattern portion 117: pixel electrode
119: organic light emitting layer 120: counter electrode
212: active layer 214: gate electrode
216a: source electrode 216b: drain electrode
312: first electrode of the capacitor 317: second electrode of the capacitor
PXL: Pixel area TR: Transistor area
CAP: capacitor area

Claims (18)

Board;
A buffer layer disposed on the substrate;
An insulating layer disposed on the buffer layer;
A pixel electrode disposed on the insulating layer in the first region of the substrate;
An intermediate layer disposed on the pixel electrode and including an organic emission layer; And
It includes; a counter electrode disposed on the intermediate layer;
The buffer layer includes a first opening around the pixel electrode in the first region,
The insulating layer covers the buffer layer and the first opening, and in the first region, the buffer layer and the insulating layer penetrate the buffer layer and the insulating layer outside the first opening and have a second opening having the same etching surface. Equipped,
A conductive partition is disposed along the side surface of the second opening,
The counter electrode is in contact with the conductive partition wall in the second opening, an organic light emitting display device. delete delete According to claim 1,
The first opening exposes the surface of the substrate, an organic light emitting display device. According to claim 1,
The conductive partition wall is in contact with the upper surface of the insulating layer, an organic light emitting display device. According to claim 1,
In the second region adjacent to the first region of the substrate, further comprising a thin film transistor including an active layer, a gate electrode, a source electrode and a drain electrode,
The buffer layer is disposed between the substrate and the active layer,
The insulating layer is disposed between the active layer and the gate electrode, the organic light emitting display device. delete According to claim 1,
The pixel electrode is an organic light emitting display device including a transparent conductive material. The method of claim 8,
The pixel electrode includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and indium galium oxide (indium galium oxide). An organic light emitting display device comprising at least one selected from the group comprising oxide: IGO) and aluminum zinc oxide (AZO). delete According to claim 1,
The buffer layer and the insulating layer are organic light emitting display devices having different refractive indices. delete The method of claim 6,
And a capacitor first electrode disposed on the same layer as the active layer and a capacitor second electrode including the same material as the pixel electrode. According to claim 1,
The counter electrode is an organic light emitting display device as a reflective electrode. The method of claim 6,
And a pixel defining layer covering the edge of the pixel electrode and the thin film transistor. Forming a buffer layer on a substrate having a first region and a second region adjacent to the first region, and forming a first opening and a second opening outside the first opening in the buffer layer of the first region of the substrate ;
Forming an active layer of a thin film transistor on the second region of the substrate;
A first insulating layer (GI) is formed on the active layer, and a gate electrode of the thin film transistor is formed on the first insulating layer of the second region of the substrate, and the first insulating layer of the first region of the substrate is formed. Forming an etch stop portion on the;
A third opening forming a second insulating layer (ILD), exposing the active layer to the first insulating layer and the second insulating layer in the second region of the substrate, and the etch-stopping portion of the first region of the substrate Forming a fourth opening having the same etch surface as the second opening in the first insulating layer exposed to;
Forming a source electrode and a drain electrode on a second insulating layer in the second region of the substrate, and forming a conductive partition wall disposed along side surfaces of the second opening and the fourth opening of the first region of the substrate ;
Forming a pixel electrode on the first insulating layer in which the etch stop portion of the first region of the substrate is removed;
Forming a third insulating layer covering an edge of the pixel electrode and having an opening exposing the pixel electrode;
Forming a light emitting layer in the opening of the third insulating layer; And
And forming a counter electrode on the light emitting layer.
A method of manufacturing an organic light emitting display device, wherein the counter electrode contacts a conductive partition wall in the fourth opening. delete delete

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