KR102100882B1 - Display device and data interpolation method thereof - Google Patents

Abstract

The present invention relates to a display device and an interpolation method thereof, wherein a display panel in which pixels are written in a matrix form; A compensation circuit for modulating data of the input image into compensation values; And a driver for writing data output from the compensation circuit to pixels of the display panel. The compensation circuit includes an intermediate value calculating unit having a plurality of calculation logics to output a compensation value calculated as an intermediate value between previously derived compensation values; And a delay unit for delaying the compensation value output from the calculation logics and inputting them to other calculation logics.

Description

DISPLAY DEVICE AND DATA INTERPOLATION METHOD THEREOF}

The present invention relates to a display device and an interpolation method for removing stains generated in a manufacturing process by a method of modulating data of an input image.

The flat panel display device is an electroluminescence display (ELD), field emission display device such as a liquid crystal display (LCD) or an organic light emitting diode display (OLED). Display, FED), plasma display panel (PDP), and electrophoresis display (Electrophoresis Display, EPD).

The liquid crystal display device displays an image by modulating light incident from the backlight unit by controlling an electric field applied to the liquid crystal layer. The active matrix type liquid crystal display device uses a thin film transistor (hereinafter referred to as "TFT") to drive a liquid crystal cell, which has the advantage of excellent image quality and low power consumption. Recent mass production technology development and research and development As a result, it is rapidly developing with large-scale and high-resolution. Such liquid crystal display devices are widely used in applications such as portable computers such as notebook PCs, office automation devices, audio / video devices, and indoor and outdoor advertising display devices.

The manufacturing process of the liquid crystal display device is a semiconductor process including a photolithography process to manufacture a TFT array substrate. The photolithography process will include a series of exposure, development, and etching processes.

Due to non-uniformity of the exposure amount in the photolithography process, various types of stains may be found in the inspection process for inspecting the display state of the finished substrate. The unevenness can be measured based on the result of displaying luminance data on the display panel and measuring luminance on the screen of the display panel. These stains look different in luminance or chromaticity compared to other normal pixels. The cause of the spots is that pixels with irregular spots such as the overlapping area between the gate and drain of the TFT, the height of the spacer, the parasitic capacitance between the signal wirings, and the parasitic capacitance between the signal wiring and the pixel electrode due to the difference in the exposure amount in the photolithographic process This is due to the position being different from other normal display pixels.

Although it is possible to improve the staining by improving the process technology or the repair process, there are limitations. Recently, a technique of reducing a defect level by applying a method of removing a spot from a display image by applying a preset compensation value to data to be displayed on pixels at a spot using a compensation circuit has been applied.

When a compensation value is generated for each pixel and the compensation value is optimized for each gray level, luminance measurement and compensation value calculation are repeated until the compensation values are derived, thereby increasing the processing time. In addition, if a large number of compensation values are stored in the compensation circuit, the memory capacity of the compensation circuit increases, thereby increasing the circuit cost. To improve this, a method of generating a compensation value to be applied to some pixels at a spot location and using the compensation data to generate a compensation value of the remaining pixels by an interpolation method has been proposed. The applicant of the present application has proposed an example of generating compensation values by an interpolation method through the domestic patent application 10-2012-0120631 (2012. 10. 29.). The proposed interpolation method can simplify the hardware logic by using the logic to calculate the intermediate value without using many multipliers required in the existing interpolation method. However, this method needs to be improved by repeating the same calculation process.

The present invention provides a display device capable of minimizing redundancy logic in hardware logic for generating a compensation value for compensating stains by an interpolation method, and calculating the compensation value, and the interpolation method.

The display device of the present invention includes a display panel in which pixels are arranged in a matrix form; A compensation circuit for modulating data of the input image into compensation values; And a driver for writing data output from the compensation circuit to pixels of the display panel.

The compensation circuit includes an intermediate value calculating unit having a plurality of calculation logics to output a compensation value calculated as an intermediate value between previously derived compensation values; And a delay unit for delaying the compensation value output from the calculation logics and inputting them to other calculation logics.

The interpolation method of the display device includes receiving previously derived compensation values; Outputting a compensation value calculated as an intermediate value between neighboring compensation values using a plurality of calculation logics; And delaying the compensation value calculated as an intermediate value between the neighboring compensation values and inputting it to other calculation logics.

The present invention includes a delay unit for delaying the compensation value generated earlier and inputting it to other calculation logic. As a result, the present invention can minimize redundancy logic in hardware logic for calculating the compensation value.

1 is a view showing a stain measurement method and a method of compensating stains based on the results.
2 is a flowchart showing a stain compensation method.
3 is a diagram showing a block interpolation method.
4 is a diagram showing a grayscale interpolation method.
5 to 7 are diagrams showing an interpolation method according to an embodiment of the present invention.
8 is a diagram illustrating an example of a hardware configuration for implementing the parallel interpolation method as in FIG. 7.
9 is a block diagram showing a compensation circuit according to an embodiment of the present invention.
10 is a block diagram showing in detail the intermediate value calculator illustrated in FIG. 9.
11 to 13 are diagrams showing examples in which the redundancy logic is deleted in the intermediate value calculator shown in FIG. 9.
14 and 15 are block diagrams illustrating a display device according to an exemplary embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Throughout the specification, the same reference numerals refer to substantially the same components. In the following description, when it is determined that a detailed description of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description is omitted. The component names used in the following description may be selected in consideration of ease of specification preparation, and may be different from parts names of actual products.

The display device of the present invention is any liquid crystal display (LCD), field emission display (FED), organic light emitting diode display (OLED Display), plasma display panel (PDP), electrophoretic display (Electrophoresis Display, EPD), etc. It is also applicable to flat panel display devices.

1 and 2, in the spot detection step (S1), data of the same gradation is written into all pixels of a display panel, the luminance at that time is captured by a camera, and an image of the camera is analyzed To measure the luminance of the pixels. As a result, when spots with uneven luminance of pixels are found, the compensation value generation step S2 generates a compensation value having an inverse relationship with the luminance distribution characteristic. The stain measurement and compensation value generation are repeated several times with varying gradations.

The compensation values are stored in the memory of the display device (S3). When the display device is normally driven and the data of the input image is input to the display panel driving circuit, the display panel driving circuit modulates the data by adding or subtracting the compensation values read from the memory to the data of the input image and modulating the data (S4). ). As a result, unevenness can be removed from the screen of the display panel.

To reduce the hardware burden, only the compensation values of some pixels at the spot position are stored in the memory, and the compensation values of the remaining pixels can be calculated by an interpolation method.

The interpolation method may include block interpolation methods (S41, S42) and grayscale interpolation method (S43). The block interpolation method can be divided into a vertical interpolation method and a horizontal interpolation method.

The compensation value generation step S2 does not calculate compensation values for all pixels, but divides pixels into I (I is a positive integer of 4 or more) x I blocks, such as 4x4 or 8x8. And the compensation value generation step (S2) is the pixel of the four vertex positions (P1 (x1, y1), P2 (x2, y2), P3 (x3, y3), P4 (x4, y4)) of the block as shown in FIG. Generate compensation values to be applied to the fields.

The vertical interpolation method S41 generates compensation values therebetween by using neighboring compensation values along the vertical direction y. The horizontal interpolation method S42 generates compensation values therebetween using neighboring compensation values along the horizontal direction x. For example, in FIG. 3, the compensation value at the C position is generated as an intermediate value between the compensation values at the P1 (x1, y1) and P3 (x3, y3) positions, and the compensation value at the D position is P2 (x2, y2) and P4. It may be generated as an intermediate value of the compensation values at the (x4, y4) position. The compensation value to be applied to the pixel at position A is generated as an intermediate value of the compensation values at P1 (x1, y1) and P2 (x2, y2), and the compensation value to be applied to the pixel at position B is P3 (x3, y3) and P4 ( x4, y4) may be generated as an intermediate value of the compensation values of the position. The compensation value of the P (x, y) position may be generated as an intermediate value of A and B or an intermediate value of C and D.

The gradation interpolation method (S43) does not generate compensation values for all the gradations that can be expressed in the pixel data of the input image, but of some gradations (Q1, Q2, Q3, Q4) divided at equal intervals in the gamma characteristic curve shown in FIG. 4. Compensation values are generated, and the compensation values of the remaining grayscales are calculated by an interpolation method.

The compensation values generated by the interpolation methods S41, S42, and S43 may be stored in the memory. These compensation values are added to or subtracted from the data of the input image (S44).

The interpolation method of the present invention is applied to a block interpolation method. In the following embodiments, the interpolation method in the horizontal direction is mainly described, but may be applied to the interpolation method in the vertical direction.

5 and 6, the interpolation method of the present invention includes a median calculation step, a search step, and a repeat calculation determination step.

The median calculation step calculates the median value using two reference values (Ref A, Ref B). The retrieval step determines whether the intermediate value has reached the intermediate value of the target position, and when the target position is reached, bypasses the intermediate value into memory and stores it as a new compensation value. And the search step calculates new reference values (Ref A ', Ref B') if the median is not the median of the target location. The iterative calculation step determines whether to execute the iteration by comparing N, which satisfies the maximum number of times N = Log ₂ (x2-x1), in which the intermediate value calculation step must be repeated to reach the target position, with the current number of iterations. The intermediate value calculation step and the search step are repeated N times to generate a compensation value up to the final target position.

The median calculation step may be implemented with a median filter. The intermediate value calculation step, the search step, and the iterative calculation decision step are designed in a pipeline structure so that the effect of latency required for filtering can be neglected since the intermediate value calculation must be performed for every clock in hardware implementation.

In the example of FIG. 5, if the compensation value of the final target position is Q (X), the median calculation step calculates the median three times to obtain Q (X). First, in the intermediate value calculation step, Q (x1) and Q (x2) are added and divided by 2 to generate a compensation value at the X3 position, and then Q (x3) and Q (x2) are added and divided by 2 to the compensation value at the X4 position Produces Subsequently, in the intermediate value calculating step, Q (x3) and Q (x4) are added and divided by 2 to generate a compensation value Q (x) of the final target external value. Since the median calculation can be implemented only with an adder and a bit shift operator, it can be easily implemented with logic without multipliers.

In general, data of an input image is inputted through one M port through one port. When M> N or M = N, M-1 interpolation blocks are configured in parallel to find new compensation values of M-1 by an interpolation method at the same time. 7 shows an example of a parallel interpolation method in which N = M = 8.

7 and 8, the intermediate value calculating unit of the compensation circuit uses seven interpolation blocks that receive first and ninth compensation values (Q (1) and Q (9)) and process the intermediate value in parallel. Then, Q (2) to Q (8) between Q (1) and Q (9) are calculated.

The median calculator first generates Q (5) by calculating the median of the first and ninth compensation values (Q (1) and Q (9)), and then intermediates between Q (1) and Q (5). Calculate the value and the median between Q (5) and Q (9) to produce Q (3) and Q (7). Subsequently, the intermediate value calculating unit is the intermediate value between Q (1) and Q (3), the intermediate value between Q (2) and Q (5), the intermediate value between Q (5) and Q (7), and Q Calculate the median between (7) and Q (9) to produce Q (2), Q (4), Q (6) and Q (8). In this way, the intermediate value calculating unit as shown in FIG. 8 calculates the intermediate value of various stages in order to generate the compensation value of the target position. As a result, interpolation blocks can include logics that compute the same median value. For example, as shown in FIG. 8, the interpolation block for generating Q (2) includes Q (5) calculation logic, and the interpolation block for generating Q (8) also includes Q (5) calculation logic. have. Since the same computational logic is redundantly used for interpolation blocks, the hardware resource and circuit cost of the compensation circuit are increased.

The present invention deletes redundant calculation logic, that is, redundancy logic between interpolation blocks to reduce hardware resources and circuit costs required for the compensation circuit by using the delay unit 12 as shown in FIGS. 9 and 10.

9 and 10, the compensation circuit of the present invention includes an intermediate value calculating unit 10 and a delay unit 12.

The intermediate value calculating unit 10 receives the first and M + 1 compensation values Q (1) and Q (M + 1) as reference values Ref A and Ref B, and the reference values Ref A and Ref B) Calculate the intermediate value between to generate new compensation values, and use the previously calculated intermediate values as reference values (Ref A ′, Ref B ′, Ref A ″, Ref B ″) without redundancy calculation. Create values.

The delay unit 12 delays the calculated intermediate value to generate a new compensation value, and inputs it to the calculation logic for generating another compensation value.

11 to 13 are diagrams showing examples in which the redundancy logic is deleted in the intermediate value calculator shown in FIG. 9. 11 is an example in which N = M = 8, and FIG. 12 is an example in which N> M (N = 8, M = 6). 13 is an example in which N <M (N = 8, M = 11).

11 to 13, the number of ports of compensation values generated by the interpolation method in the compensation circuit is M-1.

In the example of FIG. 11, Q (5) calculated as the intermediate value of Q (1) and Q (9) is delayed by the delay unit 12 and input as a reference value to generate other compensation values. In the calculation logic for generating Q (2) and (Q6), Q (2) and (Q6) are generated using Q (5) delayed by the delay unit 12 without Q (5) calculation logic. The compensation circuit includes Q (2) calculation logic, Q (3) calculation logic, Q (4) calculation logic, Q (5) calculation logic, Q (6) calculation logic, Q (7) calculation logic, and Q (8) Includes one calculation logic each. Therefore, in the compensation circuit, there is no redundancy logic to calculate the same intermediate value.

In the example of FIG. 12, Q (4) calculated as an intermediate value between Q (1) and Q (7) is delayed by the delay unit 12 and input as a reference value to generate other compensation values. In the calculation logic for generating Q (2) and (Q6), Q (2) and (Q6) are generated using Q (5) delayed by the delay unit 12 without Q (5) calculation logic. The compensation circuit includes Q (2) calculation logic, Q (3) calculation logic, Q (4) calculation logic, Q (5) calculation logic, and Q (6) calculation logic, respectively. Therefore, in the compensation circuit, there is no redundancy logic to calculate the same intermediate value.

Even in the example of FIG. 13, the compensation values Q (2) to Q (11) between Q (1) and Q (12) are calculated as calculation logics in which delayed compensation values are input without redundancy logic.

14 and 15 are block diagrams illustrating a display device according to an exemplary embodiment of the present invention.

14 and 15, the display device of the present invention includes a compensation circuit 200, a driving unit 110, and a display panel 100.

The display panel 100 includes a pixel array in which an input image is displayed. The pixel array includes data lines DL to which a data voltage is supplied, gate lines (or scan lines GL) orthogonal to the data lines DL and to which a gate pulse (or scan pulse) is supplied, and data lines. It includes pixels arranged in a matrix form defined by the intersection of (DL) and gate lines (GL). Each of the pixels may include one or more TFTs and capacitors.

When power is supplied to the display device, compensation values sampled from the read only memory (ROM) 120 are input to the compensation circuit 200. The sampled compensation values are compensation values generated as optimized values in some pixels and in some grayscales based on the stain detection method shown in FIG. 1. The compensation circuit 200 includes an intermediate value calculating unit 10 for calculating an intermediate value of neighboring compensation values as shown in FIGS. 9 and 10 to implement a block interpolation method, and a delay unit for delaying previously generated compensation values ( 12) to generate compensation values. The intermediate value calculating unit 10 receives the sampled compensation values as reference values, generates a new compensation value as an intermediate value of the reference values, and delays the previously calculated compensation values to reference values of calculation logic to generate other compensation values Use it as a.

 The compensation circuit 200 modulates the data of the input image by adding or subtracting the compensation values generated by the block interpolation method and the compensation values generated by the grayscale interpolation method to the digital video data (RGB) of the input image.

The driving unit 110 writes the data RGB ′ modulated by the compensation circuit 200 to the pixels PIX of the display panel 100. The driver 110 includes a data driver 101, a gate driver (or scan driver) 102, and a timing controller 103. The compensation circuit 200 may be built in the timing controller 103.

The data driver 101 converts digital video data RGB 'of the input image input from the timing controller 103 into an analog gamma compensation voltage to generate a data voltage, and supplies the data voltage to the data lines DL do. The gate driver 102 generates a gate pulse synchronized with the data voltage and sequentially supplies the gate lines GL while shifting the gate pulse.

The timing controller 103 receives digital video data (RGB) of an input image from a host system (not shown), and also vertical / horizontal synchronization signals (Vsync, Hsync), data enable signal (DE), and main clock (DCLK) Timing signals such as are received. The timing controller 103 transmits digital video data RGB ′ compensated by the compensation circuit 200 to the data driver 101. In addition, the timing controller 103 generates timing control signals DDC and GDC for controlling the operation timing of the data driver 101 and the gate driver using the timing signals Vsync, Hsync, DE, and CLK.

The host system may be any one of a television system, a set top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

Through the above description, those skilled in the art will appreciate that various changes and modifications can be made without departing from the spirit of the present invention. Therefore, the present invention should not be limited to the contents described in the detailed description, but should be defined by the claims.

100: display panel 110: drive unit
200: compensation circuit

Claims (5)

A display panel in which pixels are arranged in a matrix form;
A compensation circuit for modulating data of the input image into compensation values; And
And a driver for writing data output from the compensation circuit to pixels of the display panel,
The compensation circuit,
An intermediate value calculator having a plurality of calculation logics to output a compensation value calculated as an intermediate value between previously derived compensation values; And
And a delay unit for delaying the compensation value output from the calculation logics and inputting them to other calculation logics. According to claim 1,
In the display device,
Display device characterized in that there is only one calculation logic to calculate the same median. According to claim 1,
The compensation circuit,
Divide the screen of the display panel into blocks of a predetermined size and generate compensation values of all pixels in the block by using the intermediate value calculator and the delay unit,
A display device characterized by generating compensation values of other gradations than the previously derived gradation by an interpolation method. An interpolation method of a display device including a display panel in which pixels are arranged in a matrix form, a compensation circuit for modulating data of an input image into compensation values, and a driver for writing data output from the compensation circuit to pixels of the display panel. In,
Receiving previously derived compensation values;
Outputting a compensation value calculated as an intermediate value between neighboring compensation values using a plurality of calculation logics; And
And delaying the compensation value calculated as an intermediate value between the neighboring compensation values and inputting it to other calculation logics. The method of claim 4,
The step of generating the compensation values,
Divide the screen of the display panel into blocks of a predetermined size and generate compensation values of all pixels in the block,
An interpolation method of a display device, characterized in that compensation values of other gradations than the previously derived gradations are generated by an interpolation method.

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