KR102096458B1 - Structure with embedded memory device and contact isolation scheme - Google Patents

Abstract

The present disclosure provides a method of manufacturing an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; Depositing an interlayer dielectric (ILD) layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

Description

STRUCTURE WITH EMBEDDED MEMORY DEVICE AND CONTACT ISOLATION SCHEME

This application claims priority to U.S. Provisional Application 62 / 592,810 (filed on November 30, 2017), incorporated herein by reference in its entirety.

In an integrated circuit, an integrated circuit pattern can be formed on a substrate using a number of manufacturing techniques including photolithography patterning, etching, film formation, and implantation. Thus, the integrated circuit formed includes a number of devices such as field effect transistors, diodes, bipolar transistors, imaging sensors, light emitting diodes, memory cells, resistors, and capacitors integrated together. The memory device can include a passive device, such as a capacitor or resistor, connected to another device, such as a field effect transistor. In existing technology, passive devices such as resistors are formed through a number of semiconductor technologies, including etching. This technique limits and inaccurately controls the dimensions of passive devices, which results in large variations in device dimensions and device performance. In some cases, the device parameters may be out of specification, causing errors in the circuit. In addition, existing methods are difficult to implement in high-tech nodes due to large processing variations and small feature sizes. In particular, when semiconductor technology advances to advanced feature nodes of smaller feature sizes, such as 7 nm or less, misalignment has less tolerance and can lead to leakage, short circuit, open or other error defects or reliability problems. have. Accordingly, the present invention provides structures and methods for solving the above problems.

The present disclosure provides a method of manufacturing an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; Depositing an interlayer dielectric (ILD) layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

Aspects of the invention are best understood from the following detailed description with reference to the accompanying drawings. It is emphasized that, according to standard practice in this industry, various features are not shown proportionally. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
1A is a top view of a semiconductor device structure constructed in accordance with various aspects of the present disclosure in one embodiment.
1B and 1C are cross-sectional views along dashed lines AA 'and BB', respectively, of the semiconductor structure of FIG. 1A, in accordance with some embodiments.
1D is a cross-sectional view of the gate stack of the semiconductor device structure in FIG. 1B constructed in accordance with some embodiments.
2A is a flowchart of a method of forming an integrated circuit (IC) structure in accordance with some embodiments.
2B is a flowchart of the operation in the method of FIG. 2A in accordance with some embodiments.
3A and 3B show cross-sectional views of exemplary integrated circuit structures at a manufacturing stage made by the method of FIG. 2A in accordance with multiple embodiments.
4, 5, 6, 7, and 8 illustrate cross-sectional views of exemplary integrated circuit structures among multiple manufacturing stages made by the method of FIG. 2A constructed in accordance with multiple embodiments.
9A is a top view of a semiconductor device structure constructed in accordance with various aspects of the present disclosure in one embodiment.
9B and 9C are cross-sectional views along dashed lines AA 'and BB', respectively, of the semiconductor structure of FIG. 9A, in accordance with some embodiments.
10A and 10B are flowcharts of each operation in the method of FIG. 2A in accordance with some embodiments.
11, 12, 13, and 14 show cross-sectional views of exemplary integrated circuit structures among multiple manufacturing stages constructed in accordance with some embodiments.
15A is a top view of a semiconductor device structure constructed in accordance with various aspects of the present disclosure in one embodiment.
15B and 15C are cross-sectional views along dashed lines AA 'and BB', respectively, of the semiconductor structure of FIG. 15A, in accordance with some embodiments.
16A, 16B, and 16C are flowcharts of operations in the method of FIG. 2A in accordance with multiple embodiments.
17, 18, 19, 20, and 21 show cross-sectional views of exemplary integrated circuit structures among multiple manufacturing stages constructed in accordance with some embodiments.
22A is a top view of a semiconductor device structure constructed in accordance with various aspects of the present disclosure in one embodiment.
22B and 22C are cross-sectional views along dashed lines AA 'and BB', respectively, of the semiconductor structure of FIG. 22A, in accordance with some embodiments.
23 is a flowchart of operation in the method of FIG. 2A in accordance with some embodiments.
24, 25, 26, 27, 28, and 29 illustrate cross-sectional views of exemplary integrated circuit structures among multiple manufacturing stages constructed in accordance with some embodiments.
30A is a top view of a semiconductor device structure constructed in accordance with various aspects of the present disclosure in one embodiment.
30B and 30C are cross-sectional views along dashed lines AA 'and BB', respectively, of the semiconductor structure of FIG. 30A, in accordance with some embodiments.
31A is a flowchart of operation in the method of FIG. 2A in accordance with some embodiments.
32, 33, 34, 35, 36, 37, and 38 illustrate cross-sectional views of exemplary integrated circuit structures among multiple manufacturing stages constructed in accordance with some embodiments.

The following description provides a number of different embodiments or embodiments for implementing different features of the present invention. Specific embodiments of components and arrangements are described below to simplify the present invention. Of course, this is only an example and is not intended to be limiting. For example, in the following description, the formation of the first feature on or on the second feature may include embodiments in which the first and second features are formed and in direct contact, with the first and second features in direct contact. It may also include embodiments in which additional features may be formed between the first and second features so as not to. In addition, the present invention may be repeated in reference numerals and / or characters in various embodiments. This repetition is for simplicity and clarity, and does not itself represent a relationship between the various embodiments and / or configurations discussed. It will be understood that the following description provides a number of different embodiments or embodiments for implementing different features of various embodiments. Specific embodiments of components and arrangements are described below to simplify the present invention. Of course, this is only an example and is not intended to be limiting.

Also, spatially related terms such as “below”, “below”, “low”, “high”, “upper”, and the like, as illustrated in the drawings, the relationship of features to one element or another element It may be used for convenience of explanation to indicate. Space-related terms are intended to include different orientations of the device in use or operation for the orientation depicted in the figures. For example, when the device in the figure is turned over, an element described as “below” or “below” other elements or features is oriented “above” the other elements or features. Thus, the exemplary term “below” can include both an orientation of above and below. The device may be oriented differently (rotate 90 degrees or other orientation), and accordingly the spatial descriptors used herein may be interpreted as well.

1A is a top view of a semiconductor structure (or work piece) 100 constructed in accordance with various aspects of the present disclosure in one embodiment. 1B is a cross-sectional view along the dotted line AA ′ of the semiconductor structure 100, in accordance with some embodiments. 1C is a cross-sectional view along the dotted line BB 'of the semiconductor structure 100, in accordance with some embodiments. The semiconductor structure 100 and its manufacturing method are collectively described with reference to FIGS. 1A to 1C and other drawings. In some embodiments, semiconductor structure 100 includes a fin active region and a fin field-effect transistor (FinFET) formed thereon. In some embodiments, the semiconductor structure 100 may include a flat active region on which a flat field-effect transistor (FET) is formed. The semiconductor structure 100 includes an FET that can be an n-type FET (nFET) or a p-type FET (pFET). The semiconductor structure 100 further includes a capacitor electrically connected to the FET, such as a source of the FET. As an example for illustrative purposes only, not limitation, the FET is an nFET. The FET and the capacitor are connected to collectively function as a memory device such as resistive random-access memory (RRAM) or dynamic RAM (DRAM). In some other embodiments, the memory device is one-time programming (OTP) memory (eg, embedded OTP memory).

The semiconductor structure 100 includes a substrate 102. The substrate 102 includes a bulk silicon substrate. Alternatively, the substrate 102 may include a basic semiconductor such as silicon or germanium in the crystal structure; Silicon germanium, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide antimonide), or combinations thereof. In addition, possible substrates 102 include silicon-on-insulator (SOI) substrates. SOI substrates are manufactured using separation by implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods.

Substrate 102 also includes multiple isolation features, such as isolation features 104, formed on substrate 102 and defining multiple active regions on substrate 102, such as active region 106. do. Isolation feature 104 uses isolation techniques such as shallow trench isolation (STI) to define and electrically isolate multiple active regions. Isolation feature 104 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The isolation region 104 is formed by any suitable process. In one embodiment, forming the STI feature comprises a lithography process to expose a portion of the substrate, etching the trench to the exposed portion of the substrate (eg, by using dry etching and / or wet etching), (eg, Filling the trench with one or more dielectric materials (by using a chemical vapor deposition process), and planarizing the substrate by a polishing process such as a chemical mechanical polishing (CMP) process and removing excess portions of the dielectric material (s). do. In some embodiments, the filled trench can have a multi-layer structure, such as a thermal oxide liner layer and a filling layer (s) of silicon nitride or silicon oxide.

Active region 106 is an area having a semiconductor surface on which a number of doped features are formed and composed of one or more devices, such as diodes, transistors, and / or other suitable devices. The active region is a semiconductor material similar to the bulk semiconductor material (such as silicon) of the substrate 102 or different semiconductor materials such as silicon germanium (SiGe), silicon carbide (SiC), or performance enhancement, such as a deformation effect to increase carrier mobility For, it may include multiple layers of semiconductor material (eg, alternative silicon and silicon germanium layers) formed on the substrate 102 by epitaxial growth. In this embodiment, the active region 106 has an elongated shape oriented in the X direction.

In this embodiment, the active region 106 is three-dimensional, such as a pin active region extending over the isolation feature 104. The fin active region protrudes from the substrate 102 and has a three-dimensional profile to more effectively connect between the channel region (or simply referred to as a channel) and the gate electrode of the FET. The fin active region 106 may be formed by selective etching to recess the isolation feature 104 or selective epitaxial growth to grow the active region with the same or different semiconductor as the substrate 102, or a combination thereof. You can. The fin active region 106 is also referred to simply as the fin 106.

The semiconductor substrate 102 further includes multiple doping features, such as n-type doping wells, p-type doping wells, source and drain, other doping features, or combinations thereof, configured to form multiple devices or components of the device. In one embodiment, semiconductor structure 100 includes doped well 110 of a first type dopant on fin active region 106. The doping well 110 can be extended to an area underneath the isolation feature 104 by diffusion. As described above for illustrative purposes only, the FET formed on fin 106 is an nFET. In this case, doped well 110 is doped with a p-type dopant (henceforth referred to as p-well). The dopant (boron, etc.) in the doping well 110 can be introduced into the fin 106 by ion implantation or other suitable technique. For example, forming a patterned mask having an opening on the substrate 102, the opening defining an area for the doping well 110; And a doping well 110 may be formed by a procedure including performing ion implantation to introduce a p-type dopant (boron, etc.) into the fin 106 using a pattern mask as an implantation mask. . The pattern mask can be a patterned resist layer or film formed by lithography, a pattern hard mask formed by lithography process, etching. In an alternative embodiment, the FET on fin 106 is a pFET, and the doping well 110 can be doped with an n-type dopant, such as phosphorous.

The semiconductor structure 100 further includes a gate stack 114 disposed in the fin 106 and having a rectangular shape oriented in the Y direction. The Y direction is orthogonal to the X direction, and both the X direction and the Y direction define the upper surface of the substrate 102. The upper surface has a normal direction along the Z direction orthogonal to both the X direction and the Y direction. The gate stack 114 includes a gate dielectric layer 116 and a gate electrode 120 formed on the gate dielectric layer. The gate stack 114 may have a height in the range of 10 nm to 20 nm, according to some embodiments.

Gate dielectric layer 116 comprises a dielectric material, such as silicon oxide. In other embodiments, the gate dielectric layer alternatively or additionally includes other suitable dielectric materials for circuit performance and manufacturing integration. For example, the gate dielectric layer 116 includes a layer of high k dielectric material, such as metal oxide, metal nitride, or metal oxynitride. In various embodiments, the high k dielectric material layer is a metal formed by a suitable method such as metal organic chemical vapor deposition (MOCVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or molecular beam epitaxy (MBE). Oxides, ie ZrO ₂ , Al ₂ O ₃ , and HfO ₂ . The gate dielectric layer may further include an interfacial layer interposed between the semiconductor substrate 102 and the high-k dielectric material. In some embodiments, the interfacial layer comprises silicon oxide formed by ALD, thermal oxidation, or ultraviolet-Ozone Oxidation.

Gate electrode 120 includes metal, such as aluminum, copper, tungsten, metal silicide, metal alloys, doped poly-silicon, other suitable conductive materials, or combinations thereof. The gate electrode 120 includes multiple conductive films designed such as a capping layer, a work function metal layer, a blocking layer, and a filling metal layer (such as aluminum or tungsten). can do. Multiple conductive films are designed for work functions that match nFETs (or pFETs). In some embodiments, the gate electrode 120 for the nFET includes a work function metal having a composition designed with a work function of 4.2 eV or less. In other cases, the gate electrode for the pFET includes a work function metal having a composition designed with a work function of 5.2 eV or higher. For example, a work function metal layer for an nFET includes tantalum, titanium, aluminum, titanium aluminum nitride, or combinations thereof. In other embodiments, the work function metal layer for the pFET comprises titanium nitride, tantalum nitride, or combinations thereof.

The gate stack 114 may further include a gate spacer 122 formed on a sidewall of the gate electrode 120. Spacer 122 includes silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The spacer 122 may have a multi-layer structure and may be formed by anisotropic etching such as plasma etching after depositing a dielectric material.

The gate stack 114 is formed by a suitable procedure such as a gate-last process, dummy gates are formed first, and after formation of the source and drain, they are replaced by metal gates. Alternatively, the gate stack is formed by a high k last process, and both the gate dielectric material layer and the gate electrode are replaced with high k dielectric material and metal, respectively, after formation of the source and drain. The gate stack 114 may have a different structure due to the gate material and formation. One exemplary gate stack 114 is shown in cross section in FIG. 1D. How to make this is further described according to some embodiments. In this embodiment, the gate stack 114 is formed with a dummy gate stack on the fins; Source and drain are formed; ILD is deposited on the source and drain, the dummy gate stack is removed to obtain a gate trench; A metal gate material is deposited in the gate trench; It is a metal gate formed by a procedure where a CMP process is applied to remove excess gate material. In this embodiment shown in FIG. 1D, the gate stack 114 includes a gate dielectric layer 116 that is U-shaped with a high k dielectric material. The gate electrode 120 includes multiple layers, such as 120A, 120B, and 120C. In the implementation of the embodiment, the gate electrode layer 120A is a capping layer to prevent internal diffusion and other integration considerations; The gate electrode layer 120B is a metal layer for tuning the work function (also referred to as a puncture function metal layer); The gate electrode layer 120C is a filling metal such as tungsten, copper, aluminum, copper aluminum alloy or other low resistance metal.

The semiconductor structure 100 includes a channel region 124 defined on the fin 106 and lying under the gate stack 114. Channel 124 provides a current path between the source and drain. Channel 124 has the same type of dopant as doping well 110 (p well in this embodiment), but has a higher doping concentration depending on the application and device specifications. Channel 124 can be adjusted by ion implantation with a suitable threshold voltage and dopant concentration suitable for other parameters.

The semiconductor structure 100 includes source / drain (S / D) features (or simply referred to as source and drain) formed on fins 106 on either side of the channel 124. The S / D feature is doped with a second type dopant opposite to the first type dopant. In this case, the S / D feature is doped with an n-type dopant (such as phosphorus). S / D features can be formed by ion implantation and / or diffusion. Other processing steps may be further included to form S / D features. For example, a rapid thermal annealing (RTA) process can be used to activate the injected dopant. The S / D features can have different doping profiles formed by multi-step implantation. For example, additional doping features such as light doped drain (LDD) or double diffused drain (DDD) may be included. In addition, the S / D features can have different structures, such as raised, recessed, or strained. For example, formation of S / D features may include etching to recess source and drain regions; Selective epitaxial growth to form epitaxial S / D features with in-situ doping; And annealing for activation. Thus, the formed S / D features are epitaxial S / D features with improved carrier mobility and straining effect for device performance. The S / D feature is one or more selective epitaxial growths in which silicon (Si) features, silicon germanium (SiGe) features, silicon carbide (SiC) features, and / or other suitable semiconductor features are grown in a crystalline state on fins in the source and drain regions. It can be formed by. For convenience of the following description, S / D features are referred to as drain 126 and source 128, respectively.

Source 128, drain 126, channel 124, and gate stack 114 are configured to form a FET. In this embodiment, the FET is an nFET, which is for illustrative purposes only, not limitation. In an alternative embodiment, the FET is a pFET.

The semiconductor structure 100 further includes an interlayer dielectric (ILD) layer 130 disposed on the substrate 102. ILD layer 130 includes one or more dielectric materials to provide isolation for multiple device components. ILD layer 130 includes a dielectric material, such as silicon oxide, low k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the low k dielectric material is fluorinated silica glass (FSG), carbon doped silicon oxide, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, Bis-benzocyclobutenes (BCB), polyimide, and / or other suitable dielectric material having a dielectric constant substantially lower than thermal silicon oxide. The formation of the ILD layer 130 includes, for example, film formation and CMP. The deposition can include spin-on coating, CVD, other suitable deposition techniques, or combinations thereof.

The semiconductor structure 100 also includes a gate stack 114 and a capping layer 132 deposited on the ILD layer 130. The capping layer 132 covers the gate stack 114 and provides protection to the gate stack 114 such as preventing oxidation or etch damage during subsequent processes. The capping layer 132 may perform other functions, such as etch-stop. The capping layer 132 provides several advantages over conventional methods such as film formation without etching to eliminate corresponding etch damage. The capping layer 132 includes dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, other suitable dielectric materials, or combinations thereof. The capping layer 132 can be formed by any suitable deposition technique, such as CVD or atomic layer deposition (ALD). In this embodiment, the capping layer 132 is a flat layer having a bottom surface that is coplanar with the top surface of the gate stack 114 and the ILD layer 130. In some embodiments, the capping layer 132 has a thickness in the range of 0.5 nm to 5 nm. In other embodiments, the capping layer 132 has a thickness in the range of 2 nm to 4 nm.

The semiconductor structure 100 further includes a second ILD layer 134 disposed on the capping layer 132. The second ILD layer 134 is similar to the ILD layer 130 in terms of composition and formation. For example, the second IlD layer 134 may include a low-k dielectric material, and may be formed by deposition and CMP.

The semiconductor structure 100 further includes contact features such as a first contact feature 136 and a second contact feature 138 to provide electrical connection. The first contact feature 136 and the second contact feature 138 include conductive material (s), such as metal or metal alloy, and are formed in the ILD layers 130 and 134. The first contact feature 136 is aligned with the drain 126 and lands directly on the drain 126. The second contact feature 138 is aligned with the source 128 without direct contact with the source. Each of the first contact feature and the second contact feature includes an adhesive layer 140 and a filling metal 142. The adhesive layer 140 provides various functions such as adhesion and prevention of inter-diffusion. In this embodiment, the adhesive layer 140 includes titanium and titanium nitride. The adhesive layer 140 may be deposited by physical vapor deposition (PVD), ALD, other suitable deposition, or a combination thereof. Fill metal 142 includes tungsten, copper, aluminum, copper aluminum alloys, other suitable conductive materials, or combinations thereof. Fill metal 142 is deposited by any suitable technique, such as CVD, PVD, plating, or a combination thereof.

The semiconductor structure 100 further includes another layer of dielectric material 146 surrounding the first contact feature and the second contact feature. Dielectric material layer 146 includes a suitable dielectric material that is the same or different than capping layer 132. In some embodiments, dielectric material layer 146 includes oxide, nitride, or carbide, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, other suitable dielectric materials, or combinations thereof. The dielectric material layer 146 can be deposited by CVD, ALD, or other suitable technique. In some embodiments, dielectric material layer 146 has a thickness in the range of 0.5 nm to 5 nm. In some embodiments, dielectric material layer 146 has a thickness ranging from 1 nm to 2 nm. In particular, the thickness T of the dielectric material layer 146 and the height H of the gate stack 114 have a ratio (T / H) in the range of 1/20 to 1/2 according to some embodiments.

In particular, a layer of dielectric material 146 extends between the source 128 and the second contact feature 138 and isolates the source 128 from the second contact feature 138. The extended portion of dielectric material layer 146 interposed between source 128 and second contact feature 138 functions as a sandwiched capacitor between source 128 and second contact feature 138. In some embodiments, the source 128, the second contact feature 138, and the extended portion of the dielectric material layer 146 function as a capacitor, and the second contact feature 138 and the source 128 are two capacitors. It functions as an electrode. FETs and capacitors form memory devices such as RRAM or DRAM or eOTP.

Formation of the contact feature comprises patterning the ILD layer to form a contact hole; Depositing a layer of dielectric material 146 in the contact hole; Selectively removing a portion of the dielectric material layer 146 from the bottom surface of the contact hole aligned with the drain; Depositing the adhesive layer 140; Depositing a filling metal 142 on the adhesive layer in the contact hole; And performing a CMP process to remove the adhesive layer 140 and excess fill metal 142 on the ILD layer. Selective removal of a portion of the dielectric material layer 146 on the bottom surface of the contact hole corresponding to the drain 126 covers the contact hole for the source 128 and uncovers the contact hole for the drain 126. Forming a patterned mask to do so; Performing an anisotropic etching process (such as a dry etching process) to selectively remove a lower portion in the contact hole aligned with the drain; And removing the patterned mask layer. In one embodiment, dielectric material layer 146 is deposited by ALD with precise control to a corresponding thickness.

1A and 1C, the semiconductor structure 100 is aligned with the gate stack 114 and placed on the isolation portion 104 on the extended portion of the gate stack 114, as shown in FIGS. 1A and 1C. 114) further comprising a third contact feature 148 lying directly on. The third contact feature 148 is similar to the procedure for forming the first contact feature and the second contact feature, but can be formed by an independent procedure.

The semiconductor structure 100 includes metal lines from multiple metal layers to provide horizontal electrical connections; And via features for further providing vias for providing vertical connections between metal lines in adjacent metal layers.

By implementing the disclosed method and structure, a resistor (or capacitor) is formed by deposition, and the resistance (or capacitance) is determined by the thickness of the dielectric material layer 146. Since the thickness can be precisely controlled by the film formation, the resistance can be more precisely controlled. In addition, the process is easy to implement and is more compatible with advanced technology nodes such as 7 nm technology nodes.

2A is a flowchart of a method 200 for manufacturing a semiconductor structure, such as semiconductor structure 100. The method 200 and the semiconductor wafer 80 will be described in general with reference to FIG. 2 and other drawings. However, the semiconductor structure 100 is one structure manufactured only by the method 200 according to some embodiments, and this is not limiting. Other semiconductor structures can also be fabricated by method 200, as identified in the description below. Since some descriptions are provided in FIGS. 1A-1D, these descriptions will not be repeated below.

Referring to block 202 of FIGS. 2A and 3A, method 200 includes an operation to form an isolation feature 104 within semiconductor substrate 102 defining one or more active regions 106. The formation of the isolation features includes forming a mask patterned by lithography; Etching the substrate 102 through the opening of the patterned mask to form a trench; Filling the trench with one or more dielectric physics; And performing a CMP process. The patterned mask includes an opening for defining an area of the isolation feature 104. The patterned mask can be a soft mask (such as a photoresist layer) or a hard mask (silicon oxide, silicon nitride, or combinations thereof). The patterned photoresist layer is formed by a lithographic process further comprising spin-on coating, exposure, development, and one or more baking steps. The formation of the patterned hard mask comprises depositing a hard mask layer; Forming a patterned resist layer by a lithography process; Etching the hard mask through the opening of the patterned resist layer; And removing the patterned resist layer by wet stripping or plasma ashing.

In an alternative embodiment, the active region 106 is a fin active region with a three-dimensional profile. In this case, operation 202 further includes forming a fin active region 106 protruding onto the isolation feature 104, as shown in FIG. 3B. The semiconductor structure 100 may include a plurality of fin active regions collectively referred to as fin structures. In some embodiments, the fin structure can be formed by selective etching to recess the isolation feature 104. In some embodiments, the fin structure can be formed by selective epitaxial growth into an active region having one or more semiconductor materials. In some embodiments, the fin structure can also be formed by a hybrid procedure with both selective etching and selective epitaxial growth for recipeing. The fin structure may have a rectangular shape oriented along the X direction. The epitaxially grown semiconductor material can include silicon, germanium, silicon germanium, silicon carbide, or other suitable semiconductor material. The selective etching process may include wet etching, dry etching, other suitable etching, or combinations thereof. In the following figures, the semiconductor structure 100 represents a flat active region 106, but it is understood that the active region 106 can be a fin active region.

Method 200 may include an operation for forming a doped well, such as doped well 110 on pin 106, as shown in FIGS. 3A (and 3B). In this embodiment, the doping well 110 is a p-type doping well (p-well), and the p-type dopant (boron, etc.) is introduced into the pin 106 by a suitable technique such as ion implantation.

Referring to block 204 of FIGS. 2A and 3A, method 200 proceeds with an operation to form gate stack 114 on fin 106. The formation of the gate stack 114 includes deposition and patterning steps, such as depositing a gate dielectric layer, depositing gate electrode material (s), and patterning the deposited gate material to form a gate stack. Includes. In some embodiments, operation 204 forms a dummy gate stack comprising polysilicon, and the dummy gate stack is replaced with a metal gate stack after formation of the source and drain. For example, the dummy gate stack is formed by a film forming and patterning process, and the patterning process further includes a lithography process and etching. In one embodiment, the procedure for forming the dummy gate stack comprises forming a thermal oxidation layer on the fin by thermal oxidation; Depositing a poly-silicon layer by CVD; Forming a mask layer patterned by a photolithography process; And performing an etching process on the deposited dummy gate material. The patterned mask layer includes openings to define areas of the dummy gate stack. The patterned mask layer is a soft mask (such as a photoresist layer) or a hard mask (silicon oxide, silicon nitride, or a combination thereof) formed by a similar process to form a hard mask for isolation features 104 during operation 202. Combination, etc.). Operation 204 also includes forming a gate spacer 122 on the sidewall of the gate stack. The gate spacer 122 includes one or more dielectric materials, such as silicon oxide, silicon nitride, or combinations thereof. The formation of the gate spacer 122 includes depositing one or more layers of dielectric material on the dummy gate stack; And performing an anisotropic etching process on the dielectric material layer. In some embodiments, the anisotropic etching process includes dry etching using a suitable etchant such as fluorine-containing gas or chlorine-containing gas.

Referring to block 206 of FIGS. 2A and 3A, method 200 includes an operation for forming source 128 and drain 126 on fin 106. The source and drain are inserted by a channel 124 lying beneath the gate stack. In this embodiment, the source and drain are doped with an n-type dopant such as phosphorus. Channel 124 is doped with a p-type dopant such as boron. The source and drain can be formed by a number of steps.

In some embodiments, the source and drain are epitaxial source and drain. The epitaxial source and drain can be formed by selective epitaxial growth for a deformation effect with improved carrier mobility and device performance. The source and drain are formed by one or more epitaxial growth steps, and the silicon (Si) feature, silicon germanium (SiGe) feature, silicon carbide (SiC) feature, and / or other suitable semiconductor features may include source and drain regions (patterned Grown in a crystalline state on the pins within the defined hard mask). In an alternative embodiment, an etching process is applied to recess portions of the active regions 106 in the source and drain regions prior to epitaxy growth. The etching process can also remove any dielectric material disposed on the source / drain regions, such as during the formation of gate sidewall features. Suitable epitaxial growth processes include chemical vapor deposition (CVD) deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and And / or other suitable processes. Sources and drains are formed during the epitaxy process by incorporating a dopant-containing gas into an epitaxial precursor, such as a phosphorus or arsenic-containing gas (or alternatively a p-type dopant-containing gas (e.g., boron or BF2 containing gas) if the FET is a pFET) Can be in-situ doped If the source and drain are not in-situ doped, an implantation process can be performed to introduce a dopant corresponding to the source and drain. Elevated source and drain are formed by epitaxial growth with a layer of semiconductor material, in some embodiments, a silicon layer or silicon carbide is epitaxially grown on fin 106 to form the source and drain of the nFET, or Alternatively, a layer of silicon germanium is deposited on fin 106 to form a source and drain for the pFET. It is grown physically.

Referring to block 208 of FIGS. 2A and 3A, method 200 includes an operation for forming source 128 and drain 130 on fin 100. ILD layer 130 includes one or more dielectric materials to provide isolation for multiple device components. ILD layer 130 includes a dielectric material, such as silicon oxide, low k dielectric material, other suitable dielectric materials, or combinations thereof. In some embodiments, the low k dielectric material is fluorinated silica glass (FSG), carbon doped silicon oxide, Xerogel, Aerogel, amorphous fluorinated carbon, Parylene, Bis-benzocyclobutenes (BCB), polyimide and / or other suitable dielectric material having a lower dielectric constant than thermal silicon oxide. The formation of the ILD layer 130 includes, for example, film formation and CMP. The deposition can include spin-on coating, CVD, other suitable deposition techniques, or combinations thereof.

In this embodiment, operation 204 forms a dummy gate stack and is replaced by a metal gate stack after operation 208. Referring to block 210 of FIGS. 2A and 3A, method 200 includes forming a metal gate stack 114 to replace a dummy gate stack. The formation of the metal gate stack includes etching, film formation, and CMP. The metal gate stack 114 includes a gate electrode 120 and a gate dielectric layer 116 having the structure shown in FIG. 1D in accordance with some embodiments.

Referring to block 211 of FIGS. 2A and 4, method 200 may include forming capping layer 132 on gate stack 114 and ILD layer 130. The capping layer 132 includes a suitable dielectric material, such as silicon oxide, silicon nitride, or silicon oxynitride. The capping layer 132 may be formed by a suitable film deposition technique such as CVD or atomic layer deposition (ALD). In this embodiment, the capping layer 132 is a flat layer having a bottom surface that is coplanar with the top surface of the gate stack 114 and the ILD layer 130. In some embodiments, the capping layer 132 has a thickness in the range of 0.5 nm to 5 nm. In other embodiments, the capping layer 132 has a thickness in the range of 2 nm to 4 nm.

Referring to FIG. 4, the method 200 may include forming another ILD layer 134 on the capping layer 132. ILD layer 134 is similar to ILD layer 130 in terms of composition and formation.

Referring to block 212 of FIGS. 2A and 5, the method 200 forms contact holes 150 and 152 in the ILD layer, particularly the ILD layer 130, the capping layer 132, and the ILD layer 134. It includes the action to do. Contact holes 150 and 152 are aligned with drain 126 and source 128, respectively, and expose drain 126 and source 128. Formation of the contact hole may include forming a patterned mask using a lithography process; And etching through the opening of the patterned mask. The etching step can include one or more etching steps with a suitable etchant for etching each layer of material. In this embodiment, the etching process may include dry etching, wet etching, or a combination thereof. The patterned mask can be a soft mask (such as photoresist) or a hard mask (such as a layer of dielectric material having sufficient etch selectivity).

Method 200 proceeds to operation 214 of forming a dielectric material layer 146 in the contact hole. In this embodiment, the dielectric material layer 146 is formed on the sidewall and bottom surface of the contact hole 152 for the source 128, but only on the sidewall in the contact hole 150 of the drain 126, There is no dielectric material layer 146 on the bottom surface of the contact hole 150. Operation 214 is further described with reference to FIG. 2B as a flowchart of operation 214 that includes multiple sub-operations.

Referring to block 218 of FIGS. 2B and 6, the method 214 is an operation of depositing a dielectric material layer 146 in the contact hole and on the ILD layer 134 by a suitable deposition technique such as ALD or CVD. It includes. Dielectric material layer 146 includes a suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or combinations thereof. The film formation is controlled to have an appropriate thickness. Dielectric material layer 146 is formed on the sidewalls and bottom surfaces of contact holes 150 and 152. In some embodiments, dielectric material layer 146 has a thickness in the range of 0.5 nm to 5 nm. In some embodiments, dielectric material layer 146 has a thickness ranging from 1 nm to 2 nm.

Referring to block 220 of FIGS. 2B and 6, the method 214 covers a second contact hole 152 and a patterned mask (soft mask or hard mask) to uncover the first contact hole 150 ) 162.

Referring to block 222 of FIGS. 2B and 7, the method 214 uses the patterned mask 162 as an etch mask to fill the lower portion of the dielectric material layer 146 in the first contact hole 150. And performing an anisotropic etching process, such as dry etching, to remove. The etching process may remove a portion of the dielectric material layer 146 on the ILD layer 134. The patterned mask 162 can be removed after the anisotropic etching process.

Referring to block 216 of FIGS. 2A and 8, the method 200 includes forming contact features 136 and 138 within contact holes 150 and 152, respectively. Formation of the contact feature comprises depositing an adhesive layer 140 in the contact hole by ALD, PVD, or a combination thereof; Depositing a conductive material 142 to fill the contact holes by PVD, plating, ALD, or a combination thereof; And performing a CMP process to remove conductive material on the ILD layer 134. The adhesive layer 140 includes a titanium film and titanium nitride in this embodiment. The conductive material 142 includes tungsten, copper, aluminum, aluminum copper alloy, or combinations thereof, in accordance with some implementations.

Contact features 148 to gate stack 114 are also formed in a separate process. Formation of the contact feature 148 includes forming a patterned mask with an opening for the gate stack 114; Etching the ILD to form contact holes aligned with the gate stack; Depositing an adhesive layer; Depositing a conductive material to fill the contact hole; And performing a CMP process.

9A-9C provide a semiconductor structure 900 formed by a method 200 in accordance with some other embodiments. 9A is a top view of a semiconductor structure 900 constructed in accordance with various aspects of the present disclosure in one embodiment. 9B is a cross-sectional view along the dotted line AA 'of the semiconductor structure 900, in accordance with some embodiments. 9C is a cross-sectional view along the dotted line BB 'of the semiconductor structure 900, in accordance with some embodiments. The semiconductor structure 900 is similar to the semiconductor structure 100. Descriptions of similar features are not repeated. Also, the second contact feature 902 in the semiconductor structure 900 is aligned with the source 128 and overlaid the portion 130A of the ILD layer 130, as shown in FIG. 9B. Source 128 is isolated and isolated from contact feature 902 by portion 130A of ILD layer 130. The portion 130A of the ILD layer 130 underlying the second contact feature 902 functions as a capacitor (collectively with the second contact feature 902 and the source 128). The FETs and capacitors are connected together to form a memory device such as RRAM, DRAM or eOPT. A number of features are formed by the method 200 of FIG. 2 as shown in FIGS. 11-14 at different manufacturing stages. For example, the method 200 includes act 202 of forming an isolation feature 104; Forming a source and a drain (206); Forming a metal gate stack (210); Forming a contact hole (212); Operation 214 of forming a dielectric material layer 146, and the like. Similar explanations are not repeated. In particular, the operation 212 of forming the contact hole and the operation 214 of forming the dielectric material layer 146 are described in detail with reference to FIGS. 10A and 10B.

In this embodiment, the first contact features 136 and the second contact holes 902 of the semiconductor structure 900 are formed in separate procedures. In the implementation of the embodiment, the second contact feature 902 is formed with the same procedure for forming the gate contact feature 148.

Referring to FIGS. 10A and 13, the method 212 includes forming the first contact hole 150 by a similar procedure to form the contact hole 150 of FIG. 5. For example, operation 1002 includes forming a patterned mask and etching with a patterned mask as an etch mask. In particular, the etching process is controlled to be etched through the first ILD layer 130, so that the drain 126 is exposed in the first contact hole 150.

The method 212 also includes an operation 1004 of forming the second contact hole 1302 by another procedure that collectively forms the contact hole 148 of the gate stack 114. The gate contact feature 148 and the contact feature 902 are collectively formed by the same operation 1004, and the contact feature 136 is formed by another operation 1002.

Operation 1004 also includes forming a patterned mask with an opening defining an area of the contact hole; And performing an etching process on the ILD layer to form corresponding contact holes aligned with the source 128 and gate stack 114. The etching process is controlled to etch through the second ILD layer 134 and the capping layer 132 to expose the gate stack 114 in the corresponding contact hole (not shown here). In addition, the etching process is controlled to etch through the first ILD layer 130 so that a portion of the ILD layer 130 remains at a desired thickness in the second contact hole 1302. In some embodiments, the etching process includes multiple etching steps with each etchant. For example, the first etch step is applied to the second ILD layer 134 and stopped at the capping layer 132; A second etch step is applied to etch the capping layer 132 and is stopped at the gate stack 114; The third etch step is applied to selectively etch the first ILD layer 130. In the advanced technology node, due to the height difference between the gate stack and the S / D feature, the gate contact is formed separately from the formation of the S / D feature. In method 212, the second contact feature 902 for source 128 is grouped with the gate contact without using additional photomask and lithography processes to reduce manufacturing costs.

10B and 13, operation 214 of method 200 of forming dielectric material layer 146 is a first procedure as a procedure for forming first contact feature 136 aligned with drain 126. It is applied only to the contact hole 150. As described above, the first contact hole 150 is formed by an operation 1002 further comprising forming a patterned mask and etching. After operation 1002, operation 214 continues using the same patterned mask to form dielectric material layer 146 in first contact hole 150. In particular, as shown in FIG. 13, operation 214 includes: a lower operation 1006 of depositing a dielectric material layer 146 in the first contact hole 150; And a bottom operation 1008 of performing an anisotropic etching process to remove the dielectric material layer 146 from the bottom surface of the first contact hole 150 to expose the drain 126 within the contact hole 150. Includes. Thereafter, as shown in FIG. 14, contact features 136, 902, and 148 are formed by operation 216.

15A-15C provide a semiconductor structure 1500 formed by a method 200 in accordance with some other embodiments. 15A is a top view of a semiconductor structure 1500 constructed in accordance with various aspects of the present disclosure in one embodiment. 15B is a cross-sectional view along the dotted line AA 'of the semiconductor structure 1500, in accordance with some embodiments. 15C is a cross-sectional view along the dotted line BB 'of the semiconductor structure 1500, in accordance with some embodiments. The semiconductor structure 1500 is similar to the semiconductor structure 100. Descriptions of similar features are not repeated. Also, the second contact feature 1502 in the semiconductor structure 1500 is aligned with the source 128 and overlies the resistive feature (or dielectric feature) 1504. Source 128 is isolated and isolated from contact feature 1502 by resistive feature 1504. The FET and resistive feature 1504 form a memory device such as eOPT (or alternatively RRAM). In some embodiments, resistive feature 1504 differs from dielectric material layer 146 in composition. 17-21, a number of features are formed by method 200. For example, the method 200 includes act 202 of forming an isolation feature 104; Forming a source and a drain (206); Forming a metal gate stack 114 (210); Forming a contact hole (212); Operation 214 of forming a dielectric material layer 146, and the like. Similar explanations are not repeated. In particular, the operation (or method) 214 of forming the dielectric material layer 146 includes forming the resistive feature 1504 and is described in detail with reference to FIG. 16A.

Referring to block 1602 of FIGS. 16A and 20, the method 214 includes depositing a dielectric material layer 146 in the first contact hole 150 and the second contact hole 152.

Referring to block 1604 of FIGS. 16A and 20, the method 214 includes performing an anisotropic etching process to remove the lower portion of the dielectric material layer 146 in the contact hole.

Referring to block 1606 of FIGS. 16A and 20, the method 214 performs an operation of uncovering the second contact hole 152 and forming a patterned mask to cover the first contact hole 150. Includes.

Referring to block 1608 of FIGS. 16A and 20, the method 214 includes depositing a second layer of dielectric material (or layer of resistive material) 1504 in the second contact hole 152. The second dielectric material layer 1504 includes any dielectric material different from the first dielectric material layer 146, and is a silicon oxide, silicon nitride, silicon oxynitride, high k dielectric material (metal oxide, metal nitride, or metal) Oxynitride, etc.), or a combination thereof. The deposition process can include CVD, ALD, or other suitable deposition techniques. The deposition process is controlled to deposit a second dielectric material layer 1504 to a desired thickness.

Referring to block 1610 of FIGS. 16A and 20, the method 214 performs an anisotropic etching process to remove the second dielectric material layer 1504 from the sidewall of the second contact hole 152 to perform the second contact And obtaining a dielectric feature in the hole 152 (continued labeled 1504). Thereafter, by operation 216, contact features including 136, 1502, and 148 are formed in each contact hole.

In an alternative embodiment, a method 214 of forming the same structure is provided in FIG. 16B and described in detail.

16B and 20, the method 214 includes an operation 1602 of depositing a second layer of dielectric material 146 in the first contact hole 150 and the second contact hole 152; Performing an anisotropic etch process (1604) to remove the lower portion of the dielectric material layer 146 in the contact hole; And an operation 1606 of uncovering the second contact hole 152 and forming a patterned mask to cover the first contact hole 150, similarly to the corresponding operation in FIG. 16A.

Referring to block 1612 of FIGS. 16B and 20, the method 214 includes depositing a second layer of dielectric material 1504 to fill the second contact hole 152. The second dielectric material layer 1504 includes any dielectric material different from the first dielectric material layer 146, and is a silicon oxide, silicon nitride, silicon oxynitride, high k dielectric material (metal oxide, metal nitride, or metal) Oxynitride, etc.), or a combination thereof. The deposition process can include CVD, ALD, spin-on coating, or other suitable deposition techniques. The deposition process fills the second contact hole 152.

Referring to block 1614 of FIGS. 16B and 20, method 214 includes performing a CMP process to planarize the top surface by removing second dielectric material layer 1504 from ILD layer 134. do.

Referring to block 1616 of FIGS. 16B and 20, the method 214 performs an etching process to recess the second dielectric material layer 1504 in the second contact hole 152 to a desired thickness to perform a second And obtaining dielectric feature 1504 in contact hole 152.

In another alternative embodiment, a method 214 of forming the same structure is provided in FIG. 16C and described in detail below.

16C and 20, the method 214 includes an operation 1602 of depositing a dielectric material layer 146 in the first contact hole 150 and the second contact hole 152; Performing an anisotropic etch process (1604) to remove the lower portion of the dielectric material layer 146 in the contact hole; And an operation 1606 of uncovering the second contact hole 152 and forming a patterned mask to cover the first contact hole 150, similarly to the corresponding operation in FIG. 16A.

Referring to block 1622 of FIGS. 16C and 20, the method 214 is a bottom-up deposition process (bottom-up) of depositing a second layer of dielectric material 1504 on the bottom surface of the second contact hole 152. deposition process) to obtain a resistor 1504 in the second contact hole 152. The bottom-up metal deposition process fills the openings from the bottom-up and does not have a step coverage issue. Bottom-up deposition may include glass-cluster ion beam (GCIB), initiated CVD (iCVD), cyclic-deposition-etch (CDE), or other suitable deposition technique. In some embodiments, since the bottom-up deposition process is a cyclic deposition etching process, and deposition and etching are simultaneously implemented, and the deposition on the sidewalls of the second contact hole 152 is removed by etching, the second dielectric material is It is deposited only on the lower surface.

22A-22C provide a semiconductor structure 2200 formed by a method 200 in accordance with some other embodiments. 22A is a top view of a semiconductor structure 2200 constructed in accordance with various aspects of the present disclosure in one embodiment. 22B is a cross-sectional view along the dotted line AA 'of the semiconductor structure 2200, in accordance with some embodiments. 22C is a cross-sectional view along the dotted line BB 'of the semiconductor structure 2200, in accordance with some embodiments. The semiconductor structure 2200 is similar to the semiconductor structure 100. Descriptions of similar features are not repeated. Also, the second contact feature 2202 in the semiconductor structure 2200 is aligned with the source 128 and lies directly on the source 128. The second contact feature 2202 is substantially similar to the first contact feature 136 in terms of formation and structure. As shown in FIGS. 24-29, multiple features are formed by method 200. For example, the method 200 includes act 202 of forming an isolation feature 104; Forming a source and a drain (206); Forming a metal gate stack 114 (210); Forming a contact hole (212); Operation 214 of forming a dielectric material layer 146, and the like. Similar explanations are not repeated. In particular, the operation (or method) 214 of forming the dielectric material layer 146 is described in detail with reference to FIG. 23.

Referring to block 218 of FIGS. 23 and 27, the method 214 includes depositing a dielectric material layer 146 in the first contact hole 150 and the second contact hole 152.

Referring to block 2302 of FIGS. 23 and 28, method 214 includes performing an anisotropic etching process to remove the lower portion of dielectric material layer 146 from the first and second contact holes. . The anisotropic etching process also removes the dielectric material layer 146 on the ILD layer 134.

30A-30C provide a semiconductor structure 3000 formed by a method 200 in accordance with some other embodiments. 30A is a top view of a semiconductor structure 3000 constructed in accordance with various aspects of the present disclosure in one embodiment. 30B is a cross-sectional view along the dotted line AA 'of the semiconductor structure 3000, in accordance with some embodiments. 30C is a cross-sectional view along the dotted line BB 'of the semiconductor structure 3000, in accordance with some embodiments. The semiconductor structure 3000 is similar to the semiconductor structure 2200. Descriptions of similar features are not repeated. However, the semiconductor structure 3000 includes a silicide feature 3002 that is self-aligned to the gate stack 114. The silicide feature 3002 protects the gate stack 114 from oxidation or etch damage during subsequent processes, and because the gate electrode 120 includes some conductive materials with high resistance (as shown in FIG. 1D). , Reduces contact resistance. 32-38, multiple features are formed by method 200. For example, the method 200 includes act 202 of forming an isolation feature 104; Forming a source and a drain (206); Forming a metal gate stack 114 (210); Forming a contact hole (212); Forming a dielectric material layer 146 (214); And forming a contact feature (216). Similar explanations are not repeated. In particular, the operation (or method) 210 of forming the gate stack 114 is also described in detail with reference to FIG. 31.

Referring to block 3102 of FIGS. 31 and 32, method 210 includes an operation of removing a dummy gate stack by an etching process to obtain a gate trench.

Referring to block 3104 of FIGS. 31 and 32, the method 210 deposits a number of gate materials (high k dielectric material, work function metal and filled metal, etc.) into the gate trench, as described in FIG. 1D. And forming the metal gate stack 114 by a procedure further comprising a step.

Referring to block 3106 of FIGS. 31 and 32, method 210 includes depositing a silicon layer on a metal gate stack by a suitable method such as CVD.

Referring to block 3108 of FIGS. 31 and 32, the method 210 is a temperature suitable for reacting the metal layer 120 with the silicon layer to form the silicide feature 3002 directly on the gate electrode 120. And performing the thermal annealing process. In some embodiments, because the gate electrode 120 can include multiple metals or metal alloys, the silicide feature 3002 can include multiple portions of different compositions.

Referring to block 3110 of FIGS. 31 and 32, method 210 may include performing an etching process to selectively remove unreacted silicon from gate stack 114 and ILD layer 134. have. The etching process may include wet etching, dry etching, or a combination thereof. In some embodiments, the etching process can use an etching solution with HNO ₃ , H ₂ O, and HF to selectively remove silicon.

Method 200 and semiconductor structures fabricated by method 200 are provided in a number of embodiments. Method 200 may additionally include other actions before, during, and after the above-described actions. For example, method 200 may further include forming an interconnect structure that electrically connects multiple features, such as a source, drain, gate stack, capacitor, resistor, or combination thereof, to form an integrated circuit. have. In some embodiments, integrated circuits include memory devices such as eOTPs, RRAMs, DRAMs, or combinations thereof. In the above description of some embodiments, to better understand the structure of the FET, source 128 and drain 126 have been described characteristically and distinctly, or the memory device with one of the S / D features is aligned. Connected to the contact feature, the other of the S / D features is separated from the aligned contact feature. However, the source and drain can be swapped according to other embodiments. In another embodiment, the silicide feature 3002 self-aligned to the metal gate stack 114 in the semiconductor structure 300 includes a semiconductor structure 100, a semiconductor structure 900, a semiconductor structure 1500, and a semiconductor structure 2200. ).

The present disclosure provides a semiconductor structure and a method of manufacturing the semiconductor structure in a number of embodiments. The semiconductor structure includes a FET in which a dielectric material is deposited in a contact hole before contact features are formed therein. In some embodiments, the layer of dielectric material extends between the contact feature and the underlying source (or alternatively drain) and functions as a capacitor (or resistor). In some embodiments, FETs and capacitors form memory devices such as RRAM or DRAM or eOTP. In addition, a layer of dielectric material in the contact hole provides isolation between the gate and source / drain features with reduced leakage. In some embodiments, a semiconductor structure includes a method of forming a silicide feature that is on a metal gate stack and is aligned with a gate electrode. By implementing the methods disclosed in various embodiments, some of the advantages described below may appear. However, it is understood that the different embodiments disclosed herein provide different advantages and that particular advantages are not necessarily required in all embodiments. In one embodiment, a layer of dielectric material 146 is formed in the contact hole by deposition, and the thickness of the dielectric material layer 146 is controlled by the deposition process. Thus, since the thickness can be more precisely controlled by film formation than etching, the electrical parameters (such as capacitance or resistance) of the dielectric material layer can be more precisely controlled. In another embodiment, a layer of dielectric material 146 is disposed on the sidewall of the contact hole (s) and provides isolation between the source / drain feature (s) and the gate stack to prevent leakage. In addition, the process is easy to implement and is more compatible with advanced technology nodes such as 7 nm technology nodes.

Accordingly, the present disclosure provides a method of manufacturing an integrated circuit in accordance with some embodiments. The method includes forming a source and a drain on a fin active region of a semiconductor substrate; Depositing an interlayer dielectric (ILD) layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

The present disclosure provides a method of manufacturing an integrated circuit according to another embodiment. The method includes forming a metal gate stack on a fin active region of a semiconductor substrate; Forming a source and a drain on the fin active region; Forming a self-aligned silicide layer on the metal gate stack; Forming an interlayer dielectric (ILD) layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

The present disclosure provides an integrated circuit in accordance with some embodiments. The IC structure includes a fin active region on a substrate; A metal gate stack on the fin active region; Source and drain on the fin active region (a metal gate stack is interposed between the source and drain); An interlayer dielectric (ILD) layer disposed on the source and drain; First conductive features and second conductive features formed in the ILD layer and aligned on the source and drain, respectively; And a layer of dielectric material surrounding the first conductive feature and the second conductive feature. The dielectric material layer includes a portion that extends continuously to the lower surface of the first conductive feature and is interposed between the first conductive feature and the source. The second conductive feature is in direct contact with the drain.

1) A method of manufacturing an integrated circuit according to an embodiment of the present invention includes forming a source and a drain on a fin active region of a semiconductor substrate; Depositing an interlayer dielectric (ILD) layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

2) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, the first conductive feature is separated from the source by the layer of dielectric material.

3) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, the step of forming the dielectric material layer includes depositing the dielectric material layer directly above the source in the first contact hole. The step of forming the first conductive feature and the second conductive feature includes forming the first conductive feature directly above the layer of dielectric material in the first contact hole.

4) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, the step of forming the first conductive feature and the second conductive feature comprises depositing an adhesive layer in the first contact hole and the second contact hole. step; Filling a conductive material on the adhesive layer in the first contact hole and the second contact hole; And performing chemical mechanical polishing to remove excess portions of the conductive material on the ILD layer.

5) A method of manufacturing an integrated circuit according to an embodiment of the present invention, further comprising forming a gate stack on the fin active region and interposed between the source and the drain, wherein the gate stack, the source , And the drain constitute a field effect transistor.

6) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, the dielectric material layer includes one of silicon oxide, silicon nitride, and silicon oxynitride.

7) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, the adhesive layer includes a titanium film and a titanium nitride film, and the conductive material includes one of tungsten, copper, aluminum, and combinations thereof. .

8) A method of manufacturing an integrated circuit according to an embodiment of the present invention, further comprising forming a dielectric capping layer on the gate stack and the ILD layer prior to deposition of the ILD layer on the source and drain.

9) In a method of manufacturing an integrated circuit according to an embodiment of the present invention, forming a dielectric material layer in the first contact hole may include: depositing a dielectric material layer in the first contact hole; And removing an lower portion of the layer of dielectric material in the first contact hole to perform an anisotropic etching process to expose the source.

10) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, further comprising forming a dielectric feature in the first contact hole, the dielectric feature comprising a lower surface and the first surface in direct contact with the source. It has sidewalls in direct contact with the dielectric material layer.

11) In the method of manufacturing an integrated circuit according to an embodiment of the present invention, forming a dielectric feature in the first contact hole includes performing bottom-up deposition, and the dielectric feature Includes a dielectric material different from the dielectric material layer.

12) A method of manufacturing an integrated circuit according to an embodiment of the present invention, comprising: forming a gate stack comprising a metal electrode on the fin active region; Depositing a silicon layer on the metal electrode; Annealing to react the metal of the metal electrode with the silicon layer to form a silicide layer on the metal electrode; And etching to remove unreacted silicon.

13) A method according to another embodiment of the present invention includes forming a metal gate stack on a fin active region of a semiconductor substrate; Forming a source and a drain on the fin active region; Forming a self-aligned silicide layer on the metal gate stack; Forming an ILD layer on the source and drain; Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively; Forming a layer of dielectric material in the first contact hole; And forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.

14) In a method according to another embodiment of the present invention, forming a layer of dielectric material in the first contact hole comprises depositing the layer of dielectric material directly above the element in the first contact hole, The forming of the first conductive feature and the second conductive feature includes forming the first conductive feature on the layer of dielectric material in the first contact hole, wherein the first conductive feature is the layer of dielectric material Separated from the source.

15) In a method according to another embodiment of the present invention, forming a dielectric material layer in the first contact hole may include depositing the dielectric material layer in the first contact hole and the second contact hole; And removing a portion of the layer of dielectric material from the bottom surfaces of the first contact hole and the second contact hole.

16) The method according to another embodiment of the present invention further comprises forming a layer of resistive material in the first contact hole, the layer of resistive material being surrounded by the layer of dielectric material and overlying the source. , The first conductive feature lies directly above the layer of resistive material.

17) A method according to another embodiment of the present invention includes forming a patterned mask layer on the dielectric material layer to cover the first contact hole; And performing an etching process to remove the lower portion of the layer of dielectric material in the second contact hole.

18) In a method according to another embodiment of the present invention, forming the first conductive feature and the second conductive feature includes: depositing an adhesive layer in the first contact hole and the second contact hole; Filling a conductive material on the adhesive layer in the first contact hole and the second contact hole; And performing chemical mechanical polishing to remove excess portions of the conductive material on the ILD layer.

19) In a method according to another embodiment of the present invention, forming a self-aligned silicide layer on the metal gate stack comprises: depositing a silicon layer on the metal gate stack; Reacting the metal gate stack and the silicon layer to anneal to form a silicide layer on the metal gate stack; And etching to remove unreacted silicon.

20) An integrated circuit (IC) structure according to another embodiment of the present invention includes a fin active region on a substrate; A metal gate stack on the fin active region; A source and a drain on the fin active region, the source and drain being interposed between the source and the drain; An ILD layer disposed on the source and the drain; First conductive features and second conductive features formed in the ILD layer and aligned on the source and drain, respectively; And a layer of dielectric material surrounding the first conductive feature and the second conductive feature, wherein the layer of dielectric material extends continuously to a lower surface of the first conductive feature, and from the source to the first conductive feature. And the second conductive feature is in direct contact with the drain.

Overview of features of several embodiments has been described so that those skilled in the art may better understand the details. Those skilled in the art should recognize that the present invention can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or achieve the same advantages of the embodiments disclosed herein. In addition, those skilled in the art should recognize that such equivalents do not depart from the spirit and scope of the present invention and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the present invention.

Claims (10)

In the manufacturing method of the integrated circuit,
Forming a source and a drain on the fin active region of the semiconductor substrate;
Depositing an interlayer dielectric (ILD) layer on the source and drain;
Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively;
Forming a layer of dielectric material in the first contact hole;
Forming a dielectric feature in the first contact hole, the dielectric feature having a bottom surface directly contacting the source and a sidewall directly contacting the layer of dielectric material; And
Forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.
Including,
The step of forming the dielectric material layer in the first contact hole may include:
Depositing a layer of the dielectric material in the first contact hole; And
Removing the lower portion of the layer of dielectric material in the first contact hole to perform an anisotropic etching process to expose the source
A method of manufacturing an integrated circuit that includes. According to claim 1,
Wherein the first conductive feature is separated from the source by the layer of dielectric material. According to claim 2,
The step of forming the dielectric material layer includes depositing the dielectric material layer directly above the source in the first contact hole,
The forming of the first conductive feature and the second conductive feature includes forming the first conductive feature directly over the layer of dielectric material in the first contact hole. According to claim 3,
Forming the first conductive feature and the second conductive feature,
Depositing an adhesive layer in the first contact hole and the second contact hole;
Filling a conductive material on the adhesive layer in the first contact hole and the second contact hole; And
Performing chemical mechanical polishing to remove excess portions of the conductive material on the ILD layer
A method of manufacturing an integrated circuit that includes. According to claim 4,
And forming a gate stack on the fin active region and interposed between the source and the drain, wherein the gate stack, the source, and the drain constitute a field effect transistor. Manufacturing method. The method of claim 5,
And forming a dielectric capping layer on the gate stack and the ILD layer prior to deposition of the ILD layer on the source and drain. delete According to claim 1,
Forming a gate stack including a metal electrode on the fin active region;
Depositing a silicon layer on the metal electrode;
Annealing to react the metal of the metal electrode with the silicon layer to form a silicide layer on the metal electrode; And
Etching to remove unreacted silicon
The method of manufacturing an integrated circuit further comprising. In the way,
Forming a metal gate stack on the fin active region of the semiconductor substrate;
Forming a source and a drain on the fin active region;
Forming a self-aligned silicide layer on the metal gate stack;
Forming an ILD layer on the source and drain;
Patterning the ILD layer to form a first contact hole and a second contact hole aligned with the source and drain, respectively;
Forming a layer of dielectric material in the first contact hole;
Forming a dielectric feature in the first contact hole, the dielectric feature having a bottom surface directly contacting the source and a sidewall directly contacting the layer of dielectric material; And
Forming a first conductive feature and a second conductive feature in the first contact hole and the second contact hole, respectively.
Including,
The step of forming the dielectric material layer in the first contact hole may include:
Depositing a layer of the dielectric material in the first contact hole; And
Removing the lower portion of the layer of dielectric material in the first contact hole to perform an anisotropic etching process to expose the source
The method comprising the. In an integrated circuit (IC) structure,
A pin active region on the substrate;
A metal gate stack on the fin active region;
A source and a drain on the fin active region, the source and drain being interposed between the source and the drain;
An ILD layer disposed on the source and the drain;
First conductive features and second conductive features formed in the ILD layer and aligned on the source and drain, respectively; And
A layer of dielectric material surrounding the first conductive feature and the second conductive feature
Including,
The layer of dielectric material extends continuously to the bottom surface of the first conductive feature, isolates the first conductive feature from the source,
The second conductive feature is in direct contact with the drain, an integrated circuit (IC) structure.

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