KR102096457B1 - Semiconductor device structure and method for forming the same - Google Patents

Abstract

A method of forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in the first surface of the substrate. The method includes forming a first insulating layer in the first hole and the second hole. The method includes forming a conductive layer over the first insulating layer and in the first hole and the second hole. The method includes forming a second insulating layer over the conductive layer in the first recess. The second insulating layer has a second recess in the first recess. The method includes forming a conductive structure in the second recess. The method includes the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole. And partially removing it.

Description

Semiconductor device structure and a method for forming the same {SEMICONDUCTOR DEVICE STRUCTURE AND METHOD FOR FORMING THE SAME}

The semiconductor integrated circuit (IC) industry has achieved rapid growth. Technological advances in IC materials and design have made generations of ICs. Each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs.

In the course of IC evolution, the functional density (i.e., the number of interconnected devices per chip area) generally increased while the geometrical size (i.e., the smallest element (or line) that can be created using a manufacturing process) decreased. . This reduction process generally provides advantages by increasing manufacturing efficiency and lowering associated costs.

However, as feature sizes (eg, sizes of chip package structures) continue to decrease, manufacturing processes continue to become more difficult to perform. Therefore, it is a challenge to form reliable semiconductor devices with even smaller sizes.

It is best understood if aspects of the present disclosure are read in the following detailed description while referring to the accompanying drawings. Note that, according to the standard practice in this industry, various features are not drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
1A-1O are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments.
1mb is a top view of a portion of the semiconductor device structure of FIG. 1ma, in accordance with some embodiments.
1nb is a top view of an area of the semiconductor device structure of FIG. 1na, in accordance with some embodiments.
2 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
3A is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments.
3B is a bottom view of a substrate of the semiconductor device structure of FIG. 3A, in accordance with some embodiments.

The following disclosure provides many different embodiments, or examples, to implement different features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the present disclosure. These are, of course, examples only and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on the second feature can include embodiments in which the first and second features are formed by direct contact, and the first and second features are in direct contact. In order not to, additional features may also include embodiments in which it may be formed between the first feature and the second feature. Also, the present disclosure may repeat reference numbers and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself influence the relationship between the various embodiments and / or configurations discussed.

In addition, spatially related terms such as "below", "below", "bottom", "above", "top", etc. are another element (s) or feature (s) of one element or feature shown in the drawing ) Can be used here for ease of explanation. The spatially related terms are intended to include different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device can be oriented in other cases (rotated at 90 degrees or other orientations) and the spatially relevant descriptive terms used herein can likewise be interpreted accordingly. It should be understood that additional operations may be provided before, during, and after the method, and some of the described operations may be replaced or removed for other embodiments of the method.

1A-1O are cross-sectional views of various stages of a process for forming a semiconductor device structure, in accordance with some embodiments. The semiconductor device structure may be a semiconductor substrate having through semiconductor vias or a chip package structure.

1A, in accordance with some embodiments, a substrate 110 is provided. Substrate 110 has opposing surfaces 112 and 114, according to some embodiments. The substrate 110 is made of a basic semiconductor material containing silicon or germanium in a single crystal, polycrystalline, or amorphous structure.

In some other embodiments, the substrate 100 is a compound semiconductor (eg, silicon carbide, gallium arsenide, gallium phosphorus, indium phosphorus, or indium arsenide), an alloy semiconductor (eg, SiGe, or GaAsP), or It is made of a combination of these. Substrate 110 may also include multilayer semiconductors, semiconductor on insulators (such as silicon on insulators or germanium on insulators), or combinations thereof.

1B, portions of the substrate 110 are removed from the surface 112 to form first holes 116 and second holes 118 in the substrate 112, according to some embodiments. do. In some embodiments, the width W1 of each first hole 116 is greater than the width W2 of each second hole 118.

In some embodiments, width W1 is the maximum width of each first hole 116 and width W2 is the maximum width of each second hole 118. In some embodiments, the average width of each first hole 116 is greater than the average width of each second hole 118. The removal process includes an etching process, such as a dry etching process, according to some embodiments.

1B, an insulating layer 120 is formed over the substrate 110 and in the first holes 116 and the second holes 118, according to some embodiments. The insulating layer 120 may be provided with a surface 112, inner walls 116a of the first holes 116 and lower surfaces 116b, and inner walls 118a of the second holes 118, according to some embodiments. ) And the lower surfaces 118b conformally. The insulating layer 120 is also called a liner layer, according to some embodiments.

The insulating layer 120 has a thickness T1 in a range from about 0.1 μm to about 0.2 μm, according to some embodiments. The insulating layer 120 includes oxide (such as silicon oxide), according to some embodiments. The insulating layer 120 is formed using a thermal oxidation process or a chemical deposition process, according to some embodiments.

1C, the conductive layer 130 is formed over the insulating layer 120 and in the first holes 116 and the second holes 118, according to some embodiments. The conductive layer 130 conformally covers the insulating layer 120 in the first holes 116 and the insulating layer 120 over the surface 112, according to some embodiments.

Therefore, the conductive layer 130 has recesses 131 in the first holes 116, respectively, according to some embodiments. The conductive layer 130 fills the second holes 118, according to some embodiments. Therefore, the conductive layer 130 does not have recesses in the second holes 118, according to some embodiments.

The conductive layer 130 is made of a metal material or an alloy material, according to some embodiments. Metallic materials include copper, gold, aluminum, tungsten, or other suitable metallic materials. The formation of the conductive layer 130 forms a seed layer (not shown) over the insulating layer 120, in accordance with some embodiments; Plating a layer of conductive material (not shown) over the seed layer. Plating of the conductive material layer includes an electroplating plating process, according to some embodiments.

1D, the conductive layer 130 over the surface 112 is removed, in accordance with some embodiments. The conductive layer 130 remaining in each first hole 116 forms a conductive shielding structure 132, according to some embodiments. The conductive layer 130 remaining in each second hole 118 forms a conductive structure 134, according to some embodiments.

The conductive shielding structures 132 and the conductive structures 134 are electrically isolated from each other after removal of the conductive layer 130 over the surface 112, in accordance with some embodiments. The conductive shielding structures 132 and the conductive structures 134 are electrically insulated from the substrate 110 by an insulating layer 120 therebetween, according to some embodiments.

The removal process includes performing a planarization process over the conductive layer 13 until the insulating layer 120 over the surface 112 is exposed, in accordance with some embodiments. The planarization process includes a chemical mechanical polishing (CMP) process, according to some embodiments. In some embodiments, the conductive shielding structures 132, the insulating layer 120, and the top surfaces 132a, 122, and 134a of the conductive structures 134 are coplanar after the removal process.

1E, an insulating layer 140 is formed over the conductive shielding structures 132, the conductive structures 134, and the surface 112, according to some embodiments. The insulating layer 140 conformally covers the conductive shielding structures 132, the conductive structures 134, and the surface 112, according to some embodiments. Therefore, the insulating layer 140 has recesses 142 in the recesses 131, respectively, according to some embodiments.

The conductive shielding structures 132 (or conductive layer 130) have a thickness T2, according to some embodiments. The insulating layer 140 has a thickness T3, according to some embodiments. The thickness T3 is greater than the thickness T2, according to some embodiments. The thickness T2 is greater than the thickness T1 of the insulating layer 120, according to some embodiments.

In some embodiments, the average thickness of the insulating layer 140 is greater than the average thickness of the conductive shielding structures 132 (or conductive layer 130). In some embodiments, the average thickness of the conductive shielding structures 132 (or conductive layer 130) is greater than the average thickness of the insulating layer 120.

The insulating layer 140 may be hafnium oxide, zirconium oxide, aluminum oxide, hafnium dioxide-alumina alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-K materials, Or a combination of these, made from a high-k material.

The insulating layer 140 is made of an oxide material such as silicon oxide. The insulating layer 140 is made of a polymer material such as polyimide, polybenzoxazole (PBO), benzocyclobutene (BCB), and the like. The insulating layer 140 is formed using a deposition process, such as a chemical deposition process, according to some embodiments.

1F, conductive layer 150a is formed over insulating layer 140, in accordance with some embodiments. The recesses 142 are filled with a conductive layer 150a in accordance with some embodiments. The conductive layer 150a is made of copper, gold, aluminum, tungsten, or other suitable conductive material, according to some embodiments.

The formation of the conductive layer 150a forms a seed layer (not shown) over the insulating layer 140, according to some embodiments; Plating a layer of conductive material (not shown) over the seed layer. In some other embodiments, conductive layer 150a is formed using a physical deposition process.

As shown in FIG. 1G, in accordance with some embodiments, the conductive layer 150a outside the recesses 142 is removed. The conductive layer 150a remaining in each recess 142 forms a conductive structure 150, in accordance with some embodiments.

The conductive layer 150a outside the recesses 142 is removed using a planarization process, such as a chemical mechanical polishing process, according to some embodiments. Therefore, the top surfaces 152 of the conductive structures 150 and the top surface 144 of the insulating layer 140 are coplanar, according to some embodiments.

1H, portions of insulating layer 140 are removed to form openings 146 in insulating layer 140, in accordance with some embodiments. The openings 146 expose the top surfaces 134a of the conductive structures 134, according to some embodiments. Portions of the insulating layer 140 are removed using a photolithography process and an etching process, according to some embodiments.

1H, conductive layer 160 is formed in openings 146, according to some embodiments. The conductive layer 160 is electrically connected to the conductive structures 134 below it, according to some embodiments. The conductive layer 160 is in direct contact with the conductive structures 134 below it, according to some embodiments.

Formation of conductive layer 160 forms a seed layer (not shown) over conductive structures 134 and insulating layer 140, in accordance with some embodiments; Plating a layer of conductive material (not shown) over the seed layer; And performing a planarization process over the layer of conductive material until the top surface 144 of the insulating layer 140 is exposed.

The planarization process includes a chemical mechanical polishing (CMP) process, according to some embodiments. Therefore, the top surfaces 162, 144, and 152 of the conductive layer 160, the insulating layer 140, and the conductive structures 150 are coplanar, according to some embodiments.

1I, a dielectric layer 172 is formed over the insulating layer 140 and the conductive layer 160, in accordance with some embodiments. Dielectric layer 172 is made of a polymer material (eg, polyimide, PBO, etc.), in accordance with some embodiments. In some embodiments, dielectric layer 172 is made of an oxide, such as silicon dioxide or high density plasma oxide. In some embodiments, dielectric layer 172 is a borophosphosilicate glass (BPSG), spin on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhunt TEOS (PETEOS), or a combination thereof.

Dielectric layer 172 and insulating layer 140 are made of different materials, according to some embodiments. In some other embodiments, dielectric layer 172 and insulating layer 140 are made of the same material. Dielectric layer 172 is formed using a coating process, in accordance with some embodiments.

1I, a mask layer 182 is formed over the dielectric layer 172, according to some embodiments. The mask layer 182 has openings 182a exposing portions of the dielectric layer 172, according to some embodiments. The mask layer 182 is made of a photoresist material, according to some embodiments.

1J, portions of dielectric layer 172 are removed through openings 182a to form openings 172a in dielectric layer 172, according to some embodiments. 1J, conductive via structures 192 are formed in openings 172a, in accordance with some embodiments.

Some of the conductive via structures 192 are in direct contact with the conductive structures 150 below it, according to some embodiments. Some of the conductive via structures 192 are in direct contact with the conductive structures 134 below, according to some embodiments. The conductive via structures 192 are made of copper, aluminum, or other suitable conductive material.

The formation of the conductive via structures 192 forms a conductive material layer (not shown) over the dielectric layer 172 to fill the openings 172A, according to some embodiments; And performing a planarization process over the layer of conductive material until the dielectric layer 172 is exposed. That is, the conductive via structures 192 are formed using a single damascene process, according to some embodiments.

1J, dielectric layer 174 is formed over dielectric layer 172, in accordance with some embodiments. Dielectric layer 174 is made of a polymer material (eg, polyimide, PBO, etc.), in accordance with some embodiments. In some embodiments, dielectric layer 174 is made of an oxide, such as silicon dioxide or high density plasma oxide. In some embodiments, dielectric layer 174 is a borophosphosilicate glass (BPSG), spin on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhunt TEOS (PETEOS), or a combination thereof.

1J, conductive lines 194 are formed in dielectric layer 174, in accordance with some embodiments. The conductive lines 194 are electrically connected to the conductive via structures 192, according to some embodiments. The conductive lines 194 are in direct contact with the conductive via structures 192 below it, according to some embodiments. The conductive lines 194 are made of copper, aluminum, or other suitable conductive material. The conductive lines 194 are formed using a single damascene process, according to some embodiments.

1J, dielectric layer 176 is formed over dielectric layer 174 and conductive lines 194, in accordance with some embodiments. Dielectric layer 176 is made of a polymer material (eg, polyimide, PBO, etc.), in accordance with some embodiments. In some embodiments, dielectric layer 176 is made of an oxide, such as silicon dioxide or high density plasma oxide. In some embodiments, dielectric layer 176 is borophosphosilicate glass (BPSG), spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhunt TEOS (PETEOS), or a combination thereof.

1J, conductive via structures 196 are formed in dielectric layer 176, in accordance with some embodiments. The conductive via structures 196 are electrically connected to the conductive lines 194, according to some embodiments. The conductive via structures 196 make direct contact with the conductive lines 194 below it, according to some embodiments. The conductive via structures 196 are made of copper, aluminum, or other suitable conductive material. Conductive via structures 196 are formed using a single damascene process, in accordance with some embodiments.

1J, dielectric layer 178 is formed over dielectric layer 176, in accordance with some embodiments. Dielectric layer 178 is made of a polymer material (eg, polyimide, PBO, etc.), in accordance with some embodiments. In some embodiments, dielectric layer 178 is made of an oxide, such as silicon dioxide or high density plasma oxide. In some embodiments, dielectric layer 178 is borophosphosilicate glass (BPSG), spin-on glass (SOG), undoped silicate glass (USG), fluorinated silicate glass (FSG), plasma-enhunt TEOS (PETEOS), or a combination thereof.

1J, conductive pads 198 are formed in the dielectric layer 178, according to some embodiments. The conductive pads 198 are electrically connected to the conductive via structures 196, according to some embodiments. The conductive pads 198 directly contact the conductive via structures 196 below it, in accordance with some embodiments. The conductive pads 198 are made of copper, aluminum, or other suitable conductive material. The conductive pads 198 are formed using a single damascene process, according to some embodiments.

Dielectric layers 172, 174, 176, and 178 together form dielectric structure 170, in accordance with some embodiments. The conductive via structures 192 and 196, the conductive lines 194, the conductive pads 198, and the dielectric structure 170 together form the interconnect structure 210, according to some embodiments.

In some other embodiments, conductive via structures 192 and 196, conductive lines 194, and conductive pads 198 are formed using dual damascene processes. In some other embodiments, dielectric layer 172 is made of a photosensitive material, and the formation of dielectric layer 172 and conductive via structures 192 is in accordance with some embodiments, insulating layer 140 and conductive Forming a layer of photosensitive material (not shown) over layer 160; Performing a photolithography process to form openings 172a; Forming a conductive material layer (not shown) over the dielectric layer 172 to fill the openings 172a; And performing a planarization process over the layer of conductive material until the dielectric layer 172 is exposed.

Dielectric layers 174, 176, and 178, conductive lines 194, conductive via structures 196, and conductive pads 198, according to some embodiments, dielectric layer 172 and conductive via structures It may be formed using processes similar to those mentioned above to form the fields 192.

1K, the chip 220 is bonded to the interconnect structure 210 through conductive bumps 230 between the chip 220 and conductive pads 198, according to some embodiments. , Chip 220 is electrically connected to conductive structures 150 and 134 through conductive bumps 230 and interconnect structure 210, in accordance with some embodiments.

The chip 220 is a high frequency chip, such as a radio frequency (RF) chip, a graphics processor unit (GPU) chip, or other suitable high frequency chip. The chip 220 generates a signal having a frequency in the range of about 1 Hz to about 60 Hz, according to some embodiments.

1K, underfill layer 240 is formed in gap G between chip 220 and interconnect structure 210, in accordance with some embodiments. The underfill layer 240 is made of an insulating material, such as a polymer material, in accordance with some embodiments.

1K, molding layer 250 is formed over interconnect structure 210, in accordance with some embodiments. The molding layer 250 covers the chip 220 and surrounds the chip 220, the underfill layer 240, and conductive bumps 230, according to some embodiments.

The molding layer 250 is made of an insulating material, such as a polymeric material, according to some embodiments. In some embodiments, molding layer 250 and underfill layer 240 are made of different materials. In some embodiments, molding layer 250 and underfill layer 240 are made of the same material.

1L, the molding layer 250 is bonded to the carrier substrate 260 and upside down, in accordance with some embodiments. The carrier substrate 260 is configured to provide temporary mechanical and structural support during subsequent processing steps, according to some embodiments. The carrier substrate 260 includes glass, silicon oxide, aluminum oxide, metal, combinations thereof, and the like, according to some embodiments.

As shown in FIG. 1ma, the insulating layer 120 in the substrate 110, the first holes 116 and the second holes 118, the conductive shielding structures 132, the conductive structures 134 and 150, The insulating layer 140 in the first holes 116 is partially removed from the surface 114 of the substrate 110 to expose the conductive structures 134 and 150, according to some embodiments.

After the removal process, according to some embodiments, the first holes 116 become first through holes 116T and the first holes 118 become first through holes 118T. The conductive structures 150 penetrate the first through holes 116T, respectively, according to some embodiments. The conductive structures 134 pass through the second through holes 118T, respectively, according to some embodiments.

The removal process includes a planarization process, such as a chemical mechanical polishing process, according to some embodiments. Therefore, the conductive structures 150, the insulating layer 140, the conductive shielding structures 132, the insulating layer 120, and the surfaces 154, 148, 132b, 124, and 114 of the substrate 110 are According to some embodiments, it is coplanar. The conductive shielding structures 132 are electrically insulated from the conductive structures 134 and 150 and the chip 220, according to some embodiments.

1mb is a top view of a portion of the semiconductor device structure of FIG. 1ma, in accordance with some embodiments. 1ma is a cross-sectional view illustrating a semiconductor device structure along section line I-I 'of FIG. 1mb, in accordance with some embodiments.

1ma and 1mb, the insulating layer 140 is in the first through hole 116T and continuously surrounds the conductive structure 150, according to some embodiments. The conductive shielding structure 132 is in the first through hole 116T and continuously surrounds the insulating layer 140, according to some embodiments.

The insulating layer 120 is in the first through hole 116T and continuously surrounds the conductive shielding structure 132, according to some embodiments. The insulating layer 120 is in the second through hole 118T and continuously surrounds the conductive structure 134, according to some embodiments.

1ma and 1mb, the conductive shielding structure 132 in one of the first through holes 116T is tubular, according to some embodiments. In one of the first through holes 116T, the insulating layer 140, the conductive shielding structure 132, and the insulating layer 120 are tube structures concentric with each other, according to some embodiments. The tube structures are concentric with the conductive structure 150, according to some embodiments.

In some embodiments, the width W3 of each conductive structure 150 is substantially the same as the width W4 of each conductive structure 134. The term "substantially identical" means "within 10%", according to some embodiments. For example, “substantially the same” means, according to some embodiments, “the difference between widths W3 and W4 is within 10% of width W3 or W4”.

In some embodiments, the distance S1 between the two adjacent conductive structures 150, the distance S2 between the adjacent conductive structures 150 and 134, and the distance S3 between the two adjacent conductive structures 134 are substantially equal to each other. Do.

In some embodiments, the distance S4 between the two adjacent first through holes 116T is less than the distance S5 between the adjacent through holes 116T and 118T, and the distance S5 is the distance S6 between the two adjacent second through holes 118T. Less than

1na, interconnect structure 270 is formed over surface 114 of substrate 110, in accordance with some embodiments. The interconnect structure 270 includes a dielectric structure 271, wiring layers 272, 273, and 274, conductive pads 275, and conductive via structures 276, in accordance with some embodiments.

Wiring layers 272, 273, and 274, conductive pads 275, and conductive via structures 276 are formed in dielectric structure 271, in accordance with some embodiments. The wiring layers 272, 273, and 274 and the conductive pads 275 are electrically connected to each other through conductive via structures 276 therebetween, according to some embodiments.

The wiring layers 272, 273, and 274, the conductive pads 275, and the conductive via structures 276, according to some embodiments, the conductive structures 134 and 150 and the conductive shielding structures 132 It is electrically connected to.

The wiring layer 274 includes conductive lines 274a and 274b, according to some embodiments. The conductive line 274a is electrically connected to the conductive structure 150, according to some embodiments. The conductive line 274b is electrically connected to the conductive shield structure 132, according to some embodiments. The conductive line 274a is electrically insulated from the conductive line 274b, according to some embodiments.

1mb is a top view of area A of the semiconductor device structure of FIG. 1na, in accordance with some embodiments. 1na and 1nb, the conductive line 274b is an entire conductive line (to reduce signal interference between the conductive line 274a of the wiring layer 274 and adjacent conductive lines, according to some embodiments). 274a) continuously. Wiring layers 272, 273, and 274, conductive pads 275, and conductive via structures 276 are formed using single damascene processes, in accordance with some embodiments.

1na and 1nb, conductive bumps 282 and 286 and ground bumps 284 are formed over interconnect structure 270, in accordance with some embodiments. Conductive bumps 282 and 286 and ground bumps 284 are disposed over conductive pads 275, respectively, according to some embodiments. The conductive bumps 282 are connected to the conductive structures 150 through the conductive pads 275, the wiring layers 272, 273, and 274, and the conductive via structures 276, respectively, according to some embodiments. It is electrically connected.

The conductive bumps 284 are conductive shielding structures 132 through conductive pads 275, wiring layers 272, 273, and 274, and conductive via structures 276, respectively, according to some embodiments. It is electrically connected to. The conductive bumps 286 are connected to the conductive structures 134 through the conductive pads 275, the wiring layers 272, 273, and 274, and the conductive via structures 276, respectively, according to some embodiments. It is electrically connected.

1na and 1nb, ground bumps 284 surround conductive bump 282 and are electrically connected to conductive line 274b, in accordance with some embodiments. The conductive bump 282 is electrically connected to the conductive line 274a, according to some embodiments. Ground bumps 284 are electrically insulated from conductive bump 282, according to some embodiments.

1O, the substrate 110 is upside down and the carrier substrate 260 is removed, in accordance with some embodiments. As shown in FIG. 1O, the dicing process can be performed to separate the interconnect structures 210 and 270, the substrate 110, the insulating layers 120 and 140, and the molding layer 250 according to some embodiments. It is performed to cut into semiconductor device structures 200.

For simplicity, FIG. 1O shows only one of the semiconductor device structures 200, according to some embodiments. The semiconductor device structures 200 are also referred to as chip package structures, according to some embodiments.

As shown in FIG. 1O, after the dicing process, the conductive shielding layer 290 is molded layer 250, interconnect structures 210 and 270, substrate 110, insulating layers, in accordance with some embodiments. (120 and 140).

The conductive shielding layer 290 is the top surface 252 of the molding layer 250 and the molding layer 250, the interconnection structure 210, the insulating layer 140, the insulating layer 120, according to some embodiments , Covering the substrate 110 and the sidewalls 254, 212, 149, 126, 119, and 277 of the interconnect structure 270.

The conductive shielding layer 290 is configured to reduce signal interference between the semiconductor device structure 200 and other semiconductor device structures adjacent to the semiconductor device structure 200, according to some embodiments. The conductive shielding layer 290 is electrically insulated from the chip 220, the conductive shielding structures 132, and the conductive structures 134 and 150, according to some embodiments.

The side walls 254, 212, 149, 126, 119, and 277 are coplanar, according to some embodiments. The conductive shielding layer 290 is made of a metal material or an alloy material, according to some embodiments. Metallic materials include copper, gold, aluminum, tungsten, or other suitable metallic materials. The conductive shielding layer 290 is formed using a physical deposition process or a plating process, according to some embodiments.

The conductive structures 150 are configured to transmit signals with high frequencies (eg, frequencies greater than 1 GHz), according to some embodiments. The conductive structures 134 are configured to transmit signals having frequencies lower than those of the signals transmitted by the conductive structures 150, according to some embodiments. The conductive shielding structures 132 are configured to reduce signal interference between the conductive structures 150 and / or between the conductive structures 150 and 134, according to some embodiments.

Since the conductive shielding structures 132 reduce signal interference, the distance S1 between the two adjacent conductive structures 150, the distance S2 between the adjacent conductive structures 150 and 134, and the two adjacent conductive structures 134 ), The distances S3 may remain substantially the same. That is, it is not necessary to increase the distances S1 and S2 to reduce signal interference. Therefore, the formation of the conductive shielding structures 132 can reduce the sizes of the substrate 110 and semiconductor device structures 200. In some other embodiments, depending on design requirements, at least two of the distances S1, S2, or S3 are different from each other.

2 is a cross-sectional view of a semiconductor device structure, in accordance with some embodiments. As shown in FIG. 2, the semiconductor device structure 300 is that the semiconductor device structure 300 has chips 310 and 320 and does not have the semiconductor device structure 200 of FIG. 1O, according to some embodiments. It is similar to the semiconductor device structure 200 of FIG. 1O except for that.

Chip 310 is electrically connected to conductive structures 150, in accordance with some embodiments. The chip 320 is electrically connected to the conductive structures 134, according to some embodiments. The chip 310 is a high frequency chip, such as a radio frequency (RF) chip, a graphics processor unit (GPU) chip, or other suitable high frequency chip.

The chip 320 is a low frequency chip or other suitable chip. The chip 320 generates a signal having a frequency lower than the frequency of the signal generated by the chip 310, according to some embodiments. The semiconductor device structure 300 is also referred to as chip package structures, according to some embodiments.

3A is a cross-sectional view of a semiconductor device structure 400, in accordance with some embodiments. 3B is a bottom view of the substrate 110 of the semiconductor device structure 400 of FIG. 3A, in accordance with some embodiments. 3A is a cross-sectional view illustrating a semiconductor device structure 400 along section line I-I 'of FIG. 3B, in accordance with some embodiments.

3A and 3B, the semiconductor device structure 400 has a semiconductor device structure 400 having a second through hole 118T between the first through holes 116T, according to some embodiments. It is similar to the semiconductor device structure 300 of FIG. 2, except that. That is, the conductive structures 134 in the second through holes 118T are between the conductive shielding structures 132 in the first through holes 116T, respectively, according to some embodiments.

The substrate 110 has a high frequency region 111, according to some embodiments. High frequency elements (eg, high frequency chips) may be formed in the high frequency region 111. In the high frequency region 111, the first through holes 116T and the second through holes 118T are alternately arranged, according to some embodiments.

In the high frequency region 111, the conductive structures 134 and the conductive shielding structures 132 are alternately arranged, according to some embodiments. The conductive shielding structures 132 surround one of the conductive structures 134, according to some embodiments. The conductive structures 134 surround one of the conductive shielding structures 132, according to some embodiments.

Since the distance S7 between the conductive structures 134 in the high frequency region 111 is greater than the distance S3 between the conductive structures 134 outside the high frequency region 111, the distance S7 is the conductive structures 134 in the high frequency region 111 ) Can reduce signal interference. The semiconductor device structure 400 is also referred to as chip package structures, in accordance with some embodiments.

In accordance with some embodiments, semiconductor device structures and methods of forming the same are provided. Methods (forming a semiconductor device structure) form a conductive shield structure within the substrate to surround the through substrate to reduce signal interference between the through substrate vias and other adjacent through substrate vias. Therefore, there is no need to increase the distance between through substrate vias to reduce signal interference. As a result, the formation of conductive shielding structures can reduce the size of the substrate and the size of the chip package structure with the substrate.

According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in the first surface of the substrate. The method includes forming a first insulating layer in the first hole and the second hole. The method includes forming a conductive layer over the first insulating layer and in the first hole and the second hole. The conductive layer has a first recess in the first hole and fills the second hole. The method includes forming a second insulating layer over the conductive layer in the first recess. The second insulating layer has a second recess in the first recess. The method includes forming a conductive structure in the second recess. The method includes the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole. And partially removing it. The second surface is opposite the first surface.

According to some embodiments, a method of forming a semiconductor device structure is provided. The method includes forming a first hole and a second hole in the first surface of the substrate. The method includes conformally forming a first insulating layer in the first hole and the second hole. The method includes forming a conductive layer over the first insulating layer. The conductive layer conformally covers the first insulating layer in the first hole and has a first recess in the first hole, and the conductive layer fills the second hole. The method includes forming a second insulating layer over the conductive layer. The second insulating layer has a second recess in the first recess. The method includes forming a conductive structure in the second recess to fill the second recess. The method comprises the first insulating layer in the substrate, the first hole and the second hole, from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole, And partially removing the conductive layer and the second insulating layer in the first hole and the second hole. The second surface faces the first surface, and the conductive layer in the first hole forms a conductive shielding structure.

According to some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a first conductive structure penetrating the substrate. The semiconductor device structure includes a first insulating layer penetrating the substrate and surrounding the first conductive structure. The semiconductor device structure includes a conductive shielding structure penetrating the substrate and surrounding the first insulating layer. The semiconductor device structure includes a second insulating layer penetrating the substrate and surrounding the conductive shielding structure. The semiconductor device structure includes a second conductive structure penetrating the substrate. The second conductive structure and the conductive shielding structure are made of the same conductive material. The semiconductor device structure includes a third insulating layer penetrating the substrate and surrounding the second conductive structure. The third insulating layer and the second insulating layer are made of the same conductive material.

Embodiment 1 is a method of forming a semiconductor device structure, comprising: forming a first hole and a second hole in a first surface of a substrate; Forming a first insulating layer in the first hole and the second hole; Forming a conductive layer over the first insulating layer and in the first hole and the second hole, the conductive layer having a first recess in the first hole and filling the second hole; Forming a second insulating layer over the conductive layer in the first recess, the second insulating layer having a second recess in the first recess; Forming a conductive structure in the second recess; And partially exposing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole. And removing the second surface opposite the first surface.

Example 2, in Example 1, the step of partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer is a method of forming a semiconductor device structure including a planarization process. .

Example 3 is a method of forming a semiconductor device structure, wherein the first thickness of the second insulating layer is greater than the second thickness of the conductive layer, and the second thickness is greater than the third thickness of the first insulating layer. .

Example 4 is a method of forming a semiconductor device structure in Example 1 in which the first width of the first hole is greater than the second width of the second hole.

Example 5, in Example 1, forming the second insulating layer comprises: conformally depositing the second insulating layer over the conductive layer and the first surface; And after forming the conductive structure, forming an opening in a second insulating layer, the opening exposing the conductive layer in the second hole.

Example 6, in Example 1, forming the conductive layer comprises: forming the conductive layer over the first insulating layer, wherein the conductive layer includes the first insulating layer and the first hole in the first hole; Conformally covering the first insulating layer over a first surface-; And removing the conductive layer over the first surface.

In Example 7, in Example 6, the step of removing the conductive layer on the first surface performs a planarization process on the conductive layer until the first insulating layer on the first surface is exposed. It comprises a step of forming a semiconductor device structure.

Example 8 is that in Example 1, after partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface, the conductive layer in the first hole is It is a method of forming a semiconductor device structure that becomes tubular and continuously surrounds the conductive structure.

Example 9 provides the substrate, the first insulating layer, the conductive layer, and the second insulating layer in Example 1 after forming the conductive structure in the second recess and from the second surface. Forming an interconnect structure over the first surface, the conductive structure, and the conductive layer, before partially removing; Bonding a chip to the interconnect structure; And forming a molding layer over the interconnect structure to surround the chip.

Embodiment 10 is a method of forming a semiconductor device structure, comprising: forming a first hole and a second hole in a first surface of a substrate; Conformally forming a first insulating layer in the first hole and the second hole; Forming a conductive layer over the first insulating layer-the conductive layer conformally covers the first insulating layer in the first hole and has a first recess in the first hole, the conductive layer being the first insulating layer Filling 2 holes-; Forming a second insulating layer over the conductive layer, wherein the second insulating layer has a second recess in the first recess; Forming a conductive structure in the second recess to fill the second recess; And the substrate, the first insulating layer in the first hole and the second hole, the first from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole. Partially removing the conductive layer, and the second insulating layer in one hole and the second hole, wherein the second surface faces the first surface, and the conductive layer in the first hole provides a conductive shielding structure. Forming-is a method of forming a semiconductor device structure.

Embodiment 11 is the method according to Embodiment 10, after forming the conductive structure in the second recess and from the second surface, the substrate, the first hole and the first insulating layer in the second hole, the Forming a first interconnect structure over the first surface, the conductive structure, and the conductive layer before partially removing the conductive layer in the first hole and the second hole, and the second insulating layer; Bonding a chip to the first interconnect structure-the chip is electrically connected to a conductive structure and a conductive layer in the second hole through the first interconnect structure, and the conductive layer in the first hole is the A conductive structure, the conductive layer in the second hole, and electrically insulated from the chip-; And forming a molding layer over the first interconnect structure to surround the chip.

Example 12 is the method according to Example 11, wherein the substrate, the first insulating layer in the first hole and the second hole, the conductive layer in the first hole and the second hole from the second surface, and After partially removing the second insulating layer, further comprising forming a second interconnect structure over the second surface, the second interconnect structure comprising a dielectric structure, a first conductive line in the dielectric structure, and a first A method of forming a semiconductor device structure, comprising two conductive lines, wherein the first conductive line and the second conductive line are electrically connected to the conductive structure and the conductive shielding structure, respectively.

Embodiment 13 is a semiconductor device structure according to embodiment 12, wherein the first conductive line is electrically insulated from the second conductive line, and the second conductive line continuously surrounds the entire first conductive line. It is a way to form.

Embodiment 14 further includes forming a conductive bump and a plurality of ground bumps on the second interconnect structure, the conductive bump being electrically connected to the conductive structure, and the ground bump These are methods of forming a semiconductor device structure, which are electrically connected to and surround the conductive bump.

Embodiment 15, according to Embodiment 14, after forming the conductive bumps and the ground bumps, upper surfaces of the molding layer and the chip, the molding layer, the first interconnect structure, the substrate, and the And forming a conductive shielding layer over sidewalls of the second interconnect structure, wherein the conductive shielding layer is electrically insulated from the chip and the conductive shielding structure.

Embodiment 16 is a semiconductor device structure, comprising: a substrate; A first conductive structure penetrating the substrate; A first insulating layer penetrating the substrate and surrounding the first conductive structure; A conductive shielding structure penetrating the substrate and surrounding the first insulating layer; A second insulating layer penetrating the substrate and surrounding the conductive shielding structure; A second conductive structure penetrating the substrate, wherein the second conductive structure and the conductive shielding structure are made of the same conductive material; And a third insulating layer penetrating the substrate and surrounding the second conductive structure, wherein the third insulating layer and the second insulating layer are made of the same insulating material.

Example 17 is the semiconductor device structure of Example 16, wherein the first conductive structure and the top surfaces of the first insulating layer are coplanar.

Example 18 is the method according to Example 17, wherein the first conductive structure, the first insulating layer, the conductive shielding structure, the second insulating layer, the substrate, the third insulating layer, and the second conductive structure The lower surfaces are coplanar, semiconductor device structures.

In Example 19, in Example 16, the first thickness of the first insulating layer is greater than the second thickness of the conductive shielding structure, and the second thickness is greater than the third thickness of the second insulating layer and the agent is 3 is a semiconductor device structure larger than the fourth thickness of the insulating layer.

In Example 16, in Example 16, the first thickness of the second insulating layer is substantially the same as the second thickness of the third insulating layer, and the second insulating layer is directly connected to the third insulating layer. It is a semiconductor device structure.

The foregoing describes features of various embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same objectives and / or achieve the same advantages of the embodiments described herein. You should know that there is. Those skilled in the art can also make various changes, permutations, and modifications herein without departing from the spirit and scope of the present disclosure, and such equivalent configurations without departing from the spirit and scope of the present disclosure. Be aware of it.

Claims (10)

A method of forming a semiconductor device structure,
Forming a first hole and a second hole in the first surface of the substrate;
Forming a first insulating layer in the first hole and the second hole;
Forming a conductive layer over the first insulating layer and in the first hole and the second hole, the conductive layer having a first recess in the first hole and filling the second hole;
Forming a second insulating layer over the conductive layer in the first recess, the second insulating layer having a second recess in the first recess;
Forming a conductive structure in the second recess; And
Partially the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole Removing, the second surface facing the first surface; and
Forming the second insulating layer,
Conformally depositing the second insulating layer over the conductive layer and the first surface; And
After forming the conductive structure, forming an opening in a second insulating layer, the opening exposing the conductive layer in the second hole-
A method of forming a semiconductor device structure that includes. The method of claim 1, wherein partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer includes a planarization process. A method of forming a semiconductor device structure,
Forming a first hole and a second hole in the first surface of the substrate;
Forming a first insulating layer in the first hole and the second hole;
Forming a conductive layer over the first insulating layer and in the first hole and the second hole, the conductive layer having a first recess in the first hole and filling the second hole;
Forming a second insulating layer over the conductive layer in the first recess, the second insulating layer having a second recess in the first recess;
Forming a conductive structure in the second recess; And
Partially the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole Removing, the second surface facing the first surface; and
A method of forming a semiconductor device structure, wherein a first thickness of the second insulating layer is greater than a second thickness of the conductive layer, and the second thickness is greater than a third thickness of the first insulating layer. The method of claim 1, wherein the first width of the first hole is greater than the second width of the second hole. delete According to claim 1, The step of forming the conductive layer,
Forming the conductive layer over the first insulating layer, the conductive layer conformally covering the first insulating layer in the first hole and the first insulating layer over the first surface; And
Removing the conductive layer over the first surface
A method of forming a semiconductor device structure that includes. The conductive layer in the first hole becomes tubular and the conductive material of claim 1, after partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface. A method of forming a semiconductor device structure, which continuously surrounds the structure. A method of forming a semiconductor device structure,
Forming a first hole and a second hole in the first surface of the substrate;
Forming a first insulating layer in the first hole and the second hole;
Forming a conductive layer over the first insulating layer and in the first hole and the second hole, the conductive layer having a first recess in the first hole and filling the second hole;
Forming a second insulating layer over the conductive layer in the first recess, the second insulating layer having a second recess in the first recess;
Forming a conductive structure in the second recess; And
Partially the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole Removing, the second surface facing the first surface; and
The method of forming the semiconductor device structure,
The first surface, after forming the conductive structure in the second recess and before partially removing the substrate, the first insulating layer, the conductive layer, and the second insulating layer from the second surface Forming an interconnect structure over the conductive structure and the conductive layer;
Bonding a chip to the interconnect structure; And
And forming a molding layer over the interconnect structure to surround the chip. A method of forming a semiconductor device structure,
Forming a first hole and a second hole in the first surface of the substrate;
Conformally forming a first insulating layer in the first hole and the second hole;
Forming a conductive layer over the first insulating layer-the conductive layer conformally covers the first insulating layer in the first hole and has a first recess in the first hole, the conductive layer being the first insulating layer Fill 2 holes-;
Forming a second insulating layer over the conductive layer, the second insulating layer having a second recess in the first recess;
Forming a conductive structure in the second recess to fill the second recess; And
The substrate, the first insulating layer in the first hole and the second hole from the second surface of the substrate to expose the conductive layer and the conductive structure in the first hole and the second hole, the first Partially removing the conductive layer in the hole and the second hole, and the second insulating layer-the second surface faces the first surface, and the conductive layer in the first hole has a conductive shielding structure Forming-including,
A method of forming a semiconductor device structure,
After forming the conductive structure in the second recess and from the second surface, the first insulating layer in the substrate, the first hole and the second hole, the conductive in the first hole and the second hole Forming a first interconnect structure over the first surface, the conductive structure, and the conductive layer before partially removing the layer and the second insulating layer;
Chip to the first interconnect structure-the chip is electrically connected to the conductive layer and the conductive structure in the second hole through the first interconnect structure, and the conductive layer in the first hole is the conductive Bonding a structure, electrically insulated from the conductive layer and the chip in the second hole; And
And forming a molding layer over the first interconnect structure to surround the chip. A semiconductor device structure,
Board;
A first conductive structure penetrating the substrate;
A first insulating layer penetrating the substrate and surrounding the first conductive structure and extending over a surface of the substrate;
A conductive shielding structure penetrating the substrate and surrounding the first insulating layer;
A second insulating layer penetrating the substrate and surrounding the conductive shielding structure;
A second conductive structure penetrating the substrate, wherein the second conductive structure and the conductive shielding structure are made of the same conductive material;
A conductive layer penetrating the first insulating layer extending over the surface of the substrate and contacting the second conductive structure; And
A third insulating layer penetrating the substrate and surrounding the second conductive structure, wherein the third insulating layer and the second insulating layer are made of the same insulating material-
Semiconductor device structure comprising a.

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