KR102096233B1 - Semiconductor package test system suitable for parallel test and test method using the same - Google Patents

Abstract

The present invention relates to a semiconductor test, and more particularly, to a semiconductor package test system suitable for parallel testing capable of increasing the number of semiconductor devices to be tested in the test phase of the semiconductor package and a test method using the same.
In order to achieve the above object, a semiconductor package test system suitable for parallel testing according to the present invention accommodates an automatic test equipment (ATE); a semiconductor package (Device Under Test: DUT), and the received semiconductor package is An interface board to be electrically connected to an automatic test device (ATE), so that a test pattern signal generated from the automatic test device (ATE) is applied to the semiconductor package; And a test handler for automatically supplying the semiconductor package (Device Under Test: DUT) to the automatic test device and transferring the semiconductor package according to the test result of the automatic test device, wherein the interface board interfaces with the router. It is based on a network-on-chip (NOC) equipped with a plurality of interconnected semiconductor packages, and by generating and forwarding a new response packet that accumulates each test result in a router on the packet response transmission path of the network-on-chip. Resolve bottlenecks.

Description

Semiconductor package test system suitable for parallel test and test method using the same}

The present invention relates to a semiconductor test, and more particularly, to a semiconductor package test system suitable for a parallel test capable of increasing the number of semiconductor devices to be tested in the test phase of the semiconductor package and a test method using the same.

As the types of semiconductor devices are diversified according to the trend of high speed, high performance, and high integration of semiconductor devices, the test interface board for connecting between automatic test equipment (ATE) and semiconductor package (Device Under Test: DUT) is complicated. ought.

 Semiconductor wafers produced through hundreds of detailed processes undergo wafer testing. At this time, the wafer test is performed at both low and high temperatures, and a probe station, probe card, and automatic test equipment (ATE) are used for testing. The quality wafers are manufactured again in a package form after assembly, where the assembly is divided into wafer cutting, bonding, molding, and marking. The manufactured package is tested again, and only the product determined as the final good is sold or manufactured as a module or board.

A semiconductor package test system loads semiconductors into sockets to be tested one after another, and sorts them into good and grade products according to the result. In general, semiconductors that are mass-produced, such as memory, are subjected to a total inspection, so a decrease in test time for detecting defects plays an important role in reducing the overall production cost. Therefore, the package-level test performs a large amount of multi-site tests. The multi-site test refers to a technique that reduces the overall test cost by testing multiple devices simultaneously in one automatic test apparatus (ATE). For example, in the case of a high-speed memory test on the market, 1,024 memories can be tested simultaneously based on DDR 3, and the operation speed of an automatic test device (ATE) reaches 2.4 Gbps. When the number of channels (number of pins) required to test one device is N, the multi-site test can be said to be effective when the number of channels required to test m devices being tested simultaneously is smaller than m * N.

However, the current commercially available semiconductor package tester utilizes the BOST structure that implements the relevant functions on the interface board located between the automatic test device (ATE) and the semiconductor package (DUT) to increase the number of devices that can be tested simultaneously. The interface board of the BOST function is an automatic test device (ATE) or an Algorithmic Pattern Generator (ALPG) that generates a pattern based on the signal transmitted from the automatic test device (ATE), and becomes a test source to the semiconductor package (DUT). Test pattern is applied. At this time, a data connection structure for applying a pattern to multiple semiconductor packages (DUTs) at the same time, that is, an interconnect structure, is used. So far, a common bus structure has been used. The bus structure has the advantage of easy design and short transmission delay, but the number of modules that can be connected to the bus is limited and the operation of the bus controller is complicated, such as determining the priority of bus use in proportion to the number of connected modules.

In addition, data loss due to data collision in the bus should also be considered. For this reason, it is very difficult to dramatically improve test parallelism using the bus structure.

KR 10-2013-0025529 A

The present invention has been devised to solve this problem, and provides a semiconductor package test system and a test method using the semiconductor package test system suitable for parallel testing to dramatically improve parallelism by increasing the number of semiconductor devices tested in a semiconductor package test stage. The purpose is to do.

In order to achieve the above object, a semiconductor package test system suitable for parallel testing according to the present invention accommodates an automatic test equipment (ATE); a semiconductor package (Device Under Test: DUT), and the received semiconductor package is An interface board to be electrically connected to an automatic test device (ATE), so that a test pattern signal generated from the automatic test device (ATE) is applied to the semiconductor package; And a test handler for automatically supplying the semiconductor package (Device Under Test: DUT) to the automatic test device and transferring the semiconductor package according to the test result of the automatic test device, wherein the interface board interfaces with the router. It is based on a network-on-chip (NOC) equipped with a plurality of interconnected semiconductor packages, and by generating and forwarding a new response packet that accumulates each test result in a router on the packet response transmission path of the network-on-chip. Resolve bottlenecks.
Preferably, the interface board includes: a test source providing unit for generating and providing test pattern data based on a signal transmitted from the automatic test device (ATE); An interconnect unit for determining to which target semiconductor package the test pattern data generated and provided by the test source provider is transmitted; And a test response unit that analyzes and responds to a test result of the target semiconductor package based on the transmitted test pattern data when the test pattern data is transmitted to the target semiconductor package determined by the interconnect unit.
Preferably, the response packet that reaches the maximum length with a maximum length limit of the response packet is transmitted to a neighboring router without additional operation.
Another aspect of the present invention for achieving the above object is a test method using the semiconductor package test system of claim 1, (a) generating test pattern data based on a signal input from an automatic test device (ATE); (b) transferring the test pattern data generated in step (a) to a target semiconductor package; (c) configuring a test result of the target semiconductor package delivered in step (b) in the form of a response packet; And (d) generating and forwarding a new response packet that accumulates test results in each packet in a router on a transmission path of the response packet configured in step (c).
Preferably, the response packet having reached the maximum length is transmitted to a neighboring router without a separate operation with a maximum length limit of the response packet.
Preferably, the transfer of the test pattern data in step (b) is carried out by multicasting to a plurality of target semiconductor packages.

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According to the present invention, since more semiconductor packages can be tested with the same bandwidth of the automatic test device (ATE), the cost of mass-produced semiconductor testing can be greatly reduced, and a separate synchronization signal such as a test clock is not required. By using, it is possible to easily implement a high-speed at-speed test function.

In addition, test data can be easily transmitted and received without complicated processes such as serial data transmission, clock recovery, or channel width synchronization (B / W matching) like the existing SerDes method. There is no limitless effect.

1 is a schematic block diagram illustrating a semiconductor test system according to embodiments of the present invention.
FIG. 2 is a block diagram showing the structure of an interface board suitable for parallel testing in the semiconductor test system according to FIG. 1.
3 is a view showing the NOC structure.
4 is a diagram showing various NOC topologies.
FIG. 5 is a view showing an interconnect unit in which a NOC structure is applied to an interface board to be suitable for parallel testing in the semiconductor test system according to FIG. 1.
6 is a flowchart illustrating a test method using a semiconductor test system according to the present invention.
7 to 8 are diagrams illustrating a test pattern transmission method in a test method using a semiconductor test system according to the present invention.
9 is a diagram illustrating a test pattern response method in a test method using a semiconductor test system according to the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. Prior to this, the terms or words used in the present specification and claims should not be construed as being limited to ordinary or lexical meanings, and the inventor appropriately explains the concept of terms to explain his or her invention in the best way. Based on the principle that it can be defined, it should be interpreted as meanings and concepts consistent with the technical spirit of the present invention. Therefore, the embodiments shown in the embodiments and the drawings described in this specification are only the most preferred embodiments of the present invention and do not represent all of the technical spirit of the present invention, and at the time of this application, various alternatives are possible. It should be understood that there may be equivalents and variations.

1 is a schematic block diagram illustrating a semiconductor test system according to embodiments of the present invention.

As shown in FIG. 1, the semiconductor test system 10 is largely an automatic test equipment (ATE) 100, an interface board 200, a semiconductor package (Device under Test: DUT) 300, a test handler 400.

The automatic test device (ATE) 100 is a device that automatically inspects the semiconductor package (DUT) 300 and is configured as a microcomputer or microprocessor-based system. The automatic test device (ATE) 100 is electrically coupled to the interface board 200 through a test header 200a. The automatic test device (ATE) 100 is electrically connected to the semiconductor package (DUT) 300 through the interface board 200, inputs a test pattern into the semiconductor package (DUT) 300, and then supplies the semiconductor package (DUT). An error of the semiconductor package (DUT) 300 is determined by comparing the output of the 300 with an expected value. The semiconductor package (DUT) 300 is mounted on the socket 200b of the interface board 200 and is electrically coupled. The automatic test device (ATE) 100 is a DC test that tests whether the DC parameters of the semiconductor package (DUT) 300 are suitable for the digital operation of the circuit, and the delay time, set-up time, and hold of signal transmission. It may include an AC margin test related to (hold) time and the like.

The semiconductor package (DUT) 300 includes a volatile memory device such as SRAM, DRAM, SDRAM, or a nonvolatile memory device such as ROM, PROM, EPROM, EEPROM, flash memory, PRAM, MRAM, FRAM, and the like, and a memory component including them. component). Also, the semiconductor package (DUT) 300 is not limited to a memory device or a memory package, and may be, for example, a memory module, a memory card, or a memory stick formed by combining memory components. Also, the semiconductor package (DUT) 300 may include chips such as ISPs and DSPs with or without a memory device.

The test handler 400 is automatically supplied to the automatic test device (ATE) 100 for testing the semiconductor package (DUT) 300, and when the process of testing is finished, according to the inspection result of the automatic test device (ATE) 100 The semiconductor package (DUT) 300 is transferred to an appropriate location. The test handler 400 may be combined with an automatic test device (ATE) 100 in a 1; 1 or N; 1 fashion. In general, the test handler 400 is composed of a loading unit, an input stage, a test site, a shuttle, an unloading unit, an output stage, and sensors.

FIG. 2 is a block diagram showing the structure of an interface board suitable for parallel testing in the semiconductor test system according to FIG. 1.

As shown in FIG. 2, the interface board 200 includes a test source providing unit 210 for generating and providing test pattern data based on a signal transmitted from an automatic test device (ATE) 100, and a test source Test pattern to the target semiconductor package 300 determined by the interconnect unit 220 and the interconnect unit 220 to determine which target semiconductor package 300 to transmit the test pattern data generated and provided by the provider 210. When data is transmitted, a test response unit 230 that analyzes and responds to a test result of the target semiconductor package based on the transmitted test pattern data.

The test source providing unit 210 receives a signal from the automatic test device (ATE) 100, or a test pattern based on a signal transmitted from the automatic test device (ATE) 100 including an Algorithmic Pattern Generator (ALPG) Produces At this time, the signal or test pattern of the automatic test device becomes a test source to apply test pattern data to the semiconductor package 300.

On the other hand, although the interconnect unit 220 usually uses a bus, the bus structure has an advantage of easy design and short transmission delay time, but the number of modules that can be connected to the bus is limited and the bus is used in proportion to the number of connected modules. The operation of the bus controller, such as prioritization, was complicated, and data loss due to data collision in the bus also had to be considered. In addition, the test result output from the semiconductor package was fed back to the automatic test device through the interconnect structure, and a comparator had to be used to transmit only the result that is compared to the normal failure-free value.

However, in the present invention, the interconnect unit 220 is an interconnect structure of an Intellectual Property (IP) in a high-density SOC design, and the proposed network-on-chip (NoC) is an interconnect unit 220 of the interface board 200. ) To eliminate test bottlenecks and test multiple semiconductor packages 300 at the same time.

 The network on chip (NoC) is a data interconnect structure having a micronetwork connection type suitable for a high density structure. Micro-network is also called On-Chip Networks, and refers to a layer-based on-chip connection type used in computer networks. Under the on-chip network, it is free to add new cores or delete existing cores, and since data transmission between cores is done in a packet manner, simultaneous message transmission of many cores is possible. In addition, since the operating speed of the on-chip network and the core are completely separated, the entire system is asynchronous and locally synchronized.

 3 is a diagram showing the structure of the NOC and FIG. 4 is a diagram showing various NOC topologies.

As shown in FIG. 3, the NOC is composed of a router, an interconnect channel, and a network interface (NI). First, the router connects the channel and the channel and determines which output port to send data to according to the destination of the input data according to the routing algorithm. The interconnect channel is the physical data link and NI connects the internal IP and router. In addition, various types of NOC structures are created according to the configuration method, and are generally classified based on network topology, protocol, router structure, and operation method.

As such, the number of DUTs that can be connected to one interface board is theoretically unlimited due to the NOC characteristics. Normally, NOC is implemented using an FPGA or a dedicated ASIC like the existing bus interconnect, so electrical characteristics such as the number of external input / output pins and maximum current provided by the NOC-implemented hardware can determine the number of DUTs.

FIG. 5 is a diagram illustrating an interconnect unit in which a NOC structure is applied to an interface board so that the semiconductor test system according to FIG. 1 is suitable for parallel testing.

The test source and the test sink of FIG. 5 can be understood as the same concepts as the test source providing unit 210 and the test response unit 230 shown in FIG. 2 for reference. That is, a test source for generating a test pattern and a test sink for analyzing and storing test results are modules connected to the interconnect unit 220. As shown, the test source is ATE, ALPG, microprocessor, etc., and the generated data is transmitted to the target DUT through a router indicated as 'R' in the interconnect unit 220. The test result of the DUT is sent back to the test sink through the router, and ATE is mainly used, and a separate analyzer in the interface board can be installed and used. Although there may be multiple test sources in one interconnect unit 220, it is advantageous to unify the sink for failure analysis and diagnosis, and repair.

Since the interconnect unit 220 can compensate for the difference in operating speed between the connected modules using the buffering effect of the network interface NI and the router R, the speed setting between the ATE, NOC interconnect, and DUT is free. Therefore, an at-speed test using low-speed ATE can be easily implemented without precise clock control and synchronization circuit.

6 is a flowchart illustrating a test method using a semiconductor test system according to the present invention.

The interface board generates test pattern data based on the signal input from the automatic test device (ATE) (S100).

Then, the generated test pattern data is transferred to the target semiconductor package (DUT) (S110), and the target semiconductor package is analyzed by the transmitted test pattern data and the analyzed result is stored (S120).

Next, a method of testing a semiconductor package using a march test algorithm based on the NOC interconnect will be described as an embodiment of the present invention.

In general, testing means reading and writing tests in ascending or descending order in order of address, as if marching through the entire memory area, and is currently the most widely used memory test algorithm. Each gusset test consists of a combination of march elements (marked M), and the gusset elements are divided according to the operation of reading and writing to each memory cell as they move in a sequence of address sequences. The definition of symbols used in the test and detailed description of each operation are as follows.

↑: Move memory address from bottom to top (ascending)

↓: Move memory address from top to bottom (descending)

↕: Move the memory address in ascending or descending order

-R: memory read operation

-R0: read and expect the logic value stored in the memory cell to be 0

-R1: Logic value stored in memory cell is expected to be 1 and read

W: Memory write operation

-W0: Write the logical value 0 to the memory cell

-W1: Write logical value 1 to the memory cell

 For example, the MATS ++ algorithm, which is one of the test algorithms, consists of a total of three gusset elements as follows:

· {M ₀ , M ₁ , M ₂ } = {↕ (w0); ↑ (r0, w1); ↓ (r1, w0, r0)}

For reference, MATS ++ moves memory addresses in ascending or descending order. After writing 0 to all cells, it reads cell values in ascending order to check that it is 0 and writes 1 to the read cell. When the maximum address is reached, the address is lowered one by one, checking that the cell value is 1, and writing 0 and reading again. If the expected value is different from the actual read value, it is recognized that a failure has occurred, and the types of failures are fixed failure, unrelated transition failure, some address decoders and combined failures.

 In addition, the NOC interconnect unit used in the present embodiment uses the most common 2D mesh as a basic topology as shown in FIG. 5, XY routing, worm-hole switching, and credit-based flow control. Is used, but is not limited thereto. In addition, all routers have a flit buffer on the input port, and the size of one flit is equal to the channel width. Test sources, sinks, and DUTs connected to the NOC exchange data through test packets consisting of a header, a payload, and a trailer.

First, the process of transmitting the test pattern to the DUT will be described with reference to the structure of the test packet for the test of the following [Table 1].

[Table 1]

The header consists of a data type, a packet transmission method (unicast, multicast), a destination address, etc., which distinguishes an input test pattern from a test response.

7 to 8 are diagrams showing a method of transmitting a test pattern in a test method using a semiconductor test system according to the present invention.

Among the packet transmission methods, the unicast method of FIG. 7 is a method of transmitting patterns for each DUT, and is used when the test algorithms simultaneously test different DUTs. In addition, the multicast method of FIG. 8 is a method used to apply the same test pattern to all DUTs connected to the NOC and XY routing to reduce packet traffic in the NOC and eliminate loops or deadlocks. ) Use the same routing technique. The destination address is the coordinates of the destination DUT and [Table 1] is based on the NOC size of 16 (4 bits) * 16 (4 bits).

And [Table 2] is a table showing the payload composition of MATS ++ March elements.

[Table 2]

Although the test vector value is carried in the payload, a binary value array can be directly written, but if it is expressed in a certain format as a pattern, coding as shown in [Table 1] allows all algorithm-generated vectors to be transmitted. For example, in case of MATS ++, payload is composed as shown in [Table 2]. The size of the binary value of the payload is determined according to the longest value among the elements. In the case of MATS ++ in [Table 2], the address direction is 2 bits, the R / W size is 2 bits, and the R / W mode is 2 bits * 3 The total is 10 bits. Finally, the trailer contains the same value as the CRC to check for transmission errors, and the importance of the NOC is not high because it is implemented within a single chip.

 And the following [Table 3] shows the DUT test result for the pattern in the form of a response packet.

[Table 3]

 The test response packet also consists of a header, a payload, and a trailer. In the case of a header, it contains data indicating the test response packet, the address of the test sink, and information indicating the number of test results in the packet. That is, test results of multiple DUTs may be accumulated and transmitted in one response packet, because the response packet is transmitted to the same destination (test sink) unlike the test pattern packet distributed to various destinations as shown in FIG. 9. Therefore, the network load is greatly increased, and a bottleneck may occur. To solve this, a new response packet in which test results in each packet are accumulated is generated in a router on the response packet transmission path and forwarded. In addition, if the size of the NOC is large and the number of connected DUTs is large, the maximum length of the response packet is limited and the response packet that reaches the maximum length is transmitted to the neighboring router without any action. For reference, the payload information in the test response packet consists of the address of the DUT and the test result of the DUT as shown in [Table 3], and the test result information can be arbitrarily determined by the user.

As described above, although the present invention has been described by a limited number of embodiments and drawings, the present invention is not limited by this, and the technical idea of the present invention and the following will be described by those skilled in the art to which the present invention pertains. Of course, various modifications and variations are possible within the equivalent scope of the claims to be described.

10: semiconductor package test system
100: automatic test device (ATE)
200: interface board
200a: test head
200b: socket
210: test source provider
220: interconnect unit
230: test analysis unit
300: semiconductor package (DUT)
400: test handler
500: server

Claims (6)

Automatic Test Equipment (ATE);
A semiconductor package (Device Under Test: DUT) is received, and the received semiconductor package is electrically connected to the automatic test device (ATE), so that a test pattern signal generated from the automatic test device (ATE) is applied to the semiconductor package. Interface board to enable; And
A test handler for automatically supplying the semiconductor package (Device Under Test: DUT) to the automatic test device and transferring the semiconductor package according to the inspection result of the automatic test device
It includes,
The interface board is based on a network-on-chip (NOC) having a router and a network interface, and allows a plurality of semiconductor packages to be interconnected, and accumulates each test result in a router on a packet response transmission path of a network-on-chip. A semiconductor package test system suitable for parallel testing that solves bottlenecks by generating response packets and forwarding them. The method according to claim 1,
The interface board,
A test source providing unit for generating and providing test pattern data based on a signal transmitted from the automatic test device (ATE);
An interconnect unit for determining to which target semiconductor package the test pattern data generated and provided by the test source provider is transmitted; And
When the test pattern data is transmitted to the target semiconductor package determined by the interconnect unit, a test response unit that analyzes and responds to a test result of the target semiconductor package based on the transmitted test pattern data
Semiconductor package test system suitable for parallel testing, characterized in that it comprises a. The method according to claim 1,
The response packet that reaches the maximum length with a maximum length limit of the response packet is transmitted to a neighboring router without any action.
Semiconductor package test system suitable for parallel testing, characterized by. A test method using the semiconductor package test system of claim 1,
(a) generating test pattern data based on a signal input from an automatic test device (ATE);
(b) transferring the test pattern data generated in step (a) to a target semiconductor package;
(c) constructing a test result of the target semiconductor package delivered in step (b) in the form of a response packet; And
(d) generating and forwarding a new response packet that accumulates test results in each packet in a router on the transmission path of the response packet configured in step (c).
Test method using a semiconductor package test system suitable for parallel testing, including. The method according to claim 4,
Sending a response packet that has reached the maximum length to a neighboring router without a separate operation with a maximum length limit of the response packet
Test method using a semiconductor package test system suitable for parallel testing, characterized in that. The method according to claim 4,
Delivery of the test pattern data in step (b) is to be delivered by multicasting to a plurality of target semiconductor packages
Test method using a semiconductor package test system suitable for parallel testing, characterized in that.

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