KR102092670B1 - A pulse width control circuit device with the ripple free circuit - Google Patents

Abstract

The present invention relates to a pulse width modulation device with a ripple removing circuit. In particular, in a transmitter supporting constant envelope modulation, a device for pulse width modulation is configured by a digital circuit, such that a pulse width can be modulated by using two comparators, while hysteresis is applied to one comparator to remove ripple. To this end, the present invention comprises: a signal input unit in which a trigger signal is inputted; a sawtooth wave generating unit which outputs a sawtooth wave signal in accordance with the trigger signal; an inverter which receives the sawtooth wave signal to convert the same into a pulse signal of a square wave with duty, while converting the same into the pulse signal having two voltage levels by a predetermined threshold value; a low pass filter which receives the pulse signal to output a voltage proportional to a duty ratio of the pulse signal (referred as the duty ratio voltage hereinafter); and a feedback control unit which compares the duty ratio voltage to a reference voltage in order to output a bias voltage corresponding to the reference voltage, and applies the bias voltage to the voltage of the sawtooth wave signal for feedback. Therefore, according to the pulse width modulation device, the device for pulse width modulation is configured by the digital circuit in the transmitter supporting constant envelope modulation, such that a pulse width can be modulated by using the two comparators, while hysteresis is applied to one comparator to remove ripple.

Description

A pulse width control circuit device with the ripple free circuit}

In the present invention, a device for adjusting the pulse width in a transmitter supporting a constant envelope modulation is composed of a digital circuit, but the pulse width is adjusted by using two comparators, and hysteresis is given to one comparator to ripple. It relates to a pulse width adjustment device having a ripple elimination circuit to remove.

In general, a transmitter of a wireless communication system modulates and transmits a digital signal to a carrier wave in a constant envelope modulation method. For example, a binary frequency shift keying (BFSK) method for transmitting digital information through a discrete frequency change on a carrier, or a binary phase shift keying (BPSK) method for transmitting through a discrete phase change on a carrier is used. In such a system of constant envelope modulation, a pulse width adjustment device is used.

1 shows an analog type pulse width control device according to the prior art.

As shown in FIG. 1, the analog type pulse width control device 1 receives an AC input signal V _in and outputs a pulse signal, an inverter 2, and an LPF (low) outputting a duty ratio voltage of the pulse signal. It consists of a pass filter (3), a feedback control section (4) for outputting a bias signal as a feedback signal compared to the duty ratio voltage of the pulse signal.

That is, the inverter 2 is composed of a switching circuit, receives an AC (sinusoidal) signal, and outputs a pulse signal formed as a square wave.

Next, a low pass filter (LPF) 3 filters the output of the inverter 2 and outputs a voltage (or duty ratio output voltage) V _G proportional to the duty ratio of the PWM. That is, the duty ratio output voltage represents the magnitude of the duty ratio.

Next, the feedback control unit 4 compares the duty ratio output voltage V _G and the reference voltage V _D with a comparator, and outputs a feedback signal, that is, a bias signal. The reference voltage V _D is a voltage proportional to the desired duty ratio (D) for final output. In the comparator, connect the reference voltage V _D to the + terminal and the output voltage V _G to the-terminal. Therefore, when the duty ratio output voltage V _G is smaller than the reference voltage V _D , a bias signal is output to increase the duty ratio.

Therefore, by the feedback bias signal of the feedback control unit 4, the pulse width of the final output signal is adjusted by the duty ratio corresponding to the reference voltage.

However, since the analog type pulse width control device uses a comparator as an analog method, stability may be a problem. That is, the output may be unstable due to noise or external signals.

 M. Silva-Pereira and J. Caldinhas Vaz, "A Single-Ended Modified Class-E PA With HD2 Rejection for Low-Power RF Applications," in IEEE Solid-State Circuits Letters, vol. 1, no. 1, pp. 22-25, Jan. 2018.

An object of the present invention is to solve the problems as described above, the apparatus for adjusting the pulse width in a transmitter supporting a constant envelope (constant envelope) modulation is composed of a digital circuit, the pulse width using two comparators It is to provide a pulse width control device having a ripple elimination circuit that can remove ripples by adjusting and applying hysteresis to one comparator.

Particularly, an object of the present invention is to include a digital counter for counting its size to output a feedback bias voltage, but a comparator that counts up according to a comparison result with a reference voltage and a comparator that counts down. It is to provide a pulse width adjustment device having a ripple elimination circuit, configured to apply hysteresis to one of the two comparators and to hold the counter when the comparison signals of the two comparators are the same.

In order to achieve the above object, the present invention relates to a pulse width adjustment device having a ripple elimination circuit, a signal input unit to which a trigger signal is input; A sawtooth wave generator for outputting a sawtooth wave signal according to the trigger signal; An inverter which receives the sawtooth signal and converts it into a pulse signal of a square wave having a duty, and converts it into a pulse signal having two voltage levels by a predetermined threshold value; A low-pass filter that receives the pulse signal and outputs a voltage proportional to the duty ratio of the pulse signal (hereinafter, a duty ratio voltage); And a feedback control unit that compares the duty ratio voltage and the reference voltage, outputs a bias voltage corresponding to the reference voltage, and feedbacks the bias voltage by adding the bias voltage to the voltage of the sawtooth signal.

In addition, the present invention is a pulse width control device having a ripple elimination circuit, the saw-tooth wave generator supply power, a transistor for connecting or disconnecting the supply power to ground by the trigger signal, supplied from the supply power A first capacitor that charges and discharges a voltage to be formed, and is formed between the supply power and the first capacitor and is an output terminal connected to the inverter. When the transistor is grounded, the supply power and the first capacitor When the charged voltage is discharged through the ground, the voltage is not output to the output terminal, and when the transistor blocks the ground connection, the supply power is distributed to the first capacitor and the output terminal. .

In addition, the present invention, in the pulse width adjustment device having a ripple elimination circuit, the inverter outputs a higher voltage level of the two voltage levels when the voltage of the sawtooth signal is greater than the threshold value, 2 if the voltage is less than the threshold value It is characterized in that it outputs a lower voltage level among the voltage levels.

In addition, the present invention is characterized in that in the pulse width adjustment device having a ripple elimination circuit, the low-pass filter is composed of an RC circuit.

In addition, the present invention, in the pulse width adjustment device having a ripple cancellation circuit, the feedback control unit, a first comparator for outputting a count-up signal when the predetermined reference voltage is large compared to the TUBI voltage; A second comparator that outputs a countdown signal when the TBT ratio voltage is greater than the reference voltage; A counter that increases or decreases a counting value (hereinafter, bias size) by signals of the first comparator and the second comparator; And, it characterized in that it comprises a converter for converting the bias size of the counter to the bias voltage.

In addition, the present invention, in the pulse width adjustment device having a ripple cancellation circuit, the feedback control unit further comprises a logic gate for calculating whether the signals of the first comparator and the second comparator are equal, and the counter is the It is characterized in that the output of the logic gate is received as a lock signal of the counter, and the counting value is maintained in preference to the count up signal or the count down signal according to the lock signal.

In addition, the present invention is characterized in that a hysteresis is applied to one of the first comparator and the second comparator in a pulse width adjustment device having a ripple elimination circuit.

As described above, according to the pulse width adjustment device having a ripple elimination circuit according to the present invention, the pulse width is controlled by a digital signal by configuring the pulse width adjustment device as a digital circuit in a transmitter of constant envelope modulation. The effect of adjusting the adjustment more stably and accurately is obtained.

In addition, according to the pulse width adjustment device having a ripple elimination circuit according to the present invention, if a hysteresis is applied to one of the two comparators that compares the output voltage with the reference voltage and both output the same signal, a feedback control signal is generated. By maintaining it, an effect capable of removing ripples generated in a section corresponding to the variation range of hysteresis at the reference voltage is obtained.

1 is a block diagram of an analog-type pulse width control device according to the prior art.
2 is a block diagram of a pulse width adjustment device according to a first embodiment of the present invention.
3 is a configuration diagram of a feedback control unit of the pulse width adjustment device according to the first embodiment of the present invention.
Figure 4 is a signal graph in each section of the pulse width adjustment device according to the first embodiment of the present invention.
5 is a graph showing the ripple phenomenon of the duty ratio output voltage V _G according to the first embodiment of the present invention.
6 is a graph of a control signal input to the counter of the pulse width adjusting device according to the second embodiment of the present invention.
7 is a graph showing the duty ratio output voltage V _G of the pulse width adjusting device according to the second embodiment of the present invention.

Hereinafter, specific contents for carrying out the present invention will be described in accordance with the drawings.

In addition, in describing this invention, the same part is attached | subjected with the same code | symbol, and the repeated description is abbreviate | omitted.

First, the configuration of the pulse width adjusting device 100 according to the first embodiment of the present invention will be described with reference to FIG. 2.

As shown in Figure 2, the pulse width control device 100 according to an embodiment of the present invention is a signal input unit 10, a sawtooth wave generator for generating a sawtooth wave (sawtooth wave) signal, the trigger signal is input, The inverter 20 converts a sawtooth signal into a pulse signal, a low pass filter 40 that filters the output of the inverter 20 to output a duty ratio output voltage, and a feedback bias by comparing the duty ratio output voltage and a reference voltage It is composed of a feedback control unit 50 for outputting a voltage.

First, the signal input unit 10 receives an input signal that is a trigger signal. The input signal is received as a narrow peak pulse type signal. In particular, the input signal V _in is a binary signal and can be expressed as V _in = 1 and V _in = 0. That is, a value of 1 when it is a peak and a value of 0 when it is not a peak.

That is, the signal handled by the transmitter of the constant envelope modulation method is a square wave whose value is 0 or 1. In a typical transmitter, V _in converts a sinusoidal signal from a voltage-control oscillator (VCO) into a binary signal through an inverter. At this time, since the duty of the input signal that has passed through the inverter is not a desired value, it must be changed by adjusting the duty. For example, when the output of the VCO produces a binary signal through the inverter, if the duty (V _in ) is 40% or the required duty is 50%, the duty is adjusted by the pulse width controller and the desired duty is achieved. Output 50% of the adjusted duty (V _out ). This output (V _out ) is sent to the power amplifier (PA).

Next, the sawtooth wave generator 20 is configured to output a sawtooth wave signal according to an input signal (or trigger signal).

That is, the sawtooth wave generator 20 is a supply power supply (V _S ) for supplying power, a transistor (T _S ) serving as a switch, and a first capacitor for charging and discharging the voltage supplied from the supply power (V _S ) ( C ₁ ), and an output terminal V _X connected to the inverter 30.

First, the transistor T _S is connected to the supply power V _S to the collector C, the emitter E is grounded, and the input signal V _in is connected to the base B. Therefore, the transistor T _S serves as a switch that shorts the ground according to the input signal V _in .

Further, the first capacitor (C ₁₎ is connected in series with the supply voltage (V _S), the opposite side is grounded. In addition, the first capacitor C ₁ and the transistor T _S are connected in parallel to the supply power V _S.

Terminal of the output voltage (V _x) of the sawtooth signal is formed between the supply voltage (V _S) and the first capacitor (C _1). That is, the terminal and the first capacitor (C ₁₎ of the output voltage (V _x), is connected in parallel with respect to the supply voltage (V _S).

Therefore, when the input signal is V _in = 1, the transistor T _S is turned on and grounded. Therefore, the supply power V _S is grounded, and the first capacitor C ₁ is also grounded and discharged. Therefore, the output voltage V _x of the sawtooth generator 20 becomes a ground voltage.

In addition, when the input signal is V _in = 0, the transistor T _S is turned off, and the supply power V _S is supplied to the terminal of the first capacitor C ₁ and the output voltage V _x . . At this time, since a part of the supply power V _S is charged in the first capacitor C ₁ , the output voltage V _x increases linearly. That is, the output voltage V _x forms a sawtooth wave signal.

The output voltage V _x which is a sawtooth signal is supplied to the input voltage of the inverter 30.

Meanwhile, the second capacitor C ₂ serves to separate the DC bias of the V _x node and the V _y node. That is, the voltage at the V _y node is the sum of the sawtooth wave and the DC bias from the control block. When the DC bias generated in the control block changes, the duty of the output changes.

Next, the inverter 30 receives a sawtooth wave signal and converts it into a square wave pulse signal. That is, the inverter 30 converts the sawtooth signal into a square-wave pulse signal having two voltage levels using a predetermined threshold voltage or threshold.

In particular, the inverter 30, if the output (voltage of the higher of the two voltage levels level) voltages if the received input voltage threshold voltage (V _TH) above a certain size, and is lower than the threshold value or the threshold voltage (V _TH) Outputs 0 (the voltage of the lower one of the two voltage levels), and outputs a pulse signal (or pulse output signal) V _out having a duty D.

Next, a low pass filter (LPF) 40 filters the output of the inverter 20 to output a duty ratio output voltage (or a voltage of an effective value of a pulse signal). That is, a voltage (or duty ratio output voltage) V _G proportional to the duty ratio of the PWM of the pulse output signal is output. That is, the duty ratio output voltage represents the magnitude of the duty ratio.

Preferably, the low-pass filter 40 is composed of a filter by an RC circuit.

Next, the feedback control unit 50 compares the duty ratio output voltage V _G and the reference voltage V _REF to output the feedback bias voltage V _B. The feedback voltage V _Y is input to the inverter 30 by the feedback bias voltage V _B.

As shown in FIG. 3, the feedback control unit 50 includes a first comparator 51 outputting a count up signal, a second comparator 52 outputting a count down signal, and first and second outputs. Logic gate 53 for determining whether output signals of comparators 51 and 52 are equal, counter 54 for counting bias magnitude, and voltage digital-to-analog converter for converting counting values to bias voltage V _B It consists of (55).

First, in the first comparator 51, a reference voltage V _REF is input to the + terminal and a duty ratio output voltage V _G is input to the-terminal. That is, the first comparator 51 outputs 1 when the reference voltage V _REF is greater than the duty ratio output voltage V _G , and otherwise outputs 0. The output signal of the first comparator 51 is input as a count up signal of the counter 54, and if the count up signal is 1, the counting of the counter 54 is increased.

Next, in the second comparator 52, the duty ratio output voltage V _G is input to the + terminal, and the reference voltage V _REF is input to the-terminal. That is, the second comparator 52 inputs two input signals as opposed to the first comparator 51. Therefore, the second comparator 52 outputs 1 when the duty ratio output voltage V _G is greater than the reference voltage V _REF and 0 otherwise. The output signal of the second comparator 52 is input to the countdown (DN) signal of the counter 54, and if the countdown signal is 1, the counting of the counter 54 is reduced.

Next, the logic gate 53 receives the output signals of the first and second comparators 51 and 52 and determines whether the output signals are the same. Preferably, the XOR operation is performed as an XOR operation logic gate. That is, if the output signals of the first and second comparators 51 and 52 are the same, 0 is output, and if it is different, 1 is output. The output signal of the XOR gate 53 is input as a lock signal of the counter 54. In particular, a lock signal is generated so that the counting is maintained when the two output signals are the same.

On the other hand, the counter 54 increments the counting value (or bias magnitude) one by one by the count up signal and decrements the counting value by one signal by the count down signal. In addition, when a lock signal is input, the input of the count up signal or the count down signal is ignored and the current counting value is maintained.

Next, the voltage digital-analog converter (VDAC) 55 receives a counting value (or bias magnitude) and converts it into a bias voltage V _B corresponding to the received bias magnitude.

When N-bit VDAC is used, the output bias voltage (V _B ) is as follows.

[Equation 1]

Here, V _S is a supply voltage, and n is a counting value (or bias magnitude).

The feedback control unit 50 outputs the bias voltage V _B corresponding to the reference voltage V _REF by the above configuration.

When the duty ratio output voltage V _G is smaller than the reference voltage V _REF , the counting-up signal of the first comparator 51 outputs 1, so the counter 54 continues to increase the counting value (or bias magnitude) one by one. Order. When the counting value (bias size) increases, the bias voltage V _B increases. Since the feedback voltage V _Y is biased by the bias voltage V _B from the original voltage V _x , it also increases. When the feedback voltage V _Y increases, the duty ratio output voltage V _G also increases.

By repeating this feedback process, the duty ratio output voltage V _G continuously increases until the duty ratio output voltage V _G is greater than the reference voltage V _REF . That is, this feedback process is repeated until the duty ratio output voltage V _G is greater than the reference voltage V _REF .

In addition, on the contrary, when the duty ratio output voltage V _G is greater than the reference voltage V _REF , the counting down signal of the second comparator 52 outputs 1, so the counter 54 sets the counting value (or bias magnitude). Keep decreasing by one. When the counting value (bias size) decreases, the bias voltage V _B decreases and the feedback voltage V _Y also decreases. When the feedback voltage V _Y decreases, the duty ratio output voltage V _G also decreases.

In this repeat the feedback process, until the duty ratio of the output voltage (V _G) is lower than the reference voltage (V _REF), and the duty ratio output voltage (V _G) is continuously reduced. That is, this feedback process is repeated until the duty ratio output voltage V _G is smaller than the reference voltage V _REF .

That is, when the effective voltage of the pulse signal corresponding to the target duty ratio is set to the reference voltage V _{REF for the} target pulse width (or duty ratio), the target pulse signal can be obtained.

Next, the operation of the pulse width adjusting device 100 according to the first embodiment of the present invention will be described in more detail with reference to FIG. 4.

4A or 4B, first, the input signal V _in is input as a narrow peak pulse. In particular, the peak pulse is input to the input signal V _in at a constant period T _s .

Next, when the input signal V _in is input, the sawtooth wave signal V _x is output by the sawtooth generator 30.

That is, when the input signal V _in is 1, the transistor T _S is turned on, the supply power V _S is grounded, and the first capacitor C ₁ is also grounded to discharge. Therefore, the output voltage V _x of the sawtooth generator 20, that is, the sawtooth signal V _x is output to the ground voltage 0.

Then, when the input signal V _in is 0, the transistor T _S is turned off, and the supply power V _S is supplied to the terminal of the first capacitor C ₁ and the output voltage V _x . As a result, the output voltage V _x increases linearly. That is, the output voltage V _x forms a sawtooth wave signal. The output voltage V _x is input to the inverter 30.

Next, the feedback voltage (V _Y) is feedback control bias by (50) (bias) is added to the voltage (V _B), as the bias (bias original voltage (V _x) bias (bias) voltage (V _B) from )do.

Therefore, as shown in FIG. 4A or 4B, the feedback voltage V _Y is biased by a bias voltage V _B compared to the original voltage V _x . Therefore, the feedback voltage V _Y also forms a sawtooth wave signal.

Next, the output voltage V _out of the inverter 30 is output as a pulse signal having a duty D by the threshold voltage V _TH of the inverter 30. That is, if the feedback voltage V _Y is less than the threshold voltage V _TH , it is output as 0, and if the feedback voltage V _Y is greater than or equal to the threshold voltage V _TH , it is output as a voltage having a constant magnitude.

The bias voltage V _B of FIG. 4A is relatively high, and the bias voltage V _B of FIG. 4B is relatively low. As a result, it can be seen that the duty ratio (pulse width) of FIG. 4A is high and the duty ratio (pulse width) of FIG. 4B is low. That is, the pulse width (or duty ratio) of the final output signal is determined proportionally by the bias voltage V _B.

Next, a ripple phenomenon generated in the pulse width adjusting device 100 according to the first embodiment of the present invention will be described with reference to FIG. 5.

As shown in Figure 5, the duty ratio of the output voltage (V _G) is increased while continuously to the reference voltage (V _REF), the ripple in the voltage reference (V _REF) portion is generated. That is, in the vicinity of the reference voltage (V _REF), the duty ratio output voltage (V _G), the duty ratio of the output voltage (V _G) by the increase in the counter 54 or decreased with little change, and the bias voltage (V _B) is Will fluctuate. Since it is very rare that the duty ratio output voltage V _G and the reference voltage V _REF are completely the same, the feedback control unit 50 continuously decreases and increases the bias voltage V _B.

Next, the configuration of the pulse width adjusting device 100 according to the second embodiment of the present invention will be described with reference to FIGS. 6 and 7.

The second embodiment of the present invention is the same as the configuration of the first embodiment described above, but there is a difference only in the configuration in which hysteresis is applied to one of the first and second comparators 51 and 52. That is, one of the first and second comparators 51 and 52 is used as a comparator having hysteresis.

Therefore, the configuration of the second embodiment not described below refers to the configuration of the first embodiment described above.

In addition, hereinafter, for convenience of description, it will be described as an embodiment in which hysteresis is applied to the first comparator 51. However, hysteresis may be applied to the second comparator 52.

6 is a graph showing a control signal input to the counter 64 according to the difference between the reference voltage V _REF and the duty ratio output voltage V _G. That is, FIG. 6 (a) is a graph showing the count up signal of the first comparator 51, and FIG. 6 (b) is a graph showing the count down (DN) signal of the second comparator 52. 6 (c) is a graph showing a lock signal.

That is, as shown in FIG. 6 (a), since the hysteresis is applied to the first comparator 51, the duty ratio output voltage V _G decreases (ie, the reference voltage V _REF and the duty ratio output). When the difference between the voltages V _G increases, the count up signal is not generated even if the duty ratio output voltage V _G is smaller than the reference voltage V _REF . The red graph section in FIG. 6 (a) corresponds to this.

In addition, when the duty ratio output voltage V _G increases, the count up signal is continuously generated even if the duty ratio output voltage V _G is greater than the reference voltage V _REF . The blue graph section of FIG. 6 (b) corresponds to this.

And, as shown in FIG. 6 (b), since the second comparator 52 does not apply hysteresis, down (DN) is centered around a portion where the reference voltage (V _REF ) and the duty ratio output voltage (V _G ) coincide. ) 0 or 1 signal is clearly divided and output.

However, since the lock signal Lock input to the counter 54 is a signal determined by whether the first and second comparators 51 and 52 are the same, the signal is output only in the hysteresis section of the first comparator 51 ( That is, the signal 1 value is output). Therefore, in the hysteresis section, a lock signal is output, and the counting value of the counter 54 is maintained, so that the bias voltage V _B is maintained at a constant level. Therefore, the duty ratio output voltage V _G is also kept constant.

The duty ratio output voltage V _G at this time is illustrated in FIG. 7. That is, when the duty ratio output voltage V _G increases, the duty ratio output voltage V _G is maintained at a constant voltage in a section higher than the reference voltage V _REF . In addition, when the duty ratio output voltage V _G decreases, the duty ratio output voltage V _G is maintained at a constant voltage in a section lower than the reference voltage V _REF .

Above, although the invention made by the present inventors has been specifically described according to the above-described embodiments, the present invention is not limited to the above-described embodiments, and can be variously changed without departing from the gist thereof.

This patent was carried out with the support of the Civil Forces Technology Cooperation Project “UM17302RD3 ('17 .6.21)”, “Development of ultra-low-power long-distance communication for radio monitoring devices and radio” chips.

10: signal input unit 20: saw wave generator
30: inverter 40: low-pass filter
50: feedback control unit 51: first comparator
52: second comparator 53: logic gate
54: counter 55: converter

Claims (7)

In the pulse width adjustment device having a ripple removal circuit,
A signal input unit to which a trigger signal is input;
A sawtooth wave generator for outputting a sawtooth wave signal according to the trigger signal;
An inverter which receives the sawtooth signal and converts it into a pulse signal of a square wave having a duty, and converts it into a pulse signal having two voltage levels by a predetermined threshold value;
A low pass filter that receives the pulse signal and outputs a voltage proportional to the duty ratio of the pulse signal (hereinafter, a duty ratio voltage); And,
And a feedback control unit that compares the duty ratio voltage and a reference voltage, outputs a bias voltage corresponding to the reference voltage, and adds the bias voltage to the voltage of the sawtooth signal to feed back the feedback voltage.
The feedback control unit,
A first comparator for outputting a count-up signal when a predetermined reference voltage is greater than the duty ratio voltage;
A second comparator that outputs a countdown signal when the duty ratio voltage is large compared to the reference voltage;
A logic gate calculating whether the signals of the first comparator and the second comparator are identical;
A counter that increases or decreases a counting value (hereinafter, bias size) by signals of the first comparator and the second comparator; And,
And a converter for converting the bias size of the counter to a bias voltage,
The counter receives the output of the logic gate as a lock signal of the counter, maintains the counting value in preference to the count up signal or the count down signal according to the lock signal,
A pulse width adjusting device having a ripple elimination circuit, characterized in that hysteresis is applied to one of the first comparator and the second comparator.
According to claim 1,
The saw wave generator includes a supply power supplying power, a transistor connecting or blocking the supply power to ground by the trigger signal, a first capacitor charging and discharging a voltage supplied from the supply power, the supply power and the It is formed between the first capacitor and is composed of an output terminal connected to the inverter,
When the transistor is grounded, the voltage supplied to the supply power and the first capacitor is discharged through ground, so that no voltage is output to the output terminal.
When the transistor blocks the ground connection, the pulse width control device having a ripple elimination circuit, characterized in that the voltage is distributed to the supply voltage of the first capacitor and the output terminal.
According to claim 1,
The inverter outputs a high voltage level of two voltage levels when the voltage of the sawtooth signal is greater than the threshold value, and a low voltage level of the two voltage levels when the voltage of the sawtooth signal is less than the threshold value. Pulse width adjustment device with.
According to claim 1,
The low-pass filter is a pulse width control device having a ripple elimination circuit, characterized in that consisting of an RC circuit.
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