KR102090185B1 - Apparatus and Method for optimizing phase noise - Google Patents

Abstract

The present invention relates to a digital phase locked loop (PLL) technology, and more particularly, to an apparatus and method for maintaining phase noise optimization against environmental changes by setting a loop filter of a phase locked loop (PLL) to a variable type.
According to the present invention, by configuring a loop filter of a phase locked loop (PLL) to be variable, reception sensitivity and angular resolution are improved when radar is applied by optimizing phase noise characteristics.

Description

Apparatus and method for optimizing phase noise

The present invention relates to a digital phase locked loop (PLL) technology, and more particularly, to an apparatus and method for maintaining phase noise optimization against environmental changes by setting a loop filter of a phase locked loop (PLL) to a variable type.

In particular, the present invention provides a phase noise optimization device and method for varying the phase frequency detector (PFF) gain and the loop filter bandwidth in a direction that reduces phase error between two signals (reference signal / feedback signal) to minimize output signal jitter. It is about.

1 is a diagram showing the configuration of a typical digital PLL. Referring to Figure 1, the digital phase locked loop (PLL) is an adaptive phase frequency detector (PFD) 110, an adaptive loop filter 120, an iDAC (current digital-to-analog converter) 130, and an ICO (current controlled) Oscillator) 140 and the divider 150.

The adaptive PFD 110 receives a reference signal and a feedback signal, determines a phase error between the two signals, and provides a PFD value during each phase comparison period. The PFD is sized to achieve fast frequency acquisition and reduced jitter (phase shake).

In addition, the criterion for optimization is the reference clock of the adaptive PFD 110 and the degree of phase error of the feedback signal. Therefore, the PFD 110 adjusts the output current magnitude of the PFD and the band of the adaptive loop filter to minimize the phase error in time.

Each time a PFD value is received, it updates its output, widening the PLL loop bandwidth if a large error value is detected, and narrowing the loop bandwidth when a small average phase error is detected. IDAC 130, which can be implemented through both a regulated current source and a single-ended current source, converts the loop filter output to analog current.

The ICO 140 provides an oscillator signal with a phase determined by the iDAC output. Divides the divider signal by factor N and provides a feedback signal. Since the digital PLL shown in FIG. 1 is described in Korean Patent No. 10-1040915, further description will be omitted.

However, in the case of such a PLL configuration, a variable element (PFD / loop filter) is set to minimize the output signal jitter regardless of the system bandwidth, so there is a problem that jitter is not optimized in an actual application system.

In addition, in the case of rapidly sweeping a frequency with time, such as a frequency modulated continous wave (FMCW) radar, loop bandwidth adjustment through phase error cannot have sufficient time, so there is a problem in that it is difficult to optimize phase noise in practice.

Incidentally, RMS jitter due to phase locked loop (PLL) phase noise is an important factor in determining the signal-to-noise ratio in a radar system, and is an important factor in determining the angular resolution and the maximum detection distance.

The phase noise of the PLL is created by adding or subtracting various noise elements constituting it in the sub-feedback structure, and the main factor determining the phase noise is the bandwidth of the loop. Even if the bandwidth of the loop filter is adjusted so that the phase noise is minimized at room temperature, the phase noise is changed by changing the entire loop bandwidth, especially when the characteristic value of the voltage controlled oscillator (VCO) changes with temperature.

As described above, in general, an adaptive structure in which the bandwidth of the loop filter is varied so that the phase noise maintains an optimization even for such an environmental change has been proposed.

In such an adaptive structure, a criterion for optimizing phase noise is a phase error of a phase frequency detector (PFD), and the bandwidth of the loop filter is variable to minimize this. However, considering the phase noise effect of each component constituting the PLL, this method could not be an optimization criterion in a real system.

In addition, previously known methods cannot be used in an FMCW structure in which a frequency such as a vehicle radar changes rapidly with time. This is because the phase error of the PFD continuously changes for each change step when the frequency changes rapidly with time.

1. Korean Registered Patent No. 10-1040915 2. Korean Patent Publication No. 10-2013-0079868 3. Korean Registered Patent No. 10-1298621

The present invention is proposed to solve the problems according to the above background, and provides a phase noise optimization apparatus and method for maintaining phase noise optimization against environmental changes by setting a PLL (Phase Locked Loop) loop filter as a variable type. There is a purpose.

In addition, another object of the present invention is to provide an apparatus and method for optimizing phase noise so that a criterion for optimizing phase noise is not a phase error caused by PFD but a self-generated bit mean RMS (Root Mean Square) Jitter. have.

In addition, another object of the present invention is to provide an apparatus and method for phasing noise optimization capable of optimizing and correcting real-time phase noise even in a frequency modulated continous wave (FMCW) radar using such a structure.

In addition, the present invention can receive a phase error as much as a band through a band limitation of a self-generated bit frequency signal, and thus a phase noise optimization device capable of optimizing phase noise at an applied system bandwidth that was not possible with known technologies. Another purpose is to provide a method.

The present invention provides a phase noise optimization device that maintains a phase noise optimization for environmental changes by placing a PLL (Phase Locked Loop) loop filter in a variable form to achieve the above-described problems.

The phase noise optimization device,

A voltage-controlled oscillator outputting an output frequency corresponding to the input voltage;

A power divider for allocating output power for feedback loop control for generating chirp signals or for generating bit frequency signals;

A first coupler for connecting the output power amount for generating a chirp signal or a bit frequency signal;

A frequency divider that divides the output frequency to generate a chirp signal and generates a feedback signal frequency;

A phase detector generating a charge corresponding to a phase difference between the feedback frequency of the feedback signal and the reference clock frequency;

A loop filter that converts the charge into an input voltage according to the bandwidth;

A second coupler that distributes the output power amount to generate a modulated or demodulated signal for bit frequency signal generation;

A first mixer that generates a modulated signal from the chirp signal using frequency upconversion;

A second mixer that demodulates the modulated signal to generate a bit frequency;

And a microcontrolled unit (MCU) that adjusts the bandwidth of the loop filter by comparing the phase error magnitude of the generated bit frequency with a preset initial value.

In addition, a first reference frequency oscillator providing a reference frequency for the frequency up-conversion to the second mixer; And a second reference frequency oscillator providing the reference clock frequency to the phase detector.

In addition, the chirp signal is generated using an initial information value of a preset chirp signal, and the initial information value includes at least one of a frequency bandwidth, a frequency deviation, a dwell time, and a number of frequency steps. It may be characterized by including.

In addition, LPF (Low Pass Filter) for limiting the size of the phase error through band limitation; And an analog-to-digital converter (ADC) that converts a bit frequency from an analog signal to a digital signal and provides it to the MCU.

In addition, the phase error magnitude is a Root Means Square (RMS) jitter size, and the MCU may be characterized by calculating a Root Means Square (RMS) jitter through a voltage peak point at a bit frequency.

In addition, the LPF has a pass band corresponding to the bandwidth of a radar system, the pass band is changed according to the size of the phase error, and the radar system may be characterized by a FMCW (Frequency Modulated Continous Wave) radar system.

In addition, the path of generating the chirp signal may be characterized in that a voltage-controlled oscillator, a first coupler, a frequency divider, a phase detector, and a loop filter are in this order.

In addition, the generation path of the bit frequency signal is composed of a signal modulation path and a signal demodulation path, and the signal modulation path includes: a first path of a second reference frequency oscillator, a voltage controlled oscillator, a power divider, a first coupler, and 2 is a path combining the second path of the coupler, the signal demodulation path is a voltage control oscillator, a power divider, a first coupler, the second path of the second coupler and the third path of the first mixer can do.

In addition, the bandwidth of the loop filter may be increased when the linearity is improved compared to the set initial value, and the bandwidth of the loop filter may be decreased when the bandwidth is reversed.

On the other hand, another embodiment of the present invention, setting the initial value of the loop filter using the initial information value of the chirp signal from a microcontrol unit (MCU); Generating a chirp signal according to the set initial value; Generating a bit frequency signal using the chirp signal; Collecting the bit frequency signal generated by the MCU; Calculating a phase error magnitude from the generated bit frequency; And comparing the calculated phase error magnitude with a preset initial value to adjust the bandwidth of the loop filter.

According to the present invention, by configuring a loop filter of a phase locked loop (PLL) to be variable, reception sensitivity and angular resolution are improved when radar is applied by optimizing phase noise characteristics.

In addition, another effect of the present invention is that the determination criterion for optimizing the phase noise is not the phase error caused by the PFD, but the size of the RMS jitter of the bit frequency generated by itself. Can be lifted.

In addition, another effect of the present invention is that it is possible to optimize phase noise during operation in a vehicle radar system having a frequency modulated continous wave (FMCW) modulation method.

1 is a view showing the configuration of a typical digital phase-sync loop.
2 is a block diagram illustrating a concept of a phase locked loop (PLL).
FIG. 3 is a diagram showing a linear model of the PLL shown in FIG. 2.
4 is a diagram for explaining the concept of a PLL in which a noise source is considered.
5 is a graph for explaining the concept of PLL phase noise characteristics.
6 is a block diagram of a phase noise optimization apparatus 600 according to an embodiment of the present invention.
7 shows a bit frequency signal after the second blender 611 shown in FIG. 6 and is a graph showing the principle of generating the bit frequency.
8 shows a bit frequency signal after passing through the LPF 612 shown in FIG. 6, and is a graph showing the phase error of the bit frequency.
FIG. 9 is a graph showing phase noise on a frequency according to a bandwidth change by the LPF 612 shown in FIG. 6.
10 is a graph showing a chirp profile and a synchronization signal according to an embodiment of the present invention.
FIG. 11 is a diagram showing a path of generating a chirp signal in the configuration block diagram illustrated in FIG. 6.
FIG. 12 is a diagram showing a generation path of a bit frequency signal in the configuration block diagram illustrated in FIG. 6.
13 is a flowchart illustrating a phase noise optimization process according to an embodiment of the present invention.

The present invention can be applied to various changes and can have various embodiments, and specific embodiments will be illustrated in the drawings and described in detail in the detailed description. However, this is not intended to limit the present invention to a specific embodiment, it should be understood to include all modifications, equivalents, and substitutes included in the spirit and scope of the present invention.

In describing each drawing, similar reference numerals are used for similar components.

Terms such as first and second may be used to describe various components, but the components should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from other components.

For example, the first component may be referred to as a second component without departing from the scope of the present invention, and similarly, the second component may be referred to as a first component. The term “and / or” includes a combination of a plurality of related described items or any one of a plurality of related described items.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by a person skilled in the art to which the present invention pertains.

Terms such as those defined in a commonly used dictionary should be interpreted as having meanings consistent with meanings in the context of related technologies, and should not be interpreted as ideal or excessively formal meanings unless explicitly defined in the present application. Should not.

Hereinafter, an apparatus and method for optimizing phase noise according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram illustrating a concept of a phase locked loop (PLL). Referring to FIG. 2, the PLL takes a reference clock as an input and generates an output clock having an N times frequency of the reference clock as an output. To this end, the PLL 200 is composed of a phase frequency detector (PFF) 210, a charge pump 220, a loop filter 230, a voltage controlled oscillator (VCO) 240, and a frequency divider 250. .

2, the PFD 210 first generates an Up / Down pulse by comparing the phase and frequency differences between the reference clock and the divided VCO output clock. Then, the charge pump 220 and the loop filter 230 convert the discrete Up / Down pulse into an analog voltage capable of controlling the VCO, so that the VCO output frequency is finally controlled to be N times the reference clock frequency. .

In order to briefly indicate the PLL block, the charge pump 220 is usually indicated together with a phase frequency detector (PFF), and FIG. 3 shows a linear model of the PLL.

Where Kd is the gain of the phase comparator, F (s) is the transfer function of the loop filter, and Kvco is the gain of the VCO. Since the output frequency variation of the VCO is expressed by Equation 1 and Equation 2, the VCO can be expressed by an integrator.

In addition, the transfer function of the PLL linear model is expressed as Equation 3 below.

Since Kd and Ko are constants, the order of the total transfer function is determined by the order of F (s). It can be seen that when the coefficient is changed due to environmental changes, the transmission characteristics may be changed, and even if some of the coefficients are changed, the entire transmission characteristics are maintained through variable of some coefficients.

FIG. 4 shows noise elements of components constituting the PLL shown in FIG. 3. Several noise factors contribute to the phase noise, but noise other than the reference clock noise, VCO noise, PDF noise, and frequency divider have no significant effect.

Figure 4 shows the overall phase noise characteristics of the four elements mentioned above. The total phase noise appears as the sum of each noise considering the transmission characteristics due to the negative feedback.

In the sub-feedback structure, VCO noise based on the loop bandwidth is attenuated in-band noise signal due to the high-pass transmission characteristics in the loop, and noise due to PFD and frequency divider is out-of-band noise signal due to the low-pass transmission characteristics in the loop. It is attenuated. Accordingly, when the attenuation characteristics due to the feedback response characteristics of each noise element are reflected, the total phase noise appears as the total phase noise of FIG. 5.

5 is a graph for explaining the concept of PLL phase noise characteristics. Referring to FIG. 5, since the total phase noise characteristic is changed according to the loop bandwidth, the loop bandwidth should be adjusted to follow the good noise characteristic of each component.

That is, when comparing VCO noise, PFD noise, and frequency divider noise, extending the loop band to a frequency band in which the PFD and frequency divider noise is smaller than the VCO noise is advantageous in reducing the overall phase noise. The phase noise measurement methods include a spot phase noise measurement method that measures the amount of power energy for each offset frequency at the original frequency, and a RMS (Root Means Square) Jitter measurement method that measures the degree of phase fluctuation in time.

6 is a block diagram of a phase noise optimization apparatus 600 according to an embodiment of the present invention. Referring to FIG. 6, in the case of the invention described in the background art, the degree of optimization is determined through the phase error of the PFD. Judge. That is, the magnitude of the phase error is determined by calculating the RMS jitter through the data collected by the MCU 614 through the ADC 613.

To this end, the phase noise optimization device 600, the voltage control oscillator 601 for outputting an output frequency corresponding to the input voltage, feedback loop control for generating a chirp signal or for distributing the output power for generating a bit frequency signal Power divider 602, a first coupler 603 connecting the output power amount to generate a chirp signal or a bit frequency signal, a frequency divider 604 to divide the output frequency to generate a chirp signal and generate a feedback signal frequency , Phase detector 605 for generating charge corresponding to the phase difference between the feedback frequency of the feedback signal and the reference clock frequency, loop filter 606 for converting charge into an input voltage according to the bandwidth, modulation or demodulation for generating a bit frequency signal A second coupler 608 that distributes the output power amount to generate a signal, a modulated signal from a chirp signal using frequency upconversion A first mixer 609 to generate, a second mixer 611 to demodulate the modulated signal to generate a bit frequency, and compare the phase error magnitude of the generated bit frequency with a preset initial value to adjust the bandwidth of the loop filter It comprises a MCU (Micro Controlled Unit) 614 and the like.

Further, a first reference frequency oscillator 610 that provides a reference frequency for the frequency up-conversion to the second mixer 609, a second reference frequency oscillator that provides the reference clock frequency to the phase detector 605, and the like. This is included.

In addition, a low-pass filter (LPF) 612 that limits the magnitude of the phase error through band limitation, and an analog-to-digital converter (ADC) 614 that converts a bit frequency from an analog signal to a digital signal and provides it to the MCU. ) And the like are further included.

7 shows a bit frequency signal after the second blender 611 shown in FIG. 6 and is a graph showing the principle of generating the bit frequency. Referring to FIG. 7, since the time delay between the two inputs in the second mixer 611 is very small, the phase error due to chirp nonlinearity is ignored and only the phase error due to phase noise is reflected.

8 shows a bit frequency signal after passing through the LPF 612 shown in FIG. 6, and is a graph showing the phase error of the bit frequency. Referring to FIG. 8, LPF 612 has a pass band corresponding to a bandwidth of a radar system, and a phase error varies according to the bandwidth. The MCU 614 calculates the RMS jitter through the voltage peak point from the data collected through the ADC 613.

FIG. 9 is a graph showing phase noise on a frequency according to a bandwidth change by the LPF 612 shown in FIG. 6. The technology described in the background technology has a disadvantage that it cannot be applied to a FMCW (Frequency Modulated Continous Wave) structure in which the frequency continuously changes with time, such as a vehicle radar. However, since the present invention generates a bit frequency signal by itself using the FMCW signal, it is possible to always compensate for phase noise optimization during operation.

In addition, in the technique described in the background art, jitter optimization is implemented regardless of system bandwidth. That is, it is determined as the bandwidth 910 that can optimize the jitter size by minimizing the phase error of the PLL regardless of the bandwidth of the applied system.

If the system bandwidth is 10 kHz, noise after 10 kHz is independent of the system signal to noise power ratio (SNR) performance. Therefore, when adjusted with the bandwidth 920 shown in FIG. 9, the jitter size in the application system can be further improved. In the present invention, the LPF 612 performs such a band limiting role to optimize the phase noise characteristics in the applied system.

10 is a graph showing a chirp profile and a synchronization signal according to an embodiment of the present invention. Referring to FIG. 10, an initial information value for a chirp signal is determined in a radar system. The initial information value of the chirp signal may include frequency bandwidth, frequency deviation, dwell time, and number of frequency steps.

In particular, when the information (frequency bandwidth, frequency deviation, dwell time, frequency step number) of the chirp signal in the radar system is determined as shown in FIG. 10, the loop filter 606 generates a chirp signal with an initial value.

This Chirp signal generation is performed by a control command that the MCU 610 gives an initial value to the loop filter 606, and some Chirp signals generated simultaneously with signal generation are up-frequency modulated by the second reference frequency oscillator 610 frequency. The second mixer 611 demodulates the bit frequency again.

The demodulated signal always maintains a constant frequency when the phase noise is good, but otherwise, a frequency fluctuation occurs, causing an RMS jitter on the time axis.

FIG. 11 is a diagram showing a path of generating a chirp signal in the configuration block diagram illustrated in FIG. 6. Referring to FIG. 11, the chirp signal generation path is in the order of the voltage controlled oscillator 601, the first coupler 603, the frequency divider 604, the phase detector 605, and the loop filter 606.

FIG. 12 is a diagram showing a generation path of a bit frequency signal in the configuration block diagram illustrated in FIG. 6. Referring to FIG. 12, the bit frequency signal generation path is composed of a signal modulation path and a signal demodulation path by the first mixer 609 and the second mixer 611.

The signal modulation path is composed of the LO2 path and the IF path based on the first mixer 609. These routes are:

i) LO2 path: second reference frequency oscillator

ii) IF path: voltage controlled oscillator 601, power divider 602, first coupler 603, second coupler 608

The signal demodulation path is composed of an LO2 path and an RF path based on the second mixer 611. These routes are:

i) LO1 path: voltage controlled oscillator 601, power divider 602, first coupler 603, second coupler 608

ii) RF path: first blender 609

The modulated bit frequency has a phase error as much as the system band through LPF 612, and the bit frequency is collected by voltage over time through ADC 613.

The MCU 614 measures the size of the RMS jitter through the voltage peak generation time from the collected data. The MCU 614 adjusts the loop response time by increasing the bandwidth of the loop filter 606 and measures the size of the RMS jitter of the bit frequency under the changed condition and compares it with the initial value.

When the linearity compared to the initial value is improved, it is controlled in the direction of increasing the bandwidth of the loop filter 606, and in the opposite case, it is controlled in the direction of reducing the loop bandwidth. These loops are repeated indefinitely to keep phase noise optimal during operation.

13 is a flowchart illustrating a phase noise optimization process according to an embodiment of the present invention. Referring to FIG. 13, when the MCU 614 provides an initial value for the loop filter 606, a chirp signal is generated according to the initial value setting, and a bit frequency signal is generated using a portion of the chirp signal. (Steps S1300, S1310).

The modulated bit frequency has a phase error as much as the system band through the LPF 612, and the bit frequency is collected through the ADC 613 as a voltage over time (step S1320).

The MCU 614 measures the size of the RMS jitter through the voltage peak generation time from the collected data. The MCU 614 adjusts the loop response time by increasing the bandwidth of the loop filter 606 and measures the size of the RMS jitter of the bit frequency under the changed condition and compares it with the initial value.

When the linearity compared to the initial value is improved, it is controlled in the direction of increasing the bandwidth of the loop filter 606, and in the opposite case, it is controlled in the direction of reducing the loop bandwidth (steps S1330 to S1380). These loops are repeated indefinitely to keep phase noise optimal during operation.

110: adaptive phase frequency detector (PFF) 120: adaptive loop filter
130: iDAC (current Digital-to-Analog)
140: ICO (current controlled oscilator) 150: divider
601: voltage controlled oscillator 602: power divider
603: first coupler 604: frequency divider
605: phase detector 606: loop filter
608: second coupler 609: first blender
610: second reference frequency oscillator 611: second mixer
612: LPF (Low Pass Filter)
613: Analog-to-Digital Converter (ADC)
614: Micro Control Unit (MCU)

Claims (13)

A voltage-controlled oscillator outputting an output frequency corresponding to the input voltage;
A power divider for allocating output power for feedback loop control for generating chirp signals or for generating bit frequency signals;
A first coupler for connecting the output power amount to generate a chirp signal or a bit frequency signal;
A frequency divider that divides the output frequency to generate a chirp signal and generates a feedback signal frequency;
A phase detector generating a charge corresponding to a phase difference between the feedback frequency of the feedback signal and the reference clock frequency;
A loop filter that converts the charge into an input voltage according to the bandwidth;
A second coupler that distributes the output power amount to generate a modulated or demodulated signal for generating a bit frequency signal;
A first mixer that generates a modulated signal from the chirp signal using frequency upconversion;
A second mixer that demodulates the modulated signal to generate a bit frequency signal;
A microcontrolled unit (MCU) for calculating the phase error magnitude from the generated bit frequency signal and comparing the calculated error magnitude with a preset initial value to adjust the bandwidth of the loop filter;
Phase noise optimization device comprising a. According to claim 1,
A first reference frequency oscillator providing a reference frequency for the frequency up-conversion to the second mixer; And
And a second reference frequency oscillator providing the reference clock frequency to the phase detector.
According to claim 1,
The chirp signal is generated using an initial information value of a preset chirp signal, and the initial information value includes at least one of a frequency bandwidth, a frequency deviation, a dwell time, and a number of frequency steps. Phase noise optimization device, characterized in that.
According to claim 1,
A low pass filter (LPF) that limits the magnitude of the phase error through band limitation; And
An analog-to-digital converter (ADC) that converts a bit frequency signal from an analog signal to a digital signal and provides it to the MCU.
According to claim 1,
The phase error magnitude is a Root Means Square (RMS) jitter size, and the MCU calculates a Root Means Square (RMS) jitter through a voltage peak point in a bit frequency signal.
The method of claim 4,
The LPF has a pass band corresponding to a bandwidth of a radar system, the pass band is changed according to the magnitude of the phase error, and the radar system is a FMCW (Frequency Modulated Continous Wave) radar system.
According to claim 2,
The path for generating the chirp signal is a phase noise optimizing device, characterized in that in order of a voltage controlled oscillator, a first coupler, a frequency divider, a phase detector, and a loop filter.
According to claim 2,
The generation path of the bit frequency signal is composed of a signal modulation path and a signal demodulation path, and the signal modulation path includes a first path and a voltage controlled oscillator, a power divider, a first coupler, and a second coupler of a second reference frequency oscillator. A path summing the second paths of the signal, wherein the signal demodulation path is a path combining the second path of the voltage controlled oscillator, the power divider, the first coupler, and the second coupler and the third path of the first mixer. Noise optimizer.
According to claim 1,
The bandwidth of the loop filter is increased when the linearity is improved compared to the set initial value, and the opposite is the phase noise optimization device, characterized in that the bandwidth of the loop filter is reduced.
Setting an initial value of the loop filter using an initial information value of the chirp signal from a microcontrol unit (MCU);
Generating a chirp signal according to the set initial value;
Generating a bit frequency signal using the chirp signal;
Collecting the bit frequency signal generated by the MCU;
Calculating a phase error magnitude from the generated bit frequency signal;
Adjusting the bandwidth of the loop filter by comparing the calculated phase error magnitude with a preset initial value;
Phase noise optimization method comprising a.
The method of claim 10,
The initial information value comprises at least one of a frequency bandwidth, frequency deviation (deviation), dwell time, and the number of frequency steps, phase noise optimization method.
The method of claim 10,
The phase error magnitude is a Root Means Square (RMS) jitter size, and the MCU calculates a Root Means Square (RMS) jitter through a voltage peak point in a bit frequency signal.
The method of claim 10,
The bandwidth of the loop filter is increased when the linearity is improved compared to the set initial value, and if the opposite, the bandwidth of the loop filter is reduced.

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