KR102086060B1 - Dram cell memory element, memory array and manufacturing method of memory element - Google Patents

Abstract

A memory device is disclosed. The memory device may be formed on a silicon substrate doped with a first concentration of impurities of a first type, a drain region doped with a first concentration of a second type of impurities, and a pillar shape on a drain region. And a body region doped with a second type of impurities at a predetermined second concentration, an insulating layer formed to surround the surface of the body region on the drain region, a gate insulating layer formed to surround the surface of the body region on the insulating layer, and an insulating layer The gate is formed to surround the surface of the gate insulating layer, and includes a source region formed on one side of the body region and doped with a second type of impurity at a concentration higher than the second concentration.

Description

DRAM cell memory device, memory array and method of manufacturing memory device {DRAM CELL MEMORY ELEMENT, MEMORY ARRAY AND MANUFACTURING METHOD OF MEMORY ELEMENT}

The present disclosure relates to a memory semiconductor device, a memory array, and a method of manufacturing a memory device, and more particularly, a DRAM (DRAM) cell memory device for receiving a charge transporter from a bulk silicon substrate to perform a program operation. A method of manufacturing a memory array and a memory device.

In order to improve the integration of the DRAM chip, the size of the DRAM cell must be continuously reduced, but the conventional DRAM cell has a limitation in reducing the cell area by the area occupied by the capacitor.

In order to solve this problem of DRAM reduction, so-called capacitorless 1T (one transistor) DRAMs without capacitors have been proposed.

The conventionally proposed capacitorless 1T DRAM has used a silicon on insulator (SOI) substrate as a data store for storing holes in a P-type body by using a body floating effect.

However, the capacitorless 1T DRAM using the body floating effect not only has poor data retention capability but also has a high manufacturing cost due to the use of expensive SOI substrates.

SUMMARY OF THE INVENTION An object of the present disclosure is to provide a memory device capable of performing a program operation at a low voltage and a high speed without using an expensive SOI substrate by implementing a vertical nanowire junctionless transistor on a bulk Si substrate. have.

The present disclosure can be used to manufacture a highly integrated chip, and an object thereof is to provide a memory device having excellent data retention capability.

Another object of the present invention is to provide a memory array including a plurality of the above-described memory elements and a method of manufacturing the above-described memory elements.

A memory device according to an embodiment of the present disclosure may include a silicon substrate doped with a first type of impurity at a predetermined concentration, and a drain formed on the silicon substrate and doped with a second type of impurity at a predetermined first concentration. A region formed in a pillar shape on the drain region, the body region doped with the second type of impurities at a predetermined second concentration, an insulating layer formed to surround the body region on the drain region, and on the insulating layer A gate insulating layer formed to surround the body region, a gate formed to surround the gate insulating layer on the insulating layer, and formed on one side of the body region so that the second type of impurities are formed in the first concentration and the second concentration A source region doped at a higher concentration.

In this case, the body region may receive a charge transporter from the silicon substrate.

Meanwhile, the height of the drain region may be formed between 10 nm and 100 nm.

The impurity of the first type may be a P-type impurity, the impurity of the second type may be an N-type impurity, and the charge transporter may be a hole.

In this case, the drain region and the body region may be doped with N- concentration, and the source region may be doped with N + concentration.

In this case, when a predetermined negative voltage is applied to the drain region and a predetermined negative voltage is applied to the body region, the memory device may be formed by the drift and diffusion of holes provided from the silicon substrate. The amount of holes stored in the region is increased to perform a programming (writing '1') operation.

Alternatively, in the memory device, when a predetermined positive voltage is applied to the gate and a predetermined negative voltage is applied to the drain region, the amount of holes stored in the body region is reduced by drift and diffusion. A writing '0' operation may be performed.

Alternatively, when a predetermined negative voltage is applied to the gate, the memory device may hold a hole stored in the body region to perform a hold operation.

Alternatively, when a predetermined amount of voltage is applied to the gate, the memory device may sense a current flowing in the drain region to perform a read operation.

The body region may include SiGe.

Meanwhile, the first type of impurities may be N-type impurities, the second type of impurities may be P-type impurities, and the charge transporter may be electrons.

In this case, the drain region and the body region may be doped with a P- concentration, and the source region may be doped with a P + concentration.

The memory array according to an embodiment of the present disclosure includes a plurality of the memory elements, and each silicon substrate included in the plurality of the memory elements is integrally formed.

In this case, the plurality of memory elements are disposed in a lattice form, the drain regions of the memory elements included in the same column among the plurality of memory elements are integrally formed, and the source regions of the memory elements included in the same column are integrally formed. Gates of the memory devices included in the same row among the plurality of memory devices may be integrally formed.

Meanwhile, a method of manufacturing a memory device according to an embodiment of the present disclosure may include a bulk region, a drain region, and a second region by doping impurities of a second type to a predetermined concentration on a silicon substrate doped with impurities of a first type. Forming a body region and a source region, patterning and etching the body region and the source region to form a nanowire including the body region and the source region, insulation surrounding the body region on the drain region Depositing a layer, depositing a gate insulating layer surrounding the body region on the insulating layer, depositing a gate surrounding the gate insulating layer on the insulating layer, depositing an electrode of the source region and the drain region It includes a step. In this case, the drain region, the body region and the source region are regions doped with the impurity of the second type, and the source region is doped with a higher concentration of the impurity of the second type than the drain region and the body region. It is.

Since the memory device according to the present disclosure uses a vertical nanowire non-bonded transistor formed on a bulk Si substrate, it is advantageous to reduce costs by not using an expensive SOI substrate. In addition, since the program operation is performed by receiving data charge from the bulk Si substrate, the program operation can be performed at a low voltage and a high speed.

Since the memory device according to the present disclosure can greatly improve the degree of integration using a vertical nanowire structure, it is easy to manufacture a highly integrated DRAM chip using a memory array including a plurality of the memory devices according to the present disclosure.

The memory device according to the present disclosure may secure a high sensing current margin by implementing a body region using SiGe having a high dielectric constant.

In addition, by forming an insulator between the gate and the drain region, the electron-hole recombination phenomenon can be minimized, and a gate metal having a high work function can be used to have excellent data retention capability.

As a result of the memory device according to the present disclosure having the same structure as the logic device structure, the manufacturing method of the memory device according to the present disclosure can use the existing semiconductor process equipment and manufacturing method as it is and has excellent process compatibility.

1 is a three-dimensional structure and a cross-sectional view of a memory device according to an embodiment of the present disclosure;
2 is a cross-sectional view and an energy band diagram of a memory device during a programming (1) operation;
3 is a cross-sectional view and an energy band diagram of a memory device during erasing (writing '0') operation;
4 to 5 are cross-sectional views and energy band diagrams of a memory device during a hold operation;
6 is a cross-sectional view and an energy band diagram of a memory device during a read operation;
7 is a graph showing a relationship between a gate voltage and a drain current based on a state of a memory element;
8 is a graph for explaining a sensing current margin;
9 is a graph illustrating a relationship between a sensing current margin and a hold time;
10 is a graph illustrating a sensing current margin according to a cross-sectional view of a memory device and a height of a drain region;
11 is a circuit diagram and a diagram illustrating an example of a memory array in which a plurality of memory elements are combined;
12 is a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

Before describing this disclosure in detail, the description method of this specification and drawings is demonstrated.

First, terms used in the present specification and claims have been selected in general terms in consideration of their function in various embodiments of the present disclosure, but such terms are intended to be useful to those skilled in the art or to legal or technical interpretations and It may vary depending on the emergence of new technology. In addition, some terms are terms arbitrarily selected by the applicant. Such terms may be interpreted in the meanings defined herein, and may be interpreted based on the general contents of the present specification and common technical knowledge in the art without specific term definitions.

In addition, the same reference numerals or symbols described in each drawing attached to the present specification represent parts or components that perform substantially the same function. For convenience of explanation and understanding, different embodiments will be described using the same reference numerals or symbols. That is, although all the components having the same reference numerals are shown in the plurality of drawings, the plurality of drawings does not mean an embodiment.

In addition, in the present specification and claims, terms including ordinal numbers such as “first”, “second”, and the like may be used to distinguish between components. These ordinal numbers are used to distinguish the same or similar components from each other, and the meaning of the terms should not be construed as limited by the use of these ordinal numbers. For example, the components combined with these ordinal numbers should not be limited in order of use or arrangement by the number. If necessary, the ordinal numbers may be used interchangeably.

As used herein, the singular forms "a", "an" and "the" include plural forms unless the context clearly indicates otherwise. In this application, the terms "comprise" or "consist" are intended to indicate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, and one or more other It is to be understood that the present invention does not exclude in advance the possibility of the presence or the addition of features or numbers, steps, operations, components, parts, or combinations thereof.

In the embodiments of the present disclosure, terms such as “module”, “unit”, “part”, and the like are terms for referring to a component that performs at least one function or operation, and such components are referred to as hardware or software. It may be implemented or in a combination of hardware and software. In addition, a plurality of "modules", "units", "parts", etc. are integrated into at least one module or chip, except that each needs to be implemented by a particular specific hardware, and is at least one processor. It can be implemented as.

In addition, in an embodiment of the present disclosure, when a part is connected to another part, this includes not only a direct connection but also an indirect connection through another medium. In addition, the meaning that a part includes a certain component means that the component may further include other components, without excluding other components, unless specifically stated otherwise.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a three-dimensional structure and a cross-sectional view of a memory device according to an exemplary embodiment of the present disclosure.

Referring to FIG. 1, the memory device 10 may include a bulk silicon (Si) substrate 110 and a drain region 120 formed on the bulk silicon (Si) substrate 110. In addition, the memory device 10 may include a body region 130 formed in a pillar shape on the drain region 120, and a source region 140.

In detail, the memory device 10 may include a body region 130 formed in a pillar shape on the drain region 120, a source region 140 formed on one side of the body region 130, and a body on the drain region 120. An insulating layer 200 formed to surround the surface of the region 120, a gate insulating layer 300 formed to surround the surface of the body region 130 on the insulating layer 200, and a gate insulating layer on the insulating layer 200 ( It may include a gate 400 formed to surround the 300.

FIG. 1A illustrates a three-dimensional structure of the memory device 10, and FIG. 1B illustrates a cross-sectional view of the memory device 10.

Referring to FIG. 1A, the drain region 120 formed on the bulk Si substrate 110 formed in the shape of a wide rectangular pillar may be confirmed. In addition, on the upper surface of the drain region 120, the cylindrical nanowires in which the body region 130 and the source region 140 are stacked in order may be confirmed.

Referring to FIG. 1A, the gate insulating layer 300 formed to cover a part of the surface of the body region 130 and the gate 400 again covering the surface of the gate insulating layer 300 can be seen. In addition, the insulating layer 200 formed on the upper surface of the drain region 120 to surround the cylinder under the gate 400 may be confirmed.

Referring to FIG. 1B, in detail, the insulating layer 200 may be disposed on the upper surface of the drain region 120 and may be formed to surround a portion of the lower surface of the body region 130. have. In addition, it can be seen that the gate insulating layer 300 and the gate 400 may be formed on the upper surface of the gate insulating layer 200.

Referring to FIG. 1B, the distance corresponding to the distance between the drain region 120 and the gate 400 is compared to the thickness of the gate insulating layer 200 corresponding to the distance between the body region 130 and the gate 400. It can be seen that the height of the insulating layer 400 is larger. This is to prevent the drain region 120 from being affected by the voltage applied to the gate 400.

Meanwhile, unlike FIG. 1, the insulating layer 200 and the gate insulating layer 300 may be integrally implemented.

The bulk silicon (Si) substrate 110 of the memory device 10 may be doped with impurities of a first type to a predetermined concentration.

In this case, the drain region 120 may be doped with a first concentration of a second type of impurity, and the body region 130 may be doped with a second concentration of a second type of impurity. In this case, the first concentration is preferably slightly higher than the second concentration, but the first concentration and the second concentration may be the same.

In addition, the source region 140 may be doped with a second type of impurities at concentrations higher than the first concentration and the second concentration.

As a result, the body region 130 may receive a charge transporter from the bulk silicon (Si) substrate 110 based on the voltage condition of the memory device 10.

The voltage condition of the memory device 10 refers to what polarity and how much the voltage is applied to at least one of the drain region 120, the body region 130, and the gate 400.

In addition, the charge transporter refers to a particle having a polarity as used by the memory device 10 to store and maintain data. Specifically, it means electrons and holes. The charge transporter may be used to read how much data is stored in the memory device 10.

The memory device 10 may store data corresponding to a '1' or '0' state. In this case, storing the data corresponding to the '1' state means a writing (1) operation, and storing the data corresponding to the '0' state means an erasing (writing '0') operation. .

Specifically, memory element 10 may increase or decrease the amount of specific charge transport stored in body region 130 based on a specific voltage condition, thereby writing or writing '0'. ') Can be performed.

The memory device 10 may maintain the stored data. This means hold operation. In detail, the memory device 10 may perform a hold operation by maintaining the amount of charge transporters stored in the body region 130 based on a specific voltage condition.

By applying a voltage based on a specific voltage condition to the memory device 10, it is possible to confirm the state of the memory device 10, which is called a read operation. Specifically, when a read operation is performed in which a channel through which electrons can move is formed in the body region 130 according to a specific voltage condition, a current of the drain region 120 generated based on electrons moving through the formed channel. Can be performed by measuring.

The first type of impurities for doping the bulk silicon (Si) substrate of the memory device 10 may be P-type impurities. Specifically, the bulk silicon (Si) substrate may be doped to a P- concentration.

In this case, the second type of impurities for doping the drain region 120, the body region 130, and the source region 140 may be N-type impurities.

In this case, the source region 140 may be doped to a greater concentration than the drain region 120 and the body region 130. For example, the drain region 120 and the body region 130 may be doped with an N− concentration, and the source region 140 may be doped with an N + concentration. In this case, the main charge transporter is a hole, and FIGS. 2 to 6, which will be described below according to operations of the memory device 10, assume such doping conditions.

In addition, the gate 400 may be implemented with a metal having a high work function. In this case, in the off state in which a voltage of 0 V is applied to the gate 400, the entire body region 130 may be depleted and current may not flow. As a result, the depleted region of the body region 130 may be used as the data storage of the memory device 10.

In this case, the memory device 10 is provided in the bulk silicon (Si) substrate 110 when a predetermined negative voltage is applied to the drain region 120 and a predetermined negative voltage is applied to the body region 130. The amount of holes stored in the body region 130 is increased by the drift and diffusion of the holes, thereby performing a program (writing '1') operation.

2 is a cross-sectional view and an energy band diagram of the memory device 10 during a program (writing '1') operation. FIG. 2 assumes a preset negative voltage applied to the drain region 120 and a preset negative voltage applied to the gate 400.

Referring to FIG. 2A, it can be seen that holes of the bulk silicon (Si) substrate 110 move to the body region 130, which may be explained through FIG. 2B.

Referring to FIG. 2B, when a negative voltage is applied to the drain region 120 and the gate 130, the energy levels of the drain region 120 and the body region 130 are increased to thereby increase the drain region 120. And the energy level of the body region 130 is not smaller than the energy level of the bulk silicon (Si) substrate 110.

At this time, the potential barrier formed in the drain region 120 is lowered, and holes in the bulk silicon (Si) substrate 110 may flow into the body region 130 through drift and diffusion. As a result, the amount of holes stored in the body region 130 is increased to perform a programming ('1') operation.

Unlike FIG. 2, the memory device 10 may store holes by making an electron-hole pair using a band-band tunneling phenomenon, a gate-induced-drain-leakage (GIDL), an impact ionization phenomenon, and the like. However, as a result of using the method of storing the holes flowing from the bulk silicon (Si) substrate 110 as shown in FIG. 2, there is an advantage that the programming (1 ') operation can be performed at a high speed even at a low driving voltage.

When a predetermined positive voltage is applied to the gate 400 and a predetermined negative voltage is applied to the drain region 120, the memory device 10 may be formed of holes stored in the body region 130 by drift and diffusion. The amount can be reduced to perform a writing '0' operation.

3 is a cross-sectional view and an energy band diagram of the memory device 10 during erasing (writing '0') operation. 3 is assuming that a predetermined negative voltage is applied to the drain region 120 and a predetermined positive voltage is applied to the gate 400.

Referring to FIG. 3A, it can be seen that holes in the body region 130 move to the bulk silicon (Si) substrate 110, which may be explained through FIG. 3B.

Referring to FIG. 3B, a negative voltage and a positive voltage are applied to the drain region 120 and the gate 130, respectively, so that the energy level of the drain region 120 rises and the body region 130 of the body region 130 is increased. The energy level goes down.

In this case, the energy level of the body region 130 is lower than the energy level of the bulk silicon (Si) substrate 110. In addition, as the energy level of the drain region 130 increases, the potential barrier formed in the drain region 130 is also lowered.

As a result, holes in the body region 130 are released to the bulk silicon (Si) substrate 110 through drift and diffusion, and the amount of holes stored in the body region 130 is reduced to erase (writing '0'). The operation is performed.

When a predetermined negative voltage is applied to the gate 400, the memory device 10 may hold a hole stored in the body region 130 to perform a hold operation.

4 to 5 are cross-sectional views and energy band diagrams of a memory device during a hold operation. 4 to 5 assume that a predetermined negative voltage is applied to the gate 400.

Referring to FIG. 4A, since there are many holes stored in the body region 130, holes in the body region 130 may be drained in a state where data stored in the memory device 10 corresponds to '1'. 120 or the source region 140 may not be emitted. Specifically, it may be confirmed that holes stored in the depletion region of the body region 130 may not be emitted. The reason can be confirmed through (b) of FIG. 4.

Referring to FIG. 4B, a predetermined negative voltage is applied to the gate 400 to increase the energy level of the body region 130 alone. In this case, the energy levels of the drain region 120 and the source region 140 are lower than the energy levels of the body region 130, thereby forming a potential barrier that traps holes in the body region 130.

As a result, holes in the body region 120 cannot move to either the drain region 120 or the source region 140, and a hold operation is performed in which holes stored in the body region 120 are maintained. do.

Referring to FIG. 5A, since there are not many holes stored in the body region 130 (compared with FIG. 4A), in a state in which data stored in the memory device 10 corresponds to '0', It can be seen that holes in the bulk silicon (Si) substrate 110 do not flow into the body region 130. The reason can be confirmed through (b) of FIG. 5.

Referring to FIG. 5B, a predetermined negative voltage is applied to the gate 400 to increase only the energy level of the body region 130 alone. In this case, the energy level of the drain region 120 is lower than the energy level of the body region 130. In addition, the energy level of the drain region 120 is maintained lower than the energy level of the bulk silicon (Si) substrate 110, so that a potential barrier is formed between the body region 120 and the bulk silicon (Si) substrate 110. Form.

As a result, holes in the bulk silicon (Si) substrate cannot enter the body region 120, and the body region 120 is held by a '0' state where only a small number of holes are still stored. ) Operation is performed.

In addition, the body region 130 and the drain region 120 may be separated by a predetermined value or more between the end portion of the gate 400 and the drain region 120 and between the end portion of the gate 400 and the source region 140. The electron-hole recombination phenomenon occurring between the cavities or between the body region 130 and the source region 140 may be minimized, and the hole retention ability of the memory device 10 may be improved.

When a predetermined amount of voltage is applied to the gate 400, a current flowing through the drain region 120 may be sensed to perform a read operation on the memory device 10.

When the voltage applied to the gate 400 increases, the depletion region gradually disappears from the inner center of the body region 130, and a channel through which electrons can flow may be formed.

6 is a cross-sectional view and an energy band diagram of the memory device 10 during a read operation. 6 is based on the premise that a predetermined amount of voltage is applied to the gate 400.

Referring to FIGS. 6A and 6B, a predetermined amount of voltage is applied to the gate 400 to form a channel in the body region 130, resulting in electrons between the source region 140 and the drain region 120. Can move, so that a specific current in the drain region 120 can be measured.

In this case, (a) of FIG. 6 in which the stored data is '1' and there are many holes stored in the body region 130, and (b) of FIG. 6 in which the stored data is '0' and there are few holes stored in the body region 130 (b). In either case, it can be seen that the widths of the channels through which electrons can move are different.

Specifically, it can be seen that the channel width through which electrons can move is larger in the case of FIG. 6A, which has many holes stored in the body region 130, than in the case of FIG. 6B, which has few holes. That is, the current of the drain region 120 measured in FIG. 6A becomes larger than the current of the drain region 120 measured in FIG. 6B. The reason can be confirmed through (c) of FIG. 6.

Referring to FIG. 6C, it can be seen that the energy level of the body region 130 is lower when the state of the memory device 10 is '1' than when the state of the memory device 10 is '0'. This is because even if the same amount of voltage is applied to the gate 400, the energy level of the body region 130 varies according to the amount of holes stored in the body region 130.

Specifically, the greater the amount of holes stored in the body region 130, the lower the energy level.

As a result, even if a positive voltage having the same magnitude is applied to the gate 400, when the data stored in the memory device 10 is '1', the current of the drain region 120 is '0', and when the current is '0', the drain region 120. Is greater than the current.

Therefore, by measuring a current of the drain region 120 by applying a predetermined amount of voltage to the gate 400, whether the state of the memory device 10, that is, the data stored in the memory device 10 is '1' A read operation for checking whether it is '0' may be performed.

FIG. 7 is a graph illustrating a measurement result showing how a current value of the drain region 120 varies according to a state of the memory device 10 in a read operation.

Referring to FIG. 7, when the state of the memory device 10 is '1', as shown in FIG. 6, the current I _DS flowing in the drain region 120 is equal to '0'. In this case, it may be confirmed that the current I _DS flowing in the drain region 120 is generally larger.

Regarding the difference in the current value of the drain region 120 according to the state of the memory device 10, FIG. 8 is a graph for describing a sensing current margin.

FIG. 8 lists the results of measuring current values flowing in the drain region 120 in the time axis when performing various operations such as writing '1', writing '0', hold, and read according to time.

Referring to FIG. 8, a current value in a read '1' operation section in which a read operation is performed in a state in which the memory element 10 is '1', and a read in a state in which the memory element 10 is '0' The difference between the current values of the read '0' operation section performing the (read) operation can be checked (101.0 nA / μm). This is referred to as sensing current margin ΔI _DS .

On the other hand, "101.0 nA / μm" in FIG. 8 is a result of calculating the current value assuming that the time required for the state of the memory element 10 to be stably read is about 10 ns.

The function of the memory device 10 to correctly read the stored data, the sensing current margin value is a certain time between the state that the memory device 10 is '1' or '0' during the read operation proceeds. It needs to be kept longer.

9 is a graph illustrating a relationship between a hold time and a sensing current margin in the memory device 10.

Referring to FIG. 9, it can be seen that the memory device 10 according to the present disclosure maintains a sensing current margin to some extent even when the hold time is 100 ms or more at room temperature 300K.

This satisfies 64 ms, which is a memory retention time generally required in conventional DRAMs, and thus, demonstrates that the memory device 10 according to the present disclosure has excellent memory retention capability.

The larger the sensing current margin of the memory device 10 is, the better. For this purpose, a large amount of change in the charge transporter or a material having a high dielectric constant may be used.

Specifically, a compound containing SiGe, Ge, or the like having a higher dielectric constant than Si, by increasing the voltage applied during programming (1) and / or writing (0) operation, to increase the amount of hole change. May be included in the body region 130.

Alternatively, the sensing current margin may be increased by appropriately adjusting the height of the drain region 120.

10 is a graph illustrating a sensing current margin according to a cross-sectional view of the memory device 10 and the height of the drain region 120. FIG. 10 is based on the assumption that the doping concentration of the drain region 120 is 5 * 10 ¹⁸ cm ^-3 and the doping concentration of the bulk silicon (Si) substrate is 1 * 10 ¹⁶ cm ^-3 .

The height of the drain region 120 (see FIG. 10A) may affect the potential energy barrier between the bulk silicon (Si) substrate and the drain region 120, thereby directly changing the sensing current margin. For example, the height of the drain region 120 may be formed between 10 nm and 100 nm.

FIG. 10B is a graph showing a sensing current margin value according to the height of the drain region 120 in the device structure shown in FIGS. 1 and 10A.

Referring to FIG. 10B, when the height of the drain region 120 is 50 nm, it can be confirmed that the memory device 10 has the best sensing current margin.

In FIG. 10B, when the height of the drain region 120 is increased from 10 nm to 50 nm, the sensing current margin is increased due to the programming (1) operation of holes in bulk silicon (Si). This is because the potential energy barrier is formed sufficiently high during the hold operation after being introduced into the substrate, so that a large amount of holes are stored in the body region 130. As a result, a large amount of holes increases the read current (current at read '1'), thereby increasing the sensing current margin value.

On the other hand, in FIG. 10B, when the height of the drain region 120 increases from 50 nm to 100 nm, the sensing current margin decreases. This is because the height of the drain region 120 is relatively large, so that the potential energy barrier is lowered slightly by the driving voltage between the gate 400 and the drain region 120 during a writing ('1') operation. Because it is. As a result, a relatively small amount of holes are introduced into the body region 130 during the writing ('1') operation, thereby reducing the sensing current margin.

10, when the doping concentration of the drain region 120 is 5 * 10 ¹⁸ cm ⁻³ and the doping concentration of the bulk silicon (Si) substrate 110 is 1 * 10 ¹⁶ cm ⁻³ , the height of the drain region 120 is shown. The best sensing current margin was obtained when is 50 nm, but the optimal drain region height may change as the doping concentration and distribution conditions of the drain region 120 and the bulk silicon (Si) substrate 110 change. It may be.

Table 1 below may be applied to the gate 400, the drain region 120, and the source region 140 to perform each operation (program, erase, read, and hold) in consideration of the characteristics of the memory device 10. An example of a voltage value is shown.

action program
writing '1' Eraise
writing '0' lead
read '1' or '0' Hold
hold Gate 400
Voltage [V] -1.0 1.0 0.5 -0.2 Drain region 120 voltage [V] -1.0 -1.0 0.1 0 Source area 140
Voltage [V] 0 0 0 0

On the other hand, unlike the above-described embodiments, the first type of impurities doped in the bulk silicon (Si) substrate 110 of the memory device 10 may be N-type impurities. Specifically, the bulk silicon (Si) substrate 110 may be doped to N- concentration.

In this case, the second type of impurities doped in the drain region 120, the body region 130, and the source region 140 may be P-type impurities, and the source region 140 may include the drain region 120 and the body region ( P-type impurities may be doped to a concentration higher than 130). In this case, the main charge transporter may be an electron.

In detail, the drain region 120 and the body region 130 may be doped with a P− concentration, and the source region 140 may be doped with a P + concentration.

On the other hand, unlike the above-described drawings, the position of the source region and the drain region in the memory device may be interchanged. In this case, each operation of the memory device 10 may be performed by applying a voltage applied to the drain region 120 to the source region.

Meanwhile, the memory array according to an embodiment of the present disclosure may include a plurality of memory elements 10 of FIG. 1. In this case, each of the bulk silicon (Si) substrates 110 included in the plurality of memory devices 10 may be integrally formed.

In this case, at least one of the drain region 120, the source region 140, the insulating layer 200, and the gate 400 included in at least two memory elements 10 of the plurality of memory elements 10 may be integrally formed. Can be formed.

Alternatively, the plurality of memory elements 10 may be arranged in a lattice form, and the drain regions 120 of the memory elements 10 included in the same column among the plurality of memory elements 10 may be integrally formed and included in the same column. The source region 140 of the device 10 may be integrally formed, and the gate 400 of the memory device 10 included in the same row among the plurality of memory devices may be integrally formed.

FIG. 11 is a circuit diagram and a diagram illustrating an example of a memory array 1000 in which a plurality of memory elements are combined.

FIG. 11A schematically illustrates a circuit diagram of the memory array 1000. The gate 400 of the memory elements 10 included in each wordline word lines 0, 1,. It can be seen that they can be formed integrally. In addition, it can be seen that the drain regions 120 of the memory devices 10 included in each of the bit lines bitlines 0, 1,..., 15 may be integrally formed.

FIG. 11B illustrates 16 memory devices 10 arranged in the same manner as in FIG. 11A, and the drain regions 120 of the memory devices 10 included in the same bitline are illustrated in FIG. 11B. ) And the source region 120 may be integrally formed, and the gates 400 of the memory elements 10 included in the same wordline may be integrally formed.

As such, in the memory array 1000, the connection relationship between the drain region 120 and the connection relationship between the gate 400 may be implemented in lines crossing each other, thereby individually and simultaneously bunching the plurality of memory devices 10. Enemy control is possible.

12 is a cross-sectional view illustrating a method of manufacturing a memory device according to an embodiment of the present disclosure.

In the method of manufacturing the memory device, a bulk region, a drain region, and a body region are first doped with a first concentration of a second type different from the first type on a silicon substrate doped with a first concentration of impurities of a first type. And a source region. In this case, the drain region, the body region, and the source region may be a region doped with the impurity of the second type, and the source region may be a region doped with a higher concentration of the impurity of the second type than the drain region and the body region.

For example, referring to FIG. 12A, a portion of a bulk silicon (Si) substrate doped with P-concentration is doped with N-type impurities to sequentially form a bulk region, a drain region, a body region, and a source region. can do. In this case, the drain region and the body region may be doped with N- concentration, and the source region may be doped with N + concentration.

Meanwhile, the bulk silicon (Si) substrate doped with P-concentration may be a commercial silicon substrate having a doping concentration of 10 ¹⁶ to 10 ¹⁸ cm ^-3 , and the drain region and the body region may be injected by implanting N-type impurities using an ion implant device. And a source region.

The body region and the source region may be patterned and etched to form nanowires including the body region and the source region. Specifically, referring to FIG. 12B, the body region and the source region may be patterned and etched in a pillar shape thinner than the bulk region and the drain region. In this case, the etched body region and the source region may be in the form of a thin cylindrical nanowire.

In this case, an insulating layer surrounding the surface of the body region may be deposited on the drain region. Specifically, as shown in FIG. 12C, an insulating layer surrounding a part of the surface of the body region may be formed at a portion of the portion where the body region is etched and abutted with one surface of the drain region.

In addition, a gate insulating layer surrounding the surface of the body region may be deposited on the insulating layer. In this case, the insulating layer and the gate insulating layer may include at least one of various types of insulating films, such as silicon oxide, a nitride film, aluminum oxide, hafnium oxide, hafnium oxide, and zinc oxide.

In this case, the insulating layer and the gate insulating layer may be deposited as one integrated insulating layer. In addition, the height of the insulating layer may be greater than the thickness of the gate insulating layer.

Next, a gate covering the surface of the gate insulating layer may be deposited on the insulating layer. In this case, the gate may be implemented with a metal having a relatively high work function. For example, the gate may include at least one of gold, platinum, nickel, and high concentration P-type polysilicon.

Then, the electrodes of the source region and the drain region can be deposited. Specifically, FIG. 12F corresponds to a process of patterning an electrode for applying an electrode to each of the source and drain regions, respectively.

Meanwhile, when the N-doped drain region and / or the body region are implemented to include at least one of SiGe and Ge having high electron mobility and high dielectric constant, high sensing current margin may be obtained. Additionally, in addition to silicon, separate Group 3-5 compound semiconductor materials (InGaAs, InP, InAs, etc.) may be applied to at least one of the bulk region, the drain region, the body region, and the source region in the form of a single junction or a double junction. . Through this, it is possible to manufacture a DRAM memory device having better data retention time and sensing current margin in the future.

In addition, the method of manufacturing the memory device is similar to a general bulk silicon semiconductor-based nanowire MOSFET process, and thus, there is an advantage in that it can be manufactured using existing process equipment.

Although the preferred embodiments of the present invention have been illustrated and described above, the memory device 100 according to the present disclosure is not limited to the above-described embodiments, and the present invention may be made without departing from the spirit of the present invention as claimed in the claims. Various modifications may be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

10: memory element 110: bulk silicon (Si) substrate
120: drain region 130: body region
140: source region 200: insulating layer
300: gate insulating layer 400: gate
1000: memory array

Claims (15)

A silicon substrate doped with a first concentration of impurity of a first type;
A drain region formed on the silicon substrate and doped with a second concentration of impurities of a second type;
A body region formed in a pillar shape on the drain region and doped with a second concentration of impurities of the second type;
An insulating layer formed to surround the body region on the drain region;
A gate insulating layer formed to surround the body region on the insulating layer;
A gate formed to surround the gate insulating layer on the insulating layer; And
A source region formed on one side of the body region and doped with the second type of impurities at a concentration higher than the first concentration and the second concentration;
When a predetermined negative voltage is applied to the drain region and a predetermined negative voltage is applied to the body region, the amount of holes stored in the body region is increased by drift and diffusion of holes provided from the silicon substrate. To perform a program (writing '1') operation,
When a predetermined positive voltage is applied to the gate and a predetermined negative voltage is applied to the drain region, the amount of holes stored in the body region is reduced by drift and diffusion, thereby erasing (writing '0'). ) A memory device performing the operation. delete The method of claim 1,
The height of the drain region,
A memory device formed between 10 nm and 100 nm. The method of claim 1,
The impurity of the first type is a P-type impurity,
The second type of impurities are N type impurities,
The charge carrier is a hole, the memory device. The method of claim 1,
Wherein the drain region and body region are doped with N− concentration and the source region is doped with N + concentration. delete delete The method of claim 1,
When a predetermined negative voltage is applied to the gate, holes stored in the body region are maintained to perform a hold operation. The method of claim 1,
When a predetermined amount of voltage is applied to the gate, a read operation by sensing a current flowing in the drain region to perform a read operation. The method of claim 1,
And the body region comprises SiGe. The method of claim 1,
The impurity of the first type is an N-type impurity,
The second type of impurities are P type impurities,
The charge carrier is an electron. The method of claim 1,
Wherein the drain region and the body region are doped with a P− concentration and the source region is doped with a P + concentration. A plurality of memory elements of claim 1,
Wherein each silicon substrate included in the plurality of memory elements is integrally formed. The method of claim 13,
The plurality of memory elements are arranged in a grid form,
The drain regions of the memory devices included in the same column among the plurality of memory devices may be integrally formed, and the source regions of the memory devices included in the same column may be integrally formed with each other. And the gate is integrally formed. Doping the second type of impurities to a predetermined concentration on the silicon substrate doped with the first type of impurities to a predetermined concentration to form a bulk region, a drain region, a body region and a source region;
Patterning and etching the body region and the source region to form a nanowire including the body region and the source region;
Depositing an insulating layer surrounding the body region on the drain region;
Depositing a gate insulating layer surrounding the body region on the insulating layer;
Depositing a gate surrounding the gate insulating layer on the insulating layer; And
Depositing electrodes of the source region and the drain region;
The drain region, the body region and the source region are regions doped with impurities of the second type,
The source region is doped with a higher concentration of impurities of the second type than the drain region and the body region,
When a predetermined negative voltage is applied to the drain region and a predetermined negative voltage is applied to the body region, the amount of holes stored in the body region is increased by drift and diffusion of holes provided from the silicon substrate. To perform a program (writing '1') operation,
When a predetermined positive voltage is applied to the gate and a predetermined negative voltage is applied to the drain region, the amount of holes stored in the body region is reduced by drift and diffusion, thereby erasing (writing '0'). A memory device manufacturing method for performing the operation.

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