KR102059690B1 - III-V semiconductor device and method of manufacturing the same - Google Patents

Abstract

The III-V semiconductor device includes a semiconductor layer stacked structure disposed on a substrate; Source and drain electrodes spaced apart from each other on the semiconductor layer stack structure; A gate electrode disposed between the source electrode and the drain electrode on the semiconductor layer stack structure; A first passivation layer disposed between the gate electrode and the semiconductor layer stack structure and including a SU-8 photoresist; A second passivation layer disposed to cover the semiconductor layer stack and the gate electrode, the second passivation layer comprising a SU-8 photoresist; And a third passivation layer covering the source electrode and the drain electrode and comprising a SU-8 photoresist.

Description

III-V semiconductor device and method of manufacturing the same {III-V semiconductor device and method of manufacturing the same}

The present invention relates to a group III-V semiconductor device and a manufacturing method thereof, and more particularly, to a group III-V semiconductor device having a heterojunction structure and a method of manufacturing the same.

With the development of information and communication technology, the demand for high frequency, high temperature, and high power electronic devices is increasing, and in particular, various studies on power devices capable of controlling high power are being conducted. High electron mobility transistor (HEMT) devices using heterojunction structures of group III-V compound semiconductor series have a high concentration at the junction interface due to the large band discontinuity at the junction interface. A 2-dimensional electron gas (2DEG) region in which electrons are concentrated may be formed, and may have high electron mobility in the 2DEG region. Therefore, various studies have been conducted on group III-V semiconductor devices having high breakdown voltage, high saturation current, and the like.

However, in general, drain current may decrease due to surface trapping of electrons at the interface of the 2DEG region, and a breakdown voltage characteristic may occur such that leakage current occurs in a pinch-off state. In order to solve this problem, researches for forming a protective layer of an inorganic insulating material such as silicon oxide or silicon nitride have been conducted. However, a deposition process or an etching process using plasma is required to form the inorganic insulating material. Therefore, damage such as cracks or the like may occur in the III-V semiconductor layer, which is generally an epitaxial layer, when exposed to plasma or by an etching process. 1A and 1B are images illustrating cracks generated when a protective layer is formed of silicon nitride. In addition, since such damage of the III-V semiconductor device may cause a decrease in the drain current density, a poor pinch-off phenomenon, and the like, there is a problem that the withstand voltage characteristics of the III-V semiconductor device are degraded.

The technical problem of the present invention is to provide a group III-V semiconductor device having excellent withstand voltage characteristics.

In addition, another technical problem of the present invention is to provide a method for manufacturing a III-V semiconductor device having excellent withstand voltage characteristics.

The III-V semiconductor device according to the present invention for achieving the above technical problem, the semiconductor layer laminated structure disposed on the substrate; Source and drain electrodes spaced apart from each other on the semiconductor layer stack structure; A gate electrode disposed between the source electrode and the drain electrode on the semiconductor layer stack structure; A first passivation layer disposed between the gate electrode and the semiconductor layer stack structure and including a SU-8 photoresist; A second passivation layer disposed to cover the semiconductor layer stack and the gate electrode, the second passivation layer comprising a SU-8 photoresist; A source pad and a drain pad respectively formed on the source electrode and the drain electrode; And a third passivation layer covering the second passivation layer, the source electrode and the drain electrode, the source pad and the drain pad, and including a SU-8 photoresist.
As the first passivation layer and the second passivation layer include a SU-8 photoresist, a drain current collapse shape and a leakage current in the pinch-off state and a breakdown voltage characteristic between the source and the drain are reduced. Prevent,

The third passivation layer prevents the exposed components of the source pad and the drain pad from being damaged by mechanical shock or moisture from the outside,
The gate electrode is in contact with the semiconductor layer stack structure and has a first width W1 and a second width W2 disposed above the first portion and larger than the first width W1. A second portion having:
The first passivation layer is in contact with a side surface of the first portion of the gate electrode,
The source electrode extends over the gate electrode so that the source electrode and the gate electrode overlap each other, and the second passivation layer is interposed between the gate electrode and the source electrode.

In example embodiments, the first passivation layer and the second passivation layer may include a SU-8 photoresist.

In example embodiments, the semiconductor device may further include a third passivation layer covering the source electrode and the drain electrode and including a SU-8 photoresist.

In example embodiments, the gate electrode is in contact with the semiconductor layer stack structure and has a first width W1, and is disposed over the first portion, and the first width W1. And a second portion having a larger second width W2, wherein the first passivation layer may contact a side of the first portion of the gate electrode.

In example embodiments, the second passivation layer may surround the top and side surfaces of the second portion of the gate electrode.

In example embodiments, the gate electrode has a gamma shape having a lower width having a first width W1 and an upper width having a second width W2, such that the upper width W2 is a lower width W1. It may be a gamma gate electrode having a larger gamma (Γ) shape.

In example embodiments, the gate electrode may be a T-type gate electrode having a T shape in which an upper width W2 is greater than a lower width W1.

In example embodiments, the source electrode extends over the gate electrode so that the source electrode and the gate electrode overlap, and the second passivation layer is interposed between the gate electrode and the source electrode. Can be.

The III-V semiconductor device according to the present invention has a passivation layer including a photoresist, so that exposure or etching to plasma may occur when forming a protective layer of an inorganic insulating material such as silicon oxide or silicon nitride. It is possible to prevent damage to the device by. Therefore, the group III-V semiconductor device may have excellent voltage resistance.

1A and 1B are images illustrating cracks generated when a protective layer is formed of silicon nitride.
2 is a cross-sectional view illustrating a group III-V semiconductor device according to example embodiments.
3 is a cross-sectional view illustrating a III-V semiconductor device according to example embodiments.
4 is a cross-sectional view illustrating a group III-V semiconductor device according to example embodiments.
5 through 11 are cross-sectional views illustrating a method of manufacturing a group III-V semiconductor device according to example embodiments.
FIG. 12 is an image illustrating an upper surface of a group III-V semiconductor device completed according to the manufacturing method described with reference to FIGS.
13A to 13C are graphs illustrating breakdown voltage characteristics of a III-V semiconductor device according to Experimental Examples and Comparative Examples of the present invention.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully explain the technical idea of the present invention to those skilled in the art, and the following embodiments may be modified in many different forms, and The scope of the technical idea is not limited to the following examples. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art. As used herein, the term "and / or" includes any and all combinations of one or more of the listed items. Like numbers refer to like elements all the time. Furthermore, various elements and regions in the drawings are schematically drawn. Therefore, the technical idea of the present invention is not limited by the relative size or the distance drawn in the accompanying drawings.

2 is a cross-sectional view illustrating a III-V semiconductor device 100 according to example embodiments.

Referring to FIG. 2, the group III-V semiconductor device 100 may include a substrate 110, a semiconductor layer stack 120, a source electrode 142, a drain electrode 144, and a gate electrode 146. have.

The substrate 110 may be a silicon carbide (SiC) substrate, a silicon substrate, a gallium arsenide (GaAs) substrate, a gallium nitride (GaN) substrate, an indium phosphide (InP) substrate, an aluminum nitride (AlN) substrate, a sapphire substrate, or a glass substrate. Can be used.

The semiconductor layer stack structure 120 may include a plurality of group III-V semiconductor layers sequentially stacked on the substrate 110. The concentration and composition of each III-V semiconductor layer can vary. In example embodiments, the semiconductor layer stack structure 120 may include first and second channel layers 121 and 122 and a channel supply layer 124. The first and second channel layers 121 and 122 may each include undoped gallium nitride, and the channel supply layer 124 may include aluminum gallium nitride. For example, the channel supply layer 124 may be an AlGaN layer doped with impurities such as magnesium (Mg) and silicon (Si) at a predetermined concentration. A 2-dimensional electron gas layer (2DEG layer) (not shown) may be formed near the top surface of the first channel layer 121 facing the channel supply layer 124. Such a 2DEG layer may constitute a channel region of the III-V semiconductor device 100.

In addition, a buffer layer 112 may be further formed between the substrate 110 and the first channel layer 121. The buffer layer 112 is a defect such as misfit dislocation due to a lattice constant difference between the material of the substrate 110 and the first channel layer 121 between the material of the substrate 110 and the first channel layer 121. It may be a buffer to prevent the occurrence. The buffer layer 112 may include, for example, aluminum nitride (AlN). For example, the buffer layer 112 may include a stacked structure including a plurality of aluminum gallium nitride (AlGaN) layers in which the aluminum content is gradually increased or decreased.

The semiconductor layer stack 120 further includes a spacer layer 123 disposed between the channel supply layer 124 and the second channel layer 122 and a capping layer 125 disposed on the channel supply layer 124. can do. For example, the spacer layer 123 may be an undoped AlGaN layer and the capping layer 125 may be an undoped AlGaN layer. However, the material and arrangement of the spacer layer 123 and the capping layer 125 are not limited thereto.

At least one source electrode 142 and one drain electrode 144 may be formed on the semiconductor layer stack 120. 2 illustrates that one drain electrode 144 is formed between two source electrodes 142. In detail, the source ohmic layer 132 and the drain ohmic layer 134 are formed on the semiconductor layer stack 120, and the source electrode 142 is formed on the source ohmic layer 132 and the drain ohmic layer 134, respectively. And a drain electrode 144 may be formed. The source pad 162 and the drain pad 164 may be further formed on the source electrode 142 and the drain electrode 144. The source and drain ohmic layers 132 and 134 may serve to reduce contact resistance between the source and drain electrodes 142 and 144 and the semiconductor layer stack 120.

The gate electrode 146 is formed between the source electrode 142 and the drain electrode 144 on the semiconductor layer stack 120. That is, the gate electrode 146 may be disposed on the semiconductor layer stack 120 to be spaced apart from the source electrode 142 and the drain electrode 144 between the source electrode 142 and the drain electrode 144, respectively. . In example embodiments, the gate electrode 146 may have a vertical cross section having a gamma shape. In particular, the gate electrode 146 may include a first portion 146_1 contacting the semiconductor layer stack 120 and a second portion 146_2 disposed over the first portion 146_1. The first width W1 in the horizontal direction of the first portion 146_1 of the gate electrode 146 may be smaller than the second width W2 in the horizontal direction of the second portion 146_2.

The first passivation layer 152 may be disposed on the semiconductor layer stack 120. The first passivation layer 152 may be disposed to contact the sidewall of the first portion 146_1 of the gamma-shaped gate electrode 146, and the upper surface of the first passivation layer 152 may be the gamma-shaped gate electrode 146. It may be disposed to contact the bottom surface of the second portion 146_2 of the (). Accordingly, the gamma-shaped gate electrode 146 may surround the edge portion of the first passivation layer 152. The thickness of the first passivation layer 152 may be substantially the same as the height of the first portion 146_1 of the gate electrode 146.

In example embodiments, the first passivation layer 152 may include a photoresist. In particular, the first passivation layer 152 may comprise a SU-8 photoresist. SU-8 photoresist may have excellent adhesion to substrates such as silicon, gallium arsenide, gallium nitride, indium phosphide, glass, and may have high electrical insulation properties. Accordingly, the first passivation layer 152 may be firmly attached to the semiconductor layer stack 120, and may have excellent device isolation characteristics between the gate electrode 146 and the semiconductor layer stack 120.

The second passivation layer 154 may be conformally formed on the gate electrode 146 and the semiconductor layer stack 120. In addition, the second passivation layer 154 may cover the top surface of the gate electrode 146 and cover edge portions of the source ohmic layer 132 and the drain ohmic layer 134. In particular, the semiconductor layer stack 120 may be mesa-etched to form the second channel layer 122, the spacer layer 123, the channel supply layer 124, and the capping layer 125 on the side of the semiconductor layer stack 120. When side surfaces and the top surface of the first channel layer 121 are exposed, the side surfaces of the semiconductor layer stack 120 and the top surface of the first channel layer 121 may also be conformally covered.

In example embodiments, the second passivation layer 154 may include a photoresist. In particular, the second passivation layer 154 may comprise a SU-8 photoresist. The second passivation layer 154 may be firmly attached to the semiconductor layer stack 120, and may have excellent device isolation characteristics between the gate electrode 146 and the semiconductor layer stack 120.

Table 1 below compares the physical properties of the SU-8 photoresist with inorganic oxide silicon oxide, silicon nitride, polyimide organic BC, and BCB.

BCB Polyimide Silicon nitride Silicon oxide SU-8 Dielectric constant 2.65 3.5 7.5 3.9 3.2 Volume resistivity (Ohm / cm) - 1 × 10 ¹⁹ 1 × 10 ¹³ 1 × 10 ¹² 1 × 10 ¹⁶ Young's modulus (GPa) 3.1 2-4 160 70 4.5 Tensile Strength (MPa) - 100 360-434 55 60-55 Thermal Conductivity (W / mK) 0.29 0.176 15 1.4 0.3 Coefficient of thermal expansion (ppm / K) 39.4 45-46 3.3 12.3 52 Process temperature (℃) 210-250 350 250 (PECVD) 150 (PECVD) 95-120

Referring to Table 1, the SU-8 photoresist may have properties such as volume resistivity, tensile strength, Young's modulus, and the like better than silicon oxide or silicon nitride. For example, when the passivation layer includes silicon oxide or silicon nitride, tensile or compressive stress may occur, thereby causing stress on the underlying semiconductor layer stack 120 to cause physical damage such as cracks. Can be. In addition, in the process of forming silicon oxide or silicon nitride, a plasma enhanced chemical vapor deposition (PECVD) process is generally used, and due to the plasma in such a process, the lower semiconductor layer stack structure 120 Damage can occur. However, in the case of forming the passivation layer by using the SU-8 photoresist, cracking of the passivation layer can be prevented, while also having sufficient device isolation characteristics for the operation of the group III-V semiconductor device 100. Thus, as the first passivation layer 152 and the second passivation layer 154 comprise a SU-8 photoresist, a drain current collapse shape and leakage current generation in the pinch off state and between source and drain The degradation of the breakdown voltage characteristic can be prevented. The withstand voltage characteristic by the SU-8 photoresist will be described in detail later with reference to FIGS. 13A to 13C.

The third passivation layer 156 may be formed to cover the second passivation layer 154, the source and drain electrodes 142 and 144, and the source and drain pads 162 and 164. The third passivation layer 156 may prevent components such as the exposed source pad 162 and the drain pad 164 from being damaged by mechanical shock or moisture from the outside. In example embodiments, the third passivation layer 156 may include a photoresist. In particular, the third passivation layer 156 may include a SU-8 photoresist.

In the III-V semiconductor device 100 according to the present invention, since the first and second passivation layers 152 and 154 are formed to include a SU-8 photoresist, in the case of using silicon nitride or silicon oxide, Exposure to a plasma or an etching process, etc. can be fundamentally prevented, so that damage such as cracks of the device can be prevented. Therefore, the group III-V semiconductor device 100 may have excellent withstand voltage characteristics.

3 is a cross-sectional view illustrating a group III-V semiconductor device 100a according to example embodiments. Since the group III-V semiconductor device 100a is similar to the group III-V semiconductor device 100 described with reference to FIG. 2 except for the shape of the gate electrode 146a, the above-described differences will be described.

Referring to FIG. 3, the gate electrode 146a may include a first portion 146a_1 in contact with the semiconductor layer stack 120 and a second portion 146a_2 disposed on the first portion 146a_1. The gate electrode 146a may have a T-shaped vertical cross section. The gate electrode 146a may be a T-type gate electrode having a shape whose upper width is larger than the lower width. The first passivation layer 152a may be disposed on the semiconductor layer stack 120 in contact with both sidewalls of the first portion 146a_1 of the gate electrode 146a. The second passivation layer 154a may conformally cover the top surface and both sidewalls of the second portion 146a_2 of the gate electrode 146a.

4 is a cross-sectional view illustrating a group III-V semiconductor device 100b according to example embodiments. Since the group III-V semiconductor device 100b is similar to the group III-V semiconductor device 100 described with reference to FIG. 2 except for the shape of the source electrode 142b, the above-described differences will be described.

The source electrode 142b may extend to the upper portion of the gate electrode 146 to overlap the upper portion of the gate electrode 146, where the second passivation layer 154b is formed between the gate electrode 146 and the source electrode 142b. It can be intervened in between. Accordingly, the upper portion of the gate electrode 146 may be formed to cover the source electrode 142 b to form a double field plate electrode. In such a case, the breakdown voltage of the semiconductor element can be significantly improved. In addition, the second passivation layer 154b including the SU-8 photoresist may provide electrical insulation between the gate electrode 146 and the source electrode 142b.

Meanwhile, although the source electrode 142b has a shape overlapping with the gate electrode 146 in FIG. 4, it is not limited thereto. Alternatively, the drain electrode 144 may be formed to extend over the gate electrode 146 to overlap the gate electrode 146.

5 through 11 are cross-sectional views illustrating a method of manufacturing a group III-V semiconductor device 100 according to example embodiments. The manufacturing method described with reference to FIGS. 5 through 11 may be a manufacturing method of the III-V semiconductor device 100 described with reference to FIG. 2.

Referring to FIG. 5, the semiconductor layer stack structure 120 may be formed on the substrate 110. For example, after the buffer layer 112 is formed on the substrate 110, a plurality of III-V group semiconductor layers having different compositions may be formed on the buffer layer 112.

In example embodiments, the semiconductor layer stack structure 120 may be formed using metal organic chemical vapor deposition (MOCVD). Each layer of the semiconductor layer stack 120 may have a composition of GaN or may have a composition of AlGaN. In addition, each of the layers may be undoped or doped with impurities such as Si. Accordingly, heterostructure epitaxy layers of sequentially stacked GaN and AlGaN layers may be configured.

In example embodiments, a buffer layer 112 having a thickness of several tens of nanometers to several micrometers may be formed on the substrate 110 using AlN. Thereafter, the first channel layer 121 may be formed on the buffer layer 112 as an undoped GaN layer in a thickness range of several hundred nanometers to several micrometers. The second channel layer 122 may be formed of an undoped GaN layer of several tens of nanometers thick on the first channel layer 121. A spacer layer 123 of several nanometers thick may be formed on the second channel layer 122 using AlGaN, and a channel supply layer 124 of several tens of nanometers thick may be formed on the spacer layer 123. . The channel supply layer 124 may include an AlGaN layer doped with impurities. The capping layer 125 may be formed on the channel supply layer 124 to a thickness of several nanometers. The thickness and material of each of the semiconductor layer stack structures 120 described above have been described for illustrative purposes, but the thickness of the III-V semiconductor layers according to the present invention is not limited thereto. Further, in addition to the above-described layers, other group III-V semiconductor layers may be further formed.

Thereafter, the first passivation layer 152 may be formed on the semiconductor layer stack structure 120. The first passivation layer 152 may include a SU-8 photoresist. The first passivation layer 152 may serve to protect the lower semiconductor layer stack 120 from a high temperature process such as a subsequent rapid heat treatment process, and may also improve the flatness of the substrate 110.

In an exemplary process for forming the first passivation layer 152, a spin coating is applied or deposited on the semiconductor layer stack structure 120 using a SU-8 photoresist material layer, and then the SU-8 photo The layer of resist material may be soft baked. The adhesion of the first passivation layer 152 may be improved by the soft baking process.

Optionally, the SU-8 photoresist material is heat-treated at a predetermined temperature (eg, between 40 ° C. and 80 ° C.) for a few minutes to several tens of minutes prior to application or deposition of the SU-8 photoresist material layer. Pre-treatment of the photoresist material may be performed.

Optionally, after the soft baking of the SU-8 photoresist material layer, a room temperature cooling process may be further performed for several tens of minutes. The normal temperature cooling process may be performed to prevent stress or crack generation in the first passivation layer 152.

Referring to FIG. 6, the first passivation layer 152 and the semiconductor layer stack 120 may be mesa-etched. Accordingly, etching is performed until the top surface of the first channel layer 121 is exposed.

Subsequently, portions of the first passivation layer 152 may be removed to form the source ohmic layer 132 and the drain ohmic layer 134 on the exposed top surface of the semiconductor layer stack 120. The source and drain ohmic layers 132 and 134 are formed to contact the semiconductor layer stack 120, respectively, and are formed between a subsequently formed source electrode and drain electrode (not shown) and the semiconductor layer stack 120. Serves to reduce the contact resistance. 6 illustrates that one drain ohmic layer 134 is formed between two source ohmic layers 132. For example, the source and drain ohmic layers 132 and 134 may be formed as a stacked structure of metal layers including titanium (Ti), aluminum (Al), tantalum (Ta), and gold (Au). Thereafter, at a temperature of about 700 to 1000 degrees, a rapid thermal annealing (RTA) process may be performed under a nitrogen atmosphere.

Referring to FIG. 7, the first passivation layer 152 may be patterned using a photolithography process. In detail, a portion of the first passivation layer 152 may be removed and the top surface of the semiconductor layer stack 120 may be exposed in the removed region 152p.

In FIG. 7, the first passivation layer 152 that meets the source ohmic layer 132 is disposed so that the patterned first passivation layer 152 is spaced apart from the source ohmic layer 132 and contacts the drain ohmic layer 134. It is shown that it has been removed by a predetermined length from one end of the). That is, the removed region 152p may be disposed adjacent to the source ohmic layer 132. Alternatively, however, only the central portion of the first passivation layer 152 may be removed such that the first passivation layer 152 is in contact with both the source ohmic layer 132 and the drain ohmic layer 134, respectively. That is, the removed region 152p may be disposed in the central portion of the source ohmic layer 132 and the drain ohmic layer 134.

In an exemplary process for patterning the first passivation layer 152, since the first passivation layer 152 comprises a SU-8 photoresist, directly on the first passivation layer 152 without the formation of a separate photoresist mask. Exposure and development processes may be performed. In detail, an exposure process may be performed on a portion of the first passivation layer 152, followed by a development process. After the developing process, a curing (or hard baking) process may be further performed. Optionally, a post exposure baking process may be further performed after the exposure process. When the post-exposure baking process is performed, the sharpness and precision of the formed pattern may be improved.

Referring to FIG. 8, a first mask M1 may be disposed on the source and drain ohmic layers 132 and 134 and the first passivation layer 152. The first mask M1 has a first opening M1a, and the first mask M1 exposes a portion of the first passivation layer 152 and a portion of the removed region 152p. ) May be arranged.

In this case, a portion of the removed region 152p exposed by the first opening M1a of the first mask M1 may have a first width W1, and the first opening M1a may have a second width ( W2). Therefore, since the first opening M1a exposes a portion of the first passivation layer 152 and a portion of the removed region 152p, the first width W1 may be smaller than the second width W2. Meanwhile, the first width W1 may correspond to a width where the first opening M1a and the removed region 152p overlap each other. That is, the first width W1 may be changed by adjusting the position of the first opening M1a.

In example embodiments, the first mask M1 may be a hard mask pattern. For example, the hard mask pattern may be formed using a material having an etch selectivity with respect to the first passivation layer 152, and a first opening M1a may be formed in the hard mask pattern by performing a photolithography process. Can be formed. In other embodiments, the first mask M1 may be a photoresist pattern having an etch selectivity with the first passivation layer 152.

Referring to FIG. 9, the gate electrode 146 may be formed by filling a first opening M1a by depositing a conductive material on the first mask M1. The gate electrode 146 may be formed on the exposed semiconductor layer stacked structure 120 and the first passivation layer 152 exposed by the first opening M1a to have a gamma shape. In example embodiments, the gate electrode 146 may be formed of a double layer of nickel (Ni) and gold (Au), but the type of the gate electrode 146 is not limited thereto. For example, the gate electrode 146 may be formed by an e-beam evaporation method.

Meanwhile, the lower width of the gate electrode 146 may be adjusted by adjusting the overlapping position of the first passivation layer 152 and the first opening M1a, and thus, more than the minimum width of the opening that may be formed in the mask. It is possible to form a gate electrode having a small line width. The gate electrode 146 may be formed in a gamma shape having a lower width having a first width w1 and an upper width having a second width w2.

Thereafter, the first mask M1 may be removed.

Referring to FIG. 10, a second passivation layer 154 may be formed to cover the gate electrode 146, the source ohmic layer 132, and the drain ohmic layer 134. In this case, the second passivation layer 154 may not only have an upper surface and a side surface of the gate electrode 146, a source ohmic layer 132 and a drain ohmic layer 134, but also an upper surface of the first passivation layer 152 and mesa etching in the foregoing process. To conformally cover the side surfaces of the exposed semiconductor layer stack 120. In example embodiments, the second passivation layer 154 may be formed by spin coating or the like using SU-8 photoresist.

Referring to FIG. 11, a portion of the second passivation layer 154 over the source and drain ohmic layers 132 and 134 may be removed and the top surfaces of the source and drain ohmic layers 132 and 134 may be exposed.

Since the second passivation layer 154 includes the SU-8 photoresist, the exposure and development processes are directly performed on the second passivation layer 154 without the formation of a separate photoresist mask, thereby partially removing the second passivation layer 154. Can be removed. For example, an exposure process may be performed on a portion of the second passivation layer 154, followed by a development process.

Thereafter, a source electrode 142 and a drain electrode 144 may be formed on the exposed source and drain ohmic layers 132 and 134.

Thereafter, a source pad 162 and a drain pad 164 are formed on the source electrode 142 and the drain electrode 144, respectively. In an exemplary method for forming the source pad 162 and the drain pad 164, a connection layer of a titanium / gold (Ti / Au) bilayer structure on the source electrode 142 and the drain electrode 144 (not shown) And a seed layer (not shown) on the connection layer using a process such as sputtering, and then the source pad 162 and the drain pad 164 are formed using a process such as electroplating. Can be formed.

Referring back to FIG. 2, a third passivation layer 156 may be formed to cover the structure in which the source pad 162 and the drain pad 164 are formed. The third passivation layer 156 may be formed using, for example, a SU-8 photoresist. However, the third passivation layer 156 may prevent the device from being oxidized or degraded, and may act as a protective layer to prevent moisture or the like from penetrating into the device.

By performing the above-described processes, the III-V semiconductor device 100 may be completed.

According to the manufacturing method, as the first passivation layer 152 including the SU-8 photoresist, the second passivation layer 154 including the SU-8 photoresist is formed to form a lower semiconductor layer stack structure 120 Physical damage may not occur. Conventionally, in the case of forming a protective layer using an inorganic insulating material such as silicon oxide or silicon nitride, a plasma enhanced chemical vapor deposition (PECVD) process is used in forming the inorganic insulating material. Physical damage to the semiconductor layers may occur when the semiconductor layers, which are the social layers, are exposed to the plasma. In addition, a wet / dry etching or a reactive ion etching process may be used to etch the protective layer of the inorganic insulating material, and chemical or physical damage may be applied to the lower semiconductor layers by an etching gas or an etching solution. However, according to the technical idea of the present disclosure in which the first and second passivation layers 152 and 154 are formed using SU-8 photoresist, the coating or deposition of the SU-8 photoresist material by spin coating, exposure and Patterning of the SU-8 photoresist material layer by a development process may be possible. Accordingly, physical damage to the semiconductor layer stack 120 of the lower portion in the process of forming the first and second passivation layers 152 and 154 may be minimized.

According to the manufacturing method, expensive manufacturing processes such as a plasma enhanced chemical vapor deposition (PECVD) process and a reactive ion etching process, which are required when the protective layer is formed using an inorganic insulating material, are unnecessary. In addition, only one mask in total and three photolithography processes may be performed to complete the group III-V semiconductor device 100 including the gamma-shaped gate electrode 146. Therefore, the manufacturing process cost of the III-V semiconductor device 100 can be reduced.

FIG. 12 is an image illustrating an upper surface of a group III-V semiconductor device completed according to the manufacturing method described with reference to FIGS. 5 to 11.

Referring to FIG. 12, no cracks or damages are observed on the upper surface of the group III-V semiconductor device including the SU-8 photoresist passivation layer, and the group III-V semiconductor device has a very clean surface. . This is because the process using the plasma or the etching process is not used at all in the formation of the SU-8 photoresist passivation layer, so that the lower epitaxial layers (ie, the semiconductor layer stack structure) are exposed to the plasma or etching process. This is because it is fundamentally protected from possible damage.

In contrast, in FIGS. 1A and 1B, when the surface passivation layer is formed using silicon nitride, dark spots and cracks may be generated on the surface of the device.

13A to 13C are graphs illustrating breakdown voltage characteristics of a III-V semiconductor device according to Experimental Examples and Comparative Examples of the present invention. FIG. 13A shows Comparative Example 1 (when no passivation layer is formed), FIG. 13B shows Comparative Example 2 (when a passivation layer is formed using silicon nitride) and FIG. 13C shows an experimental example (using SU-8 photoresist). For the passivation layer), graphs of the drain saturation currents Ids according to the drain-source voltage Vds before and after the stress application by the bias, respectively.

First, referring to FIG. 13A, in Comparative Example 1 in which the passivation layer is not formed, the drain saturation current of about 450 mA / mm is shown before 210_1 while stress is applied (210_2). Shows a drain saturation current of about 420 mA / mm. That is, in the case of Comparative Example 1 in which the passivation layer is not formed, it can be confirmed that the withstand voltage characteristic is not excellent.

Referring to FIG. 13B, in Comparative Example 2 in which a passivation layer of silicon nitride is formed, a high drain saturation current of about 650 mA / mm or more is shown before applying stress (220_1), but after applying stress (220_2) ) Shows a drain saturation current of about 550 mA / mm. That is, in comparison with Comparative Example 1 in which the passivation layer was not formed in Comparative Example 2, the saturation current value itself was considerably high, but after the stress was applied, the saturation current value decreased considerably. If formed, it may be considered to be somewhat vulnerable to stress such as bias. As discussed above, when the passivation layer of an inorganic insulating material such as silicon nitride is formed, it can be confirmed that damage to the device during the formation process may also affect the breakdown voltage characteristic of the device.

Referring to FIG. 13C, in the experimental example of the present invention in which the passivation layer of the SU-8 photoresist is formed, the drain saturation current of about 700 mA / mm is shown before the stress is applied (230_1), and after the stress is applied. (230_2) also showed a drain saturation current of about 690 mA / mm. That is, there was almost no difference between before and after applying the stress, and the highest drain saturation current value was shown even when compared with Comparative Examples 1 and 2. Therefore, it can be seen that the III-V semiconductor device manufactured according to the experimental example of the present invention has excellent breakdown voltage characteristics and can implement a passivation structure that most stably protects the device from the stress applied to the device. .

The technical spirit of the present invention described above is not limited to the above-described embodiment and the accompanying drawings, and various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be apparent to those of ordinary skill in the art.

110: substrate 112: buffer layer
120: semiconductor layer stacked structure 121: first channel layer
122: second channel layer 123: spacer layer
124: channel supply layer 125: capping layer
132: source ohmic layer 134: drain ohmic layer
142: source electrode 144: drain electrode
146: gate electrode 152: first passivation layer
154: second passivation layer 156: third passivation layer
162: source pad 164: drain pad

Claims (6)

A semiconductor layer stack structure disposed on the substrate;
Source and drain electrodes spaced apart from each other on the semiconductor layer stack structure;
A gate electrode disposed between the source electrode and the drain electrode on the semiconductor layer stack structure;
A first passivation layer disposed between the gate electrode and the semiconductor layer stack structure and including a SU-8 photoresist;
A second passivation layer disposed to cover the semiconductor layer stack and the gate electrode, the second passivation layer comprising a SU-8 photoresist;
A source pad and a drain pad respectively formed on the source electrode and the drain electrode; And
And a third passivation layer covering the second passivation layer, the source electrode and the drain electrode, the source pad and the drain pad, and including a SU-8 photoresist.
As the first passivation layer and the second passivation layer include a SU-8 photoresist, a drain current collapse shape and a leakage current in the pinch-off state and a breakdown voltage characteristic between the source and the drain are reduced. Prevent,
The third passivation layer prevents the exposed components of the source pad and the drain pad from being damaged by mechanical shock or moisture from the outside,
The gate electrode is in contact with the semiconductor layer stack structure and has a first width W1 and a second width W2 disposed above the first portion and larger than the first width W1. A second portion having:
The first passivation layer is in contact with a side surface of the first portion of the gate electrode,
The source electrode extends over the gate electrode so that the source electrode and the gate electrode overlap, and the second passivation layer is interposed between the gate electrode and the source electrode. Semiconductor device. delete The method of claim 1,
And the second passivation layer surrounds top and side surfaces of the second portion of the gate electrode. The method of claim 1,
The gate electrode has a gamma shape having a lower width having a first width W1 and an upper width having a second width w2, and having a gamma shape having a larger upper width W2 than the lower width W1. It is a gamma gate electrode which has a III-V group semiconductor element. The method of claim 1,
The gate electrode is a group III-V semiconductor device, characterized in that the upper width (W2) is a T-type gate electrode having a T shape larger than the lower width (W1). delete

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