KR102058045B1 - Motor driver and air conditioner including the same - Google Patents

Abstract

According to an aspect of the present invention, provided are a motor driving device and an air conditioner including the same. The motor driving device has a plurality of inverters corresponding to a plurality of motors and controls the plurality of motors to be connected to each other and driven by setting one motor as a reference inverter and the other motor as a connected inverter in a certain section within a switching cycle. When the motor is driven as the reference inverter to correspond to an output error occurring when driven as the connected inverter, output of a voltage command value is compensated so as to control the plurality of motors to be stably driven.

Description

Motor drive device and air conditioner having same {Motor driver and air conditioner including the same}

The present invention relates to a motor drive device and an air conditioner having the same, and more particularly, a motor drive device and an air conditioner having the same that can effectively reduce electromagnetic interference noise when driving a plurality of motors in conjunction. It is about the flag.

The air conditioner is installed to provide a more comfortable indoor environment for humans by discharging cold air into the room to adjust the indoor temperature and purifying the indoor air to create a comfortable indoor environment. In general, an air conditioner includes an indoor unit which is configured as a heat exchanger and installed indoors, and an outdoor unit which is configured as a compressor and a heat exchanger and supplies refrigerant to the indoor unit.

On the other hand, the motor drive device is a device for driving a motor having a rotor and a stator coiled in the rotational movement, it can be used to drive a motor in a home appliance such as an air conditioner. For example, to drive a compressor of an air conditioner, a compressor motor drive device, a fan motor drive device may be used to drive a fan.

Meanwhile, according to IEC 61000, which is an international surge protection standard, a standard for reducing harmonics is set. Accordingly, various efforts have been made to reduce harmonics due to an input AC current in a motor driving device. For example, the prior document (Korean Patent Laid-Open Publication No. 2003-0026211) includes a circuit for frequency modulation phase delay separately according to a switching frequency change in order to reduce electromagnetic noise.

Disclosure of Invention An object of the present invention is to provide a motor driving device capable of efficiently reducing electromagnetic interference (EMI) noise and an air conditioner having the same.

An object of the present invention is to provide a motor drive device and an air conditioner having the same that can efficiently reduce the EMI noise when driving a plurality of motors in conjunction.

An object of the present invention is to provide a motor drive device and an air conditioner having the same that can drive a plurality of motors in a stable interlock.

An object of the present invention to provide a motor drive device and an air conditioner having the same that can reduce the leakage current through the common mode noise reduction.

In order to achieve the above or another object, a motor driving apparatus and an air conditioner having the same according to an aspect of the present invention includes a plurality of inverters corresponding to a plurality of motors, and any one motor in a predetermined period within a switching period. By setting it as a reference inverter and setting the other inverters as the interlocking inverter, the plurality of motors may be controlled to be driven in conjunction with each other.

In order to achieve the above or another object, the motor driving device and the air conditioner having the same according to an aspect of the present invention compensate for the output of the voltage command value when driven by the reference inverter to correspond to the output error generated when driven by the interlocking inverter. By doing so, it is possible to control the plurality of motors to be driven stably.

In order to achieve the above or another object, a motor driving apparatus and an air conditioner having the same according to an aspect of the present invention operate by managing a phase difference between a voltage vector for driving a reference inverter and a voltage vector for driving an interlocking inverter. The occurrence of errors due to control can be minimized.

In order to achieve the above or another object, a motor driving device and an air conditioner having the same according to an aspect of the present invention operate based on a common input AC power source, and include: a first driving the first motor and the second motor, respectively; And an inverter controller for controlling the first inverter and the second inverter by an inverter, a second inverter, and a pulse vector variable control based on a space vector. The inverter controller includes the first and second inverters in a first half cycle of a switched cycle. A first inverter is set as a reference inverter, the second inverter is set as a linked inverter driven in conjunction with the reference inverter, and the first inverter is set as the linked inverter at a second half cycle that is a next half cycle of the first half cycle. And setting the second inverter as the reference inverter, and corresponding to an output error generated in a half cycle driven by the interlocking inverter. The first inverter and the second inverter may be controlled by compensating the output of the voltage command value in the half cycle driven by the reference inverter. Accordingly, it is possible to control the plurality of motors to be driven stably.

In order to achieve the above or another object, a motor driving device and an air conditioner having the same according to an aspect of the present invention operate based on a common input AC power source, and include: a first driving the first motor and the second motor, respectively; And an inverter controller for controlling the first inverter and the second inverter by an inverter, a second inverter, and a pulse vector variable control based on a space vector. The inverter controller includes the first and second inverters in a first half cycle of a switched cycle. A first inverter is set as a reference inverter, the second inverter is set as a linked inverter driven in conjunction with the reference inverter, and the first inverter is set as the linked inverter at a second half cycle that is a next half cycle of the first half cycle. And setting the second inverter as the reference inverter, and driving the voltage vector and the interlocking inverter to drive the reference inverter. The phase difference between the voltage vectors can be controlled nadorok 60 degrees. Accordingly, it is possible to minimize the occurrence of errors due to the interlocking control.

In addition, the inverter control unit generates a first voltage vector to control the reference inverter, the polarity of the level of the first noise generated in the first motor, and the level of the second noise generated in the second motor. EMI noise can be effectively reduced by generating a second voltage vector such that the polarity is reversed and controlling the interlocking inverter driven in conjunction with the reference inverter.

The inverter controller may generate a first voltage vector for driving the reference inverter to control the reference inverter, and when one of the three phase phase-arm switching elements of the reference inverter is turned on, When one of the three-phase phase arm switching elements of the interlocking inverter is turned off, and when any one of the three-phase phase arm switching elements of the reference inverter is turned off, the three-phase phase arm switching element of the interlocking inverter EMI noise can be effectively reduced by generating a second voltage vector such that any one of the switching elements is turned on and controlling the interlocking inverter.

The inverter controller may synchronize the switching period of the first inverter with the switching period of the second inverter.

The inverter control unit may include a voltage command generation unit for generating the voltage command value, an axis conversion unit for transforming the output of the voltage command generation unit, and an output error generated in a half cycle driven by the interlocking inverter to the output of the axis conversion unit. The switching control signal output unit may output a reference inverter switching control signal according to a pulse width modulation (PWM) method based on the compensation voltage command value in which corresponding compensation voltage values are added.

The switching control signal output unit may output a pulse width modulation (PWM) switching signal based on a compensation voltage command value obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlock inverter to the output of the axis converter. A duty generator configured to shift a pulse width modulation (PWM) switching signal generated by the duty generator in a half cycle driven by the interlocked inverter; and based on an output of the duty converter. It may include a voltage compensation unit for generating a compensation voltage value.

The voltage compensator may generate the compensation voltage value by multiplying a reference voltage value by a value obtained by subtracting the output of the duty converter from the output of the duty generator. For example, the reference voltage value may be a dc terminal voltage.

According to at least one of the embodiments of the present invention, EMI noise can be efficiently reduced.

According to at least one of the embodiments of the present invention, EMI noise can be efficiently reduced when driving a plurality of motors in conjunction.

In addition, according to at least one of the embodiments of the present invention, the motor can be stably driven by compensating or minimizing an error due to the interlocking control.

In addition, according to at least one of the embodiments of the present invention, leakage current may be reduced through common mode noise reduction.

In addition, according to at least one of the embodiments of the present invention, even if each inverter drives different loads, there is an advantage that the interlock control is possible.

On the other hand, various other effects will be disclosed directly or implicitly in the detailed description according to the embodiment of the present invention to be described later.

1 is a diagram illustrating a configuration of an air conditioner according to an embodiment of the present invention.
2 is a schematic diagram of the outdoor unit and the indoor unit of FIG. 1.
3A is an internal block diagram of a motor drive device related to the present invention.
FIG. 3B is a diagram referred to for describing the operation of FIG. 3A.
4 is an internal block diagram of a motor driving apparatus according to an embodiment of the present invention.
5A and 5B are diagrams illustrating an internal block diagram of the inverter controller of FIG. 4.
6 to 10 are views for reference to the operation of the motor drive apparatus according to an embodiment of the present invention.
11 is a view referred to for describing an error that may occur in the interlocking control according to an embodiment of the present invention.
12 to 17 are views referred to for describing an error compensation method according to an embodiment of the present invention.
18A to 18D are diagrams illustrating phase currents measured in interlocking control according to an exemplary embodiment of the present invention.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention; However, the present invention is not limited to these embodiments and may be modified in various forms.

On the other hand, the suffixes "module" and "unit" for the components used in the following description are merely given in consideration of ease of preparation of the present specification, and do not give particular meanings or roles by themselves. Therefore, the "module" and "unit" may be used interchangeably.

Further, in this specification, terms such as first and second may be used to describe various elements, but such elements are not limited by these terms. These terms are only used to distinguish one element from another.

1 is a diagram illustrating a configuration of an air conditioner according to an embodiment of the present invention.

Referring to FIG. 1, the air conditioner 50 according to an embodiment of the present invention may include a plurality of units. For example, the air conditioner 50 according to an embodiment of the present invention includes the indoor units 31 to 35, the outdoor units 21 and 22 connected to the indoor units 31 to 35, and the indoor units 31. 35) to a remote controller 41 to 45 connected to each. And the air conditioner 50 according to an embodiment of the present invention may further include a central controller 10 for controlling the plurality of indoor units (31 to 35) and the outdoor units (21, 22).

The central controller 10 may be connected to the plurality of indoor units 31 to 36 and the plurality of outdoor units 21 and 22 to monitor and control the operation thereof. In this case, the central controller 10 may be connected to a plurality of indoor units to perform operation setting, lock setting, schedule control, group control, and the like for the indoor units.

The air conditioner may be any one of a stand type air conditioner, a wall-mounted air conditioner, and a ceiling type air conditioner, but for convenience of description, a ceiling type air conditioner will be described as an example. The air conditioner may further include at least one of a ventilator, an air cleaner, a humidifier, and a heater, and may operate in conjunction with the operation of the indoor unit and the outdoor unit.

The outdoor units 21 and 22 are compressors (not shown) for receiving and compressing a refrigerant, an outdoor heat exchanger (not shown) for exchanging refrigerant and outdoor air, and an accumulator for extracting gas refrigerant from the supplied refrigerant and supplying the compressor to the compressor. (Not shown) and a four-way valve (not shown) for selecting a flow path of the refrigerant according to the heating operation. In addition, it may further include a plurality of sensors, valves and oil recovery.

The outdoor units 21 and 22 operate the compressor and the outdoor heat exchanger provided to supply or cool the refrigerant to the indoor units 31 to 35 by compressing or exchanging the refrigerant according to a setting.

The outdoor units 21 and 22 are driven by the request of the central controller 10 or the indoor units 31 to 35, and as the cooling / heating capacity is changed in response to the driven indoor units, the number of operation of the outdoor unit and the compressor installed in the outdoor unit The number of operations is variable.

In this case, the outdoor units 21 and 22 are described on the basis of supplying a refrigerant to a plurality of outdoor units, respectively, to the connected indoor units, but a plurality of outdoor units are connected to each other according to the connection structure of the outdoor unit and the indoor units, and the refrigerant to the plurality of indoor units. May be supplied.

The indoor units 31 to 35 are connected to any one of the plurality of outdoor units 21 and 22, and receive coolant to discharge cold air. The indoor units 31 to 35 include an indoor heat exchanger (not shown), an indoor fan (not shown), an expansion valve (not shown) for expanding the supplied refrigerant, and a plurality of sensors (not shown).

At this time, the outdoor unit (21, 22) and the indoor unit (31 to 35) are connected by a communication line to transmit and receive data, and the outdoor unit and the indoor unit is connected to the central controller 10 by a separate communication line to control the central controller (10). It works accordingly.

The remote controllers 41 to 45 may be connected to indoor units, respectively, to input a user's control command to the indoor unit, and receive and display state information of the indoor unit. In this case, the remote controller communicates by wire or wirelessly according to the connection type with the indoor unit. In some cases, one remote controller is connected to the plurality of indoor units, and the setting of the plurality of indoor units may be changed through one remote controller input.

2 is a schematic diagram of the outdoor unit and the indoor unit of FIG. 1.

Referring to FIG. 2, the air conditioner 50 is largely divided into an indoor unit 31 and an outdoor unit 21.

The indoor unit 31 is an indoor side heat exchanger 108 that is disposed indoors to perform a cooling / heating function, and an indoor fan 109a that is disposed on one side of the indoor side heat exchanger 108 to promote heat dissipation of the refrigerant, and an indoor unit. And an indoor blower 109 composed of an electric motor 109b for rotating the fan 109a.

At least one indoor side heat exchanger 108 may be installed. The compressor 102 may be at least one of an inverter compressor and a constant speed compressor.

In addition, the air conditioner 50 may be configured as a cooler for cooling the room, or may be configured as a heat pump for cooling or heating the room.

The outdoor unit 21 includes a compressor 102 that serves to compress the refrigerant, a compressor electric motor 102b that drives the compressor, an outdoor side heat exchanger 104 that serves to radiate the compressed refrigerant, and an outdoor unit. An outdoor blower 105 disposed at one side of the heat exchanger 104 and including an outdoor fan 105a for promoting heat dissipation of the refrigerant and an electric motor 105b for rotating the outdoor fan 105a, and an expansion for expanding the condensed refrigerant; A mechanism 106, a cooling / heating switching valve 110 for changing a flow path of a compressed refrigerant, and an accumulator 103 for temporarily storing a gasified refrigerant to remove moisture and foreign matter and then supplying a refrigerant having a constant pressure to the compressor. And the like.

Meanwhile, although one indoor unit 31 and one outdoor unit 21 are shown in FIG. 2, the driving device of the air conditioner according to the embodiment of the present invention is not limited thereto, and the multi-type unit includes a plurality of indoor units and outdoor units. Applicable to the air conditioner, an air conditioner having a single indoor unit and a plurality of outdoor units, of course.

The compressor 102 in the outdoor unit 21 of FIG. 1 may be driven by a motor driving apparatus (200 of FIG. 4) for driving a compressor driving the compressor motor 250.

Alternatively, the indoor fan 109a in the indoor unit 31 of FIG. 1 may be driven by a motor driving device (200 of FIG. 4) for driving the indoor fan 109a for driving the indoor fan motor 109b.

Alternatively, the outdoor fan 105a in the outdoor unit 21 of FIG. 1 may be driven by a motor driving device (200 of FIG. 4) for driving the outdoor fan 105a for driving the outdoor fan motor 105b.

FIG. 3A is an internal block diagram of the motor driving apparatus according to the present invention, and FIG. 3B is a view referred to for describing the operation of FIG. 3A.

First, referring to FIG. 3A, the motor driving device 200x of FIG. 3A is characterized in that a plurality of motors are driven in parallel.

To this end, the motor driving apparatus 200x of FIG. 3A includes a first inverter 220ax and a second motor that output an alternating current to the first motor 250ax, the second motor 250bx, and the first motor 250ax. The second inverter 220bx for outputting an alternating current to 250bx, the first inverter controller 230ax for controlling the first inverter 220ax, and the second inverter controller 230bx for controlling the second inverter 220bx. It can be provided.

In addition, the motor driving device 200x may include a converter 210x that operates to supply a common DC power supply to the first inverter 220ax and the second inverter 220bx.

According to the motor drive device 200x of FIG. 3A, the first inverter control unit 230ax and the second inverter control unit 230bx control the first inverter 220ax and the second inverter 220bx, respectively.

Meanwhile, FIG. 3B (a) illustrates common mode noise (Nsix) at an input terminal which is the front end of the converter 210x of the motor driving device 200x of FIG. 3A, and FIG. 3B (b). ) Illustrates common mode noise Nscx in the first motor 250ax of FIG. 3A, and FIG. 3B (c) illustrates common mode noise Nsfx in the second motor 250bx of FIG. 3A. To illustrate.

According to FIG. 3B, the common mode noise Nscx at the first motor 250ax and the second motor 250bx are caused by the first inverter 220ax and the second inverter 220bx, which are driven to each other. The common mode noise Nsfx is summed to appear as common mode noise Nsix at the input terminal.

On the other hand, the common mode noise Nscx in the first motor 250ax may be due to the leakage current isax leaking from the first motor 250ax, and the common mode noise (Nscx) in the second motor 250bx Nsfx may be due to leakage current Isbx leaking from the second motor 250bx.

Due to the common mode noise Nsix, which is a harmonic component at the input terminal, the durability of the internal circuit element may be weakened, and the power conversion efficiency may be lowered.

Accordingly, the present invention proposes a method for reducing common mode noise during parallel driving of a motor. This will be described with reference to FIG. 4 and below.

4 is an internal block diagram of a motor driving apparatus according to an embodiment of the present invention.

Referring to the drawings, the motor drive device 200 of FIG. 4 is characterized in that a plurality of motors are driven in parallel.

To this end, the motor driving apparatus 200 may include a first inverter 220a and a second motor 250b that output an alternating current to the first motor 250a, the second motor 250b, and the first motor 250a. The second inverter 220b for outputting an alternating current may be provided.

In addition, the motor driving device 200 may include a converter 210 that operates to supply a common DC power to the first inverter 220a and the second inverter 220b.

The converter 210 converts the commercial AC power supply 201 which passed through the reactor L into DC power, and outputs it. The commercial AC power supply 201 may be a single phase AC power or a three phase AC power. The internal structure of the converter 210 also varies according to the type of the commercial AC power supply 201.

On the other hand, the converter 210 may be made of a diode or the like without a switching element, and may perform a rectifying operation without a separate switching operation.

For example, in the case of a single-phase AC power supply, four diodes may be used in the form of a bridge, and in the case of a three-phase AC power supply, six diodes may be used in the form of a bridge.

The converter 210 may be, for example, a half bridge type converter in which two switching elements and four diodes are connected. In the case of a three-phase AC power supply, six switching elements and six diodes may be used. .

When the converter 210 includes a switching element, the boosting operation, power factor improvement, and DC power conversion may be performed by the switching operation of the switching element.

The dc stage capacitors C1 and C2 smooth and store the input power. In the figure, nodes between the dc stage capacitors C1 and C2 are shown as n nodes.

On the other hand, since the DC power is stored in both ends of the dc terminal capacitors C1 and C2, this may be referred to as a dc terminal or a dc link terminal.

The dc stage voltage detectors Ba and Bb may detect the dc stage voltage Vdc, which is both ends of the dc stage capacitors C1 and C2. To this end, the dc terminal voltage detectors Ba and Bb may include a resistor, an amplifier, and the like. The detected dc terminal voltage Vdc may be input to the inverter controller 230 as a discrete signal in the form of a pulse.

The input voltage detector A can detect the input voltage Vs from the input AC power supply 201.

The input voltage detector A may include a resistor, an OP AMP, or the like for voltage detection. The detected input voltage Vs may be applied to the inverter controller 230 as a discrete signal in the form of a pulse.

On the other hand, the input voltage detector A can also detect the zero crossing point of the input voltage.

Next, the input current detector D can detect the input current Is from the input AC power supply 201. Specifically, in front of the converter 210, it may be located.

The input current detector D may include a current sensor, a current trnasformer (CT), a shunt resistor, or the like for current detection. The detected input voltage Is may be applied to the inverter controller 230 as a discrete signal in the form of a pulse.

Each of the first inverter 220a and the second inverter 220b includes a plurality of inverter switching elements, and converts the DC power smoothed by the on / off operation of the switching element into an AC power source having a predetermined frequency, and thus, the first inverter 220a and the second inverter 220b. Output to the motor 250a and the second motor 250b.

The inverter controller 230 may output the first inverter switching control signal Sica to the first inverter 220a in order to control the switching operation of the first inverter 220a. The first inverter switching control signal Sica is a switching control signal of the pulse width modulation method PWM, and outputs an output current ioa flowing through the first motor 250a or a first dc terminal voltage that is both ends of the first dc terminal capacitor. Vdca) may be generated and output. In this case, the output current ioa may be detected from the first output current detector Ea, and the first dc terminal voltage Vdca may be detected from the first dc terminal voltage detector Ba.

The inverter controller 230 may output the second inverter switching control signal Sicb to the second inverter 220b in order to control the switching operation of the second inverter 220b. The second inverter switching control signal Sicb is a switching control signal of the pulse width modulation method PWM, and outputs an output current iob flowing through the second motor 250b or a second dc terminal voltage that is opposite the second dc terminal capacitor. Vdcb) can be generated and output. At this time, the output current iob may be detected from the second output current detector Eb, and the second dc terminal voltage Vdcb may be detected from the second dc terminal voltage detector Bb.

The first output current detector Ea may detect the output current ioa flowing between the first inverter 220a and the first motor 250a. That is, the current flowing through the first motor 250a is detected. The detected output current ioa may be applied to the inverter controller 230.

The second output current detector Eb may detect the output current iob flowing between the second inverter 220b and the second motor 250b. That is, the current flowing through the second motor 250b is detected. The detected output current iob may be applied to the inverter controller 230.

On the other hand, each of the first motor 250a and the second motor 250b includes a stator and a rotor, and each phase of a predetermined frequency is applied to the coils of the stators of the phases (a, b, and c). AC power is applied to the rotor to rotate.

The first motor 250a and the second motor 250b include, for example, a surface-mounted permanent magnet synchronous motor (SMPMSM) and an embedded permanent magnet synchronous motor (SM). Synchronous Motor (IPMSM), Synchronous Reluctance Motor (Synrm), and the like. Of these, SMPMSM and IPMSM are permanent magnet synchronous motors (PMSMs) with permanent magnets, and synrms have no permanent magnets.

On the other hand, the motor drive device 200 according to an embodiment of the present invention, a method for reducing the harmonics, in particular common mode noise generated by the input AC power, in parallel driving of the motor (250a, 250b).

Meanwhile, the common mode noise may be generated by asynchronous driving of the first motor 250a and the second motor 250b. Accordingly, in the present invention, in order to reduce the common mode noise caused by the first motor 250a and the second motor 250b, the first motor 250a and the second motor 250b are synchronously driven. Present a plan.

To this end, the inverter controller 230 in the motor driving apparatus 200 according to the exemplary embodiment of the present invention controls the first inverter 220a and the second inverter 220b in common.

In addition, the inverter controller 230 according to an exemplary embodiment of the present invention may include the polarity of the level of the first noise generated by the first motor 250a and the level of the second noise generated by the second motor 250b. By controlling the polarity to be reversed, common mode noise can be efficiently reduced during parallel driving of a plurality of motors.

In particular, the inverter controller 230 controls the sum of the first leakage current isa leaked from the first motor 250a and the second leakage current isb leaked from the second motor 250b to be the minimum. By doing this, common mode noise can be efficiently reduced during parallel driving of a plurality of motors.

Meanwhile, the n node, which is a node between the dc terminal capacitors C1 and C2, shown in FIG. 4, the nodes a1, b1, and c1, which are output terminals of the first inverter 220a, and an internal neutral point of the first motor 250a. By (s1), the relationship between the pole voltages Va1n, Vb1n, Vc1n, the phase voltages Va1s1, Vb1s1, Vc1s1, and the offset voltage Vs1n1 can be formed as shown in Equation 1 below.

Meanwhile, the n node, which is a node between the dc terminal capacitors C1 and C2, shown in FIG. 4, the nodes a2, b2 and c2, which are output terminals of the second inverter 220b, and an internal neutral point of the second motor 250b. By (s2), a relationship between the extreme voltages Va2n, Vb2n and Vc2n, the phase voltages Va2s2, Vb2s2 and Vc2s2, and the offset voltage Vs2n2 can be formed as shown in Equation 2 below.

In the motor drive device 200x of FIG. 3A, the common mode noise Nsix includes the polarity of the first offset voltage Vs1n1a of the first motor 250a and the second offset voltage of the second motor 250b. If the polarities of Vs2n2a are the same, the common mode noise Nsix tends to be amplified as shown in FIG. 3B (a).

Accordingly, the inverter controller 230 according to the exemplary embodiment of the present invention may include the polarity of the first offset voltage Vs1n1a of the first motor 250a and the polarity of the second offset voltage Vs2n2a of the second motor 250b. This control is made to be opposite to each other. As a result, common mode noise can be efficiently reduced during parallel driving of a plurality of motors.

On the other hand, the inverter controller 230 synchronizes the switching cycle of the first inverter 220a and the switching cycle of the second inverter 220b, and corresponds to the switching timing of the first inverter 220a so as to correspond to the switching timing of the first inverter 220a. By controlling the switching timing of 220b to be variable, common mode noise can be efficiently reduced during parallel driving of a plurality of motors.

The inverter controller 230 may control the first inverter 220a and the second inverter 220b to operate in synchronization by synchronizing switching cycles.

The inverter controller 230 may shift a switching control signal according to a pulse width modulation (PWM) method applied to the first inverter 220a or the second inverter 220b in order to reduce common mode noise. have.

That is, the switching control signal output unit 360 may reduce the common mode noise by changing the switching timing of any one of the pulse width modulation (PWM) switching patterns. The inverter controller 230 may shift any one pulse width modulation (PWM) switching pattern so that the noise of the first motor 250a and the second motor 250b is canceled. For example, the common mode noise is reduced by shifting one pulse width modulation (PWM) switching pattern so that the on and off operations of the switching elements of the first inverter 220a and the second inverter 220b are reversed. can do.

5A and 5B are diagrams illustrating an internal block diagram of the inverter controller of FIG. 4.

Referring to FIG. 5A, the inverter controller 230 may include an axis converter 310, a speed calculator 320, a current command generator 330, a voltage command generator 340, an axis converter 350, and The switching control signal output unit 360 may be included.

The axis converter 310 receives the three-phase output currents (iaa, iba, ica or iab, ibb, icb) detected by the first and second output current detectors Ea and Eb, and the two-phase current of the stationary coordinate system. Convert to (iα, iβ).

On the other hand, the axis conversion unit 310 can convert the two-phase current (iα, iβ) of the stationary coordinate system into the two-phase current (id, iq) of the rotary coordinate system.

)를 추정한다. 또한, 추정된 회전자 위치(

)에 기초하여, 연산된 속도(

)를 출력할 수 있다.The speed calculating unit 320 is based on the two-phase currents iα and iβ of the stationary coordinate system converted by the axis converting unit 310, and thus the rotor position of the motor 250 (

Estimate). In addition, the estimated rotor position (

Based on the calculated velocity (

) Can be printed.

)와 목표 속도(ω)에 기초하여, 속도 지령치(ω^* _r)를 연산하며, 속도 지령치(ω^* _r)에 기초하여, 전류 지령치(i^* _q)를 생성한다. 예를 들어, 전류 지령 생성부(330)는, 연산 속도(

)와 목표 속도(ω)의 차이인 속도 지령치(ω^* _r)에 기초하여, PI 제어기(435)에서 PI 제어를 수행하며, 전류 지령치(i^* _q)를 생성할 수 있다. 도면에서는, 전류 지령치로, q축 전류 지령치(i^* _q)를 예시하나, 도면과 달리, d축 전류 지령치(i^* _d)를 함께 생성하는 것도 가능하다. 한편, d축 전류 지령치(i^* _d)의 값은 0으로 설정될 수도 있다. On the other hand, the current command generation unit 330 has a calculation speed (

) And the speed command value ω ^* _r based on the target speed ω and a current command value i ^* _q based on the speed command value ω ^* _r . For example, the current command generation unit 330 has a calculation speed (

PI control may be performed by the PI controller 435 based on the speed command value ω ^* _r , which is a difference between the target speed ω and the target speed ω. The current command value i ^* _q may be generated. In the drawing, although the q-axis current command value i ^* _q is illustrated as a current command value, it is also possible to generate | generate a d-axis current command value i ^* _d unlike a figure. On the other hand, the value of the d-axis current command value i ^* _d may be set to zero.

On the other hand, the current command generation unit 330 may further include a limiter (not shown) for restricting the level so that the current command value i ^* _q does not exceed the allowable range.

Next, the voltage command generation unit 340 includes the d-axis and q-axis currents i _{d and} i _q which are axis-converted in the two-phase rotational coordinate system by the axis conversion unit, and the current command value in the current command generation unit 330 or the like. Based on i ^* _{d and} i ^* _q ), d-axis and q-axis voltage command values v ^* _d and v ^* _q are generated. For example, the voltage command generation unit 340 performs the PI control in the PI controller 344 based on the difference between the q-axis current i _q and the q-axis current command value i ^* _q , and q The axial voltage setpoint v ^* _q can be generated. In addition, the voltage command generation unit 340 performs the PI control in the PI controller 348 based on the difference between the d-axis current i _d and the d-axis current command value i ^* _d , and the d-axis voltage. The setpoint (v ^* _d ) can be generated. On the other hand, the value of the d-axis voltage command value v ^* _d may be set to 0, corresponding to the case where the value of the d-axis current command value i ^* _d is set to zero.

On the other hand, the voltage command generation unit 340 may further include a limiter (not shown) for restricting the level so that the d-axis and q-axis voltage command values (v ^* _d , v ^* _q ) do not exceed the allowable range. .

On the other hand, the generated d-axis and q-axis voltage command values v ^* _d and v ^* _q are input to the axis conversion unit 350.

)와, d축, q축 전압 지령치(v^* _d, v^* _q)를 입력받아, 축변환을 수행한다.The axis conversion unit 350 may be a position calculated by the speed calculating unit 320 (

), And the d-axis and q-axis voltage command values (v ^* _d , v ^* _q ) are input, and axis conversion is performed.

)가 사용될 수 있다.First, the axis conversion unit 350 converts from a two-phase rotation coordinate system to a two-phase stop coordinate system. At this time, the position calculated by the speed calculating unit 320 (

) Can be used.

In addition, the axis conversion unit 350 performs a transformation from the two-phase stop coordinate system to the three-phase stop coordinate system. Through this conversion, the axis conversion unit 350 outputs the three-phase output voltage command values v ^* a, v ^* b, v ^* c.

The switching control signal output unit 360 may include the first and second inverter switching control signals according to the pulse width modulation (PWM) method based on the three-phase output voltage command values v ^* a, v ^* b, and v ^* c. Sica, Sicb) can be generated and output.

The output inverter switching control signal Sic may be converted into a gate driving signal by a gate driver (not shown) and input to gates of the respective switching elements in the first and second inverters 220a and 220b. As a result, each of the switching elements Sa, S'a, Sb, S'b, Sc, and S'c in the first and second inverters 220a and 220b performs a switching operation.

In some embodiments, the inverter controller 230 may operate the first inverter 220a or the second inverter 220b by synchronizing switching cycles to operate the first inverter 220a or the first inverter 220a. The common mode noise may be reduced by changing the switching time point of any one of the pulse width modulation (PWM) switching patterns applied to the inverter 220b.

For example, the common mode noise is reduced by shifting one pulse width modulation (PWM) switching pattern so that the on and off operations of the switching elements of the first inverter 220a and the second inverter 220b are reversed. can do.

However, the switching timing of the switching elements of the first inverter 220a and the second inverter 220b may not coincide in the actual control process.

In addition, in the interlocking control of the first inverter 220a and the second inverter 220b, one inverter set as the reference inverter is controlled by the original intended voltage vector, but the interlock inverter operating in conjunction with the reference inverter is referred to as the reference inverter. Depending on the switching timing of the inverter may be switched to reduce the common mode noise.

Errors may occur while the two inverters operate in conjunction with each other. In particular, when the inverter operates as a linked inverter, an output error and a voltage error may occur. Therefore, it is more preferable to replace or supplement the control method of shifting the pulse width modulation (PWM) switching pattern to compensate for the error.

The motor driving apparatus 200 and the air conditioner 50 having the same according to an embodiment of the present invention include a plurality of inverters corresponding to the plurality of motors, and the motor driving apparatus 200 includes a plurality of inverters in a predetermined period within a switching period. By setting the driving inverter as the reference inverter and the inverter driving the remaining motors as the interlocking inverter, the plurality of motors may be controlled to be driven in conjunction with each other. After that, the same inverter can be controlled by changing the inverter set as the reference inverter.

In particular, in the case of using two inverters, one switching period may be divided into two switching half cycles to alternately set a reference inverter in each switching half cycle.

The inverter controller 230 may generate a first voltage vector to control the reference inverter, and control the interlocked inverter with a second voltage vector 180 degrees out of phase with the first voltage vector.

In addition, the inverter controller 230 generates a first voltage vector to control the reference inverter, the polarity of the level of the first noise generated by the first motor 250a, and the second motor 250b. The second voltage vector may be generated such that the polarity of the level of the second noise generated by the second polarity is reversed to control the interlocking inverter driving in conjunction with the reference inverter.

In addition, the inverter controller 230 generates a first voltage vector for driving the reference inverter to control the reference inverter, and any one of three-phase phase-arm switching elements of the reference inverter is turned on. When the switching element of any one of the three-phase phase arm switching element of the interlocking inverter is turned off, and the switching element of any one of the three-phase phase arm switching element of the reference inverter is turned off, The interlocking inverter may be controlled by generating a second voltage vector such that any one of the phase arm switching elements is turned on.

According to an embodiment of the present invention, by compensating the output of the voltage command value when driven by the reference inverter to correspond to the output error generated when driven by the interlocking inverter, it is possible to control the plurality of motors to be driven stably.

To this end, the switching control signal output unit 360 may output a voltage compensation value corresponding to an output error generated when the predetermined inverter is driven by the reference inverter, when the inverter is driven by the interlocked inverter in the previous switching period (v). ^* a, v ^* b, v ^* c) can be added to compensate the output of the voltage setpoint.

Accordingly, when two or more inverters are controlled by setting the reference inverter and the interlocking inverter, and controlling the inverter set as the reference inverter while controlling the inverter, the output error that may occur can be compensated by the voltage compensation method, and more stable and accurate. Interlocking control is possible.

5B illustrates a portion of an internal block diagram of the inverter controller 230 according to an embodiment of the present invention.

5A and 5B, the inverter controller 230 according to an embodiment of the present invention coordinates the output of the voltage command generator 340 and the voltage command generator 340 to generate a voltage command value. A pulse width modulation (PWM) method based on the compensation voltage command value obtained by adding the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis converter 350 and the axis converter 350. It may include a switching control signal output unit 360 for outputting a reference inverter switching control signal according to.

According to the exemplary embodiment of the present invention, the switching control signal output unit 360 includes a compensation voltage obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlocking inverter to the output of the axis conversion unit 350. The duty generator 361 generates a pulse width modulation (PWM) switching signal based on the command value, and outputs the pulse width modulation (PWM) switching signal generated by the duty generator 361 in a half cycle driven by the interlock inverter. The duty converter 362 may be configured to shift, and a voltage compensator 363 may be configured to generate the compensation voltage value based on the output of the duty converter 362.

According to an embodiment, the inverter control unit 230 according to an embodiment of the present invention is the number corresponding to the number of inverter voltage command generation unit 340, axis conversion unit 350, the switching control signal illustrated in Figure 5b The output unit 360 may be provided.

For example, when the first inverter 220a and the second inverter 220b are used, at least a portion of the voltage command generator 340, the axis converter 350, and the switching control signal output unit 360 may be modified. Each of the inverters 200a and 200b may be controlled by providing a pair.

The voltage command generation unit 340 may generate the d-axis and q-axis voltage command values vsd and vsq based on the current command value.

The generated d-axis and q-axis voltage command values vsd and vsq are input to the axis conversion unit 350.

5A and 5B, the axis converter 350 may perform axis conversion based on inputs from the speed calculator 320 and the voltage command generator 340.

The axis conversion unit 350 performs a transformation from the two-phase rotation coordinate system to the two-phase stationary coordinate system, and performs a transformation from the two-phase stationary coordinate system to the three-phase stationary coordinate system. Through this conversion, the axis conversion unit 1050 outputs the three-phase output voltage command values (va, vb, vc).

On the other hand, the three-phase output voltage command value (va, vb, vc) output from the axis converter 350 may be added to the compensation voltage value (vx_error) corresponding to the output error generated in the half cycle driven by the interlocking inverter.

The duty generator 361 is configured to output errors generated in a half cycle driven by a linked inverter to the three-phase output voltage command values va, vb, and vc output from the axis converter 350 when the corresponding inverter is driven as a reference inverter. The PWM switching signals Ta, Tb, and Tc for switching the plurality of switching elements may be generated based on the compensation voltage command values va ', vb', and vc 'summed with the corresponding compensation voltage values vx_error.

For example, the duty Ta for the a-phase switch may be determined by the ratio of the voltage command value va or va 'and the maximum value vdc.

ex) Tx = vx / vdc

On the other hand, the inverter controller 230 according to an embodiment of the present invention may further include a limiter 371 for limiting the level of the voltage command value. Referring to FIG. 5B, a limiter 371 that limits the level of the three compensation voltage setpoints va ', vb', and vc 'does not exceed an allowable range may be arranged to receive an input of the axis converter 350. have.

For example, the limiter 371 sets the dc terminal voltage vdc to the limit level, and outputs vdc when the compensation voltage setpoints va ', vb', and vc 'are greater than vdc, and is smaller than -vdc. In that case, you can print -vdc.

The limiter 371 may output the leveled compensation voltage command values va ', vb', and vc '. If the compensation voltage setpoints (va ', vb', vc ') do not exceed the limit, they will be output as is.

The limiter for limiting the level of the voltage command value may be disposed between the voltage command generator 340 and the axis converter 350 or may be provided inside the voltage command generator 340.

The inverter controller 230 according to an exemplary embodiment of the present invention may further include an offset voltage unit 372 that adds an offset voltage to the compensation voltage command values va ', vb', and vc '.

For example, as illustrated in FIG. 5B, the offset voltage unit 372 may generate the offset voltage vsn using the maximum value vmax and the minimum value vmin among the three phase voltages. The offset voltage vsn is not limited to the example of FIG. 5B and may vary depending on the design.

The duty converter 362 may include a PWM switching signal Ta ', which shifts a pulse width modulation (PWM) switching signal generated by the duty generator 361 when the inverter is driven by a cooperative inverter. Tb ', Tc').

For example, the duty converter 362 may perform a 180 degree phase difference from the voltage vector generated by the PWM switching signals Ta, Tb, and Tc generated by the duty generator 361 in the duty generator 361. The generated PWM switching signals Ta, Tb, and Tc may be shifted.

According to the PWM switching signals Ta ', Tb', and Tc 'output from the duty converter 362, the switching elements included in the inverter set as the interlocking inverter may be turned on / off.

In addition, the duty converter 362 may include the three-phase phase-arm switching element of the interlocking inverter when one of the three-phase phase-arm switching elements of the reference inverter is turned on according to the first voltage vector for driving the reference inverter. When any one of the switching element is turned off, and when any one of the three-phase phase arm switching element of the reference inverter is turned off, any one of the three-phase phase arm switching element of the interlocking inverter is turned on PWM switching signals Ta ', Tb', and Tc 'corresponding to the second voltage vector may be generated.

Accordingly, the polarity of the noise level corresponding to the interlocked inverter and the polarity of the noise level of the motor corresponding to the reference inverter may be opposite to those generated by the second motor 250b.

On the other hand, the duty converter 362 is the PWM switching signals Ta ', Tb', Tc 'to correspond to the projection vector of the voltage vector 180 degrees out of phase with the voltage vector by the PWM switching signals Ta, Tb, Tc. ) Can be created. This will be described later with reference to FIG. 8.

The voltage compensator 363 may generate the compensation voltage value vx_error based on the output of the duty generator 361 and the duty converter 362.

The shift of the PWM switching signal becomes an error component. In the voltage compensator 363, the switching timing error Tx_error may be a value obtained by subtracting the output of the duty converter 362 from the output of the duty generator 361.

Tx_error = Tx-Tx '

More preferably, the switching timing error Tx_error may be set as a ratio of a value obtained by subtracting the output of the duty converter 362 from the output of the duty generator 361 and the output of the duty generator 361. have.

Tx_error = Tx-Tx '/ Tx

The voltage compensator 363 may generate the compensation voltage value vx_error by multiplying the switching timing error Tx_error by a reference voltage value as follows. For example, the reference voltage value may be a dc terminal voltage vdc.

Accordingly, a compensation voltage value vx_error capable of compensating for the switching timing error Tx_error may be generated.

vx_error = Tx_error * vdc

Thereafter, the duty generator 361 outputs the half-cycle driven by the interlocking inverter to the three-phase output voltage command values va, vb, and vc output from the axis converter 350 when the corresponding inverter is driven by the reference inverter. The PWM switching signals Ta, Tb, and Tc for switching the plurality of switching elements may be generated based on the compensation voltage command values va ', vb', and vc 'corresponding to the compensation voltage values vx_error. have.

According to the present invention, a constant error component (PWM Duty: Time component) can be converted into a voltage, and this can be compensated for by the output of the voltage command value generator 340. As such, by calculating the error as a voltage error component and simply compensating the output of the voltage command value generator 340, PWM interworking control is possible while minimizing hardware addition and software algorithm change.

Meanwhile, according to an embodiment of the present invention, an error caused by the interlocking control may be minimized by managing the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter. For example, the inverter controller 230 may control the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter to be 60 degrees. This will be described later with reference to FIGS. 15 to 17.

6 to 10 are views for reference to the operation of the motor drive apparatus according to an embodiment of the present invention.

FIG. 6A illustrates EMI noise, particularly common mode Nsi, at the input stage that is the front end of the converter 210 of the motor driving apparatus 200 of FIG. 4, and of FIG. 6. (b) illustrates common mode noise Ncs in the first motor 250a of FIG. 4, and FIG. 6C illustrates common mode noise Nsf in the second motor 250b of FIG. 4. ).

According to FIG. 6, the common mode noise Nsc in the first motor 250a and the second motor 250b are caused by the first inverter 220a and the second inverter 220b respectively driven to each other. The common mode noise Nsf is summed to appear like the common mode noise Nsi at the input terminal.

On the other hand, the inverter control unit 230 according to the embodiment of the present invention, in order to reduce the EMI noise, as shown in Figure 6, the polarity of the level of the first noise generated in the first motor 250a and the second motor ( The polarity of the level of the second noise generated at 250b) can be controlled to be reversed.

For example, the inverter controller 230 may have a level Nsf of the second noise generated by the second motor 250b based on the polarity of the level of the first noise Nsc generated by the first motor 250a. ) Can be controlled to be reversed.

As another example, the inverter controller 230 may have a level of the first noise Nsc generated by the first motor 250a based on the polarity of the level Nsf of the second noise generated by the second motor 250b. The polarity of can be controlled to be reversed.

On the other hand, the inverter control unit 230, as shown in Fig. 6, at the first point in time, the polarity of the level of the first noise generated in the first motor 250a and the second motor 250b 2 The polarity of the noise level can be controlled to be reversed.

On the other hand, the common mode noise Nsc in the first motor 250a may be due to the leakage current isa leaked from the first motor 250a, and the common mode noise (Nsc) in the second motor 250b may be obtained. Nsf) may be due to the leakage current isb leaking from the second motor 250b.

In addition, the polarity of the common mode noise Nsc in the first motor 250a of FIG. 6B may correspond to the polarity of the first leakage current isa leaked from the first motor 250a. The polarity of the common mode noise Nsf in the second motor 250b of FIG. 6C may correspond to the polarity of the second leakage current isb leaking from the second motor 250b.

Accordingly, the inverter controller 230 has a polarity of the first leakage current isa leaked from the first motor 250a and a polarity of the second leakage current isb leaked from the second motor 250b. You can control the opposite.

On the other hand, the leakage current leaked from the first motor 250a or the second motor 250b, as shown in FIG. 7, may affect the on / off operation of the switching elements of the first inverter 220a or the second inverter 220b. It may be caused by.

In FIG. 7, a leakage current of positive polarity (positive direction) may be generated at the rise time of the switching element. Leakage current of negative polarity (negative direction) can be generated at the fall time of the switching element.

Accordingly, the inverter control unit 230 may reduce the common mode noise by adjusting the switching timing of the first inverter 220a and the second inverter 220b.

In more detail, the inverter controller 230 may synchronize the switching cycle of the first inverter 220a and the switching cycle of the second inverter 220b.

The inverter controller 230 may set any one of the first inverter 220a and the second inverter 220b as a reference inverter, and set the other inverter as a linked inverter to drive in conjunction with the reference inverter.

The interlocking inverter may be turned off when any one of the switching elements of the reference inverter is turned on, and turned on when any one of the switching elements of the reference inverter is turned off. That is, it may operate in conjunction with the operation of the reference inverter.

The inverter controller 230 may control the switching timing of the interlocking inverter to vary according to the switching timing of the reference inverter. To this end, the inverter controller 230 may use a pulse vector variable control method based on a space vector.

The inverter controller 230 sets one of the first inverter 220a and the second inverter 220b as a reference inverter, generates a first voltage vector for controlling the reference inverter, and generates a first voltage vector. On the basis, the reference inverter can be controlled.

For example, in FIG. 7, the inverter control unit 230 sets the first inverter 220a as a reference inverter, and sets an effective vector for turning on and off the switching elements in the first inverter 220a as V51. Can be generated. In addition, as shown in FIG. 7, the inverter controller 230 may control the three-phase phase-arm switching element of the first inverter 220a based on the V51 effective vector.

The inverter control unit 230 includes the second voltage vector such that the polarity of the level of the first noise generated by the first motor 250a and the polarity of the level of the second noise generated by the second motor 250b are reversed. By generating the controllable inverter can be controlled.

In particular, the inverter control unit 230, when any one of the three-phase phase arm switching element of the reference inverter is turned on, the switching element of any one of the three-phase phase arm switching element of the interlocking inverter is turned off, the reference inverter When one of the three-phase phase arm switching elements of the switching element is turned off, by generating a second voltage vector to turn on any one of the three-phase phase arm switching element of the interlocking inverter, it is possible to control the interlocking inverter have.

For example, in FIG. 8, the inverter controller 230 may generate a second voltage vector V55 corresponding to the first voltage vector V51. In addition, the inverter controller 230 may control the three-phase phase-arm switching element of the second inverter 220b based on the V55 effective vector as shown in FIG. 7.

As such, since each of the motors 230a and 230b is controlled by one inverter control unit 230, the leakage current between the two motors 230a and 230b may be attenuated by inverting the phase by 180 degrees.

As shown in FIG. 7, the switching timings of the first inverter 220a and the second inverter 220b are controlled to compare the common mode noise Nsix at the input terminal of FIG. Similarly, it can be seen that the common mode noise Nsi at the input terminal is significantly reduced.

On the other hand, as described above, the inverter controller 230, when any one of the three-phase phase arm switching element of the reference inverter is turned on, any one of the three-phase phase arm switching element of the interlocking inverter is turned on When the switching is turned off and any one of the three-phase phase-arm switching elements of the reference inverter is turned off, the second voltage vector is generated such that the switching element of any of the three-phase phase-arm switching elements of the interlocking inverter is turned on. The two voltage vectors may be any one of V52 to V57 in FIG. 8.

The inverter controller 230 of the present invention may control the second voltage vector to be located in the same sector as the first voltage vector. Accordingly, the second voltage vector may be generated in the projected shape of the first voltage vector in the same sector as the first voltage vector.

For example, in FIG. 9, when the first voltage vector is generated in sector 1, such as V51, the inverter controller 230 may convert the second voltage vector to a sector in which the first voltage vector is generated, as in V52. Sector 1, which is the same sector, can be created in the projected shape of the first voltage vector with respect to any line. As the first voltage vector and the second voltage vector are formed in the same sector, control convenience may be improved.

The inverter controller 230 of the present invention may control the second voltage vector to be located in a sector different from the first voltage vector. Accordingly, the second voltage vector may be generated in a projected shape of the first voltage vector in a sector different from the first voltage vector. In this case, the second voltage vector may be any one of V53 to V57 of FIG. 8.

In particular, it is possible to minimize the occurrence of error by controlling the second voltage vector to have a phase difference of 60 degrees with the first voltage vector.

Meanwhile, when the reference inverter is fixed to the first inverter 220a, that is, when the switching timing of the inverter is fixed only to the first inverter 220a, the reference voltage of the second inverter 220b may be distorted. have. Accordingly, the target second inverter switching control signal Sicb may not be output, and a control error of the second motor 250b may occur.

The motor drive device 200 of the present invention may alternately control the first inverter 220a and the second inverter 220b to solve such a control error. That is, the inverter control unit 230 sets the first inverter 220a as the reference inverter in the switching half cycle, and synchronously drives the first motor 250a and the second motor 250b. By setting the second inverter 220b as a reference inverter, the first motor 250a and the second motor 250b may be synchronously driven.

Specifically, the inverter controller 230 sets the first inverter 220a as the reference inverter in the first switching half cycle Ts1 of the first switching period Tsa, as shown in FIG. 10, and the second inverter. 220b may be set as the interlocking inverter. In addition, the inverter control unit 230 sets the second inverter 220b as the reference inverter in the second switching half cycle Ts2, which is the remaining switching half cycle among the first switching cycles Tsa, and the first inverter 220a. ) Can be set as a linked inverter.

Similarly, the inverter controller 230 sets the first inverter 220a as the reference inverter and the second inverter 220b as the interlocked inverter in the third switching half cycle Ts3 of the second switching cycle Tsb. Can be set. In addition, the inverter controller 230 sets the second inverter 220b as the reference inverter in the fourth switching half cycle Ts4, which is the remaining switching half cycle among the second switching cycles Tsb, and sets the first inverter 220a. ) Can be set as a linked inverter.

The above-described alternating control may be performed in all sections during the motor operation. Accordingly, the motor driving apparatus 200 of the present invention can reduce the reference voltage distortion of the first inverter 220a and the second inverter 220b.

On the other hand, when the motor drive device 200 of the present invention is provided in the indoor fan 109a and / or the outdoor fan 105a of the air conditioner 50, the indoor fan 109a and / or the outdoor fan 105a. Since only the average output value needs to be satisfied at a given carrier frequency (for example, 20 khz), there is no problem even if the first inverter 220a and the second inverter 220b are alternately controlled.

11 is a view referred to for describing an error that may occur in the interlocking control according to an embodiment of the present invention.

11 is a table showing the relationship between the outputs of the plurality of indoor fans 109a and / or the outdoor fans 105a and an error when the first inverter 220a and the second inverter 220b are alternately controlled.

Meanwhile, since the motor driving device 200 of the present invention may be the motor driving device 200 driving the indoor fan 109a and / or the outdoor fan 105a of the air conditioner 50, Fan1 of FIG. The output of may be understood as the output of the first motor 250a, Fan2 is the output of the second motor 250b.

In FIG. 11, the inverter controller 230 sets the first inverter 220a as the reference inverter in the first switching half cycle Ts1 of the first switching cycle Tsa, and interlocks the second inverter 220b. Can be set with an inverter.

In the first switching half cycle Ts1, since the first inverter 220a is a reference inverter, the inverter controller 230 may generate a first voltage vector corresponding to the target output 10 of the first motor 250a.

In addition, the inverter controller 230 may generate the second voltage vector in the same sector as the first voltage vector. The second voltage vector may be generated in the projected shape of the first voltage vector based on any line.

Since the second voltage vector is generated based on the first voltage vector, the actual output of the second motor 250a may also be ten. Accordingly, an output error of 3 may occur in the second motor 250a.

Next, the inverter controller 230 sets the second inverter 220b as the reference inverter in the second switching half cycle Ts2 among the first switching cycles Tsa, and sets the first inverter 220a as the interlocking inverter. Can be set.

In the second switching half cycle Ts2, since the second inverter 220a is the reference inverter, the inverter controller 230 considers the target output of the second motor 250b and the output error of the first switching half cycle Ts1. To generate a first voltage vector. As illustrated in FIG. 11, the inverter controller 230 may output the actual output 4 in consideration of the output error 3 of the first switching half cycle Ts1 and the target output 7.

The inverter controller 230 may generate a second voltage vector based on the first voltage vector. Similarly, since the second voltage vector is generated based on the first voltage vector, in the second switching half cycle Ts2, the actual output of the first motor 250a may also be four. Accordingly, an output error of −6 may occur in the first motor 250a.

Next, the inverter controller 230 sets the first inverter 220a as the reference inverter in the third switching half cycle Ts3 of the second switching cycle Tsb, and sets the second inverter 220b as the linked inverter. Can be set.

In the third switching half cycle Ts3, since the first inverter 220a is the reference inverter, the inverter controller 230 considers the target output of the second motor 250b and the output error of the second switching half cycle Ts2. In this way, a first voltage vector may be generated. As illustrated in FIG. 11, the inverter controller 230 may output the actual output 16 in consideration of the output error, −6, and the target output 10 in the third switching half cycle Ts3.

The inverter controller 230 may generate a second voltage vector based on the first voltage vector. By the second voltage vector, the second motor 250b may output the actual output 16. Accordingly, an output error of 9 may occur in the second motor 250b.

Next, the inverter controller 230 may set the second inverter 230b as a reference inverter and set the first inverter 230a as a linked inverter in the fourth switching half cycle Ts4.

In FIG. 11, since the output error 9 of the second motor 250b is 7 or more, which is the target output, the inverter controller 230 may output the actual output 0 to the second motor 250b. Accordingly, the actual output 0 may also be output to the first motor 250a.

As a result, when the inverter control unit 230 performs the alternating control of FIG. 10, when the target output of the first motor 250a and the second motor 250b is different, an output error is diverted and the first motor ( There is a section (Ts4 in FIG. 11) in which zero output occurs in the 250a and the second motor 250b.

This reduces the control accuracy of the motor drive device 200, and the first motor 250a and / or the second motor 250b may be stopped.

12 to 17 are views referred to for describing various error compensation methods according to an embodiment of the present invention.

The motor driving apparatus 200 of the present invention may output a magnitude compensation vector in order to compensate for a magnitude error, which may occur during such alternating control.

Specifically, the inverter controller 230 generates a magnitude compensation vector when the output error of at least one of the output errors of the first motor 250a and the second motor 250b is greater than or equal to a preset error value. The inverter 220a or the second inverter 220b may be controlled.

In this case, the inverter controller 230 may control the magnitude compensation vector to be located in a sector other than a sector in which the first voltage vector or the second voltage vector is located.

Alternatively, the inverter controller 230 may control the magnitude compensation vector to have a phase opposite to that of the first voltage vector or the second voltage vector.

For example, the first inverter 220a may be set as a reference inverter, the second inverter 220b may be set as a cooperative inverter, and the first voltage vector may be generated as V51 of FIG. 8. At this time, the second voltage vector should be generated as V52, which is present in the same sector as V51, but if the output error of the second motor 250b is greater than or equal to the preset error value, the inverter controller 230 may determine the magnitude compensation vector. It may be controlled to be generated in the V53 to V57, not the first sector.

In the above-described example, only the second voltage vector is the magnitude compensation vector, but according to the output error of the first motor 250a and the second motor 250b, the first voltage vector may be the magnitude compensation vector. Of course.

Meanwhile, the magnitude compensation vector is preferably generated in a sector farthest from the first voltage vector to be generated or the second voltage vector to be generated.

For example, in the above example, the magnitude compensation vector is preferably generated in sector 4 or sector 5 farthest from sector 1.

The preset error value may be set in consideration of a target output, an actual output, a cumulative error value, or the like of the first motor 250a or the second motor 250b.

12 is a table for explaining output error reduction by the magnitude compensation vector.

FIG. 12 is similar to FIG. 11 except that the magnitude compensation vector is output in the fourth switching half-cycle Ts4. Hereinafter, the same description as in FIG. 11 will be omitted, and the detailed operations of the third switching half cycle Ts3 and the fourth switching half cycle Ts4 will be described.

As illustrated in FIG. 11, in the third switching half cycle Ts3, an output error of the first motor 250a may be 0 and an output error of the second motor 250b may be 9.

In the fourth switching half cycle Ts4, since the second inverter 220b is the reference inverter, and 9, which is an output error of the second motor 250b, exceeds 7, which is the target output or the maximum output of the second motor 250b. The inverter controller 230 may control the magnitude compensation vector to be generated in the fourth sector or the fifth sector instead of the first sector in which the first voltage vector should be located. Meanwhile, the first voltage vector may still be generated in the first sector.

The second motor 250b may output the actual output -6 based on the second voltage vector, and the first motor 250a may output the actual output 7 based on the first voltage vector. In this case, the output error of the second motor 250b may be −4, and the output error of the first motor 250a may be −3.

As shown in FIG. 12, as the inverter controller 230 generates the magnitude compensation vector under a predetermined condition, it can be seen that, unlike FIG. 11, the output error does not diverge.

FIG. 13 is a diagram for describing a method for compensating for a phase error when the first inverter 220a and the second inverter 220b are alternately controlled.

As described above, the inverter controller 230 may control the second voltage vector to be located in the same sector as the first voltage vector.

In this case, when the second voltage vector and the first voltage vector have approximate phases in the same sector, phase errors may accumulate. In order to solve this problem, the motor driving apparatus 200 of the present invention may generate a phase compensation vector.

The inverter controller 230 generates a first phase compensation vector and a second phase compensation vector when the phase difference between the first voltage vector and the second voltage vector is equal to or less than a preset phase difference, thereby generating the first inverter 220a or the first inverter. The second inverter 220b may be controlled, and the composite vector of the first phase compensation vector and the second compensation vector may be controlled to be the first voltage vector or the second voltage vector.

In addition, the inverter controller 230 may generate the first phase compensation vector in a half period of the first switching period Tsa and generate the second phase compensation vector in a half period of the second switching period Tsb.

For example, the first inverter 220a may be set as a reference inverter, the second inverter 220b may be set as a cooperative inverter, and the first voltage vector may be generated as shown in V1301 of FIG. 13. At this time, the second voltage vector should be generated as shown in V1303 of FIG. 13, but if the phase difference between the first voltage vector and the second voltage vector is less than or equal to a preset phase difference, the inverter controller 230 replaces the first phase compensation with V1303. A vector V1305 and a second phase compensation vector V1307 may be generated.

In addition, the inverter controller 230 generates V1305, which is the first phase compensation vector, in the second switching half period Ts2 of the first switching period Tsa, and generates S107, which is the second phase compensation vector, in the second switching period ( It may be generated in the fourth switching half cycle Ts4 of Tsb).

Meanwhile, the preset phase difference may be set in consideration of a switching period, an inverter output, a switching frequency, and the like, and may be, for example, 30 degrees.

As shown in FIG. 7, in the PWM interlocking control for reducing EMI noise, the PWM output is forcibly shifted, thereby reducing stability of the control. Therefore, it is necessary to compensate the error caused by forcibly shifting the PWM output.

The method of using the magnitude compensation vector uses a magnitude compensation vector forcibly canceling the output error when the output error exceeds a predetermined level. Therefore, the method using the magnitude compensation vector is effective to prevent the output error from diverging, but it is not effective as a method of minimizing and managing the output error.

However, as described with reference to FIGS. 4, 5A, 5B, and the like, the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis converter 350 is added to the compensation voltage command value. Based on the above, the voltage error method for outputting the reference inverter switching control signal according to the pulse width modulation (PWM) method has an advantage in terms of minimizing and managing the output error.

That is, by replacing the error in the form of voltage value in the PWM output of the next cycle and performing vector compensation, the effective voltage error of the previous cycle can be compensated immediately while reducing EMI noise.

The motor driving device 200 and the air conditioner 50 according to an embodiment of the present invention operate based on a common input AC power source 201, and the first motor 250a and the second motor 250b. An inverter control unit for controlling the first inverter 220a and the second inverter 220b by controlling the first inverter 220a and the second inverter 220b and the variable pulse width based on the space vector. 230).

Inv1 and Inv2 in FIG. 14 may be understood as the first inverter 220a and the second inverter 220b described above, respectively.

When the switched cycle is divided into a first half cycle T1 and a second half cycle T2, the inverter controller 230 refers to the first inverter 220a in the first half cycle T1 of the switched cycle. The second inverter 220b may be set as an inverter, and the second inverter 220b may be set as an interlocking inverter driven in conjunction with the reference inverter, and the first inverter may be configured in a second half cycle T2 which is the next half cycle of the first half cycle T1. 220a) may be set as the interlocking inverter and the second inverter 220b may be set as the reference inverter.

In FIG. 14, an inverter set as a master may be a reference inverter, and an inverter set as a slave may be understood as an interlocking inverter.

The inverter controller 230 may synchronize the switching cycle of the first inverter 220a and the switching cycle of the second inverter 220b, and interlock the first inverter 220a and the second inverter 220b. Can be controlled. That is, one inverter may be set as the reference inverter in the switching half cycle, and the other inverters may be set as the interlocking inverter to control to operate in conjunction with the reference inverter, and the reference inverter may be alternately changed in the next half cycle.

For example, the inverter controller 230 supplies the second inverter 220b which is the interlocking inverter based on the PWM switching signal Tx1 supplied to the first inverter 220a which is the reference inverter in the first half period T1. The PWM switching signal Tx2 may be generated.

Next, in the second half period T2, the PWM switching signal Tx1 supplied to the first inverter 220a which is the interlocking inverter is generated based on the PWM switching signal Tx2 that is supplied to the second inverter 220b which is the reference inverter. can do.

Here, the PWM switching signal supplied to the interlocking inverter may reduce the common mode noise by changing the switching timing of the PWM switching signal supplied to the reference inverter.

For example, the inverter controller 230 generates a first voltage vector to control the reference inverter, and the polarity of the level of the first noise generated by the first motor 250a, A second voltage vector may be generated such that the polarity of the level of the second noise generated by the second motor 250b is reversed to control the interlocking inverter driving in conjunction with the reference inverter.

In addition, the inverter controller 230 generates a first voltage vector for driving the reference inverter to control the reference inverter, and any one of three phase phase-arm switching elements of the reference inverter is turned on. When one of the three-phase phase arm switching elements of the interlock inverter is turned off, and when any one of the three-phase phase arm switching elements of the reference inverter is turned off, the three-phase phase arm of the interlock inverter The interlocking inverter may be controlled by generating a second voltage vector such that any one of the switching elements is turned on.

According to the present invention, even when there are loads of the inverters 220a and 220b, the interlocking control is possible, and the error of the effective vector voltage due to the interlocking control can be compensated. In particular, it is desirable to directly compensate for errors generated by the PWM interlocking control.

To this end, the inverter controller 230 compensates the output of the voltage command value in the half cycle driven by the reference inverter to correspond to the output error generated in the half cycle driven by the interlocking inverter to compensate for the first inverter 220a and the second. The inverter 220b may be controlled.

As described in detail with reference to FIG. 5B, the inverter controller 230 according to an exemplary embodiment of the present invention coordinates the output of the voltage command generator 340 and the voltage command generator 340 to generate a voltage command value. Pulse width modulation (PWM) based on the compensation voltage command value obtained by adding the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis converter 350 and the axis converter 350. It may include a switching control signal output unit 360 for outputting a reference inverter switching control signal according to the scheme.

Here, the switching control signal output unit 360 is based on the compensation voltage command value is the sum of the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis conversion unit 350, the pulse width A duty generation unit 361 generating a modulation (PWM) switching signal and a duty conversion shifting the pulse width modulation (PWM) switching signal generated by the duty generation unit 361 in a half cycle driven by the interlocking inverter And a voltage compensator 363 generating the compensation voltage value based on the output of the duty converter 362.

Referring to FIG. 14, in the first half period T1, the first inverter 220a which is a reference inverter reflects a compensation voltage value generated by the voltage compensator 363 in response to a voltage error of a previous half period. Voltage error compensation may be performed, and a voltage error may be calculated by the second inverter 220b which is a linked inverter.

In addition, in the second half period T2, the second inverter 220b serving as the reference inverter compensates the voltage error generated by the voltage compensator 363 in response to the voltage error of the previous half period. In operation, the first inverter 220a which is the interlocking inverter may calculate a voltage error.

In this way, the voltage error can be reduced through the alternating compensation, and the error can be prevented from accumulating and diverging.

According to an embodiment of the present invention, by outputting a desired voltage from the controller and compensating for the error component by converting the voltage, it is possible to generate a PWM signal having a duty that can easily reduce the voltage error.

Accordingly, in order to directly compensate the switching duty (PWM Duty), the complexity of calculating the error and the duty to be compensated can be eliminated. Therefore, EMI can be reduced by software, and leakage current can be reduced by reducing common mode noise of the motor. In addition, there is an advantage that can reduce the manufacturing cost by removing the harness core (Core) for reducing EMI.

According to one embodiment of the present invention, as shown in FIG. 13, as the motor driving device 200 compensates for a phase error, control accuracy may be improved and stable driving of the motor may be possible.

More preferably, by managing the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter in parallel to the voltage compensation control method, it is possible to minimize the occurrence of errors due to the interlocking control. For example, the inverter controller 230 may control the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter to be 60 degrees.

15 to 17 are diagrams referred to for explaining the optimum phase control of the voltage vector.

Referring to FIG. 15, the inverter controller 230 may generate a reference voltage vector Vm for driving the reference inverter to control the reference inverter.

In addition, the inverter controller 230 may generate a linkage voltage vector for driving the linkage inverter based on the reference vector Vm to control the linkage inverter.

In this case, the inverter controller 230 controls the interlocked inverter with the interlocking voltage vector Vs' generated in the projected shape of the reference voltage vector Vm in the same sector as the reference voltage vector Vm or the reference voltage vector. The interlocking inverter may be controlled by the interlocking voltage vector Vs ″ generated in the projected shape of the reference voltage vector Vm in a sector different from Vm.

When the phase of the reference voltage vector Vm and the interlock voltage vector Vs' or Vs' 'are close, phase errors may accumulate, so in view of managing the phase difference, the interlock voltage vector Vs " ) Has the advantage.

However, even in this case, a voltage output error may occur, and more preferably, the inverter controller 230 may further include a phase difference θs between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter. You can control it to 60 degrees.

8 and 15, the second voltage vector corresponding to the first voltage vector V51 may be any one of V52 to V57. Like the reference voltage vector Vm and the interlock voltage vector Vs, V52 is located in the same sector as the first voltage vector V51 and has a disadvantage in terms of phase error because the phase difference is small. In addition, although V54 to V56 are located in a different sector from the first voltage vector V51, it is not preferable as a normal control method which is not one-time because the vector must be forcibly shifted forcibly.

Therefore, it may be effective to prevent an error in everyday use when V53 and V57 having a phase difference of 60 degrees from the first voltage vector V51 are selected as the second vector.

FIG. 16 illustrates a case where a phase difference between a Fan1 vector for driving Fan1 and a Fan2 vector for driving Fan2 is 60 degrees, and FIG. 17 is a phase difference between a Fan1 vector for driving Fan1 and a Fan2 vector for driving Fan2 Illustrates a case where is not 60 degrees.

Referring to FIG. 16, since the phase difference between the reference voltage vector Fan2 vector 1610 and the Fan1 vector 1630 is 60 degrees, the Fan2 synchronization control vector 1620 and the Fan1 vector 1630 for the PWM interlocking control are the same. . Therefore, since there is no difference between the Fan2 synchronization control vector 1620 and the Fan1 vector 1630, no voltage output error occurs.

Referring to FIG. 17, since the phase difference between the reference voltage vector Fan2 vector 1710 and the Fan1 vector 1730 is not 60 degrees, the Fan2 synchronization control vector 1720 and the Fan1 vector 1730 for the PWM interlocking control are different. . Therefore, a voltage output error occurs by the difference between the Fan2 synchronization control vector 1720 and the Fan1 vector 1730, and accordingly, voltage output error compensation 1740 is required.

Meanwhile, the motor driving apparatus 200 and the air conditioner 50 according to the embodiment of the present invention operate based on the common input AC power source 201, and the first motor 250a and the second motor ( An inverter that controls the first inverter 220a and the second inverter 220b by controlling the first inverter 220a and the second inverter 220b driving the 250b and the variable pulse width based on the space vector. The controller 230 may include a controller 230, and the inverter controller 230 sets the first inverter 220a as a reference inverter in the first half period T1 of the switched cycle, and the second inverter 220b. Is set as a linked inverter driven in conjunction with the reference inverter, and the first inverter 220a is set as the linked inverter in the second half cycle T2 which is the next half cycle of the first half cycle T1. An inverter 220b may be set as the reference inverter, and a voltage for driving the reference inverter The phase difference between the voltage vector to drive the emitter and the interconnecting inverter can control nadorok 60 degrees.

That is, the present embodiment can prevent occurrence of voltage output error by applying optimum phase control in preference to other error compensation schemes.

In this embodiment, the voltage output error may theoretically be zero, but for some reason, the voltage output error may occur slightly. Therefore, the above-described voltage compensation control method can also be applied to this embodiment.

That is, the inverter controller 230 compensates the output of the voltage command value in the half cycle driven by the reference inverter so as to correspond to the output error generated in the half cycle driven by the interlocked inverter to compensate for the output of the voltage command value in the first inverter 220a and the second inverter. 220b can be controlled.

As described in detail with reference to FIG. 5B, the inverter controller 230 according to an exemplary embodiment of the present invention coordinates the output of the voltage command generator 340 and the voltage command generator 340 to generate a voltage command value. Pulse width modulation (PWM) based on the compensation voltage command value obtained by adding the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis converter 350 and the axis converter 350. It may include a switching control signal output unit 360 for outputting a reference inverter switching control signal according to the scheme.

Here, the switching control signal output unit 360 is based on the compensation voltage command value is the sum of the compensation voltage value corresponding to the output error generated in the half cycle driven by the interlock inverter to the output of the axis conversion unit 350, the pulse width A duty generation unit 361 generating a modulation (PWM) switching signal and a duty conversion shifting the pulse width modulation (PWM) switching signal generated by the duty generation unit 361 in a half cycle driven by the interlocking inverter And a voltage compensator 363 generating the compensation voltage value based on the output of the duty converter 362.

Also, in the present embodiment, the inverter controller 230 may synchronize the switching period of the first inverter 220a and the switching period of the second inverter 220b, and the first inverter 220a and the first inverter 220a may be synchronized with each other. 2 can be controlled by interlocking the inverter 220b.

In addition, the inverter controller 230 generates a first voltage vector to control the reference inverter, and the polarity of the level of the first noise generated by the first motor 250a and the first voltage vector. The second voltage vector may be generated such that the polarity of the level of the second noise generated by the second motor 250b is reversed to control the interlocked inverter driven in conjunction with the reference inverter.

In addition, the inverter controller 230 generates a first voltage vector for driving the reference inverter to control the reference inverter, and any one of three phase phase-arm switching elements of the reference inverter is turned on. When one of the three-phase phase arm switching elements of the interlock inverter is turned off, and when any one of the three-phase phase arm switching elements of the reference inverter is turned off, the three-phase phase arm of the interlock inverter The interlocking inverter may be controlled by generating a second voltage vector such that any one of the switching elements is turned on.

18A to 18D are diagrams illustrating phase currents measured in interlocking control according to an exemplary embodiment of the present invention.

FIG. 18A illustrates a U phase current of a fan driven by a first inverter, which is the reference inverter of FIG. 7, and FIG. 18B illustrates a U phase current of a fan driven by a second inverter, which is a linked inverter.

18A and 18B, distortion may occur in the U phase current of the fan driven by the second inverter which is the interlocking inverter.

When the voltage error compensation control described with reference to FIGS. 5B and 14 is performed, the distortion may be improved to the state illustrated in FIG. 18C in the state illustrated in FIG. 18B. In addition, when the voltage error compensation control and the optimal phase control described with reference to FIGS. 15 to 17 are applied in parallel, the distortion may be greatly improved in the state illustrated in FIG. 18D.

Meanwhile, the above-described motor driving device 200 may be provided and used in various devices in addition to the air conditioner. For example, the home appliance may be used for a laundry treatment device, a refrigerator, a water purifier, a cleaner, and the like. In addition, the present invention can be applied to a vehicle, a robot, a drone, and the like, which can be operated by a motor.

The motor driving apparatus and the air conditioner having the same according to the present invention are not limited to the configuration and method of the embodiments described as described above, but the embodiments are all of the embodiments so that various modifications can be made. Or some may be selectively combined.

In addition, while the above has been shown and described with respect to preferred embodiments of the present invention, the present invention is not limited to the specific embodiments described above, the technical field to which the invention belongs without departing from the spirit of the invention claimed in the claims. Of course, various modifications can be made by those skilled in the art, and these modifications should not be individually understood from the technical spirit or the prospect of the present invention.

50: air conditioner
200: motor drive unit
220a: first inverter
220b: second inverter
230: inverter control unit
250a: first motor
250b: second motor

Claims (17)

A first inverter and a second inverter operating based on a common input AC power source and driving the first motor and the second motor, respectively;
And an inverter controller configured to control the first inverter and the second inverter by a variable pulse width control based on a space vector.
The inverter control unit,
In the first half cycle of the switching cycle, the first inverter is set as the reference inverter, and the second inverter is set as the linked inverter driven in conjunction with the reference inverter,
Setting the first inverter as the interlocking inverter and the second inverter as the reference inverter in a second half cycle, which is a next half cycle of the first half cycle,
And controlling the first inverter and the second inverter by compensating the output of the voltage command value in the half cycle driven by the reference inverter so as to correspond to the output error generated in the half cycle driven by the interlocked inverter. The method of claim 1,
The inverter control unit,
Generate a first voltage vector to control the reference inverter,
A second voltage vector is generated so that the polarity of the level of the first noise generated in the first motor and the polarity of the level of the second noise generated in the second motor are reversed to be driven in conjunction with the reference inverter. A motor drive device for controlling the interlocking inverter. The method of claim 1,
The inverter control unit,
Generating a first voltage vector for driving the reference inverter to control the reference inverter,
When any one of the three-phase phase arm switching elements of the reference inverter is turned on, any one of the three phase phase arm switching elements of the interlocking inverter is turned off, and the three-phase phase arm switching element of the reference inverter is turned off. When any one of the switching element is turned off, generating a second voltage vector so that any one of the three-phase phase arm switching element of the interlocking inverter is turned on, the motor characterized in that for controlling the interlocking inverter drive. The method of claim 1,
The inverter control unit,
And a switching period of the first inverter and a switching period of the second inverter are synchronized. The method of claim 1,
The inverter control unit,
A voltage command generator which generates the voltage command value;
An axis converting unit configured to coordinate transform the output of the voltage command generating unit;
Outputting a reference inverter switching control signal according to a pulse width modulation (PWM) method based on a compensation voltage command value obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlocking inverter to an output of the axis converter; And a switching control signal output unit. The method of claim 5,
The switching control signal output unit,
A duty generator configured to generate a pulse width modulation (PWM) switching signal based on a compensation voltage command value obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlock inverter to the output of the axis converter;
A duty converter configured to shift a pulse width modulation (PWM) switching signal generated by the duty generator in a half cycle driven by the interlocked inverter, and
And a voltage compensator configured to generate the compensation voltage value based on an output of the duty converter. The method of claim 6,
The voltage compensator,
And generating a compensation voltage value by multiplying a reference voltage value by a value obtained by subtracting the output of the duty converter from the output of the duty generator. The method of claim 1,
The inverter control unit,
And controlling the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter to be 60 degrees. A first inverter and a second inverter operating based on a common input AC power source and driving the first motor and the second motor, respectively;
And an inverter controller configured to control the first inverter and the second inverter by a variable pulse width control based on a space vector.
The inverter control unit,
In the first half cycle of the switching cycle, the first inverter is set as the reference inverter, and the second inverter is set as the linked inverter driven in conjunction with the reference inverter,
Setting the first inverter as the interlocking inverter and the second inverter as the reference inverter in a second half cycle, which is a next half cycle of the first half cycle,
And controlling the phase difference between the voltage vector for driving the reference inverter and the voltage vector for driving the interlocking inverter to be 60 degrees. The method of claim 9,
The inverter control unit,
Generate a first voltage vector to control the reference inverter,
A second voltage vector is generated so that the polarity of the level of the first noise generated in the first motor and the polarity of the level of the second noise generated in the second motor are reversed to be driven in conjunction with the reference inverter. A motor drive device for controlling the interlocking inverter. The method of claim 9,
The inverter control unit,
Generating a first voltage vector for driving the reference inverter to control the reference inverter,
When any one of the three-phase phase arm switching elements of the reference inverter is turned on, any one of the three phase phase arm switching elements of the interlocking inverter is turned off, and the three-phase phase arm switching element of the reference inverter is turned off. When any one of the switching element is turned off, generating a second voltage vector so that any one of the three-phase phase arm switching element of the interlocking inverter is turned on, the motor characterized in that for controlling the interlocking inverter drive. The method of claim 9,
The inverter control unit,
And a switching period of the first inverter and a switching period of the second inverter are synchronized. The method of claim 9,
The inverter control unit,
And controlling the first inverter and the second inverter by compensating the output of the voltage command value in the half cycle driven by the reference inverter so as to correspond to the output error generated in the half cycle driven by the interlocked inverter. The method of claim 13,
The inverter control unit,
A voltage command generator which generates the voltage command value;
An axis converting unit configured to coordinate transform the output of the voltage command generating unit;
Outputting a reference inverter switching control signal according to a pulse width modulation (PWM) method based on a compensation voltage command value obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlocking inverter to an output of the axis converter; And a switching control signal output unit. The method of claim 14,
The switching control signal output unit,
A duty generator configured to generate a pulse width modulation (PWM) switching signal based on a compensation voltage command value obtained by adding a compensation voltage value corresponding to an output error generated in a half cycle driven by the interlock inverter to the output of the axis converter;
A duty converter configured to shift a pulse width modulation (PWM) switching signal generated by the duty generator in a half cycle driven by the interlocked inverter, and
And a voltage compensator configured to generate the compensation voltage value based on an output of the duty converter. The method of claim 15,
The voltage compensator,
And generating a compensation voltage value by multiplying a reference voltage value by a value obtained by subtracting the output of the duty converter from the output of the duty generator. An air conditioner comprising the motor drive device according to any one of claims 1 to 16.

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