KR102026310B1

KR102026310B1 - Isolation structure and method for fabricating the same, image sensor having isolation structure

Info

Publication number: KR102026310B1
Application number: KR1020130062477A
Authority: KR
Inventors: 최충석; 문장원; 김종채; 김도환
Original assignee: 에스케이하이닉스 주식회사
Priority date: 2013-05-31
Filing date: 2013-05-31
Publication date: 2019-09-30
Also published as: KR20140141822A

Abstract

The present technology relates to a device isolation structure capable of separating a plurality of device regions and preventing interference between adjacent device regions, comprising: first device isolation including an insulating film for gap-filling a trench formed in a substrate; And a second device isolation layer including a first impurity region formed on the substrate and a second impurity region formed along an edge of the first impurity region and having an impurity doping concentration greater than that of the first impurity region. An isolation structure in which isolation and the second device isolation are stacked is provided.

Description

Isolation structure and manufacturing method, an image sensor having a device isolation structure {ISOLATION STRUCTURE AND METHOD FOR FABRICATING THE SAME, IMAGE SENSOR HAVING ISOLATION STRUCTURE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing technology, and more particularly, to a device isolation structure, a manufacturing method thereof, and an image sensor having the device isolation structure.

The image sensor is a semiconductor device that converts an optical image into an electrical signal. The image sensor may be classified into a charge coupled device type (CCD) type and a complementary metal oxide semiconductor type (CMOS type). CMOS type image sensors are commonly abbreviated as 'CIS (CMOS image sensor)'. The CIS has a plurality of pixels (Pixels) arranged in two dimensions, each pixel is separated by a device isolation structure. Each pixel separated by a device isolation structure includes a photodiode (PD). The photodiode converts incident light into an electrical signal.

Recently, with the development of semiconductor device manufacturing technology, high integration of image sensors has been accelerated. As a result of such high integration, the size of each of the pixels and the spacing between the pixels become smaller, thereby deteriorating characteristics due to cross talk between the pixels.

An embodiment of the present invention provides a device isolation structure and a method of manufacturing the same in a semiconductor device having a plurality of device regions to prevent interference between adjacent device regions.

In addition, an embodiment of the present invention provides an image sensor having a device isolation structure capable of preventing crosstalk.

A device isolation structure according to an embodiment of the present invention includes a device isolation structure for separating a plurality of device regions, the device isolation structure including an insulating film for gap-filling a trench formed in a substrate; And a second device isolation layer including a first impurity region formed on the substrate and a second impurity region formed along an edge of the first impurity region and having an impurity doping concentration greater than that of the first impurity region. Separation and the second device separation may include a device isolation structure stacked.

A method of manufacturing a device isolation structure according to an embodiment of the present invention is a method of manufacturing a device isolation structure for separating a plurality of device regions, comprising: selectively etching a substrate to form a trench; Forming an amorphous region having a lower melting temperature than the substrate in the substrate under the trench; Implanting impurities into the amorphous region; And melting the amorphous region to activate an implanted impurity and performing annealing to recrystallize the same.

An image sensor according to an embodiment of the present invention is formed along the edges of the first impurity region formed on the substrate and the first impurity region formed on the substrate and the first element isolation including an insulating film gap gap formed on the substrate than the first impurity region. A device isolation structure in which a second device isolation including a second impurity region having a large impurity doping concentration is stacked; And a photoelectric conversion region formed in the substrate corresponding to the plurality of pixels separated by the device isolation structure.

The present technology, based on the above-mentioned means for solving the above-described problems, can provide a device isolation structure in which first device isolation and second device isolation are stacked, thereby preventing interference between a plurality of device regions. Specifically, physical crosstalk and electrical crosstalk between adjacent pixels can be effectively prevented.

In addition, the second device isolation can more effectively prevent electrical crosstalk because the impurity doping concentration of the second impurity region surrounding the first impurity region is greater.

In addition, through the annealing process of selectively melting the amorphous region, it is possible to prevent the deterioration of characteristics due to diffusion of the impurity implanted and to reduce the thermal burden on the preformed structure.

1 is an equivalent circuit diagram of an image sensor according to an embodiment of the present invention.
2 is a plan view of an image sensor according to embodiments of the present invention.
3A is a cross-sectional view showing an image sensor according to a first embodiment of the present invention.
3B is a cross-sectional view showing a modification of the image sensor according to the first embodiment of the present invention.
4A to 4E are cross-sectional views illustrating a method of manufacturing the image sensor according to the first embodiment of the present invention.
5A is a sectional view of an image sensor according to a second embodiment of the present invention;
5B is a cross-sectional view showing a modification of the image sensor according to the second embodiment of the present invention.
6A to 6E are cross-sectional views illustrating a method of manufacturing the image sensor according to the second embodiment of the present invention.
7A is a sectional view of an image sensor according to a third embodiment of the present invention;
7B is a sectional view showing a modification of the image sensor according to the third embodiment of the present invention.
8A to 8G are cross-sectional views illustrating a method of manufacturing an image sensor according to a third embodiment of the present invention.
9 is a graph showing the impurity doping concentration of an impurity region formed through laser annealing including selective melting.
10 is a graph showing melting of silicon having different crystal structures according to laser irradiation energy;
11 is an image showing the lattice movement according to the laser annealing.
12 is a block diagram showing a configuration of an image sensor according to an embodiment of the present invention.
13 is a block diagram illustrating a system including an image sensor according to an embodiment of the present invention.

Hereinafter, the most preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the technical idea of the present invention.

Embodiments of the present invention to be described below provide a device isolation structure and a method of manufacturing the same in a semiconductor device having a plurality of device regions to prevent interference between adjacent device regions. Specifically, in an embodiment of the present invention, a device isolation structure capable of preventing cross talk between adjacent pixels in an image sensor having a plurality of pixels, an image sensor having the same, and a manufacturing method thereof To provide. To this end, embodiments of the present invention provide a first device isolation including an insulating film gap-filling a trench formed in a substrate and a second device isolation including an impurity region serving as a potential barrier to block the movement of carriers. Provides a device isolation structure having a stacked structure and an image sensor having the same, and a method of manufacturing the same.

On the other hand, the image sensor can be classified into a CCD type (Charge coupled device type) and a CMOS type (Complementary metal oxide semiconductor type), the CMOS type image sensor is front-side illumination (FSI) and back-irradiation (Back-Side Illumination, BSI). In the following description, the technical concept of the present invention will be described in detail by exemplifying an image sensor of a backside irradiation method.

1 is an equivalent circuit diagram of an image sensor according to an exemplary embodiment of the present invention.

As illustrated in FIG. 1, each of the pixels of the image sensor according to the exemplary embodiment may include a photoelectric conversion region PD, a transfer transistor Tx, a selection transistor Sx, a reset transistor Rx, and an access transistor Ax. It may include. The photoelectric conversion region PD may include a plurality of photoelectric conversion parts vertically overlapping each other. Each of the photoelectric conversion units may be a photodiode including an N-type impurity region and a P-type impurity region. The transfer gate of the transfer transistor (Tx) may extend into the substrate. In other words, the transfer gate may have a recess gate, a saddle-fin gate, or a buried gate. The drain of the transfer transistor Tx may be understood as the floating diffusion region FD. The floating diffusion region FD may be a source of a reset transistor Rx. The floating diffusion region FD may be electrically connected to the selection gate of the selection transistor Sx. The selection transistor Sx and the reset transistor Rx may be connected in a line. The selection transistor Sx is connected to an access transistor Ax. The reset transistor Rx, the select transistor Sx, and the access transistor Ax may be shared with each other by neighboring pixels, whereby the degree of integration may be improved.

The operation of the image sensor according to the embodiment will be described with reference to FIG. 1. First, the power voltage VDD is applied to the drain of the reset transistor Rx and the drain of the selection transistor Sx in a state where light is blocked to emit charges remaining in the floating diffusion region FD. Thereafter, when the reset transistor Rx is turned off and light from outside is incident on the photoelectric conversion region PD, an electron-hole pair is generated in the photoelectric conversion region PD. . The generated holes move to P-type impurity regions and electrons move to N-type impurity regions and accumulate. When the transfer transistor Tx is turned on, charges such as accumulated electrons and holes are transferred to and accumulated in the floating diffusion region FD. The gate bias of the selection transistor Sx changes in proportion to the accumulated charge amount, resulting in a change in the source potential of the selection transistor Sx. At this time, when the access transistor Ax is turned ON, the signal by the electric charge is read into the column line.

Here, as the image sensor is highly integrated, the size of each of the pixels and the spacing between the pixels are gradually reduced, resulting in a deterioration of characteristics due to interference between adjacent pixels, that is, a deterioration of characteristics due to crosstalk. In order to prevent crosstalk, a device isolation structure is formed on the substrate to separate the pixels.

The device isolation structure may be an impurity region formed by implanting impurities into a substrate, or an insulator region in which an insulator is gapfilled in a trench formed in the substrate. The impurity region has an advantage of preventing electrical crosstalk by acting as a potential barrier that blocks carrier transfer between pixels. However, the impurity region cannot prevent physical crosstalk due to incident light, it is very difficult to control the diffusion of impurities during the formation process, and in fact, it is not possible to increase the degree of integration of the device isolation structure. There is a disadvantage that causes deterioration of properties. On the other hand, the insulator region has an advantage of being easy to integrate and preventing physical crosstalk and electrical crosstalk due to incident light, but device isolation due to numerous defects and dangling bonds present on the surface. Insulation area for itself has a disadvantage that acts as a cause of dark current (Dark current) generation.

Accordingly, in the embodiments of the present invention described below, an isolation structure for preventing electrical crosstalk due to charge transfer and physical crosstalk due to incident light and facilitating integration and preventing generation of dark current, an image having the same The sensor and its manufacturing method will be described in detail.

2 is a plan view of an image sensor according to embodiments of the present disclosure, and FIGS. 3A and 3B are cross-sectional views taken along the line AA ′ of FIG. 2. 3A is a cross-sectional view showing an image sensor according to a first embodiment of the present invention, and FIG. 3B is a cross-sectional view showing a modification of the image sensor according to a first embodiment of the present invention.

As shown in FIGS. 2, 3A, and 3B, the image sensor according to the embodiment is formed on the substrate 101 to separate the plurality of pixels from the first device isolation 110 and the second device isolation. The device isolation structure 130 including the 120 and the photoelectric conversion region PD formed on the substrate 101 may correspond to the pixels separated by the device isolation structure 130. The substrate 101 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 101 may include a single crystal silicon-containing material.

The photoelectric conversion region PD may include a plurality of photoelectric conversion parts vertically overlapping each other, and each of the photoelectric conversion parts may be a photo diode including an N-type impurity region and a P-type impurity region. The photoelectric conversion region PD and the device isolation structure 130 may have a form spaced apart from each other by a predetermined interval.

The first device isolation 110 may include an insulating layer 112 for gap filling the trench 111 formed in the substrate 101. The insulating film 112 may be any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or two or more laminated films. For example, although not shown in the drawing, the insulating film 112 may be formed by thermal oxidation to form a sidewall oxide film formed on the surface of the trench 111, a liner nitride on the sidewall oxide film, and a liner oxide film on the liner nitride film. And a flow insulating layer including a high density plasma oxide (HDP) or a spin on dielectric (SOD) gap gap filling the trench 111 on the liner oxide layer.

The second device isolation 120 may include an impurity region that serves as a potential barrier for the photoelectric conversion region PD. The impurity region may be formed through an impurity ion implantation process and an annealing process, and may have a form in which impurities implanted along the edge of the impurity region are piled up due to the characteristics of the annealing process (see FIG. 9). Specifically, the second device isolation 120 is formed along the edges of the first impurity region 121 and the first impurity region 121 and has a second impurity dopant concentration greater than that of the first impurity region 121. 122). Since the impurity doping concentration of the second impurity region 122 is greater than that of the first impurity region 121, electrical crosstalk can be effectively prevented by increasing the potential barrier size at the impurity region interface. The first impurity region 121 and the second impurity region 122 may have the same conductivity type, and the first impurity region 121 and the second impurity region 122 may be formed simultaneously due to the characteristics of the annealing process. Can be. The conductivity type of the first impurity region 121 and the second impurity region 122 may be selected according to the conductivity type of the adjacent photoelectric conversion region PD. For example, when the conductivity type of the photoelectric conversion region PD adjacent to the second device isolation 120 is N type, the conductivity type of the first impurity region 121 and the second impurity region 122 is the photoelectric conversion region PD. It may be a P-type that can form a potential barrier for.

In addition, the first device isolation 110 and the second device isolation 120 of the device isolation structure 130 according to the embodiment may have a vertically overlapping structure. Specifically, the first device isolation 110 is stacked on the second device isolation 120 based on the back-side of the substrate 101 (see FIG. 3A), or the first device isolation is performed. The second device isolation 120 may be stacked on the 110 (see FIG. 3B). The device isolation structure 130 having a structure in which the first device isolation layer 110 is stacked on the second device isolation layer 120 based on the back-side of the substrate 101 has more effective physical crosstalk due to incident light. The device isolation structure 130 having a structure in which the second device isolation 120 is stacked on the first device isolation 110 based on the back-side of the substrate 101 may prevent dark current from occurring. Can be effectively prevented. Accordingly, the positions of the first device isolation 110 and the second device isolation 120 in the device isolation structure 130 may be selected according to required device characteristics. In addition, the device isolation structure 130 may have a depth greater than that of the photoelectric conversion region PD based on the front-side of the substrate 101. This is to improve the separation characteristic between adjacent pixels and to prevent crosstalk more effectively. For example, the device isolation structure 130 may have a form penetrating the substrate 101.

In addition, the image sensor according to the embodiment includes an interlayer insulating film 103 formed on the entire surface of the substrate 101, a signal generation circuit formed inside the interlayer insulating film 103, and a protective film formed between the substrate 101 and the interlayer insulating film 103. 102). The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 104. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. In addition, the multilayer metal wiring 104 may be electrically connected to the plurality of transistors and the plurality of metal wirings 104 through a plurality of contact plugs (not shown). The passivation layer 102 serves to prevent the inter-process signal generation circuit, in particular, the multilayer metal wiring 104 from being damaged. The passivation layer 102 may include a material layer having a lower thermal conductivity than the substrate 101, and may be a single layer or a laminated layer using a material layer having a lower thermal conductivity than the substrate 101. For example, when the substrate 101 includes a silicon-containing material, the passivation layer 102 may include a silicon-containing insulating layer 112 and a metal-containing insulating layer 112. The silicon-containing insulating layer 112 may include a silicon oxide layer (SiO ₂ ), and the metal-containing insulating layer 112 may include a zirconium oxide layer (ZrO ₂ ).

In addition, the image sensor according to the embodiment may include a color filter 105 formed on the back-side of the substrate 101 and a microlens 106 formed on the color filter 105.

The image sensor having the above-described structure includes a device isolation structure 130 in which the first device isolation 110 and the second device isolation 120 vertically overlap, thereby effectively preventing physical and electrical crosstalk between adjacent pixels. can do.

In addition, since the impurity doping concentration of the second impurity region 122 surrounding the first impurity region 121 is greater, electrical crosstalk can be more effectively prevented.

4A to 4E are process cross-sectional views illustrating a method of manufacturing the image sensor according to the first embodiment of the present invention, and illustrate an example of the method of manufacturing the image sensor shown in FIG. 3A.

As shown in FIG. 4A, a substrate 11 in which a plurality of pixels is defined is prepared. The substrate 11 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 11 may include a single crystal silicon-containing material.

Next, the substrate 11 is selectively etched along the boundary area where the plurality of pixels contact each other to form the trench 12 for first device isolation. An etching process for forming the trench 12 may be performed by dry etching.

Next, the insulating film 13 is formed so that the trench 12 may be gap-filled. The insulating layer 13 may be formed through a series of processes in which the insulating layer 13 is formed on the substrate 11 to fill the trench 12, and then the planarization process is performed until the surface of the substrate 11 is exposed. The insulating film 13 may be formed of any single film or two or more laminated films selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. For example, although not shown in the drawings, a trench is formed on the surface of the trench 12 by thermal oxidation, a liner nitride on the sidewall oxide, a liner oxide on the liner nitride, and a trench on the liner oxide. The insulating film 13 may be formed of a laminated film in which a flowable insulating film including a high density plasma oxide film (HDP) or a spin on dielectric film (SOD) having a gap fill (12) is stacked.

As a result, the first device isolation 14 including the insulating layer 13 to gap-fill the trench 12 formed in the substrate 11 can be formed.

Next, the photoelectric conversion region PD is formed in the substrate 11 to correspond to each pixel. The photoelectric conversion region PD may include a plurality of photoelectric conversion portions that vertically overlap each other, and each of the photoelectric conversion portions may be a photodiode including an N-type impurity region and a P-type impurity region. The photodiode may be formed through an impurity ion implantation process.

As shown in FIG. 4B, the passivation layer 15 is formed on the substrate 11 including the first device isolation 14 and the photoelectric conversion region PD. The protective film 15 may be formed of a material film having a lower thermal conductivity than the substrate 11, and may be formed of a single film or a laminated film using a material film having a lower thermal conductivity than the substrate 11. For example, when the substrate 11 includes a silicon-containing material, the protective film 15 may be formed of a silicon-containing insulating film and / or a metal-containing insulating film. The silicon-containing insulating film may include a silicon oxide film (SiO ₂ ), and the metal-containing insulating film may include a zirconium oxide film (ZrO ₂ ).

Next, an interlayer insulating film 16 including a signal generation circuit is formed on the protective film 15. The interlayer insulating film 16 may be any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, and may have a multilayer structure. The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 17. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. In addition, the multilayer metal wire 17 may be electrically connected to the plurality of transistors and the plurality of metal wires 17 through a plurality of contact plugs (not shown).

Although not shown in the drawing, after the signal generation circuit is formed, a thickness of the substrate 11 may be reduced by performing a thinning process on the back-side of the substrate 11. This is to increase the light receiving efficiency by reducing the reach of incident light incident on the photoelectric conversion region PD. The thinning process can be carried out through backgrinding and polishing.

As shown in FIG. 4C, after inverting the substrate 11 on which the signal generation circuit is formed, a mask pattern (not shown) is formed on the back side of the substrate 11. The mask pattern may have a shape of opening only a region where the device isolation structure is to be formed. That is, the mask pattern may have a form of opening the rear surface of the substrate 11 corresponding to the first device isolation 14 formed on the front side of the substrate 11.

Next, preamorphization is performed by implanting impurities into the back surface of the substrate 11 using a mask pattern (not shown) as an ion implantation barrier. When the substrate 11 is a silicon-containing material, germanium (Ge), silicon (Si), carbon (C), or the like may be used as impurities for pre-crystallization. An amorphous region 18 may be formed in the substrate 11 through pre-crystallization, and the bottom surface of the amorphous region 18 may be formed to contact the bottom surface of the first device isolation 14.

Pre-crystallization is for forming the amorphous region 18 having a melting temperature lower than that of the substrate 11 in the single crystal state. Specifically, the amorphous region 18 formed through pre-amorphization may have a lower melting temperature than the substrate 11 in the single crystal state. In one example, amorphous silicon has a melting temperature about 200 ° C. lower than single crystal silicon.

As shown in FIG. 4D, impurities that may act as potential barriers for the photoelectric conversion region PD are implanted into the amorphous region 18 using the mask pattern (not shown) as the ion implantation barrier. Hereinafter, the reference numeral of the amorphous region 18 into which impurities are injected will be changed to '19' and described.

An impurity capable of forming a potential barrier to the photoelectric conversion region PD may refer to an impurity having a conductivity type complementary to that of the adjacent photoelectric conversion region PD. For example, when the conductivity type of the photoelectric conversion region PD having sidewalls facing the amorphous region 19 is N-type, the impurity that may act as a potential barrier for the photoelectric conversion region PD may be a P-type impurity (eg, Boron) can be used.

As shown in FIG. 4E, an annealing process for activating the impurities injected into the amorphous region 19 and recrystallizing the amorphous region 19 is performed. In order to prevent deterioration of characteristics due to diffusion of the impurity implanted during the annealing process and to reduce the thermal burden on the formed structure, annealing is selectively performed only on the amorphous region 19. To this end, the annealing process can proceed to a laser anneal which can be locally annealed.

In the annealing process using the laser annealing, the laser is irradiated to the amorphous region 19 into which impurities are injected for a predetermined time to melt the amorphous region 19 having a lower melting temperature than the substrate 11 in a single crystal state. As a result, the molten amorphous region 19 solidifies from the point at which the laser irradiation is stopped, recrystallizes to a single crystal state while the implanted impurities are activated. At this time, even if the laser is irradiated to the substrate 11 due to the difference in melting temperature between the substrate 11 and the amorphous region 19 in the single crystal state, the substrate 11 is not melted. That is, selective melting is possible by forming the amorphous region 19 (see FIG. 10).

As a result, the second device isolation is formed along the edges of the first impurity region 20 and the first impurity region 20 and includes a second impurity region 21 having an impurity doping concentration greater than the first impurity region 20. (22) can be formed. By melting the amorphous region 19 into which the impurities are injected during the annealing process, high quality recrystallization is possible, the activation rate of the implanted impurities can be improved, and impurities injected into the boundary region during the recrystallization process are accumulated ( The second device isolation 22 including the first impurity region 20 and the second impurity region 21 can be easily formed (see FIG. 9).

Meanwhile, during the annealing process, damage to the signal generation circuit, in particular, the multi-layered metal wiring 17 formed by the protective film 15 including the material film having a lower thermal conductivity than the substrate 11 can be prevented.

Next, an image sensor can be completed using known manufacturing techniques. For example, the image sensor may be formed by sequentially forming a color filter and a microlens on the rear surface of the substrate 11 including the device isolation structure 23 including the first device isolation 14 and the second device isolation 22 vertically overlapping each other. I can complete it.

The image sensor formed by the above-described manufacturing method includes a device isolation structure 23 in which the first device isolation 14 and the second device isolation 22 vertically overlap each other, thereby providing physical and electrical crosstalk between adjacent pixels. Can be effectively prevented.

In addition, since the second device isolation 22 has a higher impurity doping concentration in the second impurity region 21 surrounding the first impurity region 20, electrical crosstalk can be more effectively prevented.

In addition, an annealing process that selectively melts the amorphous region 19 having a lower melting temperature than the substrate 11 in the single crystal state prevents deterioration of characteristics due to diffusion of the impurity implanted and is applied to the preformed structure. It can reduce the thermal burden.

5A and 5B are cross-sectional views taken along the line AA ′ of FIG. 2. 5A is a cross-sectional view showing an image sensor according to a second embodiment of the present invention, and FIG. 5B is a cross-sectional view showing a modification of the image sensor according to a second embodiment of the present invention.

As shown in FIGS. 2, 5A, and 5B, the image sensor according to the embodiment includes a first device isolation 210 and a second device isolation 220 formed on the substrate 201 to separate a plurality of pixels. The device isolation structure 230 and the photoelectric conversion region PD formed on the substrate 201 may be formed to correspond to the pixels separated by the device isolation structure 230. The substrate 201 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 201 may include a single crystal silicon-containing material.

The photoelectric conversion region PD may include a plurality of photoelectric conversion parts vertically overlapping each other, and each of the photoelectric conversion parts may be a photo diode including an N-type impurity region and a P-type impurity region. The photoelectric conversion region PD and the device isolation structure 230 may have a form spaced apart from each other by a predetermined interval.

The first device isolation 210 may include an insulating film 212 for gap filling the trench 211 formed in the substrate 201. The insulating film 212 may be any single film or two or more stacked films selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. As an example, although not shown in the drawing, the insulating film 122 may be formed by a thermal oxidation method, such as a sidewall oxide film formed on the surface of the trench 211, a liner nitride on the sidewall oxide film, and a liner oxide film on the liner nitride film. And a flow insulating film including a high density plasma oxide (HDP) or a spin on dielectric (SOD) gap gap filling the trench 211 on the liner oxide layer.

The second device isolation 220 may include an impurity region that serves as a potential barrier for the photoelectric conversion region PD. The impurity region may be formed through an impurity ion implantation process and an annealing process, and may have a form in which impurities implanted along the edge of the impurity region are piled up by the annealing process characteristic (see FIG. 9). In detail, the second device isolation 220 is formed along the edges of the first impurity region 221 and the first impurity region 221 and has a second impurity region having an impurity doping concentration greater than the first impurity region 221. 222 and a third impurity region 223 extended between the substrate 201 and the first device isolation 210. Since the impurity doping concentration of the second impurity region 222 is greater than that of the first impurity region 221, electrical crosstalk can be prevented more effectively by increasing the potential barrier size at the impurity region interface. The third impurity region 223 formed between the substrate 201 and the first device isolation 210 may prevent dangling bonds, defects, and the like at the interface between the first device isolation 210 and the substrate 201. It serves to prevent dark current by removing. The first impurity region 221 and the second impurity region 222 may have the same conductivity type, and the third impurity region 223 may be the same as the first impurity region 221 and the second impurity region 222. It may have a conductivity type or may have different conductivity types from each other. The conductivity type of the first impurity region 221 to the third impurity region 223 may be selected according to the conductivity type of the adjacent photoelectric conversion region PD.

In addition, the first device isolation 210 and the second device isolation 220 of the device isolation structure 230 according to the embodiment may have a vertically overlapping structure. Specifically, the first device isolation 210 is stacked on the second device isolation 220 based on the backside of the substrate 201 (see FIG. 5B), or the first device isolation is performed. The second device isolation 220 may be stacked on the 210 (see FIG. 5A). The device isolation structure 230 having the first device isolation 210 stacked on the second device isolation 220 based on the backside of the substrate 201 may more effectively prevent physical crosstalk due to incident light. The device isolation structure 230 of the structure in which the second device isolation 220 is stacked on the first device isolation 210 based on the back-side of the substrate 201 may prevent the occurrence of dark current. Can be effectively prevented. Accordingly, the positions of the first device isolation 210 and the second device isolation 220 in the device isolation structure 230 may be selected according to required device characteristics. In addition, the device isolation structure 230 may have a depth greater than that of the photoelectric conversion region PD based on the front-side of the substrate 201. This is to improve the separation characteristic between adjacent pixels and at the same time to prevent crosstalk more effectively. For example, the device isolation structure 230 may have a form penetrating the substrate 201.

In addition, the image sensor according to the embodiment may include an interlayer insulating film 203 formed on the entire surface of the substrate 201, a signal generation circuit formed inside the interlayer insulating film 203, and a protective film formed between the substrate 201 and the interlayer insulating film 203. 202). The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 204. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. In addition, the multi-layered metal wires 204 may be electrically connected to the plurality of transistors and the plurality of metal wires 204 through a plurality of contact plugs (not shown). The passivation layer 202 serves to prevent the inter-process signal generation circuit, in particular, the multilayer metal wiring 204 from being damaged. The passivation layer 202 may include a material layer having a lower thermal conductivity than the substrate 201, and may be a single layer or a laminated layer using a material layer having a lower thermal conductivity than the substrate 201. For example, when the substrate 201 includes a silicon-containing material, the protective film 202 may include a silicon-containing insulating film and a metal-containing insulating film. The silicon-containing insulating film may include a silicon oxide film (SiO ₂ ), and the metal-containing insulating film may include a zirconium oxide film (ZrO ₂ ).

In addition, the image sensor according to the embodiment may include a color filter 205 formed on the back-side of the substrate 201 and a microlens 206 formed on the color filter 205.

The image sensor having the above-described structure includes a device isolation structure 230 in which the first device isolation 210 and the second device isolation 220 vertically overlap each other, thereby effectively preventing physical and electrical crosstalk between adjacent pixels. You can prevent it.

In addition, the second device isolation 220 may more effectively prevent electrical crosstalk because the impurity doping concentration of the second impurity region 222 surrounding the first impurity region 221 is greater.

In addition, the second device isolation 220 may include a third impurity region 223 extended to an interface between the first device isolation 210 and the substrate 201, thereby effectively preventing dark current generation.

6A to 6E are cross-sectional views illustrating a method of manufacturing the image sensor according to the second exemplary embodiment of the present invention, and illustrate an example of the method of manufacturing the image sensor shown in FIG. 5A.

As shown in FIG. 6A, a substrate 31 in which a plurality of pixels is defined is prepared. The substrate 31 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 31 may include a single crystal silicon-containing material.

Next, a photoelectric conversion region PD is formed in the substrate 31 to correspond to each pixel. The photoelectric conversion region PD may include a plurality of photoelectric conversion portions that vertically overlap each other, and each of the photoelectric conversion portions may be a photodiode including an N-type impurity region and a P-type impurity region. The photodiode may be formed through an impurity ion implantation process.

Next, a protective film 32 is formed on the substrate 31 including the photoelectric conversion region PD. The protective film 32 may be formed of a material film having a lower thermal conductivity than the substrate 31, and may be formed of a single film or a laminated film using a material film having a lower thermal conductivity than the substrate 31. For example, when the substrate 31 includes a silicon-containing material, the protective film 32 may be formed of a silicon-containing insulating film and / or a metal-containing insulating film. The silicon-containing insulating film may include a silicon oxide film (SiO ₂ ), and the metal-containing insulating film may include a zirconium oxide film (ZrO ₂ ).

Next, an interlayer insulating film 33 including a signal generation circuit is formed on the protective film 32. The interlayer insulating film 33 may be any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, and may have a multilayer structure. The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 34. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. In addition, the multi-layered metal wires 34 may be electrically connected to the plurality of transistors and the plurality of metal wires 34 through a plurality of contact plugs (not shown).

As shown in FIG. 6B, a mask pattern (not shown) is formed on the backside of the substrate 31 after inverting the substrate 31 on which the signal generation circuit is formed. The mask pattern may have a shape of opening only a region where the device isolation structure is to be formed.

Next, the substrate 31 is etched using a mask pattern (not shown) as an etch barrier to form the trench 35 for first device isolation. An etching process for forming the trench 35 may be performed by dry etching.

Next, preamorphization is performed in which impurities are implanted into the rear surface of the substrate 31 on which the trench 35 is formed using the mask pattern (not shown) as the ion implantation barrier. Pre-crystallization can proceed a plurality of times while changing the impurity ion implantation angle. When the substrate 31 is a silicon-containing material, germanium (Ge), silicon (Si), carbon (C), or the like may be used as impurities for pre-crystallization. An amorphous region 36 may be formed in the substrate 31 through pre-crystallization. The amorphous region 36 may be formed in a pillar shape in which the top surface and the bottom surface contact the bottom surface of the trench 35 and the front side of the substrate 31, respectively. In addition, the amorphous region 36 may be formed to have a form in which a portion thereof is extended to contact the sidewall of the trench 35. That is, the amorphous region 36 may be formed in the sidewall substrate 31 of the trench 35.

Pre-crystallization is for forming the amorphous region 36 having a melting temperature lower than that of the substrate 31 in the single crystal state. Specifically, the amorphous region 36 may have a lower melting temperature than the substrate 31 in the single crystal state through pre-amorphization. In one example, amorphous silicon has a melting temperature about 200 ° C. lower than single crystal silicon.

Although not shown in the drawing, after the signal generation circuit is formed, a thickness of the substrate 31 may be reduced by performing a thinning process on the back-side of the substrate 31. This is to increase the light receiving efficiency by reducing the reach of incident light incident on the photoelectric conversion region PD. The thinning process can be carried out through backgrinding and polishing.

As illustrated in FIG. 6C, an impurity that may act as a potential barrier for the photoelectric conversion region PD is implanted into the amorphous region 36 using the mask pattern (not shown) as the ion implantation barrier. Impurity ion implantation can proceed a plurality of times while varying the ion implantation angle. Hereinafter, the reference numeral of the amorphous region 36 into which impurities are injected is changed to '37' and will be described.

An impurity capable of forming a potential barrier to the photoelectric conversion region PD may refer to an impurity having a conductivity type complementary to that of the adjacent photoelectric conversion region PD. For example, when the conductivity type of the photoelectric conversion region PD having sidewalls facing the amorphous region 37 is N-type, P-type impurities (eg, boron) may be used as impurities in the ion implantation process.

As shown in FIG. 6D, an annealing process for recrystallizing the amorphous region 37 is performed while activating impurities injected into the amorphous region 37. In order to prevent deterioration of characteristics due to diffusion of impurities implanted in the annealing process and to reduce thermal burden on the formed structure, annealing is selectively performed only on the amorphous region 37. To this end, the annealing process can proceed to a laser anneal which can be locally annealed.

In the annealing process using laser annealing, the laser is irradiated to the amorphous region 37 into which impurities are injected for a predetermined time to melt the amorphous region 37 having a lower melting temperature than the substrate 31 in a single crystal state. In addition, since the molten amorphous region 37 is solidified from the point at which the laser irradiation is stopped, the molten amorphous region 37 may be recrystallized and the implanted impurities may be activated. At this time, even if the laser is irradiated to the substrate 31 due to the difference in melting temperature between the substrate 31 and the amorphous region 37 in the single crystal state, the substrate 31 is not melted. That is, selective melting is possible by forming the amorphous region 37 (see FIG. 10).

As a result, the first impurity region 38 and the sidewalls of the second impurity region 39 and the trench 35 are formed along the edge of the first impurity region 38 and have an impurity doping concentration greater than that of the first impurity region 38. The second device isolation 41 including the formed third impurity region 40 may be formed. By melting the amorphous region 37 into which the impurities are injected during the annealing process, high quality recrystallization is possible, the activation rate of the implanted impurities can be improved, and impurities injected into the boundary region during the recrystallization process are accumulated ( pile up) The second device isolation 41 including the first impurity region 38 to the third impurity region 40 can be easily formed (see FIG. 9). In addition, since dangling bonds and defects on the surface of the trench 35 are removed by the third impurity region 40, dark current may be effectively prevented.

On the other hand, during the annealing process, damage to the signal generation circuit, in particular, the multi-layered metal wiring 34 formed by the protective film 32 including the material film having a lower thermal conductivity than the substrate 31 can be prevented.

As shown in FIG. 6E, an insulating film 42 is formed to gap fill the trench 35. The insulating film 42 may be formed through a series of processes in which the insulating film 42 is formed on the substrate 31 to fill the trench 35, and then the planarization process is performed until the surface of the substrate 31 is exposed. The insulating film 42 may be formed of any single film or two or more laminated films selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. For example, although not shown in the drawings, a trench is formed on the surface of the trench 35 by thermal oxidation, a liner nitride on the sidewall oxide film, a liner oxide on the liner nitride film, and a trench on the liner oxide film. The insulating film 42 can be formed from a laminated film in which a fluid insulating film including a high density plasma oxide film (HDP) or a spin on dielectric film (SOD) having a gap fill (35) is stacked.

As a result, the first device isolation 43 including the insulating layer 42 for gap filling the trench 35 formed in the substrate 31 can be formed. In addition, the device isolation structure 44 including the first device isolation 43 and the second device isolation 41 vertically overlapping may be formed.

Next, although not shown in the drawings, it is possible to complete an image sensor using a known manufacturing technique. For example, the image sensor may be completed by sequentially forming the color filter and the microlens on the rear surface of the substrate 31.

The image sensor formed by the above-described manufacturing method includes a device isolation structure 44 in which the first device isolation 43 and the second device isolation 41 vertically overlap each other, thereby providing physical and electrical crosstalk between adjacent pixels. Can be effectively prevented.

In addition, since the second device isolation 41 has a higher impurity doping concentration in the second impurity region 39 surrounding the first impurity region 38, electrical crosstalk can be more effectively prevented.

In addition, dark current generation can be effectively prevented by the third impurity region 40 of the second device isolation 41.

In addition, an annealing process for selectively melting the amorphous region 37 having a lower melting temperature than the substrate 31 in a single crystal state prevents deterioration of characteristics due to diffusion of the impurity implanted and is applied to the preformed structure. It can reduce the thermal burden.

7A and 7B are cross-sectional views taken along the line AA ′ of FIG. 2. 7A is a cross-sectional view showing an image sensor according to a third embodiment of the present invention, and FIG. 7B is a cross-sectional view showing a modification of the image sensor according to a third embodiment of the present invention.

As shown in FIGS. 2, 7A, and 7B, the image sensor according to the embodiment includes a plurality of elements separated by the device isolation structure 330 including a first device isolation 310 and a second device isolation 320. Formed on the substrate 301 corresponding to the respective pixels separated by the isolation structure 330 and the substrate 301 having the pixels Pix and having a surface 301A protruding corresponding to the respective pixels. It may include a photoelectric conversion region PD. The substrate 301 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 301 may include a single crystal silicon-containing material. The protruding surface 301A serves to improve the focusing ability for incident light, and may be formed on the backside of the substrate 301 to which incident light enters. The protruding surface 301A may have a curvature for effective focusing of incident light. For example, the curved surface 301A may have a convex shape that protrudes above the back surface of the substrate 301.

The photoelectric conversion region PD may include a plurality of photoelectric conversion parts vertically overlapping each other, and each of the photoelectric conversion parts may be a photo diode including an N-type impurity region and a P-type impurity region. The photoelectric conversion region PD and the device isolation structure 330 may have a form spaced apart from each other by a predetermined interval.

The first device isolation layer 310 may include an insulating layer 312 that gap-fills the trench 311 formed in the substrate 301. The insulating film 312 may be any single film selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, or two or more stacked films. As an example, although not shown in the drawing, the insulating film 112 may be formed by a thermal oxidation method, including a sidewall oxide film formed on the surface of the trench 311, a liner nitride on the sidewall oxide film, and a liner oxide film on the liner nitride film. And a flow insulating film including a high density plasma oxide (HDP) or a spin on dielectric (SOD) gap gap filling the trench 311 on the liner oxide layer.

The second device isolation 320 may include an impurity region that serves as a potential barrier for the photoelectric conversion region PD. The impurity region may be formed through an impurity ion implantation process and an annealing process, and may have a form in which impurities implanted along the edge of the impurity region are piled up due to the characteristics of the annealing process (see FIG. 9). Specifically, the second device isolation 320 is formed along the edges of the first impurity region 321 and the first impurity region 321 and has a second impurity region having an impurity doping concentration greater than the first impurity region 321. 322) (see FIG. 7A). In addition, the second device isolation 320 may include a first impurity region 321 and a second impurity region 322, and a third impurity region 323 formed between the substrate 301 and the first device isolation 310. It may further include (see Fig. 7b). Since the impurity doping concentration of the second impurity region 322 is greater than that of the first impurity region 321, electrical crosstalk can be more effectively prevented by increasing the potential barrier at the impurity region interface. The third impurity region 323 formed between the substrate 301 and the first device isolation 310 may provide dangling bonds, defects, and the like at an interface between the first device isolation 310 and the substrate 301. It serves to prevent dark current by removing. The first impurity region 321 and the second impurity region 322 may have the same conductivity type, and the third impurity region 323 is the same as the first impurity region 321 and the second impurity region 322. It may have a conductivity type or may have different conductivity types from each other. The conductivity type of the first impurity region 321 to the third impurity region 323 may be selected according to the conductivity type of the adjacent photoelectric conversion region PD.

In addition, the first device isolation 310 and the second device isolation 320 of the device isolation structure 330 according to the embodiment may have a vertically overlapping structure. In detail, the second device isolation layer 320 may be stacked on the first device isolation layer 310 based on the backside of the substrate 301. The device isolation structure 330 having the structure in which the second device isolation layer 320 is stacked on the first device isolation layer 310 based on the backside of the substrate 301 may effectively prevent dark current generation. In addition, the device isolation structure 330 may have a depth greater than that of the photoelectric conversion region PD based on the front-side of the substrate 301. This is to improve the separation characteristic between adjacent pixels and to prevent crosstalk more effectively. For example, the device isolation structure 330 may have a form penetrating the substrate 301.

In addition, the image sensor according to the embodiment may include an interlayer insulating film 303 formed on the front surface of the substrate 301, a signal generation circuit formed inside the interlayer insulating film 303, and a protective film formed between the substrate 301 and the interlayer insulating film 303. 302). The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 304. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. In addition, the multi-layered metal wires 304 may be electrically connected to the plurality of transistors and the plurality of metal wires 304 through a plurality of contact plugs (not shown). The passivation layer 302 serves to prevent the inter-process signal generation circuit, in particular, the multilayer metal wiring 304 from being damaged. The passivation layer 302 may include a material layer having a lower thermal conductivity than the substrate 301, and may be a single layer or a laminated layer using a material layer having a lower thermal conductivity than the substrate 301. For example, when the substrate 301 includes a silicon-containing material, the passivation layer 302 may include a silicon-containing insulating layer 312 and a metal-containing insulating layer 312. The silicon-containing insulating film 312 may include a silicon oxide film (SiO ₂ ), and the metal-containing insulating film 312 may include a zirconium oxide film (ZrO ₂ ).

In addition, the image sensor according to the embodiment of the present invention includes a flattening film 307 formed on the back-side of the substrate 301, a color filter 305 formed on the flattening film 307, and a micro formed on the color filter 305. It may include a lens 306. The planarization film 307 serves to remove the step caused by the protruding surface 301A.

The image sensor having the above-described structure includes a device isolation structure 330 in which the first device isolation 310 and the second device isolation 320 vertically overlap, thereby effectively preventing physical and electrical crosstalk between adjacent pixels. can do.

In addition, the second device isolation 320 may more effectively prevent electrical crosstalk because the impurity doping concentration of the second impurity region 322 surrounding the first impurity region 321 is greater.

In addition, the second device isolation 320 may include a third impurity region 323 extended to an interface between the first device isolation 310 and the substrate 301, thereby effectively preventing dark current generation.

In addition, by providing the surface 301A which protrudes to the board | substrate 301, focusing with respect to incident light can be improved.

8A to 8G are cross-sectional views illustrating a method of manufacturing the image sensor according to the third exemplary embodiment of the present invention, and illustrate an example of the method of manufacturing the image sensor shown in FIG. 7A.

As shown in FIG. 8A, a substrate 51 in which a plurality of pixels is defined is prepared. The substrate 51 may include a semiconductor substrate. The semiconductor substrate may be in a single crystal state and may include a silicon-containing material. That is, the substrate 51 may include a single crystal silicon-containing material.

Next, a photoelectric conversion region PD is formed in the substrate 51 so as to correspond to each pixel. The photoelectric conversion region PD may include a plurality of photoelectric conversion portions that vertically overlap each other, and each of the photoelectric conversion portions may be a photodiode including an N-type impurity region and a P-type impurity region. The photodiode may be formed through an impurity ion implantation process.

Next, a protective film 52 is formed on the substrate 51 including the photoelectric conversion region PD. The protective film 52 may be formed of a material film having a lower thermal conductivity than the substrate 51, and may be formed of a single film or a laminated film using a material film having a lower thermal conductivity than the substrate 51. For example, when the substrate 51 includes a silicon-containing material, the protective film 52 may be formed of a silicon-containing insulating film and / or a metal-containing insulating film. The silicon-containing insulating film may include a silicon oxide film (SiO ₂ ), and the metal-containing insulating film may include a zirconium oxide film (ZrO ₂ ).

Next, an interlayer insulating film 53 including a signal generation circuit is formed on the protective film 52. The interlayer insulating film 53 may be any one selected from the group consisting of an oxide film, a nitride film, and an oxynitride film, and may have a multilayer structure. The signal generation circuit generates (or outputs) an electric signal corresponding to the charge generated in the photoelectric conversion region PD. In detail, the signal generation circuit may include a plurality of transistors and multiple metal interconnections 54. The plurality of transistors may include a transfer transistor Tx, a reset transistor Rx, a selection transistor Sx, and an access transistor Ax. The multi-layered metal wires 54 may be electrically connected to the plurality of transistors and the plurality of metal wires 54 through a plurality of contact plugs (not shown).

As shown in FIG. 8B, after inverting the substrate 51 on which the signal generation circuit is formed, a mask pattern (not shown) is formed on the back side of the substrate 51. The mask pattern may have a shape of opening only a region where the device isolation structure is to be formed.

Next, the substrate 51 is etched using the mask pattern (not shown) as an etch barrier to form the trench 55 for first device isolation. An etching process for forming the trench 55 may be performed by dry etching.

Although not shown in the drawing, after the signal generation circuit is formed, a thickness of the substrate 51 may be reduced by performing a thinning process on the back-side of the substrate 51. This is to increase the light receiving efficiency by reducing the reach of incident light incident on the photoelectric conversion region PD. The thinning process can be carried out through backgrinding and polishing.

As shown in FIG. 8C, a first annealing process is performed to form a surface 51A on which the substrate 51 protrudes on the rear surface of the substrate 51 corresponding to the photoelectric conversion region PD. The primary annealing process may proceed to a laser annealing that can be locally annealed to form a surface 51A that protrudes selectively on the back surface of the substrate 51 corresponding to the photoelectric conversion region PD. The protruding surface 51A is to improve focusing on incident light, and may be formed by lattice movement occurring during the first annealing process (see FIG. 11).

On the other hand, damage (or defects) generated on the surface of the trench 55 during the trench 55 formation process can be cured by the primary annealing process. Therefore, the dark current can be prevented through the primary annealing process. In addition, it is possible to prevent damage to the signal generation circuit, in particular, the multi-layered metal wiring 54, formed by the protective film 52 including the material film having a lower thermal conductivity than the substrate 51 during the first annealing process.

As shown in FIG. 8D, preamorphization of ion implantation of impurities into the back surface of the substrate 51 where the trench 55 is formed using a mask pattern (not shown) for opening the trench 55 as an ion implantation barrier. Proceed. When the substrate 51 is a silicon-containing material, germanium (Ge), silicon (Si), carbon (C), or the like may be used as impurities for pre-crystallization. An amorphous region 56 may be formed in the substrate 51 through pre-amorphization. The amorphous region 56 may have a pillar shape where the top surface and the bottom surface contact the bottom surface of the trench 55 and the front side of the substrate 51, respectively.

Pre-crystallization is for forming an amorphous region 56 having a lower melting temperature than the substrate 51 in a single crystal state. Specifically, the amorphous region 56 may have a lower melting temperature than the substrate 51 in the single crystal state through pre-amorphization. In one example, amorphous silicon has a melting temperature about 200 ° C. lower than single crystal silicon.

As shown in FIG. 8E, impurities that may act as potential barriers for the photoelectric conversion region PD are implanted into the amorphous region 56 using the mask pattern (not shown) as the ion implantation barrier. Hereinafter, the reference numeral of the amorphous region 56 into which impurities are injected is changed to '57' and described.

An impurity capable of forming a potential barrier to the photoelectric conversion region PD may refer to an impurity having a conductivity type complementary to that of the adjacent photoelectric conversion region PD. For example, when the conductivity type of the photoelectric conversion region PD having sidewalls facing the amorphous region 57 is N-type, P-type impurities (eg, boron) may be used as impurities in the ion implantation process.

As shown in FIG. 8F, a second annealing process is performed to recrystallize the amorphous region 57 while activating the implanted impurities. In order to prevent deterioration of characteristics due to diffusion of impurities implanted during the second annealing process and to reduce thermal burden on the pre-formed structure, annealing is selectively performed only on the amorphous region 57. To this end, the secondary annealing process can proceed to a laser annealing that can be locally annealed.

In the secondary annealing process using laser annealing, the laser is irradiated to the amorphous region 57 into which impurities are injected for a predetermined time to melt the amorphous region 57 having a lower melting temperature than the substrate 51 in a single crystal state. And the molten amorphous region 57 is recrystallized from the point at which the laser irradiation is stopped, and the implanted impurities are activated. At this time, even if the laser is irradiated to the substrate 51 due to the difference in melting temperature between the substrate 51 in the single crystal state and the amorphous region 57, the substrate 51 is not melted. That is, by forming the amorphous region 57, selective melting is possible (see FIG. 10).

As a result, the second device isolation is formed along the edges of the first impurity region 58 and the first impurity region 58 and includes a second impurity region 59 having an impurity doping concentration greater than the first impurity region 58. 60 can be formed. By melting the amorphous region 57 into which impurities are injected during the second annealing process, high-quality recrystallization is possible, the activation rate of the injected impurities can be improved, and impurities injected into the boundary region during the recrystallization process accumulate. The first impurity region 58 and the second impurity region 59 can be simultaneously formed (see FIG. 9).

On the other hand, during the second annealing process, it is possible to prevent the signal generation circuit, in particular, the multi-layered metal wiring 54, formed by the protective film 52 including the material film having a lower thermal conductivity than the substrate 51.

As shown in FIG. 8G, the insulating film 61 is formed to gap fill the trench 55. After the insulating film 61 is formed on the substrate 51 to gap fill the trench 55, the insulating film 61 is planarized until the surface of the substrate 51 is exposed, and then the insulating film ( 61 may be formed through a series of processes that partially recess. The insulating film 61 may be formed of any single film or two or more laminated films selected from the group consisting of an oxide film, a nitride film, and an oxynitride film. For example, although not shown in the drawings, a trench is formed on a sidewall oxide film formed on the surface of the trench 55 by thermal oxidation, a liner nitride on the sidewall oxide film, a liner oxide on the liner nitride film, and a trench on the liner oxide film. An insulating film 61 is formed of a laminated film in which a fluid insulating film 61 including a high density plasma oxide film (HDP) or a spin on dielectric film (SOD) having a gap fill therebetween is stacked. can do.

As a result, the first device isolation 62 including the insulating layer 61 for gap filling the trench 55 formed in the substrate 51 can be formed. In addition, the device isolation structure 63 may include a first device isolation 62 and a second device isolation 60 that vertically overlap.

Next, although not shown in the drawings, it is possible to complete an image sensor using a known manufacturing technique. For example, an image sensor may be completed by sequentially forming a planarization film, a color filter, and a microlens on the rear surface of the substrate 51.

The image sensor formed by the above-described manufacturing method includes a device isolation structure 63 in which the first device isolation 62 and the second device isolation 60 vertically overlap each other, thereby providing physical and electrical crosstalk between adjacent pixels. Can be effectively prevented.

In addition, since the second device isolation 60 has a higher impurity doping concentration in the second impurity region 59 surrounding the first impurity region 58, electrical crosstalk can be more effectively prevented.

In addition, by forming the protruding surface 51A through the primary annealing process, focusing on incident light can be improved and dark current generation can be prevented.

In addition, the secondary annealing process for selectively melting the amorphous region 57 having a lower melting temperature than the substrate 51 in the single crystal state prevents deterioration of characteristics due to diffusion of the implanted impurities and simultaneously It can reduce the thermal burden applied.

9 is a graph showing the impurity doping concentration of an impurity region formed through laser annealing including selective melting.

Referring to FIG. 9, it can be seen that the impurity region activated by the laser annealing including the selective melting, that is, the second device isolation, accumulates impurities injected into the boundary region. That is, it can be seen that the first impurity region and the second impurity region having an impurity doping concentration greater than the first impurity region are formed by laser annealing including selective melting.

In addition, the first impurity region maintains a relatively uniform impurity doping concentration in accordance with the depth, it is possible to adjust the depth of the second device separation in accordance with the laser irradiation energy.

10 is a graph showing melting of silicon having different crystal structures according to laser irradiation energy.

Referring to FIG. 10, when the laser of the same energy is irradiated to amorphous silicon and single crystal silicon, it can be seen that selective melting is possible due to the difference in crystal structure. In other words, the amorphous silicon and the single crystal silicon have different melting temperatures due to differences in their crystal structures, and only the amorphous silicon can be selectively melted using this difference.

11 is an image showing the lattice movement according to the laser annealing.

Referring to FIG. 11, it can be seen that as the laser irradiation energy increases, the corners (corresponding to the trenches in the third embodiment) are deformed into rounded shapes. That is, the silicon lattice is moved by laser annealing and its shape is deformed. Thus, a protruding surface may be formed using the silicon lattice.

12 is a block diagram illustrating a configuration of an image sensor according to an exemplary embodiment of the present invention.

As illustrated in FIG. 12, the CMOS image sensor 2100 may include an active pixel sensor array 2110, a controller 2130, a row driver 2120, and a pixel signal processor 2140. The active pixel sensor array 2110 may include an image sensor according to the first to third embodiments of the present invention. In detail, the active pixel sensor array 2110 may include a first device isolation including an insulating layer gap-filling a trench formed in the substrate, and impurities formed along edges of the first impurity region and the first impurity region formed on the substrate, and larger than the first impurity region. The device may include a device isolation structure in which a second device isolation including a second impurity region having a doping concentration is stacked, and an image sensor including a photoelectric conversion region formed in a substrate corresponding to a plurality of pixels separated by the device isolation structure. . In addition, the second device isolation may further include a third impurity region formed between the substrate and the first device isolation. The substrate may further include a passivation layer formed on the front surface of the substrate, an interlayer insulating layer formed on the passivation layer, and a surface protruding from the rear surface of the substrate to correspond to the photoelectric conversion region. The electrical signal converted in the photoelectric conversion region is provided to the pixel signal processor 2140 through a vertical signal line. Pixel sensors in the active pixel sensor array 2110 are read out one at a time in row units. Accordingly, the pixels in one row of the active pixel sensor array 2110 are all simultaneously activated by the row select signal that is the output of the row driver 2120.

Each pixel in the selected row also provides a signal corresponding to the received light to the output line of the corresponding column. In an active pixel sensor array (APS) 1210, each column has a select line, and pixel cells of each column are selectively output in response to the column select signal. Rows in the active pixel sensor array APS 2110 are activated in response to the output signal of the row driver 2120.

The controller 2130 controls the row driver 2120 and the pixel signal processor 2140 to appropriately process the pixel signals output from the active pixel sensor array 2110. The pixel signal processor 2140 includes a correlated double sampler (CDS) 2142, an analog-to-digital converter (ADC: 2144), and a buffer (Buffer 2146).

The correlated double sampler (CDS) 2142 receives, samples, and holds an electrical signal generated by the active pixel sensor array 2110 through a vertical signal line. That is, the signal level of the specific noise level and the generated electrical signal is sampled twice, and the difference level corresponding to the difference between the noise level and the signal level is output. A ramp signal generated from a ramp signal generator (Ramp Gen. 2148) may be input and compared with each other, and the comparison results may be output to an output terminal. The ramp signal generator (Ramp Gen.) 2148 may operate based on a control signal generated by the controller 2130.

An analog-to-digital converter (ADC) 2144 converts an analog signal corresponding to a difference level into a digital signal. The buffer 2146 may include a column memory block (not shown) and a sense amplifier (not shown), and the column memory block (not shown) may include a plurality of memories (not shown).

The buffer 2146 latches the digital signal, and the latched signal is sequentially output from the column decoder (not shown) to the image processor (not shown) according to the decoding result.

The CMOS image sensor 2100 of FIG. 12 may further include an image processor (not shown) and may be implemented as one semiconductor chip. An image processor (not shown) performs image processing on the digitized pixel signals and outputs image data. The CMOS image sensor 2100 senses an object photographed through a lens under control of an image processor (not shown), and the image processor (not shown) is sensed and output by the image sensor 2100. The displayed image may be output to a display unit (not shown). In this case, the display unit (not shown) includes all devices capable of outputting an image. For example, the display unit (not shown) may include a computer, a mobile phone, and other image output terminals. The CMOS image sensor 2100 according to the embodiment of the present invention illustrated in FIG. 12 may include the image sensor according to the first to third embodiments of the present invention. Therefore, it is possible to output image data undamaged by crosstalk and dark current between adjacent pixels.

13 is a block diagram illustrating a system including an image sensor according to an exemplary embodiment of the present invention.

Here, the system 2200 of FIG. 13 may be a computer system, a camera system, a scanner, a vehicle navigation system, a video phone, a security system, and a motion detection system requiring image data.

As shown in FIG. 13, the system 2200 may include a central processing unit (CPU) 2210 or a processor 2210, a nonvolatile memory 2220, an image sensor 2230, and an input / output device (I / O) 2240. ) And RAM (Random Access Memory: 2250).

The central processing unit (CPU) 2210 communicates with the input / output device (I / O) 2240 through the bus 2260.

The image sensor 2230 communicates with a central processing unit (CPU) 2210 via a bus 2260. In addition, the RAM 2250 and the nonvolatile memory 2220 also communicate with the CPU 2210 through the bus 2260. The image sensor 2230 may exist as an independent semiconductor chip, or may be combined with the central processing unit 2210 to form one semiconductor chip.

The image sensor 2230 included in the system of FIG. 13 may include the image sensor according to the first to third embodiments of the present invention. Therefore, it is possible to output image data undamaged by crosstalk and dark current between adjacent pixels.

In the above-described embodiments of the present invention, the case in which the device isolation structure according to the technical idea of the present invention is applied to the image sensor has been described by way of example. Applicable to all semiconductor devices requiring a structure.

Although the technical spirit of the present invention has been described in detail according to the above preferred embodiment, it should be noted that the above embodiment is for the purpose of description and not of limitation. In addition, those skilled in the art will appreciate that various embodiments within the scope of the technical idea of the present invention are possible.

101: substrate 102: protective film
103: interlayer insulating film 104: metal wiring
105: color filter 106: microlens
110: first device isolation 111: trench
112: insulating film 120: second device isolation
121: first impurity region 122: second impurity region
130: device isolation structure

Claims

An element isolation structure for separating a plurality of device regions,
First device isolation including an insulating film for gap-filling trenches formed in the substrate; And
A second device isolation including a first impurity region formed on the substrate and a second impurity region formed along an edge of the first impurity region and having an impurity doping concentration greater than that of the first impurity region,
And a device isolation structure in which the first device isolation and the second device isolation are stacked.

Claim 2 has been abandoned upon payment of a set-up fee.

The method of claim 1,
And the second device isolation further comprises a third impurity region formed between the substrate and the first device isolation.

Claim 3 has been abandoned upon payment of a set-up fee.

The method of claim 1,
And the second device isolation device comprises an impurity that acts as a potential barrier for the substrate corresponding to the device region.

Claim 4 has been abandoned upon payment of a setup registration fee.

The method of claim 1,
And a second device isolation stacked on the first device isolation, or the first device isolation stacked on the second device isolation.

Claim 5 was abandoned upon payment of a set-up fee.

The method of claim 1,
And separating the first device isolation and the second device isolation to penetrate the substrate.

In the manufacturing method of the device isolation structure for separating a plurality of device regions,
Selectively etching the substrate to form a trench;
Forming an amorphous region having a lower melting temperature than the substrate in the substrate under the trench;
Implanting impurities into the amorphous region; And
Melting the amorphous region to activate an implanted impurity and simultaneously performing annealing to recrystallize
Device isolation structure manufacturing method comprising a.

Claim 7 was abandoned upon payment of a set-up fee.

The method of claim 6,
And forming an insulating film gap-filling the trench before forming the amorphous region or after the annealing.

Claim 8 has been abandoned upon payment of a set-up fee.

The method of claim 6,
And annealing after forming the trench.

Claim 9 was abandoned upon payment of a set-up fee.

The method of claim 6,
The amorphous region is a device isolation structure manufacturing method for forming through pre-amorphous.

Claim 10 has been abandoned upon payment of a setup registration fee.

The method of claim 6,
The annealing device isolation structure manufacturing method comprising a laser annealing.

Claim 11 was abandoned upon payment of a set-up fee.

The method of claim 10,
The step of proceeding the annealing,
Irradiating a laser for a predetermined time to melt the amorphous region; And
Blocking the laser irradiation to solidify the molten amorphous region
Device isolation structure manufacturing method comprising a.

Claim 12 was abandoned upon payment of a set-up fee.

The method of claim 6,
In the step of implanting impurities into the amorphous region,
And the impurity is an impurity acting as a potential barrier with respect to the substrate corresponding to the device region.

A first device isolation including an insulating layer gap-filling a trench formed in the substrate, and a second impurity region formed along the edges of the first impurity region and the first impurity region formed on the substrate and having a higher impurity doping concentration than the first impurity region. A device isolation structure including a second device isolation stacked; And
A photoelectric conversion region formed in the substrate corresponding to the plurality of pixels separated by the device isolation structure
Image sensor comprising a.

Claim 14 was abandoned upon payment of a set-up fee.

The method of claim 13,
And the second device isolation further comprises a third impurity region formed between the substrate and the first device isolation.

Claim 15 was abandoned upon payment of a set-up fee.

The method of claim 13,
The second device isolation includes an impurity that acts as a potential barrier for the photoelectric conversion region.

Claim 16 was abandoned upon payment of a set-up fee.

The method of claim 13,
And the second device isolation layer is stacked on the first device isolation, or the first device isolation layer is stacked on the second device isolation.

Claim 17 was abandoned upon payment of a set-up fee.

The method of claim 13,
And an image sensor having a depth greater than that of the photoelectric conversion region.

Claim 18 was abandoned when the set registration fee was paid.

The method of claim 13,
The device isolation structure penetrates through the substrate.

Claim 19 was abandoned upon payment of a set-up fee.

The method of claim 13,
A protective film formed on an entire surface of the substrate;
An interlayer insulating film formed on the passivation film and including a metal wiring; And
A surface protruding from a rear surface of the substrate corresponding to the photoelectric conversion region
Image sensor further comprising

Claim 20 was abandoned when the set registration fee was paid.

The method of claim 19,
The passivation layer may include a material layer having a lower thermal conductivity than the substrate.