KR102023752B1 - The converting apparatus for reducing harmonic electromagnetic interference - Google Patents

Abstract

The converting device for harmonic EMI reduction according to an embodiment of the present invention, the voltage-controlled oscillator (VCO), the N-divider (N-Divider of the Fractional-N structure connected to the voltage-controlled oscillator) ), A phase frequency detector (PFD) connected to the N-divider and a power stage of a buck converter structure connected to the PFD.

Description

CONVERTING APPARATUS FOR REDUCING HARMONIC ELECTROMAGNETIC INTERFERENCE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a converting device for harmonic EMI reduction, and more particularly, to a buck converter based on Fractional-N Digital Phase Locked Loop (DPLL) using a Sigma-Delta Modulator (SDM). (Buck converter).

In recent years, the utilization of portable electronic devices such as smart phones, wearable devices, tablet PCs, laptops, and the like, is increasing. With the convenience of the mobile convenience stores and the improved performance of devices, the number of uses of these products and the dependence of users are gradually increasing. These products are important for their small size, light weight, and long battery life, among other things, a Power Management Integrated Circuit (PMIC) is essential for effective power management to increase the life expectancy of the product and increase its service life. Among various power converters, various types of buck converters have been studied in that a buck converter (eg, a DC-DC buck converter) can obtain high efficiency and can be used in a low voltage power supply device.

However, the periodic switching pulse of the pulse width modulation (PWM) signal used to control the output of the buck converter has a high harmonic component, and these harmonic components generate noise by combining with parasitic components such as switches, inductors and capacitors. Let's do it. This phenomenon is called Electromagnetic Interference (EMI), which is fatal to the operation of RF / Analog circuits that are vulnerable to noise. In other words, in a buck converter using a PWM control method, the harmonic component of the switching frequency is represented as a conductive EMI of the output voltage due to a fixed switching frequency. This conductive EMI has a fatal effect on the operation of noise-sensitive RF / Analog circuits. Thus, to eliminate this, conventional buck converters have additional EMI protection circuitry to compensate for noise. However, additional EMI circuitry occupies a large area outside the circuit, making it difficult to apply to miniaturized electronic devices. Therefore, buck converters dealing with these EMI issues have been studied to see the effects of reducing EMI noise at the output voltage by spreading the frequency of switching pulses to remove harmonics.

1. Republic of Korea Patent Publication No. 10-2010-0092157 (published: 2010.08.20)

SUMMARY OF THE INVENTION The present invention has been made in response to the above-described problem, and aims to provide a digital phase locked loop based buck converter capable of fractional division.

As an embodiment of the present invention, a converting device for reducing harmonic EMI may be provided.

The converting device for harmonic EMI reduction according to an embodiment of the present invention, the voltage-controlled oscillator (VCO), the N-divider (N-Divider of the Fractional-N structure connected to the voltage-controlled oscillator) ), A phase frequency detector (PFD) connected to the N-divider and a power stage of a buck converter structure connected to the PFD.

In addition, a sigma-delta modulator (SDM) is connected to the N-divider, and the sigma-delta is divided into an SDM-applied Fractional-N instead of an Integer N. The modulator SDM may have a MASH structure.

The output voltage of the buck converter structure in which voltage sigma phase information that is generated when the input to the controlled oscillator (VCO) - is made to frequency division random (Random) from N- divider delta modulator is connected, and the frequency divider when the frequency (F _DIV) The reference frequency F _REF may be compared to determine the duty of the PWM signal.

The signal applied to the voltage controlled oscillator (VCO) is applied from each of the coarse loop structure and the fine loop structure, and the coarse loop structure has an N-divider, an N-divider and A connected phase frequency detector is included, and the fine loop structure may include a power stage of the buck converter structure.

The voltage controlled oscillator can be a dual loop VCO with two control loops, the voltage of the coarse loop and the voltage of the fine loop.

According to an embodiment of the present invention, a free running frequency (f ₀ ) and a conversion gain (KVCO) of the voltage controlled oscillator (VCO) are set through a coarse loop structure to determine the output signal (V _OUT ). After adjusting the frequency f _OUT to a frequency lock range, the output signal V _OUT may be controlled by finely adjusting the frequency of the voltage controlled oscillator VCO through a fine loop structure.

The buck converter, which can be implemented as an embodiment of the present invention, can effectively reduce the EMI noise of the output voltage compared to the conventional buck converter structure, and has the advantage that the low-area design is possible. have.

According to an embodiment of the present invention, in order to reduce conductive EMI, the controller may be implemented as a digital phase locked loop (DPLL) capable of fractional-N division, and in particular, a voltage controlled oscillator (VCO) using a sigma-delta modulator (SDM). Based on the Random Duty PWM Generator, the harmonic content of the output voltage can be effectively reduced.

In addition, according to an embodiment of the present invention, by generating a random PWM signal using N-Divider, SDM and PFD, the EMI noise of the output voltage may be reduced and the resolution of the output voltage may be further increased.

The structure is simpler than the conventional method, and it has advantages in terms of operation efficiency, circuit implementation size, and load transient response time.

The converting device technology for harmonic EMI reduction according to an embodiment of the present invention can be used as an effective power supply circuit by applying to the RF / analog circuit sensitive to conductive EMI noise. In addition, according to an embodiment of the present invention can be actively applied to a portable electronic device, such as a wearable device such as a smart phone, smart watch due to the low-area design.

1 illustrates a buck converter using a method of removing a harmonic component of PWM using a frequency hopping method.
Figure 2 shows a buck converter of the method for controlling the output by randomly generating a pulse corresponding to the target voltage using the SDM ADC.
3 is a block diagram of an analog PWM generator and a VCO based PWM generator used in a conventional PWM control buck converter.
4 is a block diagram illustrating a converting apparatus for reducing harmonic EMI according to an embodiment of the present invention.
5 is a block diagram and an operation example of a VCO based Fractional-N PWM Generator according to an embodiment of the present invention.
6 shows a structure and an operation example of the SDM according to an embodiment of the present invention.
7 is a block diagram illustrating a converting apparatus for reducing harmonic EMI according to another embodiment of the present invention.
8 is a block diagram illustrating a converting apparatus for reducing harmonic EMI according to another embodiment of the present invention.
9 illustrates an example PFD block diagram and timing diagram and characteristics.
10 illustrates exemplary Dual Loop VCOs and characteristics.
11 is a block diagram of an exemplary N-divider.
12 shows the loop gain of the buck converter including the compensation circuit.

DETAILED DESCRIPTION Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art may easily implement the present invention. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. In the drawings, parts irrelevant to the description are omitted in order to clearly describe the present invention, and like reference numerals designate like parts throughout the specification.

Terms used herein will be briefly described and the present invention will be described in detail.

The terms used in the present invention have been selected as widely used general terms as possible in consideration of the functions in the present invention, but this may vary according to the intention or precedent of the person skilled in the art, the emergence of new technologies and the like. In addition, in certain cases, there is also a term arbitrarily selected by the applicant, in which case the meaning will be described in detail in the description of the invention. Therefore, the terms used in the present invention should be defined based on the meanings of the terms and the contents throughout the present invention, rather than the names of the simple terms.

When any part of the specification is to "include" any component, this means that it may further include other components, except to exclude other components unless otherwise stated. In addition, the terms "... unit", "module", etc. described in the specification mean a unit for processing at least one function or operation, which may be implemented in hardware or software or a combination of hardware and software. . In addition, when a part of the specification is "connected" to another part, this includes not only "directly connected", but also "connected with other elements in the middle".

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

Two methods are used to attenuate EMI noise at the output. (i) The first method is to add an EMI filter to the power converter to attenuate EMI noise. However, this method has the disadvantage of increasing the PCB size due to the burden of attaching many passive and active devices to the outside of the chip. (ii) The second method is to remove harmonics by dispersing the frequency of the fixed PWM signal that is the source of the output EMI noise. Most buck converters implemented on chip are actively researched to remove output EMI noise using this second method.

1 illustrates a buck converter using a method of removing a harmonic component of PWM using a frequency hopping method.

When a random bit is output from a pseudo-random number generator, the bit is received and the ramp generator provides a random ramp function. According to the output of the ramp generator, the duty is generated by comparing with the error voltage. Using this method, the switching frequency can be changed according to the random number, so that the remaining components except the fundamental wave components of the switching frequency can be removed. However, it is possible to effectively attenuate the output EMI noise by generating the fundamental wave components due to the random frequency at the hopping rate and eliminating the harmonic components.However, several fundamental wave components have the efficiency, transient response and large ripple voltage of the converter. Therefore, the performance as a power converter is not considered.

Figure 2 shows a buck converter of the method for controlling the output by randomly generating a pulse corresponding to the target voltage using the SDM ADC. A controller using SDM outputs a Pulse Code Modulation (PCM) signal in accordance with the output voltage. At this time, the output PCM signal has an average value of duty to control the output voltage according to the SDM. The SDM controller has a sampling frequency but the sampling frequency and the switching frequency are not the same, and are summarized as Equation 1 according to the Markov Model.

[Equation 1]

는 SDM의 sampling frequency,

는 벅 컨버터의 switching frequency, d는 scaling factor 그리고 D는 duty를 나타낸다. 수식에 따르면 Analog SDM을 적용한 벅 컨버터는 target 전압에 맞는 duty를 random하게 내주는 대신에 target전압에 필요한 duty에 따라서 scaling factor가 변하게 되고 그에 따라서 switching frequency가 변하게 된다.

일 때를 가정하면 위 수식에 따라서 duty가 커질수록 d는 작아지게 된다. 그렇게 되면 switching frequency는 작아지며 switching frequency의 영향에 따라서 switching 손실은 줄어드는 대신에 출력 전압의 ripple이 증가하게 된다. 이는 D에 따라서 벅 컨버터의 전력변환기로서의 성능이 기존의 벅 컨버터에 비해 일관성을 유지하지 못한다는 단점이 된다. 또한 duty가 random하게 생성이 되기 때문에 도 1과 함께 전술한 기존의 low EMI 벅 컨버터의 단점인 transient response time을 확보하기 어렵고, Analog SDM ADC를 구현하기 위하여 많은 수의 capacitor와 같은 passive 소자와 OP-Amp, comparator와 같은 active 소자가 필요하다는 점에서 회로 구성에 있어서 불필요하게 면적을 과다하게 소요한다는 문제점으로 연결된다.In this formula

Is the sampling frequency of SDM,

Is the switching frequency of the buck converter, d is the scaling factor, and D is the duty. According to the equation, instead of randomly giving the duty corresponding to the target voltage, the buck converter using the analog SDM changes the scaling factor according to the duty required for the target voltage and accordingly the switching frequency.

If d is assumed, d becomes smaller as duty increases according to the above equation. This reduces the switching frequency and increases the ripple of the output voltage instead of reducing the switching loss under the influence of the switching frequency. This has the disadvantage that the performance of the buck converter's power converter is not consistent with the conventional buck converter depending on D. In addition, since the duty is generated randomly, it is difficult to secure a transient response time, which is a disadvantage of the conventional low EMI buck converter described above with reference to FIG. 1, and passive devices such as a large number of capacitors and OP- to implement an analog SDM ADC. The need for active devices such as amps and comparators leads to the problem of unnecessarily excessive area in circuit configuration.

3 shows a conventional PWM generator. In other words, FIG. 3 is a block diagram of an analog PWM generator and a VCO based PWM generator used in a conventional PWM control buck converter.

전압으로 내주게 되고 다음단의 comparator에서 sawtooth 신호와 비교하여 SR Latch의 reset 시간을 정하게 된다. 이 때 SR Latch의 set 시간은 고정된 frequency인

에 의해 결정된다. 따라서 PWM의 duty는 error 정보에 의해서 결정이 되고 switching frequency인

은

결정된다. 하지만 이 방법은 OP-amp를 사용해야하고 벅 컨버터의 루프 안정도를 확보하기 위해 error 앰프에서 2차 혹은 3차의 보상을 필요로 하기 때문에 많은 수의 passive 소자가 필요하게 되고, 생성되는 PWM의

도 OP-amp의 bandwidth에 의해서 제한된다.Referring to (a) of FIG. 3, the difference between the output voltage and the reference voltage in the error amp of the first stage is measured.

Voltage is given and the reset time of SR Latch is determined by comparing with the sawtooth signal at the next comparator. At this time, SR Latch set time is fixed frequency

Determined by Therefore, the duty of PWM is determined by the error information and the switching frequency

silver

Is determined. However, this method requires a large number of passive devices because it requires the use of an OP-amp and requires second or third order compensation in the error amplifier to ensure loop stability of the buck converter.

Also limited by the bandwidth of the OP-amp.

Figure 3 (b) shows a block diagram of a VCO based PWM generator, this method, unlike the analog method, replaced the OP-amp and comparator with VCO (Voltage Controlled Oscillator) and Phase Frequency Detector (PFD). After receiving the output voltage of the buck converter as the control voltage of the VCO, divide the frequency output from the VCO from N divider to integer N and use it as the PFD input. The reference frequency is compared with the phase of the divided frequency and used as a duty to control the output voltage of the buck converter.

[Equation 2]

, 분주된 frequency

, 분주비 N, 그리고 VCO의 gain인

에 의해서 결정이 된다.When using a VCO-based PWM generator, as shown in Equation 2, the duty may be generated based on time information having phase information. The output voltage (V _OUT ) is then the free running frequency of the VCO,

, Frequency dispensed

, The division ratio N, and the gain of the VCO

It is decided by.

 VCO-based PWM generators have limited output voltage resolution due to integer N, but they can be implemented with digital logic, resulting in smaller circuit area and relatively less bandwidth limitation. . However, since both of the above-mentioned methods switch using a fixed frequency, it cannot fundamentally solve the conductive EMI problem generated at the harmonics of the switching frequency.

The present invention aims to effectively attenuate output EMI noise by spreading the frequency using a VCO-based PWM generator using a fractional-N method.

4 is a block diagram illustrating a converting device for reducing harmonic EMI according to an embodiment of the present invention, Figure 5 is a block diagram and an operation example of a VCO based Fractional-N PWM Generator according to an embodiment of the present invention .

The converting device for harmonic EMI reduction according to an embodiment of the present invention, Voltage-controlled oscillator (VCO) 100, N- of the Fractional (Fractional) -N structure connected to the voltage-controlled oscillator 100 Power stage of the buck converter structure connected to the N-Divider 200, the phase frequency detector PFD 300 connected to the N-divider 200, and the PFD 300; 400 may include.

With the power stage of a basic buck converter and converting the output voltage into the phase domain, or time domain, the VCO can do it. After changing the information of the output voltage to time information may be input to the N divider of the fractional-N structure according to an embodiment of the present invention. FDIV, a signal divided by fractional-N, has an average value according to N code, and can have random time information corresponding to a desired target voltage.In PFD, two signals, FREF and FDIV, which are reference frequencies, are compared to determine the duty according to the target voltage. Can be generated.

Basically, duty can be generated in a manner similar to the conventional integer-N method, but duty information can be generated by dividing the N-divider into fractional-N using SDM instead of integer N. The generated fractional-N value generates an FDIV having phase information having an average value of duty required for the target voltage. If fractional-N is divided, it is possible to perform decimal point operation, so that the output voltage resolution is higher than that of integer-N operation, and the resolution of output voltage, which is a disadvantage compared to analog method, can be compensated. In addition, due to the randomly generated FIDV, the duty of the generated PWM signal is changed randomly, thereby spreading the frequency components constituting the PWM signal, thereby significantly reducing the conductive EMI noise of the buck converter output voltage.

[Equation 3]

, cos 성분의 계수

, sin 성분의 계수

을 나타낸다. duty가 50%인 신호를 가정하면 frequency 성분은 DC 성분과 sin항 혹은 cos항 중 한 성분을 취하여 기본파가 되고 그 기본파의 고조파의 성분을 가지게 된다. 하지만 duty가 50%가 아닌 다른 duty를 가지게 된다면 위 수학식 3에 의해 sin항과 cos항이 모두 나오게 된다. 이 때 위에서 언급한 random한 duty가 된다면 duty에 따라 구성되는 고조파 성분들이 달라지기 때문에 frequency 스펙트럼 상에서 전체적인 톤(tone)들이 random한 성분을 갖는 대신에 그 크기가 전체적으로 spread 된다. 따라서, 기본파를 제외한 나머지 고조파 성분들의 크기를 감쇠시킬 수 있어서 출력 전압의 EMI noise을 효과적으로 감소시킬 수 있다.Equation 3 above is a Fourier Series of PWM signals. Each coefficient is a DC component

, coefficient of cos component

, coefficient of sin component

Indicates. Assuming a signal with a duty of 50%, the frequency component takes one of the DC component and the sin or cos term to form a fundamental wave and has a harmonic component of the fundamental wave. However, if the duty has a duty other than 50%, the sin and cos terms are both shown by Equation 3 above. In this case, if the above-mentioned random duty becomes a harmonic component configured according to the duty, the entire tone is spread on the frequency spectrum instead of having a random component. Therefore, it is possible to attenuate the magnitude of the harmonic components except for the fundamental wave, thereby effectively reducing the EMI noise of the output voltage.

A phase locked loop (PLL) is a circuit that can obtain a high frequency FOUT using a low frequency FREF. Charge-Pump (CP) -PLL can be composed of PFD for detecting phase difference, Loop Filter (LF) for compensating loop stability, VCO for frequency generation, and N-divider for division. The basic operation is to change the phase difference between the FREF signal and the FDIV signal in the PFD as UP or DN signal, change the phase difference in the CP to the current signal, and then change the voltage signal from LF. Therefore, since the voltage of LF is information of the phase difference between FREF and FDIV, when it is inputted to VCO, the output frequency of VCO is controlled by the corresponding difference, and the phase difference between FREF and FDIV is adjusted to fix FOUT.

 For a given loop to be locked in a PLL, two conditions must be met. First, FOUT and FREF must be the same. Secondly, there should be no phase difference between input and output or fixed fixed. If the above conditions are met, the PLL loop is locked and all signals in the loop enter a steady state in a transient state. In this case, stability can be ensured when the loop bandwidth of a given PLL is designed to be about 10 times the FREF, for example.

6 shows a structure and an operation example of the SDM according to an embodiment of the present invention.

In addition, a sigma-delta modulator (SDM) is connected to the N-divider, and the sigma-delta is divided into an SDM-applied Fractional-N instead of an Integer N. The modulator SDM may have a MASH structure.

Referring to (a) and (b) of FIG. 6, the SDM operation may be confirmed through the primary SDM of the MASH structure. For example, to get a fractional value of 0.25, a decimal representation of 0100 is required. If this binary value is input to FA (Full Adder) input, FA_OUT coming out of delay operation from the first operation becomes 0100. In the next operation, the 0100 output will enter the input of the FA and a value of 1000 will be generated by adding X and 0100. If this operation is repeated, overflow occurs at the next value of 1100, and N value is inputted to the divider. In the case of the first SDM, only the lowest 1 bit of the N code value is moved. For example, if the value is set to integer 13, fractional 0.25 to express 13.25, N dividing is set to 13, 13, 13, 14, and the average value is 13.25.

The output voltage of the buck converter structure in which voltage sigma phase information that is generated when the input to the controlled oscillator (VCO) - is made to frequency division random (Random) from N- divider delta modulator is connected, and the frequency divider when the frequency (F _DIV) The reference frequency F _REF may be compared to determine the duty of the PWM signal.

Duty information can be generated by dispensing from N-divider to Fractional-N using SDM instead of Integer N. The generated Fractional-N value may generate an FDIV having random phase information having an average value of duty required for the target voltage. If fractional-N is divided, decimal point calculation is possible, so it can get higher resolution than Integer-N operation and can effectively compensate for resolution of output voltage which was disadvantageous compared with analog method. In addition, due to the FDIV generated by the random value, the duty of the generated PWM signal is changed randomly, which causes the frequency components constituting the PWM signal to be spread (spread), significantly reducing the conductive EMI noise of the buck converter output voltage. Can be reduced.

7 is a block diagram illustrating a converting device for reducing harmonic EMI according to another embodiment of the present invention, Figure 8 is a block diagram showing a converting device for reducing harmonic EMI according to another embodiment of the present invention.

The signal applied to the voltage controlled oscillator (VCO) is applied from each of the coarse loop structure and the fine loop structure, and the coarse loop structure has an N-divider, an N-divider and A connected phase frequency detector is included, and the fine loop structure may include a power stage of the buck converter structure.

The voltage controlled oscillator can be a dual loop VCO with two control loops, the voltage of the coarse loop and the voltage of the fine loop.

According to an embodiment of the present invention, a free running frequency (f ₀ ) and a conversion gain (KVCO) of the voltage controlled oscillator (VCO) are set through a coarse loop structure to determine the output signal (V _OUT ). frequency can be controlled (f _OUT) a fixed frequency range (frequency lock range) adjustment, by fine-tuning the frequency of the voltage-controlled oscillator (VCO) through a fine loop structure, the output signal (V _OUT) and then up.

According to an embodiment of the present invention, when the Buck converter enters a steady-state, the output voltage is locked, and at this time, the FDIV is random because the phase has the same value as the phase of the FREF due to the SDM operation. Phase. As a result, a duty duty having an average value corresponding to the duty voltage may be generated.

9 shows an exemplary PFD block diagram and timing diagram and characteristics, FIG. 10 shows an exemplary Dual Loop VCO and characteristics, and FIG. 11 is a block diagram of an exemplary N-divider. 12 illustrates loop gain of a buck converter including a compensation circuit.

In order to verify harmonic EMI reduction according to an embodiment of the present invention, a design using Samsung 65nm CMOS process was implemented. The inductor and capacitor of the power stage are 1uH and 1uF, respectively, and the target switching frequency is set to 1MHz. Since the 65nm CMOS process has a VDD voltage of 1.2V, the output of the buck converter has a voltage lower than 1.2V. Accordingly, the controller of the buck converter except for the VCO having a control voltage of 0 to 1.2V may be implemented using a field programmable gate array (FPGA) as shown in FIG. 7. Through Verilog coding, a divider capable of N-dividing based on PFD and counters was constructed, and Digital Sigma-Delta Modulator was implemented in the second MASH 1-1 method.

Referring to FIG. 9, for example, the PFD may include two D flip-flops, one and a gate, and a buffer. D Flip-Flop accepts inputs from FREF and FDIV. At this time, if the two frequencies are within the lock range and can be compared with the phase of the two signals, the D flip-flop is connected to VDD, so if the FREF is changed from low to high, the UP signal is aligned with the rising edge of the signal. It will change from low to high. After that, when the FDIV goes from low to high, the two D Flip-Flops are automatically reset because the and gate inputs are high and high, and the UP signal is also brought low at that point. As a result of simulation, we can confirm that UP signal and DN signal are generated for FREF and FDIV at 1MHz, and UP signal is used as PWM.

를 갖기 때문에 fine 전압이 커질수록 frequency는 낮아진다. 따라서 N 값이 커질수록 벅 컨버터의 출력 전압은 커진다. 전술한 예에서 시뮬레이션 결과 Vcoarse가 900mV이고 Vfine이 700mV일 때, 출력 frequency는 445.026MHz이었다.10 (b) shows a characteristic curve of voltage versus output frequency of the dual loop VCO. Referring to FIG. 10, after adjusting the output frequency by adjusting VDD of the inverter stage of the VCO, the desired output frequency may be obtained by finely adjusting the fine voltage of VDD of the latch at the output terminal of each inverter. The output voltage of the buck converter can be adjusted by the frequency obtained through the fine loop and by the N value of the N divider. Depending on the Vcoarse voltage, the operating range of the VCO changes and thus the control range that can be adjusted to fine voltage. As an example, a VCO designed

The higher the fine voltage, the lower the frequency. Therefore, as the value of N increases, the output voltage of the buck converter increases. In the example described above, when Vcoarse is 900mV and Vfine is 700mV, the output frequency is 445.026MHz.

Referring to FIG. 11, the N-divider may be designed to allow a maximum of 256 divisions using a code value of 8 bits. T Flip-Flop through N gate and output out0 ~ out7 output after using N value input by using 8 T Flip-Flop made by D Flip-Flop and output of T Flip-Flop as input of XOR gate You can create a rest signal and invert the signal to produce the final output FDIV.

Referring to FIG. 6, for verification, the SDM is a secondary SDM having a MASH 1-1 structure. In the case of using the first SDM, it is possible to construct a simple block, but there is periodicity, which is represented by spur in the frequency domain. Therefore, to eliminate the periodicity and to obtain high noise shaping effect, we used MASH 1-1 structure which cascaded MASH 1 structure.

에서 complex pole이 생성된다. 이 때 complex pole로 인해서 위상은

가 된다. 이로 인해서 UGF(Unit Gain Frequency)에서 phase margin을 확보할 수 없다. 이런 경우에서는 공진점 즉

에서 2개의 pole이 생기고 VCO의 전달함수인

로 인해 DC에 pole이 생기게 된다. 따라서 UGF가 공진점 밖에 생성되기 때문에 적절한 보상 회로가 필요하다.12 shows the loop gain of the buck converter in which the compensation circuit is present. Typical buck converter has resonance point caused by RLC of output stage

At this point a complex pole is created. At this time, due to the complex pole, the phase

Becomes Because of this, it is not possible to secure phase margin in UGF (Unit Gain Frequency). In this case, the resonance point

Two poles in the VCO, the transfer function

This causes poles in the DC. Therefore, because UGF is generated outside the resonance point, an appropriate compensation circuit is required.

위상 변화를 피하기 위해서 간단한 RC low-pass filter를 사용(예컨대, 도 12 파란 점선 박스)의 하여 UGF를 공진점 안쪽에 위치하게 하였다. In order to ensure the loop stability of the buck converter, it is caused by two complex poles at the resonance point.

In order to avoid phase shift, a simple RC low-pass filter (eg, blue dashed box in FIG. 12) was used to place the UGF inside the resonance point.

로 인해 DC에서 생기는 Pole은 -20dB/dec로 roll-off를 형성이 시키는데 1차의 low-pass filter를 사용하면 -40dB/dec로 roll-off 형성이 되기 때문에 공진점 앞쪽에 UGF를 위치시킬 수 있어서 간단하게 안정도 확보가 가능하다.VCO's Transfer Function

Due to the pole generated at DC, roll-off is formed at -20dB / dec. When the first-order low-pass filter is used, the roll-off is formed at -40dB / dec, so the UGF can be placed in front of the resonance point. It is possible to secure stability easily.

When the loop is locked, the duty is determined by fixing the phase difference between FREF and FDIV at that time. For example, it has a ripple of 37mV at 1MHz switching frequency, 1uF, 1uH capacitor, and inductor. As a result of the simulation of the above example, the duty varies randomly up to 0.45%. This allows harmonic components to be removed because the frequency components of the PWM signal change. In addition, the output voltage varies linearly from 980mV to 400mV and the maximum voltage adjustable range is from 980mV to 200mV. In other words, when the input voltage is 1.2V, the output voltage changes linearly from 980mV to about 400mV, and can control up to the output of 196mV, which has wider output voltage control range when Fractional-N operation than Integer-N. It is confirmed that it can.

으로 기존의 low EMI 벅 컨버터에 비해 적은 면적으로 설계가 될 수 있다는 것을 확인할 수 있다. 본 발명의 일 실시예에 따른 벅 컨버터는 noise에 민감한 Mobile용 RF/Analog 회로의 전원 공급 회로로써 사용될 수 있을 것이다. Function verification was performed by replacing the controller except VCO with FPGA and through this, it can be designed with effective layout when designing with chip. At this time, the active area occupied by the switching TR and the controller is

As a result, they can be designed in a smaller area than conventional low EMI buck converters. Buck converter according to an embodiment of the present invention may be used as a power supply circuit of the RF / Analog circuit for mobile noise sensitive.

As described above, the design used Samsung 65nm CMOS process for the verification, and when the switching frequency 1MHz, 1uF output capacitor, 1uH inductor was used, the output EMI noise was measured below -53dBm, and the output ripple was measured as 32mV. . Load regulation characteristics were measured as 7.92us when the load current is 100mA-> 250mA and 5.4us when 250mA-> 100mA.

A DPLL-based Buck converter capable of fractional-N division according to an embodiment of the present invention generates a random division ratio using SDM, and thus reduces the tone noise of PWM coming from a fixed frequency, rather than Integer-N. Can have a wide output control range.

With regard to a method of operating a device according to an embodiment of the present invention, the above description may be applied. Therefore, with respect to the operation method, the description of the same contents as those of the above-described apparatus is omitted.

Meanwhile, the above-described method can be written as a program that can be executed in a computer, and can be implemented in a general-purpose digital computer which operates the program using a computer readable medium. In addition, the structure of the data used in the above-described method can be recorded on the computer-readable medium through various means. A recording medium for recording an executable computer program or code for performing various methods of the present invention should not be understood to include temporary objects, such as carrier waves or signals. The computer readable medium may include a storage medium such as a magnetic storage medium (eg, a ROM, a floppy disk, a hard disk, etc.), an optical reading medium (eg, a CD-ROM, a DVD, etc.).

The foregoing description of the present invention is intended for illustration, and it will be understood by those skilled in the art that the present invention may be easily modified in other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and similarly, components described as distributed may be implemented in a combined form.

The scope of the present invention is shown by the following claims rather than the above description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

100: Voltage Controlled Oscillator (VCO)
200: N-divider
300: Phase Frequency Detector (PFD)
400: power stage
500: Sigma-Delta Modulator (SDM)

Claims (6)

In converting device for harmonic EMI reduction,
Voltage Controlled Oscillator (VCO);
An N-divider having a Fractional-N structure connected to the voltage controlled oscillator;
A phase frequency detector (PFD) connected to the N-divider; And
And a power stage of a buck converter structure connected to the PFD.
The method of claim 1,
A Sigma-Delta Modulator (SDM) is connected to the N-divider, and the N-divider divides the Fractional-N to which the SDM is applied instead of Integer N.
And a sigma-delta modulator (SDM) having a MASH structure.
The method of claim 2,
Phase information generated when the output voltage of the buck converter structure is input to the voltage controlled oscillator (VCO) is randomly divided in an N-divider connected with the sigma-delta modulator, _DIV ) and the reference frequency (F _REF ) is a conversion device for reducing harmonic EMI, characterized in that the duty (Duty) of the PWM signal is determined.
The method of claim 1,
The signal applied to the voltage controlled oscillator VCO is applied from each of a coarse loop structure and a fine loop structure,
The coarse loop structure includes the N-divider and a phase frequency detector connected to the N-divider, and the fine loop structure includes a power stage of the buck converter structure. Converting device for harmonic EMI reduction.
The method of claim 4, wherein
The voltage controlled oscillator is a converting device for harmonic EMI reduction, characterized in that the dual loop VCO having two control loops, the voltage of the coarse loop and the voltage of the fine loop.
The method of claim 4, wherein
The frequency (f _OUT) of said voltage controlled oscillator (VCO) common frequencies (free running frequency, f ₀₎ and the output by setting the conversion gain (conversion gain, KVCO) signal (V _OUT) of the through the coarse loop structure Frequency After adjusting to a fixed range (frequency lock range), the output signal (V _OUT ) is controlled by fine-tuning the frequency of the voltage controlled oscillator (VCO) through the fine loop structure for harmonic EMI reduction Converting device.

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