KR102020553B1 - Circuit of controlling sense amplifier source node in semiconductor memory device and control method thereof - Google Patents

Circuit of controlling sense amplifier source node in semiconductor memory device and control method thereof Download PDF

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KR102020553B1
KR102020553B1 KR1020130044325A KR20130044325A KR102020553B1 KR 102020553 B1 KR102020553 B1 KR 102020553B1 KR 1020130044325 A KR1020130044325 A KR 1020130044325A KR 20130044325 A KR20130044325 A KR 20130044325A KR 102020553 B1 KR102020553 B1 KR 102020553B1
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sense amplifier
source node
operation mode
driving signal
signal line
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KR1020130044325A
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Korean (ko)
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KR20140093155A (en
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서영훈
박철성
이영대
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삼성전자주식회사
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4094—Bit-line management or control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/06—Sense amplifier related aspects
    • G11C2207/065—Sense amplifier drivers

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  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

A bit line sense amplifier source node control circuit of a semiconductor memory device is disclosed. The sense amplifier source node control circuit includes a source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line to drive the source node of the sense amplifier to a set voltage level. The sense amplifier source node control circuit may be connected in parallel with the source driver between the floating unit for floating the sense amplifier driving signal line in a set operation mode, and between the source node of the sense amplifier and the sense amplifier driving signal line. And a controller for controlling the level of the sense amplifier driving signal line in a setting operation mode. According to the present invention, power consumption due to leakage current of the sense amplifier is minimized or reduced.

Description

Sense amplifier source node control circuit of a semiconductor memory device and a method for controlling the sense amplifier source node according to the present invention.

The present invention relates to a semiconductor memory device, and more particularly, to control of a sense amplifier source node of a semiconductor memory device such as a dynamic random access memory.

BACKGROUND OF THE INVENTION Semiconductor memory devices such as dynamic random access memory (DRAM) are widely used as main memories of electronic systems including computers and portable electronic devices.

DRAMs almost always include bitline sense amplifiers that sense and amplify data stored in memory cells.

In the active operation of the DRAM, for example, the read operation mode or the write operation mode, power for data access is inevitably consumed. The DRAM has a power down mode in which the driving current is consumed to the minimum when the data access operation is not performed, that is, the active operation is not performed. To further reduce power consumption, DRAM can receive power-down commands from the controller during active operation, often referred to as active power-down commands.

Even in such an active power-down mode, leakage current still flows in the bitline sense amplifier. Therefore, power consumption is generated.

The present invention has been made in an effort to provide a sense amplifier source node control circuit and a sense amplifier source node control method capable of minimizing or reducing leakage current of a sense amplifier.

According to an aspect of an embodiment of the present invention for achieving the above technical problem, a sense amplifier source node control circuit of a semiconductor memory device,

A source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line to drive the source node of the sense amplifier to a set voltage level;

A floating unit which floats the sense amplifier driving signal line in a set operation mode; And

And a control unit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line and controlling the level of the sense amplifier driving signal line in the setting operation mode.

In an embodiment according to the concept of the invention, the control unit,

A voltage level amplifier having a first input terminal and a second input terminal to which a reference voltage is applied;

A first switch for switching between the first input terminal and the source node of the sense amplifier in the set operation mode; And

And a second switch configured to switch between an output terminal of the voltage level amplifier and the sense amplifier driving signal line in the setting operation mode.

In an embodiment according to the inventive concept, the sense amplifier may be a bit line sense amplifier including N-type transistors.

In an embodiment according to the inventive concept, the setting operation mode may be an operation mode different from the active mode of the semiconductor memory device.

According to an embodiment of the inventive concept, the source driver may include at least one N-type transistor having a drain connected to a source node of the sense amplifier, a gate connected to the sense amplifier driving signal line, and a source connected to ground. Can be.

According to an embodiment of the inventive concept, the first and second switches may be Morse transistors that are switched on in the set operation mode and switched off in an operation mode other than the set operation mode.

According to an embodiment of the inventive concept, the floating unit may be a three-state buffer that applies a sense amplifier enable signal to the sense amplifier driving signal line in an active mode of the semiconductor memory device.

In an embodiment according to the inventive concept, the voltage level amplifier may include a differential amplifier for driving the source node of the sense amplifier to the level of the reference voltage in the set operation mode.

In an embodiment according to the inventive concept, the voltage level amplifier may be shared to one or more memory banks of the semiconductor memory device.

In an embodiment according to the inventive concept, an amplifier circuit may be further connected between the voltage level amplifier and a source node of the sense amplifier to drive a source node of the sense amplifier to a level equal to or greater than the reference voltage level. Can be.

According to another aspect of an embodiment of the present invention for achieving the above technical problem, the sense amplifier source node control circuit of the semiconductor memory device,

A source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line to drive the source node of the sense amplifier to a set voltage level;

A switching unit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line and switched in a set operation mode to make the source driver into a diode connection configuration; And

And a floating unit configured to float the sense amplifier driving signal line in the set operation mode.

In an embodiment according to the inventive concept, the source driver may be an N-type MOS transistor.

In an embodiment according to the inventive concept, the setting operation mode may be an active power down mode.

In an embodiment according to the inventive concept, the floating unit may be a tri-state buffer that applies a sense amplifier enable signal to the sense amplifier driving signal line in an active mode different from an active power down mode.

In an embodiment according to the inventive concept, the sense amplifier may be a DRAM bit line sense amplifier including N-type transistors.

According to another aspect of an embodiment of the present invention for achieving the above technical problem, a method of controlling a sense amplifier source node of a semiconductor memory device,

Plotting the sense amplifier drive signal line in the set operation mode;

The source node of the sense amplifier is set to a target voltage level by controlling a source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line in the setting operation mode.

In an embodiment according to the inventive concept, the setting operation mode may be an active power down mode of a DRAM.

According to embodiments of the present invention, power consumption due to leakage current of the sense amplifier is minimized or reduced in an operation mode such as an active power down mode.

1 is a block diagram of a sense amplifier source node control circuit in accordance with the inventive concept.
2 is an exemplary view of FIG. 1.
3 illustrates a specific implementation according to FIG. 2.
4 is an operation timing diagram according to FIG. 3.
5 is another exemplary view of FIG.
6 is an operation timing diagram according to FIG. 5.
7 illustrates a specific implementation according to FIG. 5.
FIG. 8 is an exemplary diagram illustrating the extension application of FIG. 5. FIG.
9 is another exemplary diagram showing another extension application of FIG. 5;
10 is an exemplary view showing a modified embodiment of FIG.
11 is a view provided to explain the operation of the bit line sense amplifier of FIG.
FIG. 12 illustrates an example of connection between a bit line sense amplifier and a memory cell block of FIG.
FIG. 13 is an exemplary implementation diagram of a memory cell block of FIG. 12; FIG.
FIG. 14 is an exemplary diagram illustrating a folded bit line structure of the bit line sense amplifier of FIG. 11. FIG.
FIG. 15 is another exemplary diagram illustrating an open bit line structure of the bit line sense amplifier of FIG. 11. FIG.
16 illustrates an application of the present invention applied to an electronic system.
Figure 17 illustrates an application of the present invention applied to a graphics memory system.
18 is an application example of the present invention applied to a graphics card.
FIG. 19 illustrates an application of a computing system including the graphics card of FIG. 18.

Objects, other objects, features and advantages of the present invention as described above will be readily understood through the following preferred embodiments associated with the accompanying drawings. However, the present invention is not limited to the embodiments described herein and may be embodied in other forms. Rather, the embodiments introduced herein are provided to make the disclosure more thorough and complete, and to fully convey the spirit of the present invention to those skilled in the art, without any intention other than to provide convenience of understanding.

In the present specification, when it is mentioned that any element or line is connected to the target element block, it includes not only a direct connection but also a meaning indirectly connected to the target element block through some other element.

In addition, the same or similar reference numerals given in each drawing represent the same or similar components as possible. In some drawings, the connection relationship between elements and lines is only shown for effective description of the technical contents, and other elements or circuit blocks may be further provided.

Each embodiment described and illustrated herein may include complementary embodiments thereof, and details regarding basic data access operations, refresh operations, and internal functional circuits for semiconductor memory devices such as DRAMs do not obscure the subject matter of the present invention. Note that it is not described in detail in order to avoid that.

1 is a block diagram of a sense amplifier source node control circuit in accordance with the inventive concept.

Referring to FIG. 1, the bit line sense amplifier 100-1 is connected between the first line L10 and the second line L20. The bit line sense amplifier 100-1 may include a type sense amplifier formed of PMOS transistors and an n type sense amplifier formed of n-type Morse transistors (NMOS). The second line L20 is connected to a source of the N-type transistors constituting the N-type sense amplifier, and thus includes a sense amplifier source node. That is, the sense amplifier source node is electrically connected to the second line L20.

On the other hand, since the first line L10 is connected to the drains of the MOS transistors constituting the Sense Amp, the first line L10 includes a sense amplifier drain node.

The source driver 10 may include at least one N-type transistors 2 and 4 having a drain connected to a source node of the sense amplifier, a gate connected to the sense amplifier driving signal line, and a source connected to ground. .

The source driver 10 is connected between the source node L20 of the sense amplifier and the sense amplifier driving signal line L22 to set the source node L20 of the sense amplifier in a setting operation mode such as an active power down mode. Drive to voltage level.

The floating unit 200 causes the sense amplifier driving signal line L22 to float in a setting operation mode such as an active power down mode. The floating unit 200 applies a sense amplifier enable signal to the sense amplifier driving signal line L22 in an active operation mode other than the active power down mode. As a result, the floating unit 200 may be implemented as a tri-state buffer that is operated on and off according to an enable signal.

The controller 300 is connected in parallel with the source driver 10 between the source node L20 of the sense amplifier and the sense amplifier driving signal line L22. The controller 300 controls the voltage level of the sense amplifier driving signal line L22 in the setting operation mode so that the voltage of the source node L20 of the sense amplifier is maintained at a constant level.

When the controller 300 is operated as a switch having only a switching function, the controller 300 may be called as a switching unit. In this case, the switching unit 300 may make the source driver 10 in the diode connection configuration by being switched in the set operation mode. The switching unit 300 will be described later in detail with reference to FIGS. 2 and 3.

2 is an exemplary view of FIG. 1.

Referring to FIG. 2, the bit line sense amplifier circuit unit 100 is connected between the first and second memory cell array blocks 400 and 410. The bit line sense amplifier circuit unit 100 includes a plurality of bit line sense amplifiers 100-1, 100-2,..., 100-n. The arbitrary bit line sense amplifier SA0 may have the same configuration as the bit line sense amplifier 100-1 of FIG. 1. The bit line sense amplifier SA0: 100-1 is connected to the bit line BL_0 and the complementary bit line BLB_0 to sense and amplify the bit line voltage.

In FIG. 2, LA may correspond to the first line L10 of FIG. 1, and LAB may correspond to the second line L20 of FIG. 1. Also, the LANG may correspond to the sense amplifier driving signal line L22 of FIG. 1. After all, the LAB is the source node of the N-type sense amplifier.

The N-type transistors 2 and 4 constitute the source driver 10 of FIG. 1.

The tri-state buffer 200 corresponds to the floating unit 200 of FIG. 1.

The switch 310 constitutes the switching unit 300 of FIG. 1. The switch 310 may switch the source driver 10 into a diode connection configuration by being switched in the set operation mode. That is, the gate and the drain of the N-type MOS transistor 2 are electrically connected by switching the switch 310. Therefore, the N-type MOS transistor 2 functions as a diode.

3 is a diagram illustrating a specific implementation according to FIG. 2. 4 is an operation timing diagram according to FIG. 3.

Referring to FIG. 3, in the active power down mode, the tri-state buffer 200 performs a floating function in response to an enable signal (Enable), and the switch 310 is switched. Accordingly, the sense amplifier drive signal line LANG does not receive the drive voltage LANG 'and is in a floating state. In addition, the source driver 10 has a diode connection configuration by the switching operation of the switch 310. Therefore, the voltage level of the source node LAB of the sense amplifier starts to rise at the time point t1 as shown in FIG. The increase of the voltage level continues until the difference between the voltage level of the source node LAB and the voltage level of the sense amplifier driving signal line LANG is equal to the threshold voltage of the diode-connected N-type transistor 2. As a result, when the voltage level difference between the LAB and the LANG reaches the threshold voltage of the diode, the voltage level rise of the LAB is stopped.

Therefore, leakage current flowing from the source node of the bit line sense amplifier to ground in the active power down mode is minimized or reduced.

In the circuit configuration of FIG. 3, a floating unit and a switching unit must be provided. However, since the source driver 10, which is a LAB driver, is used as a source node control element, the chip layout burden is low and the circuit implementation cost is relatively low. .

5 is another exemplary diagram of FIG. 1. 6 is an operation timing diagram according to FIG. 5.

Referring to FIG. 5, the voltage level amplifier 320 and the first and second switches 310 and 312 constitute the controller 300 of FIG. 1. That is, the controller 300 includes a voltage level amplifier 320 having a first input terminal (+) and a second input terminal (−) to which the reference voltage VREF_LAB is applied. In addition, the controller 300 includes a first switch 310 for switching between the first input terminal (+) and the source node LAB of the sense amplifier in a setting operation mode such as an active power down mode. In addition, the controller 300 includes a second switch 312 for switching between the output terminal of the voltage level amplifier 320 and the sense amplifier driving signal line LANG in the set operation mode.

The circuit configuration of FIG. 5 is the same as FIG. 3 except for the controller 300.

When the active power down command for powering down during the active operation is applied to the DRAM at time t1 of FIG. 6, the tri-state buffer 200 performs a floating function in response to an enable signal applied at a low level. . In addition, the first and second switches 310 and 312 are switched in response to a switching control signal Switch applied at a high level. As a result, the sense amplifier driving signal line LANG no longer receives the driving voltage LANG 'and is in a floating state. In addition, the voltage level amplifier 320 is operatively connected between the LAB and the LANG by switching operations of the first and second switches 310 and 312.

Therefore, the voltage level of the source node LAB of the sense amplifier starts to rise at time point t1 as shown in FIG. The increase of the voltage level continues until the voltage level of the source node LAB reaches the reference voltage VREF_LAB. As a result, when the voltage level of the LAB reaches the reference voltage VREF_LAB, the increase of the voltage level of the LAB is stopped. In this case, unlike FIG. 3, if the reference voltage VREF_LAB is appropriately set as the control target voltage level, the voltage level of the LAB may be controlled to a desired level.

Therefore, leakage current flowing from the source node of the bit line sense amplifier to ground in the active power down mode is minimized or reduced.

In the circuit configuration of FIG. 5, the control of the source node of the bit line sense amplifier is performed at a desired voltage level by using the voltage level amplifier 320.

7 is a diagram illustrating a specific implementation according to FIG. 5.

Referring to FIG. 7, it is shown that the first and second switches 310 and 312 in FIG. 5 are implemented with the N-type MOS transistors 310 and 312. The N-type transistors 310 and 312 are driven in response to the switching control signal SCON. The switching control signal SCON is the same as the switching control signal Switch of FIG. 6.

The circuit operation of FIG. 7 is the same as the circuit operation of FIG. 5.

In FIG. 7, an exemplary configuration of a bit line sense amplifier and a connection relationship between memory cells are shown in more detail.

The bit line sense amplifier is connected between LA and LAB. In addition, the bit line sense amplifier is connected between the bit line BL_0 and the complementary bit line BLB_0. The bit line sense amplifier includes a type sense amplifier PSA consisting of PMOS transistors P1 and P2, and an n type sense amplifier consisting of n-type NMOS transistors N1 and N2. (NSA). The LAB is connected to the sources of the N-type transistors N1 and N2 constituting the N-type sense amplifier NSA.

The LA is connected to the drains of the PMOS transistors P1 and P2 constituting the PSA.

When the bit line BL_0 is at the level of the internal power supply voltage VINTA and the complementary bit line BLB_0 is at the ground level, for example, 0 volts, leakage occurs along the current paths PA1 and PA2 in the active operation mode. Current flows Therefore, this leakage current may be a dominant current component in the active power down mode.

Accordingly, in order to reduce leakage current, the LANG line is floated by a tri-state buffer 200, and the voltage level amplifier 320 operates between the LAB and the LANG. Is connected as an enemy. Accordingly, the level of the LAB is maintained at VREF_LAB, which is a desired voltage level. The voltage level amplifier 320 properly controls the LANG level so that the LAB level becomes VREF_LAB.

A plurality of memory cells M1 including one access transistor T1 and one storage capacitor C1 are connected to the word line WL.

In the case of FIG. 7, since one voltage level amplifier 320 is required for each bit line sense amplifier, a chip size may be increased.

FIG. 8 is an exemplary diagram illustrating an extension application of FIG. 5.

Referring to FIG. 8, one memory bank 400a includes a plurality of word line drivers 420 and a plurality of memory cell array blocks 400-1 and 400-2. In FIG. 8, one voltage level amplifier 320 is installed in one memory bank 400a. The floating unit 210-1 and the switches 310-1 and 312-1 may be shared in one memory block in the memory bank 400a. In addition, the floating unit 210-n and the switches 310-n and 312-n may be shared in another memory block.

In the active mode, LANG_m and LANG_n become 'high'. When the active power down mode is entered in this state, the enable signals En_m and EN_n become 'off', and the LANG_m and LANG_n are in a floating state. The switches SW_m and SW_n are closed, and the LAB_AMP 320 controls two sense amplifier blocks through the global LAB and the global LANG. In such a structure, only one LAB_AMP 320 is required per bank.

The circuit structure of FIG. 8 solves a chip size increase problem because a single memory bank shares one voltage level amplifier 320.

FIG. 9 is another exemplary diagram illustrating another extension application of FIG. 5.

Referring to FIG. 9, a memory cell array in a DRAM may be configured by, for example, four memory banks 400a, 400b, 400c, and 400d.

In the circuit structure of FIG. 9, one voltage level amplifier 320 and one floating unit 200 are shared by the plurality of memory banks 400a, 400b, 400c, and 400d. Meanwhile, the switch unit 314 includes a plurality of switches for switching between the global LAB and the global LANG.

In the case of FIG. 9, the burden of increasing the chip size is relatively small compared to the circuit of FIG. 8.

10 is an exemplary view showing a modified embodiment of FIG.

Referring to FIG. 10, in addition to the circuit configuration of FIG. 9, an amplifier circuit 330 for driving the voltage level of the LAB to a level equal to or higher than the reference voltage level, and a pull-up for forcibly raising the voltage level of the LAB to VREF_LAB A driver (pull-up driver) 340 is further provided.

The LAB_UP_AMP 330 is implemented as an amplifier having an offset to prevent a short circuit between the PMOS transistor 340 and the LAB driver during operation.

FIG. 11 is a view provided to explain the operation of the bit line sense amplifier of FIG. 1.

The main cell 20 is disposed at the intersection of the word line WL and the bit line BL, and the reference cell 21 is disposed at the intersection of the reference word line WLref and the complementary bit line BLB. do.

The bit line sense amplifier 100-1 is connected between the bit line BL and the complementary bit line BLB, and “0” of data transferred through the pair of the bit line BL and the complementary bit line BLB. Detect and amplify it.

Here, the main cell 20 connected to the bit line BL and the reference cell 21 connected to the complementary bit line BLB are taken as examples, but at least one reference cell connected to the bit line BL and an additional The main cell may be further included, and at least one main cell and an additional reference cell connected to the complementary bit line BLB may be further included.

The main cell 20 is connected between an access transistor T1 having a gate controlled by a word line WL and a drain connected to a bit line BL, and a source of the access transistor T1 and a main plate voltage VP. The main capacitor C1 is included.

The reference cell 21 has an access transistor T2 whose gate is controlled by a reference word line WLref and whose drain is connected to the complementary bit line BLB, the source and reference plate voltage VPref of the access transistor T2. And a reference capacitor C2 connected therebetween.

In the first stage Phase0, the bit line BL and the complementary bit line BLB are precharged to the power supply voltage level Vdd. In the second stage Phase1, the bit line BL is charge-sharing and the complementary bit line BLB. ), Capacitive coupling occurs, and in phase 3, data is sensed.

Specifically, when the selected word line WL is activated, when the main cell 20 data is "0", "0V", which is the voltage stored in the main capacitor C1, and "Vdd precharged by the bit line capacitor CB." A charge sharing of Δ1 occurs between '.

Meanwhile, when the data of the main cell 20 is "1", since "Vdd" corresponding to the data stored in the main capacitor C1 and the voltage Vdd precharged to the bit line capacitor CB are the same, "Δ1 = 0V ".

At this time, in the reference cell 21 connected to the complementary bit line BLB, the reference plate voltage Vpref is set to be V2 less than the initial voltage V1 at the initial voltage V1 = Vdd, for example, 'Vdd / 2'. . Accordingly, the complementary bit line BLB becomes 'Δ2' by capacitive coupling.

When 'Vss <V2 <Vdd', it is 'Δ1> Δ2'. In addition, when 'V2 = Vdd / 2', since 'Δ1 = Δ2 / 2', reference voltages necessary for sensing "1" or "0" data may be easily generated.

FIG. 12 illustrates an example of connection between a bit line sense amplifier and a memory cell block of FIG. 11.

Referring to FIG. 12, an example in which a bit line sense amplifier is connected between two memory cell blocks BL0CK_L1 and BL0CK_L2 is illustrated. In the circuit configuration of FIG. 12, the leakage current flowing in the active power down mode is minimized or reduced when the control unit 300 and the floating unit 200 of FIG. 1 are additionally installed as in FIG. 1.

The configuration example of the memory cell block BLOCK_L2 may be implemented as shown in FIG. 13.

FIG. 13 is a diagram illustrating an implementation of a memory cell block in FIG. 12.

Referring to FIG. 13, one memory cell block may include a reference cell block 31b, a dummy cell block 32b, and a data cell block 30b. The reference cell block 31b may include a plurality of reference cells, the dummy cell block 32b may include a plurality of dummy cells, and the data cell block 30b may include a plurality of main cells.

In the above embodiments, the DRAM is taken as an example. However, this is merely illustrative. In addition, the present invention can be applied to both the folded and open structures of the bit line.

14 is a diagram illustrating a folded bit line structure of the bit line sense amplifier of FIG. 11. Referring to the drawings, the main cell M and the reference cell R are disposed at intersections of the word lines WL1 and WL2, the bit lines BL1 and BL2, and the bit lines BLB1 and BLB2, respectively. A bit line sense amplifier SA connected to the bit line pair of is disposed around the cell block B0.

In this example, the reference cell R is disposed at the end of each bit line pair. However, the reference cell R may be disposed at an arbitrary position. In addition, although the reference cell R may be separately controlled by a separate reference word line (not shown), it is assumed that the reference cell R is controlled by the same word lines WL1 and WL2 as the main cell M.

As shown, a folded bit line structure DRAM is a structure in which bit lines BL1 and BL2 and complementary bit lines BLB1 and BLB2 are arranged in the same block B0 or array. The line / complementary bit lines are all located in the same cell block.

Accordingly, coupling noise with the word lines WL1 and WL2 is the same for both the bit lines BL1 and BL2 and the complementary bit lines BLB1 and BLB2, and the amount coupled through the substrate is also the same. Since the common mode noise is removed by the differential amplification action of the bit line sense amplifier SA, the sensitivity is high.

FIG. 15 is another exemplary diagram illustrating an open bit line structure of the bit line sense amplifier of FIG. 11. Referring to FIG. 15, the main cell M and the reference cell R are disposed at the intersections of the word lines WL1 to WL9, the bit lines BL1 and BL2, and the bit lines BLB1 and BLB2. Bit line sense amplifiers SA connected to each pair of bit lines are disposed around the cell blocks B1, B2, and B3.

In this example, the reference cell R is disposed at the end of each bit line pair. However, the reference cell R may be disposed at an arbitrary position. As shown, a DRAM having an open bit line structure is a structure in which bit lines BL1 and BL2 and complementary bit lines BLB1 and BLB2 are arranged in different blocks B1 to B3, and a pair of bit lines / complementary bits are provided. As the lines are placed in different electrical environments, more precise designs are needed to sense and amplify fine signals.

In the open bit line structure, the main cell M is disposed at each intersection of the word line and the bit line. The main cell M is disposed at all intersections of the bit line and the word line, which is advantageous in terms of integration. Although the reference cell R is disposed at the end of each bit line pair as an example, the reference cell R may be disposed at an arbitrary position. In addition, although the reference cell R may be separately controlled by a separate reference word line (not shown), the same reference word lines WL1, WL3, WL4, WL6, WL7, and WL9 are the same as the main cell M. Controlled by the above.

16 is an application example of the present invention applied to an electronic system.

Referring to FIG. 16, the electronic system 1000 includes an input device 1100, an output device 1200, a processor device 1300, and a memory device 1400.

The memory device 1400 may include a DRAM 1450 according to an embodiment of the present invention. The processor device 1300 controls the input device 1100, the output device 1200, and the memory device 1400 through corresponding interfaces, respectively.

17 is an application example of the present invention applied to a graphics memory system.

Referring to FIG. 17, the graphics memory system 2000 may include a memory group 2100 including a plurality of memories 2110, an internal interface 2130, and a memory interface 2120, and a memory group ( A controller 2200 (eg, a GPU) for controlling the 2100, and a system bus 2300 between the memory group 2100 and the controller 2200. The plurality of memories 2110 are active power as described above. In down mode, leakage current can be minimized or reduced.

The controller 2200 may include a graphics engine core and transmit and receive data with the memory group 2100. The above-described system bus 2300, the memory interface 2120 and the internal interface 2130 may be integrated or implemented as a single I / O, or may be implemented through a serializer deserializer (SERDES) according to the configuration of an application system. The data format may change by itself.

18 is an application example of the present invention applied to a graphics card.

Referring to FIG. 18, the graphics card 3100 may include a memory 3110 composed of DRAM, a controller 3120 (eg, a GPU) for controlling the memory 3110, and a space between the memory 3110 and the controller 3120. And a system bus 3130. The controller 3120 transmits and receives data to and from the monitor 3300 through the first interface 3500. The controller 3120 receives images and video signals and displays them on the screen. In addition, the controller 3120 transmits and receives data to and from the chipset 3200 and the chipset through the second interface 3400. Here, the first and second interfaces 3500 and 3400 are Universal Serial Bus (USB). ), Multi-Media Card (MMC), Peripheral Component Interconnect-Express (PCIE), Serial-attached SCSI (SAS), Serial Advanced Technology Attachment (SATA), Parallel Advanced Technology Attachment (PATA), Small Computer System Interface (SCSI) , Enhanced Small Disk Interface (ESDI), and Integrated Drive Electronics (IDE) Satisfies one of a variety of interface protocols.

FIG. 19 is an application diagram of a computing system including the graphics card of FIG. 18. Referring to FIG. 19, the computing system 4000 according to the present invention includes a monitor 4100, a graphics card 4200, and a main memory 4300 electrically connected to system buses 4710, 4720, 4730, 4740, and 4750, respectively. , Chip set 4400, input / output device 4600, and CPU 4500. The graphic card 4200 may have the configuration of FIG. 18 described above, and the main memory 4300 may be mounted in the form of a module. The main memory 4300 is configured with DRAM according to embodiments of the present invention to minimize or reduce power consumption of the bit line sense amplifier in the active power down mode.

When the computing system according to the present invention is a mobile device, a battery (not shown) for supplying an operating voltage of the computing system will be further provided. Although not shown in the drawings, the computing system according to the present invention may further be provided with an application chipset, a camera image processor (CIP), a mobile DRAM, or the like.

In addition, a memory system or a computing system may be mounted using various types of packages. For example, Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), Plastic Dual In-Line Package (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board (COB), Ceramic Dual In-Line Package (CERDIP), Plastic Metric Quad Flat Pack (MQFP), Thin Quad Flat-Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package, Thin Small Outline Package (TSOP), Thin Quad Flat-Pack (TQFP), System In Package (SIP), Multi Chip Package (MCP), Wafer-level Fabricated Package (WFP), Wafer-Level Processed It can be implemented using packages such as Stack Package.

As described above, the optimum embodiment has been disclosed through the drawings and the specification. Although specific terms have been used herein, they are used only for the purpose of describing the present invention and are not used to limit the scope of the present invention as defined in the meaning or claims. Therefore, those skilled in the art will understand that various modifications and equivalent other embodiments are possible from this. For example, if the matter is different, various ways of reducing the leakage current of the sense amplifier may be variously modified and modified without departing from the technical spirit of the present invention.

* Description of the symbols for the main parts of the drawings *
100: bit line sense amplifier circuit section
200: floating part
300: control unit
400,410: memory cell array block

Claims (10)

A source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line to drive the source node of the sense amplifier to a set voltage level;
A floating unit which floats the sense amplifier driving signal line in a set operation mode; And
And a control unit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line and controlling a level of the sense amplifier driving signal line in the set operation mode. Node control circuit.
The method of claim 1, wherein the control unit,
A voltage level amplifier having a first input terminal and a second input terminal to which a reference voltage is applied;
A first switch for switching between the first input terminal and the source node of the sense amplifier in the set operation mode; And
And a second switch for switching between the output terminal of the voltage level amplifier and the sense amplifier driving signal line in the set operation mode.
The sense amplifier source node control circuit of claim 1, wherein the sense amplifier is a bit line sense amplifier including N-type transistors.
The sense amplifier source node control circuit of claim 1, wherein the setting operation mode is an operation mode different from an active mode of the semiconductor memory device.
The semiconductor memory device of claim 1, wherein the source driver comprises at least one N-type transistor connected with a drain connected to a source node of the sense amplifier, a gate connected to the sense amplifier driving signal line, and a source connected to ground. Sense amplifier source node control circuit.
3. The sense amplifier source node control circuit of claim 2, wherein the first and second switches are Morse transistors that are switched on in the set operation mode and switched off in an operation mode other than the set operation mode.
3. The sense amplifier source node control circuit of claim 2, wherein the floating unit is a three-state buffer for applying a sense amplifier enable signal to the sense amplifier driving signal line in an active mode of the semiconductor memory device.
3. The sense amplifier source node control circuit of claim 2, wherein the voltage level amplifier comprises a differential amplifier for driving the source node of the sense amplifier to the level of the reference voltage in the set operation mode.
The semiconductor memory device of claim 8, further comprising an amplifier circuit connected between the voltage level amplifier and a source node of the sense amplifier to drive a source node of the sense amplifier to a level equal to or greater than the reference voltage level. Sense amplifier source node control circuit.
A source driver connected between the source node of the sense amplifier and the sense amplifier driving signal line to drive the source node of the sense amplifier to a set voltage level;
A switching unit connected in parallel with the source driver between the source node of the sense amplifier and the sense amplifier driving signal line and switched in a set operation mode to make the source driver into a diode connection configuration; And
And a floating unit configured to float the sense amplifier driving signal line in the set operation mode.
KR1020130044325A 2013-01-17 2013-04-22 Circuit of controlling sense amplifier source node in semiconductor memory device and control method thereof KR102020553B1 (en)

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JP3260583B2 (en) * 1995-04-04 2002-02-25 株式会社東芝 Dynamic semiconductor memory and test method thereof
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KR100604824B1 (en) * 2003-08-08 2006-07-28 삼성전자주식회사 Memory device employing bitline sense amplifier having sensing direction by gate bias control and bitline sensing method
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