KR102006387B1 - An image sensor, operation method thereof, and image processing system having the same - Google Patents

Abstract

An image sensor is disclosed. An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, and a plurality of rows of the pixel array. And a sense amplifier block for detecting and amplifying each pixel signal outputted from a plurality of unit pixels included in the row entering the readout mode, wherein the row driver block enters any one of the readout modes; The row driver block enters the read out mode by controlling the source voltage and the gate voltage of the single transistors included in any one of the plurality of rows of the pixel array. According to the image sensor according to the exemplary embodiment of the present invention, the integration degree of the image sensor may be increased by including only one transistor and a photo diode per unit pixel.

Description

An image sensor, an operation method thereof, and an image processing system including the same

Embodiments of the inventive concept relate to an image sensor, and more particularly, to an image sensor including unit pixels capable of increasing the degree of integration of a pixel array, an operation method thereof, and an image processing system including the same.

CMOS image sensor is a sensing device using a complementary metal-oxide semiconductor (CMOS). CMOS image sensors have the advantages of lower manufacturing cost and smaller device power consumption compared to CCD image sensors with high voltage analog circuits. In addition, since the performance of the CMOS image sensor is improved from the early stage of development, the CMOS image sensor is mainly installed in home appliances including portable devices such as smart phones and digital cameras.

As CMOS image sensors are used for various purposes, miniaturization of pixels of CMOS image sensors is required. This trend requires a CMOS image sensor including a pixel array including smaller pixels and a driving circuit thereof.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide an image sensor, an operation method thereof, and an image processing system including the same, by improving the structure of a unit pixel included in a pixel array.

According to an embodiment of the present invention, a method of operating an image sensor includes accumulating an optical charge in a photodiode connected to a body of a single transistor, and depending on the accumulated optical charge and a read voltage applied to a gate of the single transistor. Outputting a pixel signal and removing the optical charge accumulated in the photodiode.

In some embodiments, an upper surface of the photodiode is lower than an upper surface of the source and the drain of the single transistor.

In some embodiments, the photodiode is formed closer to the drain than the source.

In some embodiments, the photodiode is a virtual photodiode due to a back-gate voltage supplied to the back-gate.

In some embodiments, the source and the drain of the single transistor are connected by a channel.

In some embodiments, the accumulating the photocharges may include applying a high voltage to at least one terminal of the gate, the source, and the drain of the single transistor to induce a photocharge amplification effect due to the avalanche effect. For example, the read voltage is determined according to the threshold voltage of the single transistor.

In some embodiments, the pixel signal is a digital signal having at least two levels.

According to an embodiment, the method may further include processing and processing the pixel signal to generate image data.

The generating of the image data may include grouping each subpixel that outputs the pixel signal and processing the pixel signals that the grouped subpixels output to generate the image data. .

An image sensor according to an embodiment of the present invention includes a pixel array including a plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, and a plurality of rows of the pixel array. And a sense amplifier block for detecting and amplifying each pixel signal outputted from a plurality of unit pixels included in the row entering the readout mode, wherein the row driver block enters any one of the readout modes; The row driver block enters the read out mode by controlling the source voltage and the gate voltage of the single transistors included in any one of the plurality of rows of the pixel array.

In an embodiment, the row driver block controls the source voltage and the gate voltage of the single transistors to enter a plurality of unit pixels into a photocharge accumulation mode and a reset mode, wherein the photodiode accumulates the intensity of incident light. And a reset mode is a mode for removing the accumulated photocharges.

In example embodiments, the photodiode has an upper surface lower than an upper surface of the source and drain of the single transistor.

In some embodiments, the photodiode is formed closer to the drain than the source.

In example embodiments, the plurality of unit pixels may further include a back-gate receiving a back-gate voltage from the row driver block.

In some embodiments, the photodiode is a virtual photodiode by the back-gate voltage.

In example embodiments, the plurality of unit pixels may further include a channel connecting a source and a drain of the single transistor.

In some embodiments, at least one surface of the channel is in contact with the photodiode.

In some embodiments, the channel is formed of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

In example embodiments, the plurality of unit pixels may further include an internal photodiode formed between the channel and the photodiode, and the internal photodiode may be formed of germanium (Ge) or silicon-germanium (SiGe).

In an exemplary embodiment, the pixel array shares a source or a drain between the single transistors adjacent in a column direction.

In example embodiments, the pixel array further includes an STI formed between the single transistors adjacent in a row direction.

In example embodiments, the pixel array further includes an STI formed between the single transistors adjacent in the column direction.

In example embodiments, the pixel array further includes an STI formed between the single transistors adjacent in a row direction.

In an embodiment, the gate voltage in the readout mode is determined according to the threshold voltage of the single transistor.

In some embodiments, the single transistor has a gate formed closer to the source than the drain.

In example embodiments, each of the plurality of unit pixels may further include a reset terminal for removing photocharges accumulated in the photodiode.

According to an embodiment, each pixel signal is a digital signal and includes a reset signal and an image signal.

An image processing system according to an embodiment of the present invention includes a plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, and amplifies the digital pixel signals of the plurality of unit pixels. And an image signal processor for outputting an image sensor and processing the amplified digital pixel signal to generate image data.

In example embodiments, the photodiode has an upper surface lower than an upper surface of the source and drain of the single transistor.

In some embodiments, the photodiode is formed closer to the drain than the source.

In example embodiments, the plurality of unit pixels may further include a back-gate receiving a back-gate voltage from a row driver block for entering the plurality of unit pixels into a read out mode in a row unit.

In some embodiments, the photodiode is a virtual photodiode by the back-gate voltage.

In example embodiments, the plurality of unit pixels may further include a channel connecting a source and a drain of the single transistor, and the channel may be formed of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

In example embodiments, the plurality of unit pixels may further include a channel connecting a source and a drain of the single transistor, and an internal photodiode formed between the channel and the photodiode, wherein the internal photodiode may be germanium (Ge) or silicon. It is formed of germanium (SiGe).

In some embodiments, the image sensor may further include a color filter or a micro lens corresponding to each of the plurality of unit pixels, and the image signal processor treats each of the plurality of unit pixels as one pixel, and the plurality of unit pixels. The pixel data output by each unit pixel is processed to generate the image data.

According to an embodiment, the plurality of unit pixels are grouped into a plurality of sub-pixel groups each including at least two or more unit pixels, and the image signal processor treats each of the sub-pixel groups as one pixel and each of The image data are generated by processing the pixel signals output by the at least two unit pixels of the sub-pixel group of.

In example embodiments, the image sensor may further include a color filter or a micro lens corresponding to each of the plurality of sub-pixel groups. According to an embodiment of the present invention, an electronic system includes a single transistor and a body of the single transistor. An image sensor including a plurality of unit pixels each including a photodiode connected to the amplified digital pixel signal, and amplifying and outputting the digital pixel signal of the plurality of unit pixels; processing the amplified digital pixel signal to generate image data; And a processor for controlling the operation of the memory, a memory for storing the image data and a program for controlling the operation of the image sensor, and a display unit for displaying the image data transmitted from the processor or the memory.

According to the image sensor according to the exemplary embodiment of the present invention, the integration degree of the image sensor may be increased by including only one transistor and a photo diode per unit pixel.

In addition, according to the image sensor according to the embodiment of the present invention, since the pixel array directly outputs a digital pixel signal, a circuit for analog-to-digital conversion can be omitted, thereby reducing noise generation and power consumption.

1 is a block diagram illustrating an image processing system according to an exemplary embodiment of the present invention.
FIG. 2 is a block diagram illustrating in detail the image sensor illustrated in FIG. 1.
3A and 3B are diagrams for describing a processing unit of the pixel array illustrated in FIG. 1.
FIG. 4 is a view schematically illustrating an embodiment of the structure of the pixel array shown in FIG. 1.
5A through 5C are diagrams illustrating layouts for implementing an embodiment of the structure of the pixel array shown in FIG. 4.
FIG. 6 is a diagram schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.
7A and 7B illustrate layouts for implementing another embodiment of the structure of the pixel array shown in FIG. 6.
FIG. 8 is a view schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.
FIG. 9 is a view schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.
FIG. 10 is a block diagram illustrating in detail a unit pixel illustrated in FIG. 2.
FIG. 11 is a diagram illustrating an embodiment of a layout for forming a unit pixel illustrated in FIG. 2.
FIG. 12 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to an example embodiment of the layout illustrated in FIG. 11.
FIG. 13A is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.
FIG. 13B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.
FIG. 13C is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.
FIG. 13D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.
FIG. 14 is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.
FIG. 15 is a diagram illustrating still another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.
FIG. 16 is a diagram illustrating an example of a cross-section along a B direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.
FIG. 17 is a diagram illustrating another example of a cross-section along a B direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.
FIG. 18 is a diagram illustrating still another example of a cross-section along a B direction of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.
FIG. 19 is a diagram illustrating another embodiment of a layout for forming a unit pixel illustrated in FIG. 2.
20 is a diagram illustrating an example of a cross-section of a B direction of a semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19.
FIG. 21 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19.
FIG. 22 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19.
FIG. 23 is a diagram illustrating still another embodiment of a layout for forming a unit pixel shown in FIG. 2.
24 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 23.
FIG. 25 is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate, according to another exemplary embodiment of the layout illustrated in FIG. 23.
FIG. 26 is a diagram illustrating still another embodiment of a layout for forming a unit pixel illustrated in FIG. 2.
FIG. 27 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 28A is a diagram illustrating another embodiment of a cross section along the A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 28B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 28C is a diagram illustrating another embodiment of a cross section in the A direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 28D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 29 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
30 is a cross-sectional view illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.
FIG. 31 is a diagram illustrating still another embodiment of a layout for forming a unit pixel shown in FIG. 2.
32 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.
33A is a view showing another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31.
33B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31.
33C is a view showing another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31.
33D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31.
FIG. 34 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.
FIG. 35 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.
36 is a diagram illustrating an example of a cross-section of a B direction of the semiconductor substrate according to example embodiments of the layout illustrated in FIG. 31.
FIG. 37 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.
FIG. 38 is a diagram illustrating still another embodiment of a cross-section B direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.
FIG. 39 is a diagram illustrating an embodiment of a voltage applied in each operation mode of a unit pixel illustrated in FIG. 2.
40 is a flowchart for describing an operation of the image processing system illustrated in FIG. 1.
FIG. 41 is a block diagram of an electronic system according to an exemplary embodiment including the image sensor illustrated in FIG. 1.
FIG. 42 is a block diagram of a system according to an exemplary embodiment including the image sensor illustrated in FIG. 1.
FIG. 43 is a diagram illustrating an example embodiment of a cross section of the pixel array illustrated in FIG. 1.
FIG. 44 is a diagram illustrating another embodiment of a cross section of the pixel array illustrated in FIG. 1.

Specific structural and functional descriptions of the embodiments of the present invention disclosed herein are for illustrative purposes only and are not to be construed as limitations of the scope of the present invention. And should not be construed as limited to the embodiments set forth herein or in the application.

The embodiments according to the present invention are susceptible to various changes and may take various forms, so that specific embodiments are illustrated in the drawings and described in detail in this specification or application. It is to be understood, however, that it is not intended to limit the embodiments according to the concepts of the present invention to the particular forms of disclosure, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention.

Terms such as first and / or second may be used to describe various components, but the components should not be limited by the terms. The terms are intended to distinguish one element from another, for example, without departing from the scope of the invention in accordance with the concepts of the present invention, the first element may be termed the second element, The second component may also be referred to as a first component.

It is to be understood that when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, . On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between. Other expressions that describe the relationship between components, such as "between" and "between" or "neighboring to" and "directly adjacent to" should be interpreted as well.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Singular expressions include plural expressions unless the context clearly indicates otherwise. In this specification, the terms "comprises ", or" having ", or the like, specify that there is a stated feature, number, step, operation, , Steps, operations, components, parts, or combinations thereof, as a matter of principle.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in the commonly used dictionaries should be construed as having meanings consistent with the meanings in the context of the related art, and are not construed in ideal or excessively formal meanings unless expressly defined herein. Do not.

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, the present invention will be described in detail with reference to the preferred embodiments of the present invention with reference to the accompanying drawings. Like reference symbols in the drawings denote like elements.

1 is a block diagram illustrating an image processing system according to an exemplary embodiment of the present invention.

1, an image processing system 10 according to an embodiment of the present invention includes an image sensor 100, an image processor (DSP) 200, a display unit 300, And a lens 500.

The image sensor 100 may include a pixel array 110, a row driver block 160, a control register block 180, and a readout block 190. have.

The image sensor 100 senses an object 400 captured by the lens 500 under the control of the image processor 200, and the image processor DSP 200 is controlled by the image sensor 100. The sensed output image may be output to the display unit 300. In this case, the display unit 300 may correspond to any device capable of outputting an image. For example, the display unit 300 may be implemented as a computer, a cellular phone, or an electronic device equipped with a camera.

The image processor (DSP) 200 may include a camera control unit 210, an image signal processor 220, and a PC I / F 230. The camera control unit 210 controls the control register block 180. In this case, the camera control unit 210 may control the image sensor 100, that is, the control register block 180 by using an inter-integrated circuit (I2C), but the scope of the present invention is not limited thereto. .

The image signal processor 220 receives the image data, which is an output signal of the readout block 190, and processes and processes the image to make it easier for a human to see, thereby processing the processed and processed image by the PC I / F 230. Output to the display unit 300 through.

Although the image signal processor 220 is illustrated as being located inside the DSP 200 in FIG. 1, the design signal may be changed by those skilled in the art. For example, the image signal processor 220 may be implemented inside the image sensor 100.

The pixel array 110 may include a plurality of unit pixels. Each unit pixel includes one single transistor and a photoelectric conversion element such as a photo diode or a pinned photo diode. Each unit pixel of the pixel array 110 may include only one single transistor to increase the integration degree of the image sensor 100. For example, the image sensor 100 may include unit pixels having a level of 0.1 μm × 0.1 μm or less. In addition, the pixel array 110 senses light using a plurality of photoelectric conversion elements and converts the light into an electrical signal to generate an image signal.

The timing generator 170 may control the operation or timing of the row driver block 160 and the readout block 190 by outputting a control signal or a clock signal to each of the row driver block 160 and the readout block 190. have.

In this case, the control register block 180 operates under the control of the camera control unit 210 and stores various commands necessary for the operation of the image sensor 100.

The row driver block 160 drives the pixel array 110 in rows. For example, the row driver block 160 may supply the reset voltage signal, the back-gate voltage signal, the source voltage signal, and the gate voltage signal of the single transistors of each unit pixel constituting the pixel array 110. That is, the control signal from the timing generator 170 may be decoded to supply the reset voltage signal, the back-gate voltage signal, the source voltage signal, and the gate voltage signal to each row of the pixel array 110.

 The pixel array 110 outputs a pixel signal, that is, a reset signal and an image signal, to the readout block 190 from a row selected by the source voltage signal and the gate voltage signal provided from the row driver block 160.

The readout block 190 temporarily stores the pixel signal output from the pixel array 110, senses it, amplifies it, and outputs the pixel signal. In this case, the readout block 190 includes a plurality of column memories (eg, SRAM) included in each column for temporary storage of the pixel signal, and a sense amplifier SA for sensing and amplifying the temporarily stored pixel signal. can do.

According to an embodiment, when the image sensor 100 includes a depth sensor, the pixel array 110 may include at least one depth pixel, and emits modulated light having a phase difference. It may include a light source (not shown). The image signal processor 220 processes image data from the image sensor 100 and calculates a distance between the image sensor 100 and the object 400 in a time of flight (TOF) manner to obtain a depth image. Can be generated.

FIG. 2 is a block diagram illustrating in detail the image sensor illustrated in FIG. 1.

1 and 2, the pixel array 110 may be implemented in the form of a matrix of n rows and m columns. Each row of the pixel array 110 has a reset voltage signal (RVS1 to RVSn), a back-gate voltage signal (BVS1 to BVSn), a source voltage signal (SVS1 to SVSn) and a gate voltage signal from the row driver block 160, respectively. It can operate by receiving (GVS1 to GVSn).

Each pixel 120 of the pixel array 110 may have a photocharge accumulation mode, a reset mode, and a read-out mode. Each operation mode will be described in detail with reference to FIG. 10.

Each pixel 120 of the pixel array 110 has a reset voltage signal (RVS1 to RVSn), a back-gate voltage signal (BVS1 to BVSn), a source voltage signal (SVS1 to SVSn), and a gate voltage signal (GVS1 to GVSn), respectively. ), The photocharge accumulation mode, the reset mode, and the read-out mode may be entered on a row-by-row basis.

The readout block 190 may include a column memory block 192 and a sense amplifier block 196.

The column memory block 192 may include a plurality of memories 194 that receive pixel signals from column lines COL1 to COLm connected to respective columns of the pixel array 110. The plurality of memories 194 may correspond to, for example, static random access memory (SRAM) or dynamic random access memory (DRAM). The column memory block 192 may temporarily store the pixel signal amplified and output from the sense amplifier block 196 and output the temporarily stored pixel signal to the image signal processor 220 under the control of the timing generator 170. As described later in FIG. 10, the pixel signal may be treated as a digital signal when the signal change due to the photoelectric charge is large. Therefore, analog-digital converting is unnecessary.

The sense amplifier block 196 may include a plurality of sense amplifiers 198 connected between the pixel array 110 and the column memory block 192. The sense amplifiers 198 may amplify and output pixel signals output from the column lines COL1 to COLm in the readout mode under the control of the timing generator 170.

For example, the sense amplifier block 196 may compare the level of the pixel signal with a reference level to amplify the pixel signals to a desired level and output the same. The pixel signal may be a digital signal having two levels (eg 0 and 1) or more levels (eg 0, 1, 2, 3).

3A and 3B are diagrams for describing a processing unit of the pixel array illustrated in FIG. 1.

1 to 3B, part of the pixel array 110, that is, the unit pixels 120 of 16 rows and 16 columns is shown.

Each unit pixel 120 may output a digital pixel signal, respectively. Assuming that the image sensor 100 acquires a color image or a depth image, in FIG. 3A, each unit pixel 120 may correspond to an RGB pixel (Red, Green or Blue) or a depth pixel, respectively. . Each unit pixel 120 includes only a single transistor (not shown) and a photo diode (not shown), so that each unit pixel 120 may be suitable for the image sensor 100 requiring a small pixel size.

Each digital pixel signal output from each unit pixel 120 of FIG. 3A may be processed into one frame by the image signal processor 220.

In FIG. 3B, the plurality of unit pixels 120 may function as sub pixels. That is, the 64 sub pixels 120 may form sub pixel groups 114-1 to 114-4 having 8 rows and 8 columns, respectively. Each of the sub pixel groups 114-1 through 114-4 includes a first sub pixel group 114-1 and a fourth sub pixel group 114-4 including a red filter layer (not shown), and a blue filter. A Bayer pattern may be formed by including the second sub pixel group 114-2 including the layer (not shown) and the third sub pixel group 114-3 including the green filter layer (not shown).

For example, assuming that pixel signals output from the plurality of unit pixels 120 included in the first sub pixel group 114-1 are digital pixel signals of 1 bit, respectively, the first sub pixel group 114 in one frame. 64 digital codes may be generated by summing the digital pixel signals output by -1). Therefore, when the 16 times are read out for the first sub pixel group 114-1, 1024 codes can be generated. This corresponds to an analog signal that may have 1024 codes. Such pixel signal processing may be applied to the second sub pixel group 114-2 to the fourth sub pixel group 114-4. Although the case in which the digital pixel signals output by the first sub-pixel group 114-1 are summed is illustrated, a processing method other than the sum may be applied, and the present invention is not limited thereto.

Although 64 subpixels 120 constitute respective sub pixel groups 114-1 to 114-4, the scope of the present invention is not limited thereto.

According to the pixel array 110 of the image sensor 100 according to the exemplary embodiment of the present invention, a circuit for analog-to-digital conversion may be omitted by directly outputting a digital pixel signal. Since a circuit for analog-to-digital conversion (eg, a ramp circuit, a comparator, a counter, etc.) causes noise and power consumption, the image sensor 100 according to the embodiment of the present invention The pixel array 110 may reduce noise generation and power consumption.

FIG. 4 is a view schematically illustrating an embodiment of the structure of the pixel array shown in FIG. 1.

1, 2, and 4, a portion 110-1 of the arrangement of the pixel array 110 shown in FIG. 1 is shown. Single transistors included in each unit pixel 120-1 are arranged in a matrix form. Single transistors included in each unit pixel 120-1 have a source and a drain formed independently of adjacent single transistors.

Each of the single transistors included in each unit pixel 120-1 has a source and a gate connected to the row driver block 160 so that the source voltage signals SVSa to SVS (a + 3) and the gate voltage signals GVSa to GVS are respectively. (a + 3)). In addition, each of the single transistors included in each unit pixel 120-1 has a drain connected to the readout block 190 so that each column line for outputting the pixel signal under the control of the row driver block 160 ( COLb to COL (b + 3)).

5A through 5C are diagrams illustrating layouts for implementing an embodiment of the structure of the pixel array shown in FIG. 4.

1, 2, and 4-5C, embodiments of a layout for implementing one embodiment of the structure of the pixel array shown in FIG. 4 are shown.

According to the exemplary embodiment 110-1a of the layout shown in FIG. 5A, the source S, the gate G, and the drain D are sequentially arranged in the row direction in each unit pixel 120-1a. . Each unit pixel 120-1a may include a well layer 121 for electrical separation from adjacent unit pixels 120-1a.

According to another embodiment 110-1b of the layout shown in FIG. 5B, each unit pixel 120-1b belonging to another adjacent column is electrically connected by a shallow trench isolation (STI) 122 formed in the column direction. Can be separated. The STI 122 formed in the column direction may be formed by a shallow trench process, and may be filled with oxide, nitride, and the like. The STI 122 formed in the column direction may prevent the photocharge generated by the photodiode (not shown) included in the unit pixel 120-1b from being transferred to other unit pixels 120-1b adjacent to each other. .

According to another embodiment 110-1c of the layout shown in FIG. 5C, each unit pixel 120-1c is electrically connected by the STI 123 formed in the row direction as well as the STI 122 formed in the column direction. Can be separated.

FIG. 6 is a diagram schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.

1, 2, 4, and 6, unlike part 110-1 of the array of pixel arrays 110 shown in FIG. 4, a part of the array of pixel arrays 110 shown in FIG. A source and a drain of the unit pixels 120-2 adjacent to each other in the column direction are shared at 110-2.

Single transistors included in the unit pixel 120-2 having a shared source may receive the same source voltage signals SVSc to SVS (c + 2). Each of the single transistors included in each unit pixel 120-2 may have its gate formed independently to receive the respective gate voltage signals GVSc to GVS (c + 3). In addition, single transistors included in each unit pixel 120-2 may be connected to each column line COLd to COL (d + 3). The unit pixels 120-2 adjacent to each other in the column direction of the portion 110-2 of the array of the pixel array 110 share a source and a drain, so that the pixel array per unit area has a large number of pixels, that is, a smaller pixel array. Implementation of 110 may be possible.

7A and 7B illustrate layouts for implementing another embodiment of the structure of the pixel array shown in FIG. 6.

1, 2, and 6-7b, embodiments of a layout for implementing another embodiment of the structure of the pixel array shown in FIG. 6 are shown.

According to an embodiment 110-2a of the layout shown in FIG. 7A, the source S and the drain D are shared in the unit pixels 120-2a adjacent in the column direction. Each unit pixel 120-2a may include a well layer 121 for electrical separation from adjacent unit pixels.

According to another embodiment 110-2b of the layout shown in FIG. 7B, each unit pixel 120-2b belonging to another adjacent column may be electrically separated by the STI 122 formed in the column direction. .

FIG. 8 is a view schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.

1, 2, 4-5C and 8, in part 110-3 of the arrangement of the pixel array 110 of FIG. 8, a part of the arrangement of the pixel array 110 shown in FIG. 4 is shown. Unlike (110-1), each of the unit pixels 120-3 adjacent to each other in the column direction may receive the same source voltage signals SVSf to SVS (f + 3).

Each of the single transistors included in each unit pixel 120-3 has a source and a gate connected to the row driver block 160 so that the source voltage signals SVSf to SVS (f + 3) and the gate voltage signals GVSe to GVS are respectively. (e + 3)). In addition, each of the single transistors included in each unit pixel 120-3 has a drain connected to the readout block 190 so that each column line for outputting the pixel signal under the control of the row driver block 160 ( COLf to COL (f + 3)).

Also, in part 110-3 of the arrangement of the pixel array 110 of FIG. 8, the source and the drain of the single transistors included in each unit pixel 120-3 are separated. The layouts of FIGS. 5A to 5C may be applied substantially the same except for the wiring state.

FIG. 9 is a view schematically illustrating another embodiment of the structure of the pixel array shown in FIG. 1.

1, 2, 4-5C, 8, and 9, in part 110-4 of the arrangement of the pixel array 110 of FIG. 9, the pixel array 110 shown in FIG. Unlike the portion 110-3 of the array, the same gate voltage signals GVSf and GVS are located between each unit pixel 120-3 in the odd-numbered position or in each unit pixel 120-3 in the even-numbered position in the column direction. (f + 2) or GVS (F + 1) and GVS (f + 3)).

Therefore, odd-numbered unit pixels 120-3 and even-numbered unit pixels 120-3 may be controlled differently. For example, when the odd-numbered unit pixels 120-3 operate in the photocharge accumulation mode, the even-numbered unit pixels 120-3 may operate in the read out mode.

In FIG. 9, only the case where the odd-numbered unit pixels 120-3 and the even-numbered unit pixels 120-3 are controlled differently is described as an example. However, the present disclosure is not limited thereto.

The portion 110-4 of the arrangement of the pixel array 110 of FIG. 9 is substantially the same as the portion 110-3 of the arrangement of the pixel array 110 of FIG. 8 except for the above difference.

FIG. 10 is a block diagram illustrating in detail a unit pixel illustrated in FIG. 2.

1, 2, and 10, the unit pixel 120 may include a single transistor SX and a photo diode PD. 10 to 39, it is assumed that the photoelectric conversion element is a photodiode for convenience of description, but the scope of the present invention is not limited thereto.

The photodiode PD may have one end connected to ground and the other end connected to the body of the single transistor SX, or may be electrically disconnected. The photodiode PD may contain photocharges generated in proportion to the intensity of incident light passing through the lens 500.

In the single transistor SX, a source and a gate are respectively connected to the row driver block 160 to receive the source voltage signal SVS and the gate voltage signal GVS, respectively. The unit pixel 120 may have three operation modes, that is, a photocharge accumulation mode, a reset mode, and a read out mode, depending on the source voltage signal SVS and the gate voltage signal GVS. An embodiment of the source voltage signal SVS and the gate voltage signal GVS capable of determining respective operation modes will be described in detail with reference to FIG. 39.

The photocharge accumulation mode refers to a case where photocharges (electrons or holes) of any one kind of photocharges (electrons, holes) generated by incident light are accumulated in the photodiode PD.

The reset mode refers to a case in which photocharges accumulated in the photodiode PD exit through the source or the drain.

The readout mode refers to a case in which a pixel signal corresponding to photocharges accumulated in the photodiode PD is output through the column line COL. The pixel signal includes an image signal and a reset signal. The image signal refers to a signal output in the readout mode immediately after the photocharge accumulation mode ends, and the reset signal refers to a signal output in the readout mode immediately after the reset mode ends.

The readout mode will be described in detail. According to the photocharges accumulated in the photodiode PD, the body voltage of the single transistor SX may vary, and as the body voltage varies, the threshold voltage of the single transistor SX ( Vth) may vary. If the threshold voltage Vth of the single transistor SX is different, the same result as that of the source voltage is different can be obtained. The unit pixel 120 may output a pixel signal of a digital form having at least two levels using this principle.

FIG. 11 is a diagram illustrating an embodiment of a layout for forming a unit pixel illustrated in FIG. 2.

2 and 11, in one embodiment 130 of the layout for forming the unit pixel 120, the source S, the gate G, and the drain D of a single transistor are sequentially formed. The channel 131 connecting the source S and the drain D is formed. In addition, one embodiment 130 of the layout may include a well layer 132 for electrical separation from adjacent unit pixels (not shown).

Although not shown, an embodiment 130 of the layout may be formed with STIs (138 of FIGS. 13C and 13D) for electrical separation from adjacent unit pixels (not shown) along the A direction or the B direction. have. In addition, a back-gate (B of FIGS. 13C and 13D) that receives the back-gate voltage signal BVS illustrated in FIG. 2 may be formed inside the STI (138 of FIGS. 13C and 13D). The back-gate (B of FIGS. 13C and 13D) may receive the back-gate voltage signal (any one of BVS1 to BVSn) from the row driver block 160.

FIG. 12 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to an example embodiment of the layout illustrated in FIG. 11.

11 and 12, one embodiment 130A-1 of the A-direction cross section of the semiconductor substrate 140-1 according to an embodiment 130 of the layout may include a source S and a gate of a single transistor. G), drain D, channel 131, well layer 132, photodiode 133, gate insulating film 134, first epitaxial layer 135 and second epitaxial layer ( second epitaxial layer 136). The semiconductor substrate 140-1 may be formed based on a silicon (Si) substrate.

The source S, gate G and drain D of the single transistor can each operate as a terminal of the single transistor. In this case, the source S and the drain D may be formed as regions doped at a high concentration by performing an ion implantation process. When the single transistor is a PMOS transistor, the source S and the drain D may be p regions doped with P +. In contrast, when the single transistor is an NMOS transistor, the source S and the drain D may be n regions doped with N +. The gate G may be formed of poly silicon.

The channel 131 may be formed to facilitate the flow of carriers between the source S and the drain D of the single transistor. The carrier is a hole when the single transistor is a PMOS transistor, and corresponds to an electron when the single transistor is an NMOS transistor. Channel 131 is not essential and may be formed selectively. The channel 131 may be formed of silicon (Si), germanium (Ge), or silicon-germanium (SiGe).

The well layer 132 may be doped with N- if the single transistor is a PMOS or doped with P- if the single transistor is an NMOS.

The photodiode 133 may be formed in the well layer 132. The photodiode 133 may be doped with n when the single transistor is a PMOS transistor and doped with p when the single transistor is an NMOS transistor.

The gate insulating layer 134 may be formed to insulate between the gate G and the channel 131. The gate insulating layer 134 may be formed of SiO 2, SiON, SiN, Al 2 O 3, Si 3 N 4, GexOyNz, GexSiyOz or a high dielectric constant material, and the high dielectric constant material may be HfO 2, ZrO 2, Al 2 O 3, Ta 2 O 5, hafnium silicate, or zirconium silicate, or a combination thereof. Combinations and the like can be formed by atomic layer deposition.

The first epitaxial layer 135 and the second epitaxial layer 136 may be formed by an epitaxial growth method. When the single transistor is a PMOS transistor, the first epitaxial layer 135 and the second epitaxial layer 136 may be doped with P− and P +, respectively. In contrast, when the single transistor is an NMOS transistor, the first epitaxial layer 135 and the second epitaxial layer 136 may be doped with P− and N +, respectively.

Although not shown in FIG. 12, the conductive lines for operating the pixel array 110, that is, the conductive lines for connection with the row driver block 160 and the readout block 190, may be the source (S) and the gate (G). ) And a BSI (Back Side Illumination) method of increasing the light receiving efficiency of the photodiode by forming on the drain D.

FIG. 13A is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.

11 to 13A, in another embodiment 130A-2a of the A-direction cross section of the semiconductor substrate 140-2a according to the embodiment 130 of the layout, the gate G is an etch process. It may be inserted into (140-2a) and formed. That is, the semiconductor substrate 140-2a may be formed in a recess gate structure.

Accordingly, the channel 131 is also inserted into the semiconductor substrate 140-2a and the photodiode 133 is formed in the semiconductor substrate 140-2a. Accordingly, the distance between the source S or the drain D in the photodiode 133 increases.

As the distance between the source S or the drain D in the photodiode 133 increases, the influence of the photodiode 133 on the channel 131 may be improved.

In particular, in the structure of the ultra-small pixel array 110 having a gate length of 50 nm or less, the distance between the source S or the drain D in the photodiode 133 is very close, so that the operation of a single transistor is difficult. It may not work smoothly. That is, when the length of the gate G is 50 nm or less, the distance between the photodiode 133 and the source S or the drain D becomes very close, thereby reducing the influence of the photodiode 133 on the channel 131. . Accordingly, a pixel signal insensitive to photocharges accumulated in the photodiode 133 may be generated.

Therefore, it is preferable that the image sensor 100 implemented with the small unit pixel forms the pixel array 110 in the recess gate structure.

The semiconductor substrate 140-2a is substantially the same as the semiconductor substrate 140-1 shown in FIG. 12 except for the above difference.

FIG. 13B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.

11 to 13B, in another embodiment 130A-2b of the A-direction cross section of the semiconductor substrate 140-2b according to the embodiment 130 of the layout, the gate G is similar to that of FIG. 13A. It may be formed of a recess gate structure.

The photodiode 133 may be formed to be biased toward the drain D rather than the source S around the gate G during the implantation process for forming the photodiode 133. That is, the photodiode 133 may be formed in an asymmetrical structure with respect to the gate G.

According to another embodiment, the photodiode 133 may be formed to be biased toward the source S rather than the drain D around the gate G.

When the photodiode 133 is formed as shown in FIG. 13B, the overall size of the photodiode 133 may be reduced. When the total size of the photodiode 133 is miniaturized, the distance between the photocharges accumulated in the photodiode 133 and the channel 131 is reduced, so that the channel 131 of the photodiode 133 is in accordance with Coulomb's law. ), The greater the impact.

In particular, the recess gate structure having a photodiode 133 having an asymmetrical structure with respect to the gate G of FIG. 13B in the structure of the ultra-small pixel array 110 having a gate G length of 32 nm or less is shown in FIG. It may have a higher photoelectric conversion rate (mV / e−) and a resistance change rate (% / e−) than the access gate structure.

For example, in the structure of the small pixel array 110 having a gate G of 22 nm in length, one photoelectric charge may generate a conversion voltage of about 60 mV and a resistance change of about 18%.

FIG. 13C is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.

11 to 13C, in another embodiment 130A-2c of the A-direction cross section of the semiconductor substrate 140-2c according to the embodiment 130 of the layout, adjacent unit pixels (not shown) in the A direction are illustrated. STI 138 may be formed for electrical separation from the backplane. The back-gate B may be formed in the STI 138.

The back-gate B may be formed of poly silicon after the STI 138 is formed in a shallow trench process and filled with oxide, nitride, and the like.

When the back-gate B receives the back-gate voltage signal (any of BVS1 to BVSn) from the row driver block 160, it is similar to the photodiode 133 of the asymmetric structure for the gate G of FIG. 13B. A virtual photo diode 133-1 having a function may be formed.

The voltage condition of the back-gate voltage signal (any one of BVS1 to BVSn) suitable for forming the virtual photodiode 133-1 is -0.5 V or less when the single transistor is an NMOS transistor, or the single transistor is a PMOS transistor. If 0.5 V or more. This is exemplary and the scope of the present invention is not limited thereto.

When the virtual photodiode 133-1 is formed, the virtual photodiode 133-1 may perform substantially the same function as the photodiode 133 having an asymmetrical structure with respect to the gate G of FIG. 13B. .

FIG. 13D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.

11-13D, in another embodiment 130A-2d of the A-direction cross section of the semiconductor substrate 140-2d according to the embodiment 130 of the layout, the asymmetry with respect to the gate G of FIG. 13B is shown. The STI 138 and the back-gate B of FIG. 13C may be formed together with the photodiode 133 having the structure.

Therefore, the influence on the channel 131 of the photodiode 133 shown in FIG. 13D may be greater than that of FIGS. 13A through 13C.

FIG. 14 is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.

11 to 14, in another embodiment 130A-3 of the A-direction cross section of the semiconductor substrate 140-3 according to an embodiment 130 of the layout, the channel 131 ′ may be formed of silicon (Si). It may be formed of germanium (Ge) or silicon-germanium (SiGe) rather than). That is, the semiconductor substrate 140-3 may have a germanium channel structure.

When the channel 131 ′ is formed of germanium (Ge) or silicon-germanium (SiGe), the channel of the photodiode 133 similarly to the semiconductor substrates 140-2a to 140-2d shown in FIGS. 13A to 13D. (131 ') can improve the impact. That is, the photodiode 133 may store photocharges in the localized channel 131 ′ to improve the influence on the channel 131 ′.

The semiconductor substrate 140-3 is substantially the same as the semiconductor substrate 140-1 shown in FIG. 12 except for the above difference.

FIG. 15 is a diagram illustrating still another example of a cross-section along an A direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.

11 to 15, in another embodiment 130A-4 of the A-direction cross section of the semiconductor substrate 140-4 according to an embodiment 130 of the layout, the channel 131 is formed of silicon (Si). It can be formed as. The photodiode 133 is a silicon (Si) region doped with P or N, and an internal photodiode 137 formed of germanium (Ge) or silicon-germanium (SiGe) between the photodiode 133 and the channel 131. ) May be formed.

When the internal photodiode 137 is formed adjacent to the photodiode 133, the influence on the channel 131 of the photodiode 133 may be improved like the semiconductor substrate 140-3 shown in FIG. 14. have. That is, the photodiode 133 may store photocharges in the internal photodiode 137 to improve the influence on the channel 131.

The semiconductor substrate 140-4 is substantially the same as the semiconductor substrate 140-1 shown in FIG. 12 except for the above difference.

FIG. 16 is a diagram illustrating an example of a cross-section along a B direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.

11 through 16, the gate of the single transistor shown in one embodiment 130B-1 of the B-direction cross section of the semiconductor substrate 140-5 according to the embodiment 130 of the layout illustrated in FIG. 11. (G), the channel 131, the well layer 132, the photodiode 133, the gate insulating film 134, the first epitaxial layer 135 and the second epitaxial layer 136 are shown in FIG. 12. Substantially the same as the configurations.

In this case, one side of the channel 131 may contact the gate insulating layer 134, and the other side of the channel 131 may contact the photodiode 133. In addition, the channel 131 may be formed such that the other sides thereof contact the well layer 132.

The source S, the gate G, the drain D, the channel 131, the well layer 132, the photodiode 133, the gate insulating layer 134, the first epitaxial layer 135 of the single transistor, and the like. The second epitaxial layer 136 is substantially the same as the configurations shown in FIG. 12.

FIG. 17 is a diagram illustrating another example of a cross-section along a B direction of a semiconductor substrate according to example embodiments of the layout illustrated in FIG. 11.

11 to 17, in another embodiment 130B-2 of the B-direction cross section of the semiconductor substrate 140-6 according to the embodiment 130 of the layout shown in FIG. One side may be in contact with the gate insulating layer 134, and three adjacent sides may be in contact with the photodiode 133.

The semiconductor substrate 140-6 is substantially the same as the semiconductor substrate 140-5 shown in FIG. 16 except for the above difference.

FIG. 18 is a diagram illustrating still another example of a cross-section along a B direction of the semiconductor substrate according to the example embodiment of the layout illustrated in FIG. 11.

11 to 18, in another embodiment 130B-3 of the B-direction cross section of the semiconductor substrate 140-7 according to the embodiment 130 of the layout shown in FIG. All four sides may be formed to contact the photodiode 133.

The semiconductor substrate 140-7 is substantially the same as the semiconductor substrate 140-5 shown in FIG. 16 except for the above difference.

FIG. 19 is a diagram illustrating another embodiment of a layout for forming a unit pixel illustrated in FIG. 2.

2, 11, and 19, another embodiment 230 of the layout includes a source S, a gate G, and a drain of a single transistor, similar to the embodiment 130 of the layout illustrated in FIG. 11. (D), the channel 131 and the well layer 132 are formed. In another embodiment 230 of the layout, an STI 138 may be formed for electrical separation from adjacent unit pixels (not shown) along the B direction.

A cross section in the A direction of the semiconductor substrate according to another exemplary embodiment 230 of the layout may include cross sections 130A-1 to 130A − in the A direction of the semiconductor substrate according to the exemplary embodiment 130 of the layout illustrated in FIGS. 12 to 15. It may correspond to any one of 4).

20 is a diagram illustrating an example of a cross-section of a B direction of a semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19. FIG. 21 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19. FIG. 22 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 19.

12, 16-18, and 19-22, embodiments 230B- in cross-section of a B direction of semiconductor substrates 240-1 through 240-3 according to another embodiment 230 of the layout. Gate G, channel 131, well layer 132, photodiode 133, gate insulating film 134, first epitaxial layer 135, and second of a single transistor shown in 1 to 230B-3 The epitaxial layer 136 is substantially the same as the configurations shown in FIG. 12.

In the embodiments 230B-1 to 230B-3 of the B-direction cross-section of the semiconductor substrates 240-1 to 240-3 shown in FIGS. Can be formed. By forming the STI 133, it is possible to effectively prevent the photocharge generated by the photodiode 133 from being transferred to another unit pixel (not shown) adjacent thereto.

In addition, the channel 131 and the photodiode 133 in the embodiments 230B-1 to 230B-3 of the B-direction cross section of the semiconductor substrates 240-1 to 240-3 shown in FIGS. 20 to 22. And the positional relationship between the gate insulating film 134 in the embodiments 130B-1 to 130B-3 of the B-direction cross section of the semiconductor substrates 140-5 to 140-7 shown in FIGS. 16 to 18, respectively. Since it is substantially the same as a positional relationship, description is abbreviate | omitted.

FIG. 23 is a diagram illustrating still another embodiment of a layout for forming a unit pixel shown in FIG. 2.

Referring to FIGS. 2, 11, and 23, another embodiment 330 of the layout may include the source S, the gate G, and the single transistor, similar to the embodiment 130 of the layout illustrated in FIG. 11. Drain D, channel 131 and well layer 132 are formed. Further, another embodiment 330 of the layout may be formed such that the gate G is adjacent to the drain D. A cross section in the B direction of the semiconductor substrate according to another embodiment 330 of the layout is shown in FIG. 16. 18 may correspond to any one of end surfaces 130B-1 to 130B-3 in the B direction of the semiconductor substrate according to the exemplary embodiment 130 of FIG. 18.

24 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another example embodiment of the layout illustrated in FIG. 23. FIG. 25 is a diagram illustrating another example of a cross-section along an A direction of a semiconductor substrate, according to another exemplary embodiment of the layout illustrated in FIG. 23.

12 and 23 to 25, embodiments 330A-1 to 330A-2 of the cross section along the A direction of the semiconductor substrates 340-1 and 340-2 according to another embodiment 330 of the layout. Source S, gate G, drain D, channel 131, well layer 132, photodiode 133, gate insulating film 134, and first epitaxial layer 135 and the second epitaxial layer 136 are substantially the same as the configurations shown in FIG. 12.

In embodiments 330A-1 and 330A-2 of the A-direction cross-section of the semiconductor substrates 340-1 and 340-2 shown in FIGS. 24 and 25, the gate G of the single transistor is connected to the drain D. FIG. It may be formed to be adjacent.

In the exemplary embodiment of FIG. 24, the photodiode 133 may have a length shorter than that of the channel 131 and may be formed adjacent to the source S. That is, the photodiode 133 and the gate G are formed to be offset, thereby minimizing the influence of the gate G during the readout operation, thereby improving the influence on the channel 131 of the photocharges accumulated in the photodiode 133. You can. In addition, when the reset voltage is applied to the drain D during the reset operation, a specific voltage may be applied to the gate G formed adjacent to the drain D so that a smooth reset may be performed.

In another embodiment of FIG. 25, the photodiode 133 may be formed to have substantially the same length as the channel 131, thereby increasing light reception efficiency than the embodiment of FIG. 24.

FIG. 26 is a diagram illustrating still another embodiment of a layout for forming a unit pixel illustrated in FIG. 2.

2, 11, and 26, another embodiment 430 of a layout includes a source S, a gate G, and a single transistor, similar to the embodiment 130 of the layout illustrated in FIG. 11. Drain D, channel 131 and well layer 132 are formed. In addition, in another embodiment 330 of the layout, the reset terminal 139 may be included in the source S. FIG.

A cross section in the B direction of the semiconductor substrate according to another exemplary embodiment 430 of the layout may include cross sections 130B-1 to 130B in the B direction of the semiconductor substrate according to the exemplary embodiment 130 of the layout illustrated in FIGS. 16 to 18. It may correspond to any one of -3).

Although not shown, another embodiment of the layout 430 may be formed with an STI (138 of FIGS. 28C and 28D) for electrical separation from adjacent unit pixels (not shown) along the A direction or the B direction. Can be. In addition, a back-gate (B of FIGS. 28C and 28D) that receives the back-gate voltage signal BVS illustrated in FIG. 2 may be formed inside the STI (138 of FIGS. 28C and 28D). The back-gate (B of FIGS. 28C and 28D) may receive the back-gate voltage signal (any one of BVS1 to BVSn) from the row driver block 160.

In addition, when another embodiment 430 of the layout includes an STI (not shown) formed along the A direction, the cross-section of the B direction of the semiconductor substrate may include another embodiment 230 of the layout illustrated in FIGS. 20 to 22. ) May correspond to any one of end surfaces 230B-1 to 230B-3 in the B direction of the semiconductor substrate.

FIG. 27 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. FIG. 28A is a diagram illustrating another embodiment of a cross section along the A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. FIG. 28B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. FIG. 28C is a diagram illustrating another embodiment of a cross section in the A direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. FIG. 28D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. FIG. 29 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26. 30 is a cross-sectional view illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 26.

12 to 15 and 26 to 30, embodiments 430A-1 to cross-sectional views of the semiconductor substrates 440-1 to 440-4 according to another embodiment 430 of the layout. Source (S), gate (G), drain (D), back-gate (B), channel 131, well layer 132, photodiode 133, gate insulating film of a single transistor shown in 430A-4 134, first epitaxial layer 135, second epitaxial layer 136, internal photodiode 137 and STI 138 are substantially the same as the configurations shown in FIGS. 12-15, respectively. .

The reset terminal 139 formed in the source S shown in FIGS. 27 to 30 may be doped with N + when the single transistor is a PMOS transistor and may be doped with P + when the single transistor is an NMOS transistor. The reset terminal 139 may remove the photocharge in the photodiode 133 by receiving the reset voltage signal RVS from the row driver block 160.

FIG. 31 is a diagram illustrating still another embodiment of a layout for forming a unit pixel shown in FIG. 2.

2, 11, and 31, another embodiment 530 of the layout may include the source S, the gate G, and the single transistor, similar to the embodiment 130 of the layout illustrated in FIG. 11. Drain D, channel 131 and well layer 132 are formed. In addition, in another embodiment 330 of the layout, the reset terminal 139 may be formed with the reset well layer 141 interposed between the gate G and the gate.

Although not shown, another embodiment of the layout 530 may be formed with an STI (138 of FIGS. 33C and 33D) for electrical separation from adjacent unit pixels (not shown) along the A direction or the B direction. Can be. In addition, a back-gate (B of FIGS. 33C and 33D) that receives the back-gate voltage signal BVS illustrated in FIG. 2 may be formed inside the STI (138 of FIGS. 33C and 33D). The back-gate (B of FIGS. 33C and 33D) may receive the back-gate voltage signal (any one of BVS1 to BVSn) from the row driver block 160.

32 is a diagram illustrating an example of a cross-section along an A direction of a semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31. 33A is a view showing another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31. 33B is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31. 33C is a view showing another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31. 33D is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another embodiment of the layout shown in FIG. 31. FIG. 34 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31. FIG. 35 is a diagram illustrating still another embodiment of the A-direction cross section of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.

12 to 15 and 32 to 35, embodiments 530A-1 to cross-sectional views of the semiconductor substrates 540-1 to 540-4 according to another embodiment 530 of the layout. Source (S), gate (G), drain (D), back-gate (B), channel 131, well layer 132, photodiode 133, gate insulating film of single transistor shown in 530A-4 134, first epitaxial layer 135, second epitaxial layer 136, internal photodiode 137 and STI 138 are substantially the same as the configurations shown in FIGS. 12-15, respectively. .

36 is a diagram illustrating an example of a cross-section of a B direction of the semiconductor substrate according to example embodiments of the layout illustrated in FIG. 31. FIG. 37 is a diagram illustrating another embodiment of a cross-section B direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31. FIG. 38 is a diagram illustrating still another embodiment of a cross-section B direction of the semiconductor substrate according to another exemplary embodiment of the layout illustrated in FIG. 31.

16 to 18 and 36 to 38, embodiments 530B-1 to cross-section B of a semiconductor substrate 540-5 to 240-7 according to another embodiment 530 of the layout. Gate G, channel 131, well layer 132, photodiode 133, gate insulating film 134, first epitaxial layer 135 and second epitaxial of single transistor shown in 530B-3 Layer 136 is substantially the same as the configurations shown in FIGS. 16-18.

In embodiments 530B-1 to 530B-3 of the B-direction cross section of the semiconductor substrates 540-1 to 540-3 shown in FIGS. 36 to 38, a reset terminal 139 and a reset well layer 141 are formed. Can be.

The reset terminal 139 may be doped with N + when the single transistor is a PMOS transistor and may be doped with P + when the single transistor is an NMOS transistor. The reset terminal 139 may remove the photocharge in the photodiode 133 by receiving the reset voltage signal RVS from the row driver block 160.

The reset well layer 141 may be formed in contact with the photodiode 133 and the reset terminal 139 to transfer photocharges in the photodiode 133 to the reset terminal 139.

In addition, in the embodiments 530B-1 to 530B-3, the positional relationship between the channel 131, the photodiode 133, and the gate insulating layer 134 may be the semiconductor substrate 140 illustrated in FIGS. 16 to 18, respectively. Since the positional relationship in the embodiments 130B-1 to 130B-3 in the B-direction cross section of -5 to 140-7 is substantially the same, the description is omitted.

The layouts, cross-sections in A direction and cross-sections in direction B in FIGS. 11 to 38 are not independent of each other and may be combined as necessary.

FIG. 39 is a diagram illustrating an embodiment of a voltage applied in each operation mode of a unit pixel illustrated in FIG. 2.

2, 10, 12, and 39, one embodiment of a voltage applied in the photocharge accumulation mode, the reset mode, and the read out mode of the unit pixel 120 is illustrated. The voltage value indicated by the source voltage signal SVS applied to the source terminal of the single transistor SX is represented by the source voltage Vs, and the voltage value represented by the gate voltage signal GVS applied to the gate terminal is represented by the gate voltage Vg, The voltage value output to the drain terminal is defined as the drain voltage Vd and the voltage value applied to the semiconductor substrate, for example, the well layer 132 of FIG. 12, as the substrate voltage Vsub.

In the photocharge accumulation mode, the source voltage Vs is the first accumulation voltage VINT1, the gate voltage Vg is the second accumulation voltage VINT2, to generate photocharge amplification by the avalanche effect. Substrate voltage Vsub may be applied to 0 V, respectively. For example, when the single transistor SX is a PMOS transistor, the first storage voltage VINT1 may be 0 V and the second storage voltage VINT2 may be 0 or a positive voltage (0 to 5 V). In contrast, when the single transistor SX is an NMOS transistor, the first storage voltage VINT1 may be 0 V and the second storage voltage VINT2 may be 0 or a negative voltage (0 to -5 V). When the voltage is applied to the single transistor SX to enter the photocharge accumulation mode as described above, the single transistor SX may be deactivated and photocharges corresponding to the intensity of incident light may be generated and accumulated in the photodiode PD. . In addition, the drain voltage Vd may correspond to 0V.

In some embodiments, in order to generate photocharge amplification due to the avalanche effect in the photocharge accumulation mode, a high voltage (for example, 3.3V or more in the case of a PMOS transistor, not a gate G). ) Or a low voltage (eg -3.3 V or less in the case of an NMOS transistor).

According to another exemplary embodiment, a specific voltage (a negative voltage in the case of a PMOS transistor and a positive voltage in the case of an NMOS transistor) is applied to the source S and the drain D to prevent photocharge accumulation by the photodiode PD. Inflow of photocharges into the photodiode PD may be blocked. That is, the electric shutter function may be implemented by adjusting the voltages of the source S and the drain D. FIG.

In the reset mode, the source voltage Vs may be applied to the first reset voltage VRESET1, the gate voltage Vg to the second reset voltage VRESET2, and the substrate voltage Vsub to 0V, respectively. For example, when the single transistor SX is a PMOS transistor, the first reset voltage VRESET1 may be a positive voltage of 1.5V or more, and the second reset voltage VRESET2 may be 0V. In contrast, when the single transistor SX is an NMOS transistor, the first reset voltage VRESET1 may be a negative voltage of −1.5 V or less and the second reset voltage VRESET2 may be 0 V. FIG. When a voltage is applied to the single transistor SX to enter the reset mode as described above, the photocharges accumulated in the photodiode PD may be reset through the semiconductor substrate, for example, the well layer 132 of FIG. 12. In addition, the drain voltage Vd may correspond to 0V.

In the readout mode, the source voltage Vs may be applied to the first read voltage VREAD1, the gate voltage Vg to the second read voltage VREAD2, and the substrate voltage Vsub to 0V, respectively. For example, when the single transistor SX is a PMOS transistor, the first read voltage VREAD1 is the power supply voltage VDD and the second read voltage VREAD2 is not affected by the photodiode PD. The voltage may be lower than the threshold voltage Vth. Conversely, when the single transistor SX is an NMOS transistor, the first read voltage VREAD1 is the power supply voltage VDD and the second read voltage VREAD2 is the voltage of the single transistor SX when there is no influence of the photodiode PD. The voltage may be higher than the threshold voltage Vth. The power supply voltage VDD may correspond to the power supply voltage of the image sensor 100 and may have a voltage value of -3 to 3V.

As described above, when the voltage is applied to the single transistor SX and enters the read-out mode, it is sensed that the threshold voltage Vth of the single transistor SX is changed according to the photocharges accumulated in the photodiode PD. VDD may be output as the pixel signal Vout.

For example, it is assumed that the threshold voltage Vth of the single transistor SX is 1V when the single transistor SX is an NMOS transistor and there is no influence of the photodiode PD. In addition, it is assumed that the threshold voltage Vth of the single transistor SX is changed to 1.4 V when one photocharge generated by the photodiode PD is generated. When one photocharge is generated by the photodiode PD, the single transistor SX may be activated to output a pixel signal Vout of a high level (for example, 1V). On the contrary, when no photocharge is generated by the photodiode PD, the single transistor SX may be inactivated to output the pixel signal Vout having a low level (eg, 0 V).

40 is a flowchart for describing an operation of the image processing system illustrated in FIG. 1.

1 to 3, 10, 39, and 40, photoelectric charges accumulated in the photodiode PD connected to the body of the single transistor SX in the reset mode are applied to the source and gate of the single transistor SX. In operation S600, the first reset voltage VRESET1 and the second reset voltage VRESET2 may be removed.

Incident light reflected from the object 400 is incident to the pixel array 110 through the lens 500. In the photocharge accumulation mode, the photodiode PD included in each unit pixel 120 of the pixel array 110 may accumulate photocharges generated according to the intensity of the incident light (S610).

In the read out mode, each unit pixel 120 may output a pixel signal according to the second read voltage VREAD2 applied to the gate of the single transistor SX by the accumulated photocharge and gate voltage signal GVS. have. Each unit pixel 120 may sequentially output pixel signals in digital form in units of rows under the control of the row driver block 160 (S620).

The readout block 190 may amplify and temporarily store the pixel signal output from the pixel array 110. The readout block 190 may sequentially transmit the temporarily stored pixel signal to the image signal processor 220 under the control of the timing generator 170. The image signal processor 220 generates an image based on each unit pixel 120 as shown in FIG. 3A, or each sub pixel group 114-1 in which a plurality of unit pixels 120 are grouped as shown in FIG. 3B. To 114-4) may be generated as a unit (S630).

FIG. 41 is a block diagram of an electronic system according to an exemplary embodiment including the image sensor illustrated in FIG. 1.

1 and 41, the electronic system 1000 may include a data processing device capable of using or supporting a mobile industry processor interface (MIPI) interface, such as a mobile phone, personal digital assistants (PDAs), and a portable multimedia player (PMP). It may be implemented as an IPTV (internet protocol television) or a smart phone.

The electronic system 1000 includes an image sensor 100, an application processor 1010, and a display 1050.

The CSI host 1012 implemented in the application processor 1010 can communicate with the CSI device 1041 of the image sensor 100 through the camera serial interface. At this time, for example, the CSI host 1012 may include an optical deserializer (DES), and the CSI device 1041 may include a serializer (SER).

The DSI host 1011 implemented in the application processor 1010 can communicate with the DSI device 1051 of the display 1050 through a display serial interface (DSI). For example, the DSI host 1011 may include an optical serializer (SER), and the DSI device 1051 may include an optical deserializer (DES).

According to an embodiment, the electronic system 1000 may further include an RF chip 1060 capable of communicating with the application processor 1010. A PHY (PHYsical channel) 1013 included in the application processor 1010 and a PHY 1061 included in the RF chip 1060 can exchange data according to the MIPI DigRF.

According to an embodiment, the electronic system 1000 includes a GPS 1020, a storage 1070, a microphone (MIC) 1080, a dynamic random access memory (DRAM) 1085 and a speaker 1090 And the electronic system 1000 may communicate using a world interoperability for microwave access (WIMAX) 1030, a wireless LAN 1100, and / or an ultra wideband (UWB) 1110, for example.

FIG. 42 is a block diagram of a system according to an exemplary embodiment including the image sensor illustrated in FIG. 1.

1 and 42, an image processing system 1100 may include an image sensor 100, a processor 1110, a memory 1120, a display unit 1130, and an interface. (interface) 1140.

The processor 1110 may control the operation of the image sensor 100. [ For example, the processor 1110 may generate two-dimensional and / or three-dimensional image data based on color information or depth information from the image sensor 100.

The memory 1120 may store a program for controlling the operation of the image sensor 100 via the bus 1150 and an image generated by the processor 1110 under the control of the processor 1110, And can access the stored information to execute the program. The memory 1120 may be implemented, for example, in a non-volatile memory.

The image sensor 100 may generate two-dimensional and / or three-dimensional image data based on each digital pixel signal (eg, color information or depth information) under the control of the processor 1110.

The display unit 1130 can receive the generated image from the processor 1110 or the memory 1120 and display it through a display (e.g., an LCD (Liquid Crystal Display), an AMOLED (Active Matrix Organic Light Emitting Diodes) .

The interface 1140 may be implemented as an interface for inputting and outputting two-dimensional or three-dimensional images. According to an embodiment, the interface 1140 may be implemented with an air interface.

FIG. 43 is a diagram illustrating an example embodiment of a cross section of the pixel array illustrated in FIG. 1.

1 to 3B, 10 to 38, and 43, FIG. 43 illustrates an embodiment 150-1 of a cross section in a row direction or a column direction of the pixel array 110 illustrated in FIG. 1. It is. For convenience of description, the cross-section 150-1 in the row direction or the column direction of the pixel array 110 is illustrated to include only six unit pixels 120.

One embodiment 150-1 of a cross-section in the row direction or the column direction of the pixel array 110 may include the unit pixel 120, the third epitaxial layer 152, the color filter layer 154, and the micro lens layer 156. It may include. It is assumed that the microlens layer 156 through which incident light passes first is lower, and the unit pixel 120 is upper.

The plurality of unit pixels 120 may be arranged in a line. Each unit pixel 120 may be implemented according to any one of the embodiments of the layouts of FIGS. 11, 19, 23, 26, and 31, and in the row direction of each unit pixel 120. Alternatively, cross-sections in the column direction may be cross-sections of the semiconductor substrate according to embodiments of the layout (FIGS. 12 to 18, 20 to 22, 24, 25, 27 to 30, and 32 to 38). It may correspond to.

Accordingly, the gate G of the plurality of unit pixels 120 may be formed farther from the second epitaxial layer 136 with respect to the third epitaxial layer 152. In this case, the photodiode 133 is formed closer to the microlens layer 156 than the metal layer (not shown) for wiring of the pixel array 110 (BSI (Back Side Illumination) structure) so that the light collecting power of the photodiode 133 can be achieved. (light gathering power) can be increased.

The third epitaxial layer 152 may be formed under the plurality of unit pixels 120. The third epitaxial layer 152 may be formed by an epitaxial growth method similarly to the first epitaxial layer 135 and the second epitaxial layer 136. The third epitaxial layer 152 may be doped with P-.

The color filter layer 154 may be formed under the third epitaxial layer 152, and may emit light of a specific wavelength (eg, red, green, blue, magenta, yellow). (Yellow, Cyan) can be selectively transmitted. According to an embodiment, a flat layer (not shown) called an over-coating layer may be formed on the color filter layer 154. According to an embodiment, the color filter layer 154 may be omitted when the unit pixel 120 is implemented as a depth pixel.

According to an embodiment, each color filter 155 may be formed at a corresponding position for each unit pixel 120. For example, different red filters R and blue filters B may be alternately formed in adjacent unit pixels 120 as shown in FIG. 43.

The micro lens layer 156 may be formed under the color filter layer 154, and each micro lens 157 may be formed at a corresponding position for each unit pixel 120. The micro lens layer 156 may be used to increase the light collecting power to improve image quality. In some embodiments, the microlens layer 156 may be omitted.

When the pixel array 110 is formed as illustrated in FIG. 43, pixel signals of the pixel array 110 may be processed into one frame by the image signal processor 220 as described with reference to FIG. 3A. That is, each unit pixel 120 may be treated as one pixel. For example, in FIG. 43, the unit pixel 120 corresponding to the red filter R may be treated as a red pixel, and the unit pixel 120 corresponding to the blue filter B may be treated as a blue pixel.

FIG. 44 is a diagram illustrating another embodiment of a cross section of the pixel array illustrated in FIG. 1.

1 to 3B, 10 to 38, 43 and 44, FIG. 44 shows another embodiment 150-2 of a cross section in a row or column direction of the pixel array 110 shown in FIG. The unit pixel 120 and the third epitaxial layer 152 of another embodiment 150-2 of the row direction or the column direction cross section of the pixel array 110 are illustrated in FIG. 43. 120 and substantially the same as the third epitaxial layer 152.

The color filters 155 ′ included in the color filter layer 154 ′ may be formed at respective positions for each of the plurality of unit pixels 120. For example, different red filters R and blue filters B may be alternately formed for each of the three unit pixels 120 as shown in FIG. 44.

The microlens 157 'of the microlens layer 156' may be formed at a corresponding position for each of the plurality of unit pixels 120, respectively.

When the pixel array 110 is formed as illustrated in FIG. 44, as described in FIG. 3B, each unit pixel 120 may be treated as one subpixel. Therefore, the unit pixels 120 of the group corresponding to the same color filter 155 ′ may function as one pixel. For example, in FIG. 44, three unit pixels 120 corresponding to the red filter R are one red pixel, and the other three unit pixels 120 corresponding to the blue filter B are one blue pixel. Can be treated as. 44 illustrates a case in which three unit pixels 120 are treated as one pixel, but the scope of the present invention is not limited thereto.

The present invention can also be embodied as computer-readable codes on a computer-readable recording medium. A computer-readable recording medium includes all kinds of recording apparatuses in which data that can be read by a computer system is stored.

Examples of the computer-readable recording medium include a ROM, a RAM, a flash memory, a CD-ROM, a magnetic tape, a floppy disk, an optical data storage device, and the like. May be transmitted in the form of a carrier wave (e.g., transmission over the Internet).

The computer readable recording medium may also be distributed over a networked computer system so that computer readable code can be stored and executed in a distributed manner. And functional programs, codes, and code segments for implementing the present invention can be easily inferred by programmers skilled in the art to which the present invention pertains.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Therefore, the true technical protection scope of the present invention will be defined by the technical spirit of the appended claims.

Image Processing System (10)
Image sensor (100)
Pixel array 110
Unit pixels (120)
Row driver block (160)
Control register block 180
Lead Out Block 190
Image Signal Processor (220)

Claims (20)

Accumulating photo charge in a photodiode connected to the body of a single transistor;
Outputting a pixel signal according to the accumulated photocharge and a read voltage applied to a gate of the single transistor; And
Removing the photo charge accumulated in the photodiode,
And the pixel signal is a digital signal having two or more levels based on the accumulated optical charges. The method of claim 1,
An upper surface of the photodiode is lower than an upper surface of the source and the drain of the single transistor,
The photodiode is formed closer to the drain than the source,
And the photodiode is a virtual photodiode by a back-gate voltage supplied to a back-gate. The method of claim 1,
And a source and a drain of the single transistor are connected by a channel. The method of claim 1,
Accumulating the photocharges
And applying a high voltage to at least one of a gate, a source, and a drain of the single transistor to induce photocharge amplification by an avalanche effect. The method of claim 1,
The read voltage is determined according to a threshold voltage of the single transistor,
And the pixel signal is a digital signal having at least two levels. The method of claim 1,
And processing the pixel signal to generate image data. The method according to claim 6,
Generating the image data
Grouping each subpixel that outputs the pixel signal; And
And processing the pixel signals output by the grouped subpixels to generate the image data. A pixel array comprising a plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor;
A row driver block for entering any one of a plurality of rows of the pixel array into a read out mode; And
And a readout block for detecting and amplifying each pixel signal output from a plurality of unit pixels included in a row entering the readout mode.
The row driver block enters the readout mode by controlling source and gate voltages of the single transistors included in any one of a plurality of rows of the pixel array.
The plurality of unit pixels may further include a back-gate receiving a back-gate voltage from the row driver block,
And the photodiode is a virtual photodiode by the back-gate voltage. 9. The method of claim 8,
The row driver block controls the source voltage and the gate voltage of the single transistors to enter the plurality of unit pixels into the photocharge accumulation mode and the reset mode,
The photocharge accumulation mode is a mode in which the photodiode accumulates photocharges varying according to the intensity of incident light,
And the reset mode is a mode for removing the accumulated photocharges. 9. The method of claim 8,
An upper surface of the photodiode is lower than an upper surface of the source and the drain of the single transistor,
And the photodiode is formed closer to the drain than the source. delete 9. The method of claim 8,
The plurality of unit pixels further include a channel connecting a source and a drain of the single transistor,
The channel has at least one side in contact with the photodiode,
The channel is formed of silicon (Si), germanium (Ge) or silicon-germanium (SiGe). The method of claim 12,
The plurality of unit pixels further include an internal photodiode formed between the channel and the photodiode,
The internal photodiode is formed of germanium (Ge) or silicon-germanium (SiGe). 9. The method of claim 8,
The pixel array shares a source or a drain between the single transistors adjacent in the column direction,
And the pixel array further comprises an STI formed between the single transistors adjacent in a row direction. 9. The method of claim 8,
And the pixel array further comprises an STI formed between the single transistors adjacent in the column direction. 9. The method of claim 8,
And the pixel array further comprises an STI formed between the single transistors adjacent in a row direction. 9. The method of claim 8,
And the single transistor has a gate formed closer to the source than the drain. 9. The method of claim 8,
Each of the plurality of unit pixels further includes a reset terminal for removing photocharges accumulated in the photodiode. A plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, amplifying and outputting a digital pixel signal of the plurality of unit pixels, wherein the photodiode accumulates an optical charge An image sensor, wherein the voltage of the body changes based on the optical charge, and the digital pixel signal is determined based on the voltage of the body; And
And an image signal processor for processing the amplified digital pixel signal to generate image data. A plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, amplifying and outputting a digital pixel signal of the plurality of unit pixels, wherein the photodiode accumulates an optical charge An image sensor, wherein the voltage of the body changes based on the optical charge, and the digital pixel signal is determined based on the voltage of the body;
A processor configured to process the amplified digital pixel signal to generate image data and to control an operation of the image sensor;
A memory storing a program for controlling the image data and the operation of the image sensor; And
And a display unit for displaying the image data transmitted from the processor or the memory.

Images