KR101997831B1 - DC-DC Converter - Google Patents

Abstract

Disclosed is a DC-DC converter which can reduce an error of a comparator. According to an embodiment of the present invention, the DC-DC converter comprises: a switch unit including a switch outputting DC input voltage into switching voltage; an LC filter outputting DC output voltage which is converted from the switching voltage to a load; a clerk generator generating a clerk signal of a first frequency; a chopping wave generator generating a chopping wave of a second frequency which is greater than a switching frequency; a compensator outputting error voltage between the DC output voltage and a reference voltage; a comparator generating a reset signal by comparing the error voltage and the chopping wave; and an SR latch outputting a switching pulse signal for controlling the switch in accordance with the switching frequency by using the clerk signal and the latch signal.

Description

A DC-DC converter (DC-DC converter)

An embodiment of the present invention relates to a DC-DC converter, and more particularly, to a DC-DC converter capable of reducing the operation error of a comparator to provide a stable output voltage.

Generally, a DC-DC converter corresponds to a power converter that receives a DC input voltage (V _IN ) and outputs a DC output voltage (V _OUT ). The DC-DC converter is called a switch-mode power supply and is simply called a DC-DC converter because it uses a switching of PMOS and NMOS transistors to deliver a stable DC output voltage regardless of changes in input voltage or load current.

It is an object of the present invention to provide a DC-DC converter for reducing the error of a comparator which can reduce the operation error of the comparator and thereby provide a stable output voltage.

A DC-DC converter according to an embodiment of the present invention includes: a switch unit including a switch for outputting a DC input voltage as a switching voltage; An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load; A clock generator for generating a clock signal of a first frequency; A triangle wave generator for generating a triangle wave of a second frequency greater than the switching frequency; A corrector for outputting an error voltage between the DC output voltage and a reference voltage; A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And an SR latch for outputting a switching pulse signal for controlling the switch in accordance with the switching frequency using the clock signal and the reset signal.

The first frequency may be the same as the switching frequency.

Wherein the DC-DC converter further comprises: a voltage detector for detecting the error voltage and outputting a frequency control signal when the error voltage is lower than a threshold voltage, wherein the triangle wave generator generates, 2 frequency in the first mode in which the frequency is equal to the switching frequency and in the second mode in which the second frequency is larger than the switching frequency.

The DC-DC converter further includes a frequency divider that divides a first frequency of the clock signal to generate a second clock signal having a third frequency smaller than the first frequency, And output the switching pulse signal using the reset signal.

The third frequency may be the same as the switching frequency.

The DC-DC converter further includes an error voltage detector for detecting the error voltage and outputting a frequency control signal when the error voltage is lower than a threshold voltage, A clock signal of the first frequency may be input from the generator, and a second clock signal of the third frequency may be generated.

A DC-DC converter according to an embodiment of the present invention includes: a switch unit including a switch for outputting a DC input voltage as a switching voltage; An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load; A clock generator for generating a clock signal of a first frequency equal to the switching frequency; A triangle wave generator for generating a triangle wave of a second frequency which is n times the first frequency; A corrector for outputting an error voltage between the DC output voltage and a reference voltage; A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And an SR latch for outputting a switching pulse signal for controlling the switch in accordance with the switching frequency using the clock signal and the reset signal.

A DC-DC converter according to an embodiment of the present invention includes: a switch unit including a switch for outputting a DC input voltage as a switching voltage; An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load; A clock generator for generating a first clock signal of a first frequency; A frequency divider for generating a second clock signal of a third frequency obtained by dividing the first frequency by 1 / n; A triangle wave generator for generating a triangle wave having a second frequency equal to the first frequency; A corrector for outputting an error voltage between the DC output voltage and a reference voltage; A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And an SR latch for outputting a switching pulse signal for controlling the switch using the second clock signal and the reset signal according to the same switching frequency as the third frequency.

According to the DC-DC converter of the present invention, since the operation error of the comparator is reduced to generate a regular and stable switching waveform, the switching operation can be performed at a constant frequency, thereby providing a stable DC output voltage. So that the influence of electromagnetic waves can be reduced.

1 and 2 are schematic views of a DC-DC converter according to an embodiment of the present invention.
FIGS. 3 and 4 are time-dependent waveforms of respective signals of the DC-DC converter shown in FIGS. 1 and 2. FIG.
5 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention.
6 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.
7 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention.
8 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.
9 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention.
10 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those skilled in the art can easily carry out the present invention.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "electrically connected" with another part in between . Also, when a part is referred to as "including " an element, it does not exclude other elements unless specifically stated otherwise.

1 and 2 are schematic views of a DC-DC converter according to an embodiment of the present invention. FIGS. 3 and 4 are time-dependent waveforms of respective signals of the DC-DC converter shown in FIGS. 1 and 2. FIG.

1 and 2, a DC-DC converter 100 according to an embodiment of the present invention includes a switch 110, LC filters L and C, a clock generator 120, a triangle wave generator 130, A corrector 140, a comparator 150, an SR latch 160, and a gate driver 170. The DC-DC converter according to an embodiment of the present invention may be a buck converter.

The switch unit 110 may include at least one switch for performing a switching operation for controlling the output of the DC input voltage V _IN . For convenience of description, the transistor is exemplified by a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The switch unit 110 may include a first switch 112 implemented as a PMOS transistor and a second switch 114 implemented as an NMOS transistor.

The first terminal of the first switch 112 may be connected to the DC input voltage V _IN and the second terminal may be connected to the first terminal of the second switch 114 to form a contact. The first terminal of the second switch 114 may be connected to the first terminal of the first switch 112 and the second terminal may receive the ground voltage GND. The first terminal and the second terminal may denote a drain terminal and a source terminal, respectively.

Gate terminals of the first switch 112 and the second switch 114 may receive a gate control signal from the gate driver 170, respectively. The gate control signal may be a signal corresponding to the switching pulse signal SW. The ON or OFF operation of the first switch 112 and the second switch 114 can be controlled according to the gate control signal. The frequency at which the first switch 112 changes from on to off or from off to on may be a switching frequency (f _SW ). The first switch 112 is turned on or off in accordance with the gate control signal and the gate driver 170 outputs the gate control signal using the switching pulse signal SW so that the frequency of the switching pulse signal SW becomes the switching frequency .

The second switch 114 may be in the on state while the first switch 112 is in the on state and the second switch 114 may be in the on state while the first switch 112 is in the off state. The switch unit 110 may switch the DC input voltage V _IN according to the gate control signal and output the switching voltage V _X through the contact between the two transistors.

The LC filter may include an inductor L and a capacitor C. LC filter can supply converts the switching voltage (V _X) output from the switch unit 110, a stable DC voltage load DC output voltage (V _OUT) to (R _L).

The clock generator 120 may generate the clock signal SET of the first frequency f1. The first frequency f1 may be equal to the switching frequency _fsw . The clock generator 120 may output the clock signal SET to the S terminal of the SR latch 160. The clock signal SET may be an impulse-like waveform that occurs at a period of 1 / f _SW .

The triangle wave generator 130 generates a triangle wave V _SAW of the second frequency f2 and outputs the triangle wave V _SAW to the non-inverting terminal (+ terminal) of the comparator 150. A second frequency (f2) may be more than the switching frequency (f _SW) frequency. For example, the triangle wave generator 130 can generate a triangle wave V _SAW of a second frequency (f2 = nf _SW ) having n times (n is an integer of 1 or more) of the switching frequency f _SW . If n = 5, the second frequency may be 5f _SW .

The compensator 140 may perform a voltage comparison between the DC output voltage and the reference voltage and output an error voltage V _ERR based on the voltage comparison result. The compensator 140 may include an error amplifier 142 and a voltage divider circuit 144, as shown in FIG. The error amplifier 142 receives the feedback voltage V _FB which is the divided voltage of the voltage dividing circuit 144 and the reference voltage V _REF to the non-inverting terminal (+ terminal) have. 2, the embodiment of the present invention is not limited to this, and the voltage dividing circuit may generate a feedback voltage that is input to the inverting terminal of the error amplifier 142 based on the DC output voltage Or the like.

The comparator 150 receives the error voltage V _ERR and the triangular wave V _SAW through the (-) terminal and the (+) terminal, compares the voltage levels of the error voltage V _ERR and the triangular wave V _SAW Thereby generating a reset signal RST. The comparator 150 outputs a high level when the voltage level of the triangular wave V _SAW is equal to or higher than the error voltage V _ERR (V _SAW ≥V _ERR ), and when the voltage level of the triangular wave V _SAW exceeds the error voltage The reset signal RST can be generated in such a manner that a low level is output when the output voltage _VTH is less than (V _ERR ) (V _SAW <V _ERR ). The comparator 150 may output the reset signal RST to the R terminal of the SR latch 160. [

The SR latch 160 generates the switching pulse signal SW using the clock signal SET and the reset signal RST respectively input to the S terminal and the R terminal and outputs the switching pulse signal SW through the Q terminal Real-time output is possible. The switching pulse signal SW output from the SR latch 160 may be a PWM signal. The switching pulse signal SW can be used to control the on / off switching operation of the first switch 112 and the second switch 114 included in the switch unit 110. [

The gate driver 170 drives the gates of the first switch 112 and the second switch 114 using the switching pulse signal SW output from the SR latch 160. [ The gate driver 170 may be individually connected corresponding to each transistor. Since the gate driver 170 is commonly used in a DC-DC converter, a detailed description thereof will be omitted.

Hereinafter, the operation of the DC-DC converter 100 will be described with reference to FIGS. FIG. 3 and FIG. 4 are waveform diagrams for respective signals in FIG. 1 and FIG. 2 according to an embodiment of the present invention. 3 shows a case where the second frequency f2 of the triangular wave V _SAW generated by the triangle wave generator 130 is equal to the switching frequency f _SW (when n = 1). 4 shows a case where the frequency f2 of the triangular wave V _SAW generated by the triangular wave generator 130 is larger than the switching frequency f _SW (when n = 2 or more).

The error voltage V _ERR output from the corrector 140 of the DC-DC converter 100 according to the embodiment of the present invention can be expressed by Equation (1).

... (1)

... (One)

In the equation 1, V _PEAK is the peak voltage of the triangular wave V _SAW , L is the inductance value of the inductor, f _SW is the switching frequency, I _LOAD is the current of the load (I ₀ ), V _IN and V _OUT are the DC input voltage And a DC output voltage, and n represents a multiple of the switching frequency f _SW of the second frequency f2 of the triangular wave V _SAW .

Referring to Equation 1, the error voltage V _ERR can be determined according to the relationship between the switching frequency f _SW and the triangular wave V _SAW frequency. The error voltage V _ERR may be proportional to the peak voltage of the triangular wave V _SAW . For example, the error voltage V _ERR may be n times the peak voltage of the triangular wave V _SAW .

Referring to FIG. 3, the triangle wave generator 130 may generate a triangle wave V _{SAW at} a second frequency f 2 = f _SW equal to the switching frequency f _SW . That is, the triangle wave generator 130 can generate one triangle wave V _SAW every switching cycle (T = 1 / f _SW ). Clock generator 120 may generate a clock signal (SET) equal to the first frequency (f1 = f _SW), the switching frequency (f _SW). That is, the clock generator 120 may generate one clock signal (SET) at every switching cycle (T). The comparator 150 may generate the reset signal RST by comparing the voltage level of the triangular wave V _SAW with the error voltage V _ERR . The SR latch 160 can generate the switching pulse signal SW in accordance with the combination of the clock signal SET and the reset signal RST.

If the load current I _LOAD is lowered, the error voltage V _ERR can also be lowered. 3, when the error voltage V _ERR is lowered as the load current I _LOAD is lowered, the comparator 150 outputs the error voltage V _ERR to the comparator 150 from the time t1 when the error voltage V _ERR becomes lower than the threshold value The difference between the triangular wave V _SAW and the error voltage V _ERR becomes smaller and the operation error of the comparator 150 becomes larger. As a result, the reset signal RST output from the comparator 150 becomes unstable, and the switching pulse signal SW output from the SR latch 160 irregularly occurs. As a result, the ON / OFF operation of the first switch 112 of the switch unit 110 becomes unstable, and the switching frequency f _SW fluctuates with time. Irregular fluctuations in the switching frequency (f _SW ) can destabilize the output voltage of the DC-DC converter and degrade EMI characteristics.

4, when the error voltage V _ERR is lower than the predetermined threshold value, the second frequency f2 of the triangular wave V _SAW is lower than the switching frequency f _SW And can be set to a large frequency (for example, more than twice the switching frequency).

Referring to FIG. 4, the triangle wave generator 130 may generate a triangle wave V _{SAW at} a frequency greater than the switching frequency f _SW , for example, 5f _SW . That is, the triangle wave generator 130 can generate five triangular waves (V _SAW ) every switching period (T). The clock generator 120 may generate the clock signal SET at the same frequency as the switching frequency f _SW . That is, the clock generator 120 may generate one clock signal (SET) at every switching cycle (T). The comparator 150 may generate the reset signal RST by comparing the voltage level of the triangular wave V _SAW with the error voltage V _ERR . The SR latch 160 can generate the switching pulse signal SW in accordance with the combination of the clock signal SET and the reset signal RST.

4, where n = 5, the peak voltage V _PEAK of the triangular wave V _SAW is increased by five times, and the error voltage V _ERR is lower than that of the embodiment of FIG. It can also be seen that it can be increased 5 times.

When the clock signal SET is high, a high signal is inputted to the S terminal of the SR latch 160 and a high level is outputted through the Q terminal. The clock signal SET is kept in the low state until the impulse of the next cycle is generated while the impulse is generated in a very short moment and the low signal is inputted to the S terminal of the R latch 160 during the period. In this state, when the reset signal RST goes high and a high signal is inputted to the R terminal of the SR latch 160, a low level is outputted through the Q terminal and thereafter the Low and High signals are repeated to the R terminal The Q terminal remains at the low level even if it enters. Thereafter, an impulse of the next period is generated in the clock signal SET, and when a high signal is again input to the S terminal, the high level is outputted again through the Q terminal. Accordingly, as shown in FIG. 4, the error voltage V _ERR lower than the threshold value is raised by a multiple of the triangular wave V _SAW frequency with respect to the switching frequency f _SW , and the DC-DC converter 100 The switching pulse signal SW having a constant frequency can be generated.

4, the frequency of the triangular wave V _SAW is increased by n (where n is 2 or more) times the switching frequency f _SW , so that n By inputting the multiple triangular wave into the comparator 150, the error voltage V _ERR of the DC-DC converter 100 can be increased n times.

4 can thus increase the error voltage V _ERR applied to the comparator 150 over the embodiment shown in FIG. 3, which allows the two input signals &lt; RTI ID = 0.0 &gt; The difference between the voltage level of the triangular wave V _SAW and the error voltage V _ERR can be made larger than that of the prior art and the output error of the comparator 150 can be reduced.

The embodiment of the present invention can reduce the error of the comparator 150 only by changing the frequency or period of the triangular wave V _SAW without changing the design of the comparator 150.

5 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention. 6 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.

5, a DC-DC converter 200 according to an embodiment of the present invention includes a switch unit 210, LC filters L and C, a clock generator 220, a triangle wave generator 230, a corrector 240 A comparator 250, an SR latch 260, a gate driver 270, and a voltage detector 290. The DC-DC converter 200 of the embodiment shown in FIG. 5 differs from the DC-DC converter 100 of the embodiment shown in FIGS. 1 and 2 in that it further includes a voltage detector 290. Hereinafter, different configurations from those of the embodiment shown in FIG. 1 and FIG. 2 will be mainly described, and detailed description of the same configuration will be omitted.

The switch unit 210 performs a switching operation to control the output of the DC input voltage V _{IN and} includes a first switch 212 implemented as a PMOS transistor and a second switch 214 implemented as an NMOS transistor . The switch unit 210 may switch the DC input voltage V _IN according to the gate control signal and output the switching voltage V _X through the contact between the two transistors.

The LC filter may include an inductor L and a capacitor C. LC filter can supply converts the switching voltage (V _X) output from the switching unit 210 at a stable DC voltage load DC output voltage (V _OUT) to (R _L).

The clock generator 20 can generate and output the clock signal SET of the first frequency f1 to the S terminal of the SR latch 260. [ The first frequency f1 may be equal to the switching frequency _fsw .

The triangle wave generator 230 generates a triangle wave V _SAW of the second frequency f2 and outputs it to the non-inverting terminal (+ terminal) of the comparator 250. A second frequency (f2) may be more than the switching frequency (f _SW) frequency. For example, the triangle wave generator 230 may generate a triangle wave V _SAW of a second frequency (n _SW ) having n times the switching frequency (where n is an integer equal to or greater than 1).

The compensator 240 performs a voltage comparison between the DC output voltage and the reference voltage, and can output the error voltage V _ERR based on the result of the voltage comparison. The compensator 240 may include an error amplifier 142 and a voltage divider circuit 144, as shown in FIG.

The comparator 250 receives the error voltage V _ERR and the triangular wave V _SAW through the (-) terminal and the (+) terminal, respectively, and compares the voltage levels of the error voltage V _ERR and the triangular wave V _SAW Thereby generating a reset signal RST.

The SR latch 260 generates the switching pulse signal SW using the clock signal SET and the reset signal RST respectively input to the S terminal and the R terminal and outputs the switching pulse signal SW through the Q terminal Real-time output is possible.

The gate driver 270 drives the gates of the first switch 212 and the second switch 214 by using the switching pulse signal SW output from the SR latch 260.

The voltage detector 290 can detect the error voltage V _ERR output by the corrector 240. The voltage detector 290 may include a comparator that compares the error voltage V _ERR with a threshold voltage V _TH . The voltage detector 290 can output the frequency control signal FC which changes the triangle wave frequency to the triangle wave generator 230 when the error voltage V _ERR is equal to or less than the threshold voltage V _TH . Accordingly, the DC-DC converter 200 can change the operation mode from the first mode to the second mode.

In the first mode, the frequency of the triangular wave V _SAW input to the non-inverting terminal of the comparator 250 may be the same as the switching frequency f _SW . The second mode is a mode in which the frequency of the triangular wave V _SAW input to the non-inverting terminal of the comparator 250 is higher than the switching frequency f _SW , for example, nf _SW (n is 2 or more) .

The triangle wave generator 230 can generate the triangle wave V _{SAW at the} frequency set in the second mode when the frequency control signal FC is input.

6, the triangle wave generator 230 generates a triangle wave V _{SAW at the} same frequency as the switching frequency f _SW in accordance with the first mode, and the voltage detector 290 generates the triangle wave V _SAW in real time or periodically, an error voltage (V _ERR) to the output can be compared to the threshold voltage (V _TH). The voltage detector 290 can output the frequency control signal FC to the triangle wave generator 230 when it is detected that the error voltage V _ERR is equal to or less than the threshold voltage V _TH at time t1. The triangle wave generator 230 receiving the frequency control signal FC from the voltage detector 290 can generate the triangle wave V _{SAW at a} frequency greater than the switching frequency f _SW in accordance with the second mode from the time t2 have. In the first mode and the second mode, the switching frequency f _SW is the same. According to the feedback operation of the DC-DC converter 200, the error voltage V _ERR gradually increases during the transients t2 to t3, increases from the time t3 to a constant value, and can be output from the corrector 240.

7 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention. 8 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.

Referring to FIG. 7, a DC-DC converter 300 according to an embodiment of the present invention includes a switch unit 310, LC filters L and C, a clock generator 320, a triangle wave generator 330, 340, a comparator 350, an SR latch 360, a gate driver 370, and a frequency divider 380.

The DC-DC converter 300 of the embodiment shown in FIG. 7 differs from the DC-DC converter 100 of the embodiment shown in FIGS. 1 and 2 in that it further includes a frequency divider 380. Hereinafter, different configurations from those of the embodiment shown in FIG. 1 and FIG. 2 will be mainly described, and detailed description of the same configuration will be omitted.

The switch unit 310 performs a switching operation to control the output of the DC input voltage V _{IN and} includes a first switch 312 implemented as a PMOS transistor and a second switch 314 implemented as an NMOS transistor . The switch unit 310 may switch the DC input voltage V _IN according to the gate control signal and output the switching voltage V _X through the contact between the two transistors.

The LC filter may include an inductor L and a capacitor C. LC filter can supply converts the switching voltage (V _X) output from the switching unit 210 at a stable DC voltage load DC output voltage (V _OUT) to (R _L).

The clock generator 320 may generate the first clock signal SET of the first frequency f1.

The frequency divider 380 may be provided between the clock generator 320 and the SR latch 360. The frequency divider 380 divides the first frequency f1 of the first clock signal SET generated by the clock generator 320 by a third frequency f3 obtained by dividing the first frequency f1 by 1 / n = f1 / n) and outputs the second clock signal SET 'to the S terminal of the SR latch 360.

The triangle wave generator 330 generates a triangle wave V _SAW of the second frequency f2 and outputs it to the non-inverting terminal (+ terminal) of the comparator 350. The second frequency f2 may be equal to the first frequency f1 of the clock generator 320. [

The compensator 340 may perform a voltage comparison between the DC output voltage and the reference voltage and output an error voltage V _ERR based on the result of the voltage comparison. The corrector 340 may include an error amplifier 142 and a voltage divider circuit 144, as shown in FIG.

The comparator 350 receives the error voltage V _ERR and the triangular wave V _SAW through the (-) terminal and the (+) terminal and compares the voltage levels of the error voltage V _ERR and the triangular wave V _SAW Thereby generating a reset signal RST.

The SR latch 360 generates the switching pulse signal SW using the second clock signal SET 'and the reset signal RST respectively input to the S terminal and the R terminal, and outputs the switching pulse signal SW) can be output in real time. The frequency of the switching pulse signal _SW is equal to the switching frequency f _SW .

The gate driver 370 drives the gates of the first switch 312 and the second switch 314 using the switching pulse signal SW output from the SR latch 360. [

In an embodiment of the present invention, since the third frequency f1 / n is smaller than the first frequency f1, the second clock signal SET 'may have a longer period than the first clock signal SET. If n = 3, the second clock signal SET 'may have a period three times longer than the first clock signal SET. In this case, the frequency of the switching pulse signal SW produced by the SR latch 360, that is, the switching frequency f _SW becomes f _SW = f 1 / n, which is slowed by a multiple of the frequency divider 'n' (T = 1 / f _SW ), n multiple triangular waveforms can occur. Thus, the second frequency f2 of the triangular wave V _SAW may be n times the switching frequency f _SW (where n is an integer greater than or equal to 2).

The error voltage V _ERR output from the corrector 340 of the DC-DC converter 300 according to the embodiment of the present invention can be expressed by Equation (2).

... (2)

... (2)

In the equation 2, V _PEAK is the peak voltage of the triangular wave V _SAW , L is the inductance value of the inductor, f _SW is the switching frequency, I _LOAD is the current of the load (I ₀ ), V _IN and V _OUT are the DC input voltage And the DC output voltage n represents a frequency division factor of the frequency divider 380 or a multiple of the switching frequency f _SW of the second frequency f2 of the triangular wave V _SAW .

Referring to Equation 2, the error voltage V _ERR may be determined according to the frequency division factor of the frequency divider 380 or the relationship between the switching frequency f _SW and the triangular wave V _SAW frequency. The error voltage V _ERR may be proportional to the peak voltage of the triangular wave V _SAW . For example, the error voltage (V _ERR ) may be √ n times the peak voltage of the triangular wave (V _SAW ).

8, the clock generator 320 generates a clock signal SET at a first frequency f1 and the triangle wave generator 330 generates a triangle wave V _SAW at a second frequency f2. have. The first frequency f1 of the clock generator 320 and the second frequency f2 of the triangle wave generator 330 may be the same frequency. The frequency divider 380 divides the first frequency f1 of the first clock signal SET generated by the clock generator 320 by a second frequency f3 = f1 / n, which is obtained by dividing the first frequency f1 by 1 / Signal &lt; RTI ID = 0.0 &gt; SET '. &Lt; / RTI &gt; The comparator 150 may generate the reset signal RST by comparing the voltage level of the triangular wave V _SAW with the error voltage V _ERR . The SR latch 160 can generate the switching pulse signal SW according to the combination of the second clock signal SET 'and the reset signal RST. In the embodiment of FIG. 7, the principle of generation of RST according to the comparison of V _SAW and V _ERR and the principle of generation of SW using RST and SET 'refer to those previously described in the embodiment of FIG.

Fig. 8 illustrates the case where n = 3. The second clock signal SET 'has a period that is three times higher than the period of the first clock signal SET by the frequency divider 380 and is the same as that of the first clock signal SET generated by the clock generator 320 And has a third frequency f3 that is 1/3 times smaller than the first frequency f1.

The frequency of the switching pulse signal SW is the switching frequency f _SW , which is the same as the third frequency f3 of the second clock signal SET '. The triangular wave V _SAW has a second frequency f2 which is three times larger than the third frequency f3 of the second clock signal SET 'and accordingly the switching pulse signal SW generated by the SR latch 260, It can be seen that three triangular waves (V _SAW ) are generated every one switching cycle (T = 1 / f _SW ).

From the equation (2), the embodiment of FIG. 8 with n = 3 shows that the peak voltage V _PEAK of the triangular wave V _SAW is increased by 3 times and the error voltage V _ERR ) Can also be increased to √3 times.

8, the frequency of the triangular wave V _SAW is increased by n (where n is 2 or more) times the switching frequency f _SW , so that n By inputting the multiple triangular wave into the comparator 350, the error voltage V _ERR of the DC-DC converter 300 can be increased by n times.

8 can thus increase the error voltage V _ERR applied to the comparator 350 over the embodiment shown in FIG. 3, by which the two input signals &lt; RTI ID = 0.0 &gt; The difference between the voltage level of the triangular wave V _SAW and the error voltage V _ERR can be increased compared with the conventional case and the output error of the comparator 350 can be reduced.

An embodiment of the present invention can reduce the output error of the comparator 350 only by changing the frequency or period of the clock signal SET without changing the design of the comparator 350. [

9 is a diagram illustrating a configuration of a DC-DC converter according to another embodiment of the present invention. 10 is a time-dependent waveform of each signal of the DC-DC converter shown in FIG.

Referring to FIG. 9, a DC-DC converter 400 according to an embodiment of the present invention includes a switch 410, LC filters L and C, a clock generator 420, a triangle wave generator 430, 440, a comparator 450, an SR latch 460, a gate driver 470, a frequency divider 480, and a voltage detector 490.

The DC-DC converter 400 of the embodiment shown in FIG. 9 differs from the DC-DC converter 300 of the embodiment shown in FIG. 7 in that it further includes a voltage detector 490. Hereinafter, a configuration different from the embodiment shown in FIG. 7 will be mainly described, and a detailed description of the same configuration will be omitted.

The switch unit 410 performs a switching operation to control the output of the DC input voltage V _{IN and} includes a first switch 412 implemented as a PMOS transistor and a second switch 414 implemented as an NMOS transistor . The switch unit 410 may switch the DC input voltage V _IN according to the gate control signal and output the switching voltage V _X through the contact between the two transistors.

The LC filter may include an inductor L and a capacitor C. LC filter can supply converts the switching voltage (V _X) from the output switch unit 410 as a stable DC voltage load DC output voltage (V _OUT) to (R _L).

The clock generator 420 may generate the first clock signal SET of the first frequency f1. The clock generator 420 may output the first clock signal SET at the first frequency f1 to the S terminal of the SR latch 460 in one embodiment. In another embodiment, the clock generator 420 may output the first clock signal SET of the first frequency f1 to the frequency divider 480.

The frequency divider 480 divides the first frequency f1 of the first clock signal SET generated by the clock generator 420 into a third frequency f3 by dividing the first frequency f1 by 1 / n = f1 / n) and outputs the second clock signal SET 'to the S terminal of the SR latch 460.

The triangle wave generator 430 generates the triangle wave V _SAW of the second frequency f2 and outputs it to the non-inverting terminal (+ terminal) of the comparator 450. The second frequency f2 may be the same as the first frequency f1 of the clock generator 420.

The compensator 440 (Compensator) performs a voltage comparison between the DC output voltage and the reference voltage, and can output an error voltage (V _ERR ) based on the result of the voltage comparison. The compensator 440 may include an error amplifier 242 and a voltage divider circuit 244, as shown in FIG.

The comparator 450 receives the error voltage V _ERR and the triangular wave V _SAW through the (-) terminal and the (+) terminal, respectively, and compares the voltage levels of the error voltage V _ERR and the triangular wave V _SAW Thereby generating a reset signal RST.

The SR latch 460 generates the switching pulse signal SW using the clock signal SET and the reset signal RST input to the S terminal and the R terminal respectively and outputs the switching pulse signal SW through the Q terminal Real-time output is possible. In one embodiment, the SR latch 460 generates the switching pulse signal SW using the first clock signal SET and the reset signal RST and outputs the switching pulse signal SW through the Q terminal to the real- can do. In another embodiment, the SR latch 460 generates the switching pulse signal SW using the second clock signal SET 'and the reset signal RST, and outputs the switching pulse signal SW in real time Can be output.

The gate driver 470 drives the gates of the first switch 412 and the second switch 414 using the switching pulse signal SW output from the SR latch 460.

The voltage detector 490 can detect the error voltage V _ERR output by the corrector 440. The voltage detector 490 may include a comparator that compares the error voltage V _ERR with a threshold voltage V _TH . The voltage detector 490 outputs a frequency control signal FC that changes the clock frequency to the clock generator 420 and / or the frequency divider 480 when the error voltage V _ERR is less than or equal to the threshold voltage V _TH can do. Accordingly, the DC-DC converter 400 can change the operation mode from the first mode to the second mode.

The first mode may be a mode in which the clock signal input to the S terminal of the SR latch 460 is the first clock signal SET of the first frequency f1. The second mode may be a mode in which the clock signal input to the S terminal of the SR latch 460 is the second clock signal SET 'of the third frequency f3.

The frequency divider 480 is activated when the frequency control signal FC is input and the first frequency f1 of the first clock signal SET is 1 / n, where n is 2 The second clock signal SET 'of the third frequency f3 = f1 / n divided by the frequency of the second clock signal SET' and outputting it to the S terminal of the SR latch 460.

The clock generator 420 may output the first clock signal SET of the first frequency f1 to the frequency divider 480 when the frequency control signal FC is input.

Referring to FIG. 10, the voltage detector 290 may compare an error voltage V _ERR output by the corrector 440 with a threshold voltage V _TH in real time or periodically. The voltage detector 490 detects the frequency control signal FC in the clock generator 420 and / or the frequency divider 480 when the error voltage V _ERR is detected to be below the threshold voltage V _TH at time t1. Can be output. The clock generator 420 receiving the frequency control signal FC from the voltage detector 290 outputs the first clock signal SET of the first frequency f1 to the frequency divider 480 according to the second mode The frequency divider 480 divides the first frequency f1 of the first clock signal SET by 1 / n (where n is an integer of 2 or more) according to the second mode from time t2, The second clock signal SET 'having the frequency f3 = f1 / n can be generated. The second mode, the switching frequency (f _SW) in may be greater than n times the first mode, the switching frequency (f _SW) from. The error voltage V _ERR gradually increases during the transient period t2 to t4 according to the feedback operation of the DC-DC converter 400 and can be output from the corrector 440 at a constant value from the time t4.

As described above, the DC-DC converter according to the embodiments of the present invention generates a triangular wave at a frequency higher than the switching frequency and inputs the triangular wave to the comparator, thereby reducing the operation error of the comparator even when the error voltage is equal to or less than the threshold value, It is possible to generate a stable and stable switching waveform, thereby enabling a switching operation at a constant frequency, thereby providing a stable DC output voltage and improving EMI characteristics, thereby reducing the influence of electromagnetic waves.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (8)

delete A switch unit including a switch for outputting a DC input voltage as a switching voltage;
An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load;
A clock generator for generating a clock signal of a first frequency;
A triangle wave generator for generating a triangle wave of a second frequency greater than the switching frequency;
A corrector for outputting an error voltage between the DC output voltage and a reference voltage;
A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And
And an SR latch for outputting a switching pulse signal for controlling the switch according to the switching frequency using the clock signal and the reset signal,
Wherein the first frequency is equal to the switching frequency. 3. The method of claim 2,
And a voltage detector for detecting the error voltage and outputting a frequency control signal when the error voltage is lower than a threshold voltage,
Wherein the triangular wave generator is operated by the frequency control signal in a first mode in which the second frequency is the same as the switching frequency and in a second mode in which the second frequency is larger than the switching frequency. A switch unit including a switch for outputting a DC input voltage as a switching voltage;
An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load;
A clock generator for generating a clock signal of a first frequency;
A triangle wave generator for generating a triangle wave of a second frequency greater than the switching frequency;
A corrector for outputting an error voltage between the DC output voltage and a reference voltage;
A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And
And an SR latch for outputting a switching pulse signal for controlling the switch according to the switching frequency using the clock signal and the reset signal,
And a frequency divider dividing a first frequency of the clock signal to generate a second clock signal having a third frequency smaller than the first frequency,
And the SR latch outputs the switching pulse signal using the second clock signal and the reset signal. 5. The method of claim 4,
And the third frequency is equal to the switching frequency. 5. The method of claim 4,
And a voltage detector for detecting the error voltage and outputting a frequency control signal when the error voltage is lower than a threshold voltage,
Wherein the frequency divider receives the clock signal of the first frequency from the clock generator by the frequency control signal and generates a second clock signal of the third frequency. A switch unit including a switch for outputting a DC input voltage as a switching voltage;
An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load;
A clock generator for generating a clock signal of a first frequency equal to the switching frequency;
A triangular wave generator for generating a triangular wave of a second frequency which is n times (n is an integer of 2 or more) of the first frequency;
A corrector for outputting an error voltage between the DC output voltage and a reference voltage;
A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And
And a SR latch for outputting a switching pulse signal for controlling the switch in accordance with the switching frequency using the clock signal and the reset signal. A switch unit including a switch for outputting a DC input voltage as a switching voltage;
An LC filter for outputting a DC output voltage obtained by converting the switching voltage to a load;
A clock generator for generating a first clock signal of a first frequency;
A frequency divider for generating a second clock signal of a third frequency obtained by dividing the first frequency by 1 / n;
A triangle wave generator for generating a triangle wave having a second frequency equal to the first frequency;
A corrector for outputting an error voltage between the DC output voltage and a reference voltage;
A comparator for comparing the error voltage with the triangular wave to generate a reset signal; And
And a SR latch for outputting a switching pulse signal for controlling the switch according to a switching frequency same as the third frequency by using the second clock signal and the reset signal.

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