KR101995027B1 - Low Power Transmitter without Static Current Consumption - Google Patents

Abstract

The present invention relates to a low power transmitter without constant current consumption, and more particularly, to a low power transmitter that consumes only dynamic current and operates at low power and has no constant current consumption. A low-power transmitter without a constant current consumption of the present invention includes: an intermediate voltage unit providing at least one intermediate voltage having a magnitude smaller than a reference voltage; A driver for selecting the reference voltage or the intermediate voltage according to a combination of data sequences to be transmitted; And an output unit for outputting a voltage selected by the driving unit. .

Description

TECHNICAL FIELD [0001] The present invention relates to a low power transmitter without a constant current consumption,

The present invention relates to a low power transmitter without constant current consumption. More particularly, the present invention relates to a transmitter that operates at low power by removing the constant current consumption of a conventional finite filter wireline transmitter.

Recently, in order to process data of a portable electronic device including a smart phone using a battery, an increase in the data transfer rate of an internal chip such as an application processor is required, but the data transfer rate per pin is a problem due to a limited number of pins of the chip. Currently, ARM in the United Kingdom and INTEL in the US are constantly developing technology in response to the need for low-power, high-speed IO interfaces used in processors, and processor semiconductors are expected to be the largest in the semiconductor market.

In inter-chip communication, inter-chip communication is basically performed through a wired channel and transmits data by applying a voltage corresponding to data to be transmitted to an input / output pad electrically connected to a wired channel. Because the limited bandwidth between the input and output pads can cause inter-symbol interference and degrade the signal quality, the FIR driver is used to transmit data at high speed without degrading the signal quality. However, in the case of the conventional finite filter wired transmitter, additional power consumption due to the constant current has occurred.

Further, in the case of the conventional finite filter wired transmitter, the segment structure is used, and when the circuit is integrated, the complexity of the circuit is increased and a large area is occupied in the substrate.

Accordingly, there is a need to develop a technology of a transceiver that operates with low power and reduces battery consumption in chip-to-chip communication, and at the same time, it is required to develop a technique capable of high-speed data transmission while maintaining low interchannel interference (ISI).

Korean Registered Patent No. 10-0431651 (registered on May 05, 2004)

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a low power transmitter which consumes only a dynamic current and operates at a low power and has no constant current consumption. And more particularly, to a low-power transmitter that reduces the chip area and reduces the complexity of the circuit and has no constant current consumption. Also disclosed is a low power transceiver without constant current consumption.

In order to achieve the above object, the present invention provides a low-power transmitter having no constant current consumption, comprising: an intermediate voltage unit for providing at least two intermediate voltages having a magnitude smaller than a reference voltage; A driver for selecting at least one of the reference voltage, the intermediate voltage, and the ground voltage according to a combination of data sequences to be transmitted; And an output unit for outputting a voltage selected by the driving unit. .

In the present invention, the low power transmitter without the constant current consumption may include a tap signal generator receiving the data sequence to be transmitted and generating the tap signal by combining the applied data sequence according to a predetermined method; And the driving unit may select the at least one voltage in response to the generated tap signal.

Wherein the intermediate voltage includes a first intermediate voltage and a second intermediate voltage having different voltage magnitudes, and the driving unit controls ON / OFF of at least four transistors performing a switching function to control the reference voltage, the ground voltage , At least one of the first intermediate voltage and the second intermediate voltage can be selected.

The driving unit may select the at least one voltage through the at least four resistors connected at one end to the output unit and the at least one transistor connected in series to the other end of the resistor.

The transistor includes a PMOS transistor and an NMOS transistor, and the driving unit controls ON / OFF of the PMOS transistor and the NMOS transistor according to the combination of the data sequence to select the at least one voltage.

Wherein the tap signal generator receives a data sequence to be transmitted, serializes the applied data sequence at a predetermined data transmission rate, and outputs the first serial data sequence and the second serial data sequence; And generate the tap signal using the output first serial data sequence and the second serial data sequence.

Wherein the tap signal generator comprises: a delay unit delaying the first serial data sequence and the second serial data sequence by different time intervals; And generate the tap signal using the delayed first serial data sequence and the second serial data sequence.

 Wherein the tap signal generator comprises: a combining unit for combining the delayed first serial data sequence and the second serial data sequence according to the predetermined method; And generate the tap signal using the combined first serial data sequence and the second serial data sequence.

Wherein the intermediate voltage unit receives a predetermined 4-bit control signal and sets a tap weight for a magnitude of the first intermediate voltage and the second intermediate voltage to adjust a magnitude of the first intermediate voltage and the second intermediate voltage, ; And may provide the driving unit with a first intermediate voltage and a second intermediate voltage having the magnitude of the regulated voltage.

The intermediate voltage unit includes at least two operational amplifiers connected at one end to the power control unit, a transistor connected to the output terminal of the operational amplifier unit to perform a switching function, and a decoupling capacitor connected between the transistors, A low voltage bottom with a feedback resistor; And the noise of the first intermediate voltage and the second intermediate voltage of which the magnitude of the voltage is adjusted can be removed and provided to the driving unit.

Wherein the driver compares two bits of the data sequence to select one of the first intermediate voltage and the second intermediate voltage when the two bits are equal, One of the ground voltages can be selected.

The combination of the first serial data sequence and the second serial data sequence according to the predetermined method logically calculates the delayed first serial data sequence and the second serial data sequence according to the type of the transistor of the driving unit, Sequences may be muxed and combined.

Wherein the tap signal generator comprises: a timing controller for adjusting the timing of the combined first serial data sequence and the second serial data sequence; And generate the tap signal using the timing-adjusted first serial data sequence and the second serial data sequence.

Wherein the tap signal generator comprises: an inverter chain having a gradually increased strength for driving the driver; And generate the tap signal using the timing-adjusted first serial data sequence and the second serial data sequence that have passed through the chain of inverters.

The time interval is defined as a UI (Unit Interval) of the data sequence, the delay unit includes a first delay element for delaying the data sequence by 1 UI (Unit Interval), and a second delay element for delaying the data sequence by 0.5 UI And delaying the first serial data sequence and the second serial data sequence by the different time intervals using the first delay element and the second delay element.

According to another aspect of the present invention, there is provided a low-power transceiver having no constant current consumption, comprising: an intermediate voltage unit providing at least two intermediate voltages having a magnitude smaller than a reference voltage; A tap signal generating unit receiving a data sequence to be transmitted and combining the applied data sequence according to a predetermined method to generate a tap signal; A driver for selecting at least one of the reference voltage, the intermediate voltage, and the ground voltage in response to the generated tap signal; An output unit for outputting a voltage selected by the driving unit; And a receiving driver for receiving the selected voltage and for restoring the data sequence by determining a pattern of the received voltage; .

The intermediate voltage includes a first intermediate voltage and a second intermediate voltage having different voltage magnitudes and the driving unit includes at least four resistors connected to the output unit at one end and a switch function connected in series to the other end of the resistor The at least one of the reference voltage, the ground voltage, the first intermediate voltage, and the second intermediate voltage can be selected by controlling ON / OFF of at least four transistors to be performed.

Wherein the tap signal generator receives the data sequence, serializes the applied data sequence at a predetermined data transmission rate, and outputs the first serial data sequence and the second serial data sequence; A delay unit delaying the first serial data sequence and the second serial data sequence by different time intervals; And a combining unit for combining the delayed first serial data sequence and the second serial data sequence according to the predetermined method. And generate the tap signal using the combined first serial data sequence and the second serial data sequence.

The combination of the first serial data sequence and the second serial data sequence according to the predetermined method logically calculates the delayed first serial data sequence and the second serial data sequence according to the type of the transistor of the driving unit, Sequences can be muxed and combined.

Wherein the driver compares two bits of the data sequence to select one of the first intermediate voltage and the second intermediate voltage when the two bits are equal, One of the ground voltages can be selected.

Wherein the intermediate voltage unit receives a predetermined 4-bit control signal and sets a tap weight for a magnitude of the first intermediate voltage and the second intermediate voltage to adjust a magnitude of the first intermediate voltage and the second intermediate voltage, ; And at least two or more operational amplifiers receiving the first intermediate voltage and the second intermediate voltage whose voltages are adjusted in size, a transistor connected to the output terminal of the operational amplifier and performing a switching function, A low voltage drop bottom including a feedback resistor including a decoupling capacitor at both terminals; And the noise of the first intermediate voltage and the second intermediate voltage of which the magnitude of the voltage is adjusted can be removed and provided to the driving unit.

According to the present invention, a low-power transmitter without a constant current consumption consumes only a dynamic current and has the advantage of being able to operate at low power.

Particularly, since the constant current is not consumed, the heat generation is advantageously reduced.

1 is a block diagram of a low power transmitter without constant current consumption according to an embodiment of the present invention.
2 is an enlarged block diagram of the intermediate voltage portion in the embodiment of FIG.
3 is an enlarged block diagram of the tap signal generating unit in the embodiment of FIG.
4 is a block diagram of a low power transmitter without a constant current consumption including an enlarged block diagram of a tap signal generator according to an embodiment of the present invention.
5 is an exemplary diagram showing a waveform of an output signal of the delay unit in the embodiment of FIG.
6 is a conceptual diagram showing the operation principle of the driving unit in the embodiment of FIG.
FIG. 7 is a diagram illustrating the structure of a driving unit used in a conventional finite filter transmitter and a path of consumed constant current.
8 is a circuit diagram of a low power transmitter without a constant current consumption according to an embodiment of the present invention.
9 is a conceptual diagram of a transceiver including a low-power transmitter without constant current consumption.
10 shows an example of the waveform of the pre-emphasis signal measured at the output unit in the embodiment of FIG.
FIG. 11 shows an example of the waveform of the pre-emphasis signal measured at the receiving end when the driving unit is turned on / off in the embodiment of FIG. 1
12 shows an example of the waveform of the pre-emphasis signal measured according to the tap weight measured by the output unit of the present invention.
Figure 13 shows an example of an actual implementation layout of a low power transmitter without constant current consumption of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description with reference to the accompanying drawings, the same or corresponding components are denoted by the same reference numerals, and a duplicate description thereof will be omitted.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope. The singular expressions include plural expressions unless the context clearly dictates otherwise.

Each of the steps described below may be implemented by one or a plurality of software modules, or hardware that is responsible for each function, or a combination of software and hardware. Throughout the specification, when an element is referred to as "including" an element, it does not exclude other elements unless specifically stated to the contrary. The terms "part", "unit", "module", "block", and the like described in the specification mean units for processing at least one function or operation, And a combination of software. Specific meanings and examples of the terms will be described below in accordance with the order of each drawing. Hereinafter, a configuration of a low power transmitter without a constant current consumption according to an embodiment of the present invention will be described in detail with reference to the related drawings.

1 is a block diagram of a low power transmitter 10 without constant current consumption according to an embodiment of the present invention.

The low power transmitter 10 without constant current consumption includes an intermediate voltage unit 100, a tap signal generator 200, a driver 300, and an output unit 400.

The low power transmitter 10 without a constant current consumption is a transmitter of a structure that operates at low power by eliminating the consumption of a constant current of a conventional finite filter high speed wire transmitter. The low power transmitter 10 having no constant current consumption is located in a transmitting terminal that transmits data through chip-to-chip communication, and operates with low power while reducing inter-channel interference, so that the data sequence can be transmitted.

The low power transmitter 10 without constant current consumption can transmit a data sequence of NRZ (Non-Return to Zero) format, and the data sequence of the NRZ format is data of a form in which the signal level does not return to 0 after each bit, And is suitable for high-speed transmission compared to the data of the Return to Zero format. Will be described with reference to FIG.

The intermediate voltage section 100 includes a power regulation section 120 and a low voltage drop section 140.

The intermediate voltage section 100 provides at least one intermediate voltage having a magnitude less than the reference voltage. In the present invention, the reference voltage may be set to a driving voltage for driving a low-power transmitter without constant current consumption.

For example, the intermediate voltage section 100 may provide at least two or more intermediate voltages having a magnitude smaller than the reference voltage. In the present invention, the intermediate voltage may include a first intermediate voltage VH and a second intermediate voltage VL having a voltage magnitude between a reference voltage VDD and a ground voltage GND. The first intermediate voltage and the second intermediate voltage together with the reference voltage and the ground voltage constitute a voltage signal level output from the output section.

The power regulator 120 adjusts the magnitudes of the first intermediate voltage and the second intermediate voltage by setting a tap weight with respect to the magnitude of the first intermediate voltage and the second intermediate voltage by receiving a predetermined 4-bit control signal. For example, the first intermediate voltage VH may be expressed by a driving voltage * Ck, and the second intermediate voltage VL may be expressed by a driving voltage * (1-Ck). Here, Ck denotes a tap weight, and the tap weight serves as a constant for adjusting the magnitudes of the first intermediate voltage and the second intermediate voltage.

For example, the power regulator 120 may be implemented as a 4-bit binary R-DAC, and may be configured to have different voltage magnitudes for each node in accordance with the principle of voltage division in a resistance line connected in series to a reference voltage and a ground voltage. To the lower voltage lower portion 140 through a switch that is switched according to the 4-bit binary control signal to adjust the magnitudes of the first intermediate voltage and the second intermediate voltage applied to the driving portion 300.

The lower voltage lower part 140 includes at least two operational amplification parts connected to the power supply control part 120 at one end thereof, a transistor connected to the output terminal of the operational amplification part and performing a switching function, A feedback resistor including a decoupling capacitor may be provided to remove noise of the first intermediate voltage and the second intermediate voltage to provide the driving unit 300 with the noise. The low voltage drop bottom 140 can be implemented with a Low Power LDO (Low Drop Output).

The tap signal generating unit 200 includes a serializer 220, a delay unit 240, a combining unit 260, a timing adjusting unit 280, and an inverter chain 290. Will be described with reference to FIG.

The tap signal generator 200 may receive the data sequence to be transmitted and may generate the tap signal by combining the applied data sequence according to a predetermined method. The tap signal is a kind of a control signal for controlling ON / OFF of at least one transistor that performs the switching function included in the driver 300. [ In the present invention, the tap signal is represented by Sa, Sb, Sc, and Sd and may have values of 0100, 1000, 1110, and 1101 in order.

The serializer 220 receives the data sequence to be transmitted, and serializes the applied data sequence at a predetermined data transmission rate to output the first serial data sequence and the second serial data sequence. In the present invention, the serializer 220 receives data at a data transmission rate of 400 Mbp for each input port, and can transmit two serialized data sequences at a transmission rate of 1.6 Gbps, which is a preset data transmission rate.

For example, in the present invention, the serializer 220 may be implemented as an 8 to 2 serializer to receive a data sequence at eight input ports and to transmit a first serial data sequence and a second serial data sequence to two Serial output to the output port. Referring to FIG. 8, the serializer 220 has eight input ports and two output ports. One input port can receive a data sequence at 400 Mbps, and one output port can transmit data at a speed of 1.6 Gbps And outputs a first serial data sequence and a second serial data sequence.

For example, serializer 220 may include a de-flip-flop, a latch, and a mux to delay the data sequence to receive and apply the parallel data sequence to a serial data sequence. Will be described with reference to FIG.

The delay unit 240 delays the first serial data sequence D0 and the second serial data sequence D1 output from the serializer 220 by different time intervals and outputs a plurality of delayed data sequences. The delay unit 240 may be divided into a first delay unit for delaying the first serial data sequence and a second delay unit for delaying the second serial data sequence. In this case, the second delay unit may include one more number of latches than the first delay unit.

For example, in the present invention, different time intervals are defined as a UI (Unit Interval) of a data sequence, a delay unit 240 delays a data sequence by 1 UI, and a data sequence is delayed by 0.5 UI The first and second serial data sequences may be delayed by different time intervals, including the second delay element. The first delay element may be implemented as a D-Flip Flop and the second delay element may be implemented as a latch. Will be described with reference to FIG.

The delay unit 240 includes two D flip-flops and three latches, and outputs delayed data denoted as Q0C, Q0Cb, Q0B, Q0Bb, Q1C, Q1Cb, Q1B, Q1Bb, Q1A and Q1Ab in each D flip- The sequence is output. The signal Q0B delayed by 1 UI from the delayed first serial data sequence and delayed by 0.5 UI from the signal QOC delayed by 1 UI from the first serial data sequence is delayed by the delay signal Q0B ) Is 0.5 UI ahead of the delayed signal Q0C.

The combining unit 260 combines the first serial data sequence and the second serial data sequence delayed by the delay unit 240 according to the predetermined method. The combination of the first serial data sequence and the second serial data sequence according to a predetermined method may be performed by logic operation of the delayed first serial data sequence and second serial data sequence in accordance with the type of the transistor of the driving unit, It can be combined by mux.

For example, the combining unit 260 may include a NAND gate for performing a plurality of NAND operations, a NOR gate for performing a NOR operation, and a MUX. The delayed first serial data sequence applied to the combiner unit 260 may be applied to the NOR gate and the delayed second serial data sequence may be applied to the NAND gate to be logically operated.

The criterion for logic operation of the first serial data sequence and the second serial data sequence applied to the combination unit 260 depends on the type of the transistor of the driving unit 300 to which each data sequence is input. That is, the first serial data sequence applied to the PMOS transistor in the driver 300 performs NAND operation, and the second serial data sequence applied to the NMOS transistor performs Noah operation. The combining unit 260 multiplexes the first serial data sequence and the second serial data sequence, which are logically calculated, to select at least four data sequences, and transmits the sequence to the timing adjuster 280.

The timing adjuster 280 adjusts the timing of the first serial data sequence and the second serial data sequence combined according to a predetermined method in the combiner 260. [

For example, the output timings of the respective logic gates after the logic operation in the NAND gate and the NOR gate may not coincide with each other in device characteristics. In order to use the output timing of the logic gates as the tap signal, the first serial data sequence and the second serial data sequence The timing of

The inverter chain 290 is a plurality of inverter elements having a gradually increased strength for driving the driving unit 300. The first serial data sequence and the second serial data sequence whose timings are adjusted are sequentially inverted to set the Strength for driving the driving unit 300.

The driving unit 300 selects a reference voltage or an intermediate voltage according to a combination of data sequences to be transmitted.

For example, the driver 300 may select at least one of a reference voltage, an intermediate voltage, and a ground voltage according to a combination of data sequences to be transmitted. The driving unit 300 can select at least one of the reference voltage, the intermediate voltage, the first intermediate voltage, and the second intermediate voltage in response to the tap signal generated by the tap signal generating unit 200, And at least one of at least four transistors is controlled to select at least one of a reference voltage, a ground voltage, a first intermediate voltage, and a second intermediate voltage. Will be described with reference to Figs. 6 and 7. Fig.

In the present invention, unlike the FIR driver of the conventional segment structure, the driving unit 300 consumes only the dynamic current and does not consume the constant current. The conventional FIR driver has a segment structure that pre-emphasizes the magnitudes of the first and second intermediate voltages whose magnitudes are adjusted in accordance with the tap weights, and sets the enable segment of the main driver and the enable segment of the main driver to match the set terminal impedance set to 50 ohms The ratio of the number of enable segments of the sub driver is adjusted. Therefore, the magnitude of the first intermediate voltage VH among the output voltages of the conventional FIR driver is equal to VDD * (n / m).

The FIR driver of the conventional segment structure increases hardware complexity and occupies a large area in the layout. At the same time, there is a problem that a constant current flows from the reference voltage source to the ground through the resistor. 7, when the output of the FIR driver is maintained at the first intermediate voltage VH and the second intermediate voltage VL, the constant current flows from the reference voltage source to the ground (ground voltage, GND), for example, Therefore, the constant current can be consumed through the resistor.

In the present invention, the driving unit 300 may select at least one of the four resistors connected at one end to the output unit 400 and the at least one voltage through the transistor connected in series to the other end of the resistor. The transistors of the driver 300 include NMOS and PMOS. The driving unit 300 compares two bits including the current bit and the past bit of the data sequence and selects one of the first intermediate voltage and the second intermediate voltage when two bits are equal, In other cases, one of the reference voltage and the ground voltage is selected.

For example, the driving unit 300 selects and outputs the reference voltage VDD when the data sequence changes from 0 to 1. The driving unit 300 receives tap signals of Sa (0), Sb (1), Sc (0), and Sd (0) in the tap signal generating unit 200 when the data sequence is changed from 0 to 1, In response to the tap signal, a PMOS transistor connected to a reference voltage among the PMOS transistors is turned on to select a reference voltage, and the selected reference voltage is transmitted to the output unit. That is, in the present invention, the driver 300 selects the first intermediate voltage and the second intermediate voltage, which are set according to the ratio of the number of segments enabled in the main driver and the number of enabled segments in the sub driver as in the conventional FIR driver The first intermediate voltage and the second intermediate voltage selected by the intermediate voltage unit 100 are directly selected through the transistor and applied in series to the output unit. In addition, in the present invention, the driving unit 300 can reduce the reflection noise by setting a resistance value that is impedance matched to the receiving end.

In other words, in the present invention, the driving unit 300 includes at least four transistors whose ends are directly connected to voltage terminals of four levels, at least four resistors connected in series to the other end of the transistors, and an output unit 400 ), And selects one of four voltage signals while consuming only the dynamic current.

The output unit 400 outputs the voltage selected by the driving unit 300.

For example, the output unit 400 includes at least two output ports, and outputs the selected voltage from the driving unit 300 through each output port. In the present invention, one output port included in the output unit 400 can transmit data at a transmission rate of 3.2 Gbps.

2 is an enlarged block diagram of the intermediate voltage portion in the embodiment of FIG.

The intermediate voltage section 100 includes a power regulation section 120 and a low voltage drop section 140. The intermediate voltage section 100 may provide at least two or more intermediate voltages having a magnitude smaller than the reference voltage.

For example, the intermediate voltage unit 100 receives a predetermined 4-bit control signal, adjusts the magnitude of the first intermediate voltage and the second intermediate voltage by setting the tap weight according to the applied control signal, And transmits the first intermediate voltage and the second intermediate voltage having the magnitude of the applied voltage to the driving unit 300. As described above, in the present invention, the driving unit 300 selects the first intermediate voltage and the second intermediate voltage, and connects the direct intermediate voltage to the direct output unit 400. The above description related to the intermediate voltage unit 100 is redundant and will be omitted.

3 is an enlarged block diagram of the tap signal generating unit in the embodiment of FIG.

The tap signal generating unit 200 includes a serializer 220, a delay unit 240, a combining unit 260, a timing adjusting unit 280, and an inverter chain 290.

The tap signal generator 200 receives a data sequence and combines the applied data sequence according to a predetermined method to generate a tap signal. The method of combining the tap signals according to a predetermined method, the types of the tap signals, and the functions thereof are the same as those described above, so they are omitted.

4 is a block diagram of a low power transmitter without a constant current consumption including an enlarged block diagram of a tap signal generator according to an embodiment of the present invention.

In the present invention, the tap signal generator 200 may be divided into a serializer 220 and other devices in terms of functionality. For example, the tap signal generator 200 is implemented by a finite filter method, and generates a tap signal by combining data sequences to be transmitted according to a predetermined method. The matters related to the tap signal generator 200 and the driver 300 are the same as described above, and therefore will not be described.

5 is an exemplary diagram showing a waveform of an output signal of the delay unit in the embodiment of FIG.

The delay unit 240 delays the first serial data sequence and the second serial data sequence by different time intervals. The items for the different time intervals are as described above, so they are omitted.

The delay unit 240 includes a first delay element and a second delay element. The data delay is delayed by 1 UI by passing the data sequence through the first delay element, and is delayed by 0.5 UI by passing the data sequence through the second delay element.

6 is a conceptual diagram showing the operation principle of the driving unit in the embodiment of FIG.

The driving unit 300 selects and outputs at least one of a reference voltage, a first intermediate voltage, a second intermediate voltage, and a ground voltage.

For example, as shown in FIG. 6, the driving unit 300 selects a reference voltage in response to a tap signal combined with Sa (0), Sb (1), Sc (0), and Sd (400). The driving unit 300 includes two PMOS transistors connected in series with the reference voltage VDD and a first intermediate voltage VH and two NMOSs connected in series with the ground voltage GND and the second intermediate voltage VL, Transistor.

The driving unit 300 performs a switching function to connect the reference voltage, the ground voltage, the first intermediate voltage, and the second intermediate voltage to the output unit. The PMOS is turned on when the 0 signal is applied, (ON) when a 1 signal is applied and can connect a voltage to the output unit 400. [ In the present invention, unlike the FIR driver of the conventional finite filter transmitter, the driving unit 300 does not combine the number of segments enabled in the main driver and the sub driver for the intermediate voltage but the number of segments generated in the intermediate voltage unit 100 The intermediate voltage is directly connected to the output unit 400, so that there is no path through which the constant current flows, so that only the dynamic current can be consumed and the operation can be performed with low power.

7 is an exemplary diagram showing a path of a constant current consumed in an FIR driver having a conventional segment structure.

An FIR driver having a conventional segment structure includes a main driver including m segment units and a sub driver including n segment units. The FIR driver having the conventional segment structure selects n enabled segment units out of m segment units in the main driver and selects m-n segment units in the sub driver including n segment units to output a voltage. The conventional FIR driver sets tap weights using the ratio of the number of segment units selected in the main driver and the sub driver, and matches the magnitude and impedance of the intermediate voltage according to the set tap weights.

8 is a circuit diagram of a low power transmitter without a constant current consumption according to an embodiment of the present invention.

The low power transmitter 10 without constant current consumption includes an intermediate voltage unit 100, a tap signal generator 200, a driver 300, and an output unit 400.

The tap signal generating unit 200 includes a serializer 220, a delay unit 240, a combining unit 260, a timing adjusting unit 280, and an inverter chain 290. In the present invention, the power regulator 120 includes a 4-bit binary R-DAC, the low voltage lower 140 is a Low Power LDO, the serializer 220 includes an 8 to 2 serializer, a delay unit 240, May correspond to a Half rate Tap Generation block.

The output 400 of the low power transmitter 10 without constant current consumption includes two output ports and includes a low power transmitter with no constant current consumption corresponding to the block diagram shown in FIG. 8 for each output port.

9 is a conceptual diagram of a transceiver including a low-power transmitter without constant current consumption.

The low power transceiver 20 without constant current consumption includes an intermediate voltage unit 100, a tap signal generating unit 200, a driving unit 300, an output unit 400, and a receiving driver 500.

A low-power transceiver (20) without a constant current consumption receives a voltage output from a low-power transmitter (10) which is located in a transmitting terminal that transmits data through inter-chip communication and which does not consume a constant current, discriminates a pattern of the received voltage, . For example, the low-power transceiver 20, which does not consume a constant current, operates at low power to reduce interchannel interference in a transmitting terminal that transmits data through chip-to-chip communication and outputs a voltage according to a data sequence, And can recover the data sequence by discriminating the pattern of the received voltage.

The low power transmitter 10 having no constant current consumption is located in the transmitter 600 and outputs a voltage to the wire channel 650 in accordance with the inputted data sequence. The receiver driver 500 is located in the receiver 700, Receives the output voltage, and determines the pattern of the received voltage.

The low-power transmitter 10 without the constant current consumption included in the low-power transceiver 20 without the constant current consumption is as described above and will not be described here.

10 shows an example of the waveform of the pre-emphasis signal measured at the output unit in the embodiment of FIG.

The low-power transmitter 10 without a constant current consumption selects and outputs one of a reference voltage, a ground voltage, a first intermediate voltage VH and a second intermediate voltage VL according to a data sequence to be transmitted.

For example, assume that a low power transmitter 10 without constant current consumption receives a data sequence of 0101110. Outputs a reference voltage VDD when the received data sequence changes from 0 to 1, outputs a first intermediate voltage VH when the data sequence changes from 1 to 1, and outputs the first intermediate voltage VH when the data sequence changes from 0 to 0 2 Outputs the intermediate voltage (VL), and outputs the ground voltage (GND) when the data sequence changes from 1 to 0. The conventional FIR driver has a problem that the constant current flows from the reference voltage end to the ground voltage end through the resistor to consume the constant current when the data sequence is maintained in Fig. 10 (for example, 0, 0 or 1, 1) As shown above.

For example, when the received data sequence changes from 0 to 1, the low-power transmitter 10 without constant current consumption generates the tap signal S a (0), S b (1), Sc (0) (0) and Sb (1) are applied to the PMOS, Sc (0) and Sd (0) are applied to the NMOS, and only the transistor to which the VDD voltage is connected among the PMOS transistors And is turned on to select and output the reference voltage VDD. The process of pre-emphasizing the reference voltage to the first intermediate voltage and the second intermediate voltage by setting the tap weight by the low power transmitter 10 without the constant current consumption will be omitted.

Since the low power transmitter 10 without constant current consumption transfers the voltage of four levels to the direct output unit 400, the constant current does not flow even when the data sequence is maintained. Thus, the low power transmitter 10 without constant current consumption can operate at low power.

FIG. 11 shows an example of the waveform of the pre-emphasis signal measured at the receiving end when the driving unit is turned on / off in the embodiment of FIG. 1

The low power transmitter 10, which does not consume the constant current, can reduce intra-channel intersymbol interference (ISI) through pre-emphasis. The pre-emphasis waveform has an eye pattern, and the larger and sharper the eye pattern, the larger the signal can be transmitted at the receiver.

In the case where the voltage output from the low power transmitter 10 which does not consume the constant current is observed at the receiving end and the driving unit 300 is turned off, the eye pattern is the eye pattern of the eye 300 when the driving unit 300 is turned on. It is not clearer than the pattern. Vertical eye opening and horizontal eye opening are used as means for observing the sharpness of the eye pattern. When the driving unit 300 is turned off, the vertical eye opening of the channels 1 and 2 is 5%, and 4%, and horizontal eye opening is 33.6% and 30.1%, respectively. However, when the driving unit 300 is turned on, it can be observed that the vertical eye opening of the channels 1 and 2 increases to 31.9% and 32.9%, and the horizontal eye opening increases to 59.8% and 57.9%, respectively .

Therefore, when a data sequence is transmitted using a low-power transmitter 10 that does not consume the constant current of the present invention, it is possible to transmit data sequences with low power and at the same time to reduce data inter- There is an advantage.

12 shows an example of the waveform of the pre-emphasis signal measured according to the tap weight measured by the output unit of the present invention.

When the tap weight is adjusted in the intermediate voltage unit 100 of the present invention, the waveform of the pre-emphasis signal at the output terminal of the low power transmitter 10 which does not consume the constant current may be varied.

When the low power transmitter 10 consuming no constant current is used, it can be seen that the vertical eye opening decreases as the tap weight increases. That is, in the present invention, when the tap weight is increased, the pre-emphasis waveform is distorted and output.

Figure 13 shows an example of an actual implementation layout of a low power transmitter without constant current consumption of the present invention.

The low power transmitter 10 consuming the constant current of the present invention can be implemented in a chip area of approximately 0.009 milli squares when designed with a 45 nm CMOS process and consumes a low power of 2.25 Mw per channel at a transmission rate of 3.2 Gbps.

Table 1 shows the comparison of the power consumption and the data transmission speed of the low power transmitter that does not consume the constant current of the present invention compared to the conventional transmission / reception driver.

In Table 1, Normalized Power shows consumption power consumed based on 1Gbps data transmission rate, Process shows scale of CMOS design process, Data Rate is data transmission speed, Power is power consumption, Vertical Eye Opening is vertical eye opening , And jitter means noise during data transmission. In the case of the present invention, it consumes the lowest power consumption of 0.7 Mw. The low power transmitter 10 consuming no constant current of the present invention can significantly reduce power consumption and at the same time reduce interchannel interference and is advantageous in that it does not increase circuit complexity as compared with the conventional FIR driver.

All or part of the method of an embodiment of the present invention described above can be implemented in the form of a computer-executable recording medium (or a computer program product) such as a program module executed by a computer. Here, the computer-readable medium may include computer storage media (e.g., memory, hard disk, magnetic / optical media or solid-state drives). Computer readable media can be any available media that can be accessed by a computer and includes both volatile and nonvolatile media, removable and non-removable media.

Also, all or part of the method according to an embodiment of the present invention may include instructions executable by a computer, the computer program comprising programmable machine instructions to be processed by a processor, Language, an object-oriented programming language, an assembly language, or a machine language.

Means or module in the present specification may mean hardware capable of performing the functions and operations according to the respective names described herein and may be implemented by computer program code , Or may refer to an electronic recording medium, e.g., a processor or a microprocessor, having computer program code embodied thereon to perform particular functions and operations. In other words, a means or module may mean a functional and / or structural combination of hardware for carrying out the technical idea of the present invention and / or software for driving the hardware.

Thus, a method according to an embodiment of the present invention may be implemented by a computer program as described above being executed by a computing device. The computing device may include a processor, a memory, a storage device, a high-speed interface connected to the memory and a high-speed expansion port, and a low-speed interface connected to the low-speed bus and the storage device. Each of these components is connected to each other using a variety of buses and can be mounted on a common motherboard or mounted in any other suitable manner.

It will be apparent to those skilled in the art that various modifications, substitutions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. will be. Therefore, the embodiments disclosed in the present invention and the accompanying drawings are intended to illustrate and not to limit the technical spirit of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments and the accompanying drawings . The scope of protection of the present invention should be construed according to the following claims, and all technical ideas within the scope of equivalents should be construed as falling within the scope of the present invention.

Claims (23)

An intermediate voltage section providing at least one intermediate voltage having a magnitude less than the reference voltage;
A driver for selecting the reference voltage or the intermediate voltage according to a combination of data sequences to be transmitted; And
And an output unit for outputting a voltage selected by the driving unit,
Further comprising a tap signal generating unit receiving the data sequence to be transmitted and combining the applied data sequence according to a predetermined method to generate a tap signal,
Wherein the driving unit selects the reference voltage or the intermediate voltage in response to the generated tap signal. delete 2. The apparatus of claim 1, wherein the driving unit
Considering further the ground voltage in addition to the reference voltage and the intermediate voltage,
And selects at least one of the reference voltage, the intermediate voltage, and the ground voltage in response to the generated tap signal. The method according to claim 1,
Wherein the intermediate voltage includes a first intermediate voltage and a second intermediate voltage having different voltage magnitudes,
Wherein the driving unit controls ON / OFF of a transistor performing a switching function to select at least one of the reference voltage, the first intermediate voltage, the second intermediate voltage, and the ground voltage. transmitter. The apparatus as claimed in claim 4, wherein the driving unit
A first intermediate voltage, a second intermediate voltage, and a ground voltage through the resistor connected at one end to the output unit and the transistor connected in series to the other end of the resistor, Wherein the power supply is applied in series with the constant current. 6. The method of claim 5,
Wherein the transistor comprises a PMOS and an NMOS,
Wherein the driving unit controls ON / OFF of PMOS and NMOS according to a combination of the data sequence to select the one voltage. The apparatus of claim 3, wherein the tap signal generator comprises:
A serializer receiving the data sequence to be transmitted and serializing the applied data sequence at a predetermined data transmission rate and outputting the first serial data sequence and the second serial data sequence; Further comprising:
Wherein the tap signal is generated using the output first serial data sequence and the second serial data sequence. The apparatus of claim 7, wherein the tap signal generator comprises:
A delay unit delaying the first serial data sequence and the second serial data sequence by different time intervals; Further comprising:
Wherein the tap signal is generated using the delayed first serial data sequence and the second serial data sequence. The apparatus of claim 8, wherein the tap signal generator
A combining unit for combining the delayed first serial data sequence and the second serial data sequence according to the predetermined method; Further comprising:
Wherein the tap signal is generated using the combined first serial data sequence and the second serial data sequence. 5. The plasma display panel of claim 4,
A power regulator for receiving a predetermined 4-bit control signal and adjusting a magnitude of the first intermediate voltage and the second intermediate voltage by setting a tap weight for a magnitude of the first intermediate voltage and the second intermediate voltage; Further comprising:
And provides a first intermediate voltage and a second intermediate voltage having the magnitude of the regulated voltage to the driving unit. The plasma display apparatus of claim 10, wherein the intermediate voltage section
A feedback resistor connected between the transistors and including a decoupling capacitor at both terminals; and at least two operational amplifiers connected at one end to the power adjuster, a transistor connected to the output terminals of the operational amplifier, Low-voltage river bottom; Further comprising:
Wherein the first intermediate voltage and the second intermediate voltage are removed to provide noise to the driving unit. The apparatus as claimed in claim 5, wherein the driving unit
Compare the two bits of the data sequence to select one of the first intermediate voltage and the second intermediate voltage if the two bits are equal,
And selects one of the reference voltage and the ground voltage when the two bits are changed. 10. The method of claim 9, wherein combining according to the predetermined method
The delayed first serial data sequence and the second serial data sequence are logically operated in accordance with the type of the transistors of the driving unit and the logically calculated first serial data sequence and second serial data sequence are muxed and combined Low power transmitter with no constant current consumption. The apparatus of claim 9, wherein the tap signal generator comprises:
A timing adjuster for adjusting the timing of the combined first serial data sequence and the second serial data sequence; Further comprising:
Wherein the tap signal is generated using the first serial data sequence and the second serial data sequence with the timing adjusted. 15. The apparatus of claim 14, wherein the tap signal generator
An inverter chain having a gradually increased strength to drive the drive; Further comprising:
Wherein the tap signal is generated using the timing-adjusted first serial data sequence and the second serial data sequence that have passed through the chain of inverters. 9. The method of claim 8,
Wherein the time interval is defined as a UI (Unit Interval) of the data sequence,
Wherein the delay unit includes a first delay element that delays the data sequence by 1 UI (Unit Interval), and a second delay element that delays the data sequence by 0.5 UI (Unit Interval)
Wherein the first serial data sequence and the second serial data sequence are delayed by the different time intervals using the first delay element and the second delay element. An intermediate voltage section providing at least one intermediate voltage having a magnitude less than the reference voltage;
A tap signal generating unit receiving a data sequence to be transmitted and combining the applied data sequence according to a predetermined method to generate a tap signal;
A driver for selecting the reference voltage or the intermediate voltage in response to the generated tap signal;
An output unit for outputting a voltage selected by the driving unit; And
And a reception driver for receiving the selected voltage and for restoring the data sequence by discriminating a pattern of the received voltage,
Further comprising a tap signal generating unit receiving the data sequence to be transmitted and combining the applied data sequence according to a predetermined method to generate a tap signal,
Wherein the driving unit selects the reference voltage or the intermediate voltage in response to the generated tap signal. 18. The apparatus of claim 17, wherein the driving unit
Considering further the ground voltage in addition to the reference voltage and the intermediate voltage,
And selects at least one of the reference voltage, the intermediate voltage, and the ground voltage in response to the generated tap signal. 19. The method of claim 18,
Wherein the intermediate voltage includes a first intermediate voltage and a second intermediate voltage having different voltage magnitudes,
The driving unit may include at least one resistor connected at one end to the output unit and at least one transistor for performing a switching function connected in series to the other end of the resistor to control the ON / OFF of the reference voltage, the ground voltage, Voltage and a second intermediate voltage, and applies the selected voltage in series to the output unit. The apparatus of claim 19, wherein the tap signal generator comprises:
A serializer receiving the data sequence, serializing the applied data sequence at a predetermined data transmission rate and outputting the first serial data sequence and the second serial data sequence;
A delay unit delaying the first serial data sequence and the second serial data sequence by different time intervals; And
A combining unit for combining the delayed first serial data sequence and the second serial data sequence according to the predetermined method; Further comprising:
Wherein the tap signal is generated using the combined first serial data sequence and the second serial data sequence. 21. The method of claim 20, wherein combining according to the predetermined method
The delayed first serial data sequence and the second serial data sequence are logically operated in accordance with the type of the transistors of the driving unit and the logically calculated first serial data sequence and second serial data sequence are muxed and combined Low power transceiver without constant current consumption. 21. The apparatus of claim 20, wherein the driving unit
Compare the two bits of the data sequence to select one of the first intermediate voltage and the second intermediate voltage if the two bits are equal,
And selects one of the reference voltage and the ground voltage when the two bits are changed. 20. The method of claim 19, wherein the intermediate voltage portion
A power regulator for receiving a predetermined 4-bit control signal and adjusting a magnitude of the first intermediate voltage and the second intermediate voltage by setting a tap weight for a magnitude of the first intermediate voltage and the second intermediate voltage; And
At least two operational amplifiers for receiving the first intermediate voltage and the second intermediate voltage of which the magnitude of the voltage is adjusted, a transistor connected to the output terminal of the operational amplifier for performing a switching function, A low voltage drop bottom including a feedback resistor including a decoupling capacitor at a terminal; Further comprising:
And removing the noise of the first intermediate voltage and the second intermediate voltage of which the magnitude of the voltage is adjusted, and providing the noise to the driving unit.

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