KR101976039B1

KR101976039B1 - Semiconductor device

Info

Publication number: KR101976039B1
Application number: KR1020120139679A
Authority: KR
Inventors: 조문기; 안은철; 김상영; 신주원; 이민호
Original assignee: 삼성전자 주식회사
Priority date: 2012-12-04
Filing date: 2012-12-04
Publication date: 2019-08-28
Also published as: KR20140071745A; CN103855133A; CN103855133B

Abstract

It is to provide a semiconductor device having improved reliability by preventing fuses cut through the repair process from being electrically connected again through electrochemical migration. The semiconductor device may include a substrate, a first fuse pattern and a second fuse pattern formed on the substrate, the first fuse pattern and the second fuse pattern spaced apart from each other by a first width, and the first fuse pattern and the second fuse pattern. A first insulating film formed on the fuse pattern, the first insulating film including an opening having a second width smaller than the first width.

Description

Semiconductor device

The present invention relates to a semiconductor device.

In general, a semiconductor device may be manufactured through a fabrication process, an electrical die sorting process (EDS process), an assembly process, and a test process. Among these, the EDS process includes a pre-laser test for inspecting semiconductor chips, a repair process for replacing a defective semiconductor chip identified in the pre-laser test with a redundant semiconductor chip, and a replacement. Post-laser test to check the normal semiconductor chip.

The repair process is a process of switching an electrical signal through a fuse cut, and replacing a defective cell with a normal cell or a defective circuit with a normal circuit. In general, a repair process is performed by cutting a fuse connecting a defective cell and then replacing the defective cell with an extra normal cell.

An object of the present invention is to provide a semiconductor device having improved reliability by preventing the fuse cut through the repair process from being electrically connected again through electrochemical migration.

Problems to be solved by the present invention are not limited to the above-mentioned problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

An aspect of a semiconductor device of the present invention for solving the above problems is a substrate, a first fuse pattern and a second fuse pattern formed on the substrate, the first fuse pattern and the first fuse pattern spaced apart from each other by a first width And a first insulating film formed on the second fuse pattern and the first insulating film formed on the first fuse pattern and the second fuse pattern, the first insulating film including an opening having a second width smaller than the first width.

In some embodiments, at least one of the first fuse pattern and the second fuse pattern is undercut under the first insulating layer.

In some embodiments of the present invention, the opening non-overlaps with at least one of the first fuse pattern and the second fuse pattern.

In some embodiments of the present invention, the first fuse pattern and the second fuse pattern are electrically insulated from each other.

In some embodiments of the present disclosure, the semiconductor device may further include an insulating material formed between the first fuse pattern and the second fuse pattern.

In some embodiments of the present disclosure, the air purifier may further include an air gap formed between at least one of the first fuse pattern and the insulating material and between the second fuse pattern and the insulating material.

In some embodiments of the present invention, the air gap includes a first air gap and a second air gap, the first air gap is formed between the first fuse pattern and the insulating material, and the second air gap Is formed between the second fuse pattern and the insulating material.

In some embodiments of the present disclosure, the insulating material includes a first portion and a second portion, and the first portion of the insulating material is formed between the first fuse pattern and the second fuse pattern through the opening. The second portion of the insulating material is connected to the first portion and is formed on the first insulating layer.

In some embodiments, the semiconductor device may further include a second insulating film formed under the first fuse pattern and the second fuse pattern, and the second insulating film may include a trench overlapping the opening.

In some embodiments of the present invention, the semiconductor device may further include conductive particles formed between the first fuse pattern and the second fuse pattern.

In some embodiments of the present disclosure, the air purifier may further include an air gap formed between the first fuse pattern and the conductive particles and between the second fuse pattern and the conductive particles.

In some embodiments of the present invention, the conductive particles include a material included in the first and second fuse patterns.

In some embodiments, the semiconductor device may further include a spacer formed between at least one of the first fuse pattern and the opening and between the second fuse pattern and the opening.

In some embodiments of the present invention, the spacer includes a first spacer and a second spacer, and further includes a first air gap formed between the first spacer and the first fuse pattern.

In some embodiments of the present invention, the semiconductor device may further include a second air gap formed between the second spacer and the second fuse pattern.

In some embodiments of the present invention, a conductive pattern is not formed directly above the opening.

In some embodiments of the present disclosure, the semiconductor device may further include a first metal wire and a second metal wire formed under the first fuse pattern and the second fuse pattern, and the first metal wire may be formed through the first via. The second fuse is electrically connected to the first fuse pattern, and the second metal wire is electrically connected to the second fuse pattern through a second via.

In some embodiments of the present disclosure, the electronic device may further include a first metal wire electrically connected to the first fuse pattern and a second metal wire electrically connected to the second fuse pattern. The second fuse pattern, the first metal wiring, and the second metal wiring are formed to be spaced apart from the substrate by the same distance.

In some embodiments of the present disclosure, the first fuse pattern may further include a first circuit pattern and a second circuit pattern formed under the first fuse pattern and the second fuse pattern, and the first fuse pattern may be electrically connected to the first circuit pattern. The second fuse pattern is electrically connected to the second circuit pattern.

In some embodiments of the present disclosure, the semiconductor device may further include a barrier metal layer formed in contact with the first fuse pattern and the second fuse pattern, respectively.

In some embodiments of the present invention, the first fuse pattern and the second fuse pattern each include at least one of copper and aluminum.

Another aspect of the semiconductor device of the present invention for solving the above problems is a substrate, formed on the substrate, and spaced apart from each other on the first fuse pattern and the second fuse pattern, the first fuse pattern and the second fuse pattern A first insulating layer formed between the first fuse pattern and the second fuse pattern, an insulating material formed between the first fuse pattern and the second fuse pattern, and the first fuse pattern; And an air gap formed between at least one of the insulating material and at least one of the second fuse pattern and the insulating material.

In some embodiments of the present invention, the width of the first fuse pattern and the second fuse pattern is greater than the width of the opening.

In some embodiments of the invention, the insulating material fills the trench.

In some embodiments of the present invention, the conductive particles are surrounded by the insulating material.

In some embodiments, the semiconductor device may further include a spacer formed between at least one of the first fuse pattern and the insulating material and between the second fuse pattern and the insulating material.

In some embodiments of the present invention, the spacer includes a first spacer and a second spacer, the air gap includes a first air gap and a second air gap, and the first air gap is connected to the first spacer. The second fuse may be formed between the first fuse pattern, and the second air gap may be formed between the second spacer and the second fuse pattern.

In some embodiments of the invention, the insulating material and the spacer are formed in contact.

Another aspect of the semiconductor device of the present invention for solving the above problems is a first fuse pattern and a second fuse pattern formed on a substrate, the substrate yarn, and spaced apart from each other, and the first fuse pattern and the second fuse pattern And an insulating layer formed on the first fuse pattern, the insulating layer including an opening formed between the first fuse pattern and the second fuse pattern, wherein at least one of the first fuse pattern and the second fuse pattern is undercut under the insulating film. have.

In some embodiments of the present invention, an air gap is formed between at least one of the first fuse pattern and the insulating material and between the second fuse pattern and the insulating material.

Other specific details of the invention are included in the detailed description and drawings.

1 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
FIG. 2 is a diagram for explaining the semiconductor device of FIG. 1 after assembly. FIG.
3 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
4 is a plan view of FIG. 3.
FIG. 5 is a diagram for describing the semiconductor device of FIG. 3 after assembly. FIG.
FIG. 6 is a diagram for describing the semiconductor device of FIG. 3 further including a pad. FIG.
7 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
FIG. 8 is a diagram for explaining the semiconductor device of FIG. 7 after assembly. FIG.
9 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
FIG. 10 is a diagram for describing the semiconductor device of FIG. 9 after assembly. FIG.
11 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
12 is a diagram for explaining the semiconductor device of FIG. 11 after assembly.
13 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts.
14 is a plan view of FIG. 13.
FIG. 15 is a diagram for describing the semiconductor device of FIG. 13 after assembly. FIG.
16 is a block diagram of a memory card including a semiconductor device according to example embodiments.
17 is a block diagram of an information processing system using a semiconductor device according to example embodiments.
18 is a block diagram of an electronic device including a semiconductor device according to some example embodiments of the inventive concepts.

Advantages and features of the present invention and methods for achieving them will be apparent with reference to the embodiments described below in detail with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in various forms, and only the present embodiments are intended to complete the disclosure of the present invention, and the general knowledge in the art to which the present invention pertains. It is provided to fully convey the scope of the invention to those skilled in the art, and the present invention is defined only by the scope of the claims. In the drawings, the relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.

When an element is referred to as being "connected to" or "coupled to" with another element, it may be directly connected to or coupled with another element or through another element in between. This includes all cases. On the other hand, when one device is referred to as "directly connected to" or "directly coupled to" with another device indicates that no other device is intervened. Like reference numerals refer to like elements throughout. “And / or” includes each and all combinations of one or more of the items mentioned.

When elements or layers are referred to as "on" or "on" of another element or layer, intervening other elements or layers as well as intervening another layer or element in between. It includes everything. On the other hand, when a device is referred to as "directly on" or "directly on" indicates that no device or layer is intervened in the middle.

Although the first, second, etc. are used to describe various elements, components and / or sections, these elements, components and / or sections are of course not limited by these terms. These terms are only used to distinguish one element, component or section from another element, component or section. Therefore, the first device, the first component, or the first section mentioned below may be a second device, a second component, or a second section within the technical spirit of the present invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. In this specification, the singular also includes the plural unless specifically stated otherwise in the phrase. As used herein, “comprises” and / or “comprising” refers to the presence of one or more other components, steps, operations and / or elements. Or does not exclude additions.

Unless otherwise defined, all terms (including technical and scientific terms) used in the present specification may be used in a sense that can be commonly understood by those skilled in the art. In addition, the terms defined in the commonly used dictionaries are not ideally or excessively interpreted unless they are specifically defined clearly.

Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. 1 and 2.

1 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. FIG. 2 is a diagram for explaining the semiconductor device of FIG. 1 after assembly. FIG.

Referring to FIG. 1, the semiconductor device 10 may include a substrate 100, a first fuse pattern 130, a second fuse pattern 140, and a first insulating layer 150.

The substrate 100 may be bulk silicon or silicon-on-insulator (SOI). Alternatively, the substrate 100 may be a silicon substrate, or may include other materials such as silicon germanium, indium antimonide, lead tellurium compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonium, It is not limited to this.

The first circuit pattern 105 and the second circuit pattern 110 may be formed on the substrate 100. The first circuit pattern 105 and the second circuit pattern 110 may be formed in, for example, a cell region, but are not limited thereto. The first and second circuit patterns 105 and 110 may each include a transistor, a diode, a capacitor, and the like. The first and second circuit patterns 105 and 110 may constitute circuit elements. Therefore, the semiconductor device 10 may be a semiconductor chip having a plurality of circuit elements formed therein. The circuit element may include a plurality of memory elements. Examples of the memory device include volatile semiconductor memory devices and nonvolatile semiconductor memory devices. The volatile semiconductor memory device may be, for example, DRAM, SRAM, or the like. The nonvolatile semiconductor memory device may be, for example, an EPROM, an EEPROM, a Flash EEPROM, or the like. In the description according to the embodiment of the present invention, it is described as being formed on the first and second circuit patterns 105 and 110, but is not limited thereto. That is, the first and second circuit patterns 105 and 110 may be embedded in the substrate 100.

The second insulating layer 102 may be formed on the substrate 100 and may cover the first and second circuit patterns 105 and 110. The first metal wire 120 and the second metal wire 122 may be formed in the second insulating layer 102. The first metal wire 120 is electrically connected to the first circuit pattern 105 through the first connection wire 106, and the second metal wire 122 is formed through the second connection wire 111. 2 may be electrically connected to the circuit pattern 110. The second insulating film 102 may include, for example, an oxide, a nitride, or an oxynitride, and a low dielectric constant material may be used. Low dielectric constant materials may include, for example, FOX, TOSZ, USG, BSG, PSG, BPSG, PRTEOS, FSG, HDP, PEOX, FCVD, or a combination thereof. The first metal wire 120 and the second metal wire 122 may include, for example, a metal such as aluminum (Al).

The third insulating layer 104 may be formed on the first metal wire 120 and the second metal wire 122. The third insulating layer 104 may include, for example, an oxide, nitride, or oxynitride, and a low dielectric material may also be used.

The first fuse pattern 130 and the second fuse pattern 140 may be formed on the third insulating layer 104. The first fuse pattern 130 and the second fuse pattern 140 may be formed in the fourth insulating layer 107 formed on the third insulating layer 104. The third insulating film 104 and the fourth insulating film 107 may be formed at the same level. The first fuse pattern 130 and the second fuse pattern 140 are spaced apart from each other. The first fuse pattern 130 and the second fuse pattern 140 may be spaced apart by the first width w1. The first fuse pattern 130 and the second fuse pattern 140 may include, for example, at least one of aluminum and copper (Cu), but is not limited thereto. The first fuse pattern 130 and the second fuse pattern 140 may be formed at the same level. Here, "same level" means formed by the same manufacturing process. For example, the fourth insulating layer 107 may include an oxide, nitride, or oxynitride, and a low dielectric material may be used.

The first metal wire 120 and the second metal wire 122 may be positioned under the first fuse pattern 130 and the second fuse pattern 140. The first fuse pattern 130 is electrically connected to the first metal wire 120 through the first via 125, and the second fuse pattern 140 is connected to the second metal via the second via 127. It may be electrically connected to the wiring 122. Therefore, the first fuse pattern 130 and the second fuse pattern 140 may be electrically connected to the first circuit pattern 105 and the second circuit pattern 110, respectively. The first via 125 and the second via 127 may be formed through the third insulating film 104 in the third insulating film 104. For example, the first via 125 and the second via 127 may include at least one of aluminum, copper, and tungsten (W). A barrier metal (not shown) may be interposed between the first via 125, the second via 127, and the third insulating layer 104, but is not limited thereto.

In the description of some embodiments of the present invention, it is described that the first fuse pattern 130 and the second fuse pattern 140 are formed on the first metal wire 120 and the second metal wire 122. It is not limited to this. That is, the first fuse pattern 130, the second fuse pattern 140, the first metal wire 120, and the second metal wire 122 may all be formed in the second insulating film 102. Will be described in detail with reference to FIGS. 13 to 15.

The first barrier metal film 132 and the second barrier metal film 142 are disposed between the third insulating film 104 and the first fuse pattern 130 and between the third insulating film 104 and the second fuse pattern 140, respectively. ) May be further formed. The first barrier metal layer 132 and the second barrier metal layer 142 may be formed to contact the first fuse pattern 130 and the second fuse pattern 140, respectively. The first barrier metal layer 132 and the second barrier metal layer 142 may prevent the materials included in the first fuse pattern 130 and the second fuse pattern 140 from being diffused into the third insulating layer 104. can do. The first barrier metal film 132 and the second barrier metal film 142 are formed at the same level, and include, for example, a material such as Ta, TaN, Ti, TiN, Ru, Co, Ni, NiB, WN, or the like. can do.

The first insulating layer 150 may be formed on the first fuse pattern 130 and the second fuse pattern 140. The first insulating layer 150 may include an opening 155, and the opening 155 formed in the first insulating layer 150 may have a second width w2. The first insulating layer 150 may include, for example, an oxide, nitride, or oxynitride, but is not limited thereto.

The opening 155 may be formed between the first fuse pattern 130 and the second fuse pattern 140. The second width w2 of the opening 155 is smaller than the first width w1 in which the first fuse pattern 130 and the second fuse pattern 140 are spaced apart from each other. That is, the distance between the first fuse pattern 130 and the second fuse pattern 140 is greater than the width of the opening 155. Since the width spaced apart between the first fuse pattern 130 and the second fuse pattern 140 is greater than the width of the opening 155, the opening 155 may include the first fuse pattern 130 and the second fuse pattern ( Non-overlapping with at least one of the 140).

In other words, at least one of the first fuse pattern 130 and the second fuse pattern 140 may be undercut under the first insulating layer 150. The undercut formed under the first insulating layer 150 may be formed by, for example, wet etching, dry etching, or a combination thereof.

In the semiconductor device according to the first embodiment of the present invention, the opening 155 is not overlapped with the first fuse pattern 130, and the side surface of the second fuse pattern 140 and the side surface of the opening 155 are coplanar. Explain that there is.

FIG. 2 illustrates that an adhesive is formed on the first insulating layer 150 to facilitate bonding with another semiconductor device in order to assemble the semiconductor device 10 of FIG. 1. That is, FIG. 1 may be a state in which a fuse is repaired before assembling using the semiconductor device 10, and FIG. 2 may be in a state after assembling another semiconductor device from the semiconductor device 10 including the repaired fuse. .

Referring to FIG. 2, the semiconductor device 10 may further include an insulating material 160. At least a portion of the insulating material 160 may be formed between the first fuse pattern 130 and the second fuse pattern 140. The insulating material 160 is formed between the first fuse pattern 130 and the second fuse pattern 140, thereby, between the first fuse pattern 130 and the insulating material 160, and the second fuse pattern 140. An air gap 170 may be formed in at least one of the insulating materials 160.

In detail, the insulating material 160 may include a first portion 162 and a second portion 164. The first portion 162 of the insulating material extends through the opening 155 to the third insulating layer 104 and is formed between the first fuse pattern 130 and the second fuse pattern 140. The second portion 164 of the insulating material may be connected to the first portion 162 of the insulating material and formed on the first insulating layer 150. The insulating material 160 may be, for example, a die attach film (DAF) or an epoxy molding compound (EMC), but is not limited thereto.

In the description of the first embodiment of the present invention, the insulating material 160 is spaced apart from the first fuse pattern 130, but may be formed in contact with the second fuse pattern 140. That is, the first portion 162 of the insulating material may be positioned between the first fuse pattern 130 and the second fuse pattern 140, and may contact the second fuse pattern 140. Since the first portion 162 of the insulating material and the first fuse pattern 130 are spaced apart from each other, a first air gap is formed between the first portion 162 and the first fuse pattern 130 of the insulating material 160. 170 is formed. However, since the first portion 162 and the second fuse pattern 140 of the insulating material contact each other, no air gap is formed between the first portion 162 and the second fuse pattern 140 of the insulating material 160. Do not.

In FIG. 2, the first portion 162 of the insulating material is illustrated as not including a conductive material, but is not limited thereto. Since the insulating material 160 may be a porous material, when the semiconductor device 10 is exposed to a high temperature and high humidity environment, a material included in the second fuse pattern 140 may undergo electrochemical migration. It may be diffused into the insulating material 160 through. As such, when the second fuse pattern 140 is diffused into the insulating material 160, a line-shaped conductive material band may be formed in the first portion 162 of the insulating material.

However, since the first air gap 170 is formed between the first portion 162 of the insulating material and the first fuse pattern 130, the conductive material in the first portion 162 of the insulating material may be the first fuse pattern. Can not be connected with (130). That is, the first air gap 170 is formed between the first fuse pattern 130 and the second fuse pattern 140 to electrically insulate the first fuse pattern 130 and the second fuse pattern 140. . Therefore, since the first fuse pattern 130 and the second fuse pattern 140 are electrically insulated by the first air gap 170, the reliability of the semiconductor package manufactured using the semiconductor device 10 may be improved. have.

In the description of the first embodiment of the present invention, the insulating material 160 is described as not being inserted into the lower portion of the first insulating film 150 undercut the first fuse pattern 130, but is not limited thereto. That is, a portion of the insulating material 160 may be inserted into the lower portion of the first insulating layer 150 in which the first fuse pattern 130 is undercut. However, even if a portion of the insulating material 160 is inserted into the lower portion of the first insulating film 150 in which the first fuse pattern 130 is undercut, the first air is disposed between the insulating material 160 and the first fuse pattern 130. The gap 170 is formed.

3 to 6, a semiconductor device according to a second embodiment of the present invention will be described. This embodiment is substantially the same as the first embodiment described above except for whether the second fuse pattern is undercut, and therefore, the same reference numerals are used for parts overlapping with the first embodiment described above. Or omit it.

3 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. 4 is a plan view of FIG. 3. FIG. 5 is a diagram for describing the semiconductor device of FIG. 3 after assembly. FIG. FIG. 6 is a diagram for describing the semiconductor device of FIG. 3 further including a pad. FIG.

Referring to FIG. 3, the semiconductor device 20 includes a substrate 100, a first fuse pattern 130, a second fuse pattern 140, and a first insulating layer 150.

The first circuit pattern 105 and the second circuit pattern 110 may be formed on the substrate 100. On the first circuit pattern 105 and the second circuit pattern 110, the first metal wiring 120 and the second metal wiring electrically connected to the first circuit pattern 105 and the second circuit pattern 110, respectively. 122 is formed. The first metal wire 120 and the second metal wire 122 may be formed in the second insulating layer 102 formed on the substrate 100. The first fuse pattern 130 and the second fuse pattern 140 are formed on the first metal wire 120 and the second metal wire 122. The first fuse pattern 130 and the second fuse pattern 140 are electrically connected to the first metal wire 120 and the second metal wire 122, respectively. A first via 125 is formed between the first fuse pattern 130 and the first metal wire 120, and a second via 127 is formed between the second fuse pattern 140 and the second metal wire 122. Is formed. The first via 125 and the second via 127 may be formed in the third insulating layer 104 interposed between the first fuse pattern 130 and the second fuse pattern 140 and the second insulating layer 102. have. The first insulating layer 150 is formed on the first fuse pattern 130 and the second fuse pattern 140, and the first insulating layer 150 is disposed between the first fuse pattern 130 and the second fuse pattern 140. The opening 155 is formed.

When the first fuse pattern 130 and the second fuse pattern 140 are spaced apart by the first width w1, the second width w2 of the opening 155 is smaller than the first width w1. Since the width spaced apart between the first fuse pattern 130 and the second fuse pattern 140 is greater than the width of the opening 155, the opening 155 may include the first fuse pattern 130 and the second fuse pattern ( Non-overlapping with at least one of the 140). In addition, at least one of the first fuse pattern 130 and the second fuse pattern 140 may be undercut under the first insulating layer 150.

In the semiconductor device according to the second exemplary embodiment of the present invention, the opening 155 is non-overlapping with both the first fuse pattern 130 and the second fuse pattern 140. In the semiconductor device according to the second exemplary embodiment of the present invention, both the first fuse pattern 130 and the second fuse pattern 140 are undercut under the first insulating layer 150.

In the description of the second embodiment of the present invention, the widths of the first fuse pattern 130 and the second fuse pattern 140 undercut under the first insulating layer 150 are the same, but the present invention is not limited thereto. . That is, the width of the first fuse pattern 130 undercut under the first insulating layer 150 may be different from the width of the second fuse pattern 140 undercut under the first insulating layer 150.

Referring to FIG. 4, an opening 155 is formed in the first insulating layer 150. The third insulating layer 104 under the first insulating layer 150 may be exposed by the opening 155. A pair of first fuse patterns 130 and a second fuse pattern 140 are disposed under the first insulating layer 150. The first fuse pattern 130 and the second fuse pattern 140 are not overlapped with the opening 155 as a whole. An area 170a in which the first fuse pattern 130 is undercut is positioned between the opening 155 and the first fuse pattern 130, and a second fuse pattern is formed between the opening 155 and the second fuse pattern 140. An area 175a undercut 140 is positioned.

For convenience of description, a pair of first fuse patterns 130 and a second fuse pattern 140 are illustrated, but is not limited thereto. In addition, for convenience of description, the first fuse pattern 130 and the second fuse pattern 140 is shown as being aligned in one direction, but is not limited thereto.

For convenience of description, the shape of the fuse before the repair is shown as a dog-bone type fuse, but is not limited thereto. That is, the fuse shape before the repair may be straight, or may have a dog-bone shape or a third shape other than the straight shape.

Referring to FIG. 5, the semiconductor device 20 may further include an insulating material 160. The insulating material 160 includes a first portion 162 and a second portion 164, and the first portion 162 of the insulating material penetrates through the opening 155 to form the first fuse pattern 130 and the first portion 162. The second fuse pattern 140 may be formed between the second fuse patterns 140 and the second portion 164 of the insulating material may be formed on the first insulating layer 150. The insulating material 160 is formed between the first fuse pattern 130 and the second fuse pattern 140, thereby, between the first fuse pattern 130 and the insulating material 160, and the second fuse pattern 140. Air gaps 170 and 175 may be formed in at least one of the insulating materials 160.

In FIG. 5, a first air gap 170 is formed between the first fuse pattern 130 and the insulating material 160, and a second air gap between the second fuse pattern 140 and the insulating material 160 is formed. 175 is shown to be formed. However, the width of the first fuse pattern 130 undercut under the first insulating layer 150 and the width of the second fuse pattern 140 undercut under the first insulating layer 150 are different from each other. If a part is inserted into the undercut portion, only one of the first air gap 170 and the second air gap 175 may be formed.

In detail, the first portion 162 of the insulating material 160 is spaced apart from the first fuse pattern 130 and the second fuse pattern 140. That is, a first air gap 170 is formed between the first fuse pattern 130 and the first portion 162 of the insulating material, and between the second fuse pattern 140 and the first portion 162 of the insulating material. The second air gap 175 is formed in the. The first air gap 170 is surrounded by the first fuse pattern 130, the first insulating film 150, the insulating material 160, the third insulating film 104, and the fourth insulating film 107, and the second air The gap 175 is surrounded by the second fuse pattern 140, the first insulating layer 150, the insulating material 160, the third insulating layer 104, and the fourth insulating layer 107.

The first air gap 170 and the second air gap 175 are formed between the first fuse pattern 130 and the second fuse pattern 140, and the first fuse pattern 130 and the second fuse pattern ( 140 may be electrically insulated. In addition, even when the semiconductor device 20 is exposed to a high temperature and high humidity environment, a first air gap 170 and a second air gap 175 are formed between the first fuse pattern 130 and the second fuse pattern 140. As a result, the first fuse pattern 130 and the second fuse pattern 140 are not electrically connected.

Referring to FIG. 6, a first circuit pattern 105, a second circuit pattern 110, a first metal wire, and a second metal wire may be formed on the first insulating layer 150 positioned on the substrate of the cell region and the peripheral circuit region. A pad 135 may be formed to transmit an electrical signal to the 122. The pad 135 may be formed using a conductive material such as a metal, a conductive metal nitride, or a metal silicide. The pad 135 may be formed using, for example, a low resistivity metal such as aluminum or tungsten.

The pad 135 may not be formed directly on the first fuse pattern 130 and the second fuse pattern 140. Specifically, the pad 135 is not formed directly above the opening 155. In the semiconductor device according to the embodiments of the inventive concept, the opening 155 may be an open area of the semiconductor device 20, and a conductive pattern is not formed directly above the opening 155.

A semiconductor device according to a third embodiment of the present invention will be described with reference to FIGS. 7 and 8. This embodiment is substantially the same as the second embodiment described above except that the third insulating film includes a trench, so that overlapping portions are briefly omitted or omitted.

7 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. FIG. 8 is a diagram for explaining the semiconductor device of FIG. 7 after assembly. FIG.

Referring to FIG. 7, the semiconductor device 30 may include a first fuse pattern 130, a second fuse pattern 140, a trench 104t, and a first insulating layer 150.

The first fuse pattern 130 electrically connected to the first circuit pattern 105 and the second fuse pattern 140 electrically connected to the second circuit pattern 110 are formed on the third insulating layer 104. The first insulating layer 150 including the opening 155 is formed on the first fuse pattern 130 and the second fuse pattern 140. The opening 155 is formed between the first fuse pattern 130 and the second fuse pattern 140 and does not overlap at least one of the first fuse pattern 130 and the second fuse pattern 140. That is, at least one of the first fuse pattern 130 and the second fuse pattern 140 is undercut under the first insulating layer 150.

The third insulating layer 104 under the first fuse pattern 130 and the second fuse pattern 140 includes a trench 104t. The trench 104t is formed in the third insulating film 104. The trench 104t may at least partially overlap the opening 155 included in the first insulating layer 150. In addition, the trench 104t may be formed between the first fuse pattern 130 and the second fuse pattern 140, and may not overlap the first fuse pattern 130 and the second fuse pattern 140. That is, although the first fuse pattern 130 and the second fuse pattern 140 do not protrude onto the trench 104t, the width and the trench 104t in which the first fuse pattern 130 and the second fuse pattern 140 are spaced apart from each other. ) May have the same width.

In the semiconductor device 30 according to the third embodiment of the present invention, the width of the trench 104t and the width of the opening 155 are the same, and the entire trench 104t is shown to overlap with the opening 155. It is not limited to this. Since the trench 104t is intended to make the spatial separation and the electrical separation between the first fuse pattern 130 and the second fuse pattern 140 more clear, the width of the trench 104t is not a problem. Further, in the manufacturing method, since the trench 104t may be manufactured using the opening 155 as a window, the trench 104t may overlap the opening 155 as a whole, but the trench 104t and the opening 155 may be overlapped. The extent to which is overlapped does not matter.

Referring to FIG. 8, the semiconductor device 30 may further include an insulating material 160 including a first portion 162 and a second portion 164. The first portion 162 of the insulating material formed between the first fuse pattern 130 and the second fuse pattern 140 through the opening 155 may extend to the inside of the trench 104t. That is, the insulating material 160 may fill the trench 104t formed in the third insulating layer 104.

A first air gap 170 is formed between the first fuse pattern 130 and the first portion 162 of the insulating material, and between the second fuse pattern 140 and the first portion 162 of the insulating material. 2 air gaps 175 are formed. The first air gap 170 and the second air gap 175 may be farther from the substrate 100 than the bottom surface of the trench 104t. If the width of the trench 104t is greater than the width of the opening 155, a portion of at least one of the first air gap 170 and the second air gap 175 may be formed in the third insulating layer 104.

A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIGS. 9 and 10. This embodiment is substantially the same as the above-described second embodiment except that it includes the conductive particles, so that overlapping portions are briefly omitted or omitted.

9 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. FIG. 10 is a diagram for describing the semiconductor device of FIG. 9 after assembly. FIG.

Referring to FIG. 9, the semiconductor device 40 includes a first fuse pattern 130, a second fuse pattern 140, conductive particles 180, and a first insulating layer 150.

The first fuse pattern 130 and the second fuse pattern 140, which are electrically connected to the first circuit pattern 105 and the second circuit pattern 110, respectively, are formed on the third insulating layer 104. The first insulating layer 150 including the opening 155 is formed on the first fuse pattern 130 and the second fuse pattern 140. The opening 155 is formed between the first fuse pattern 130 and the second fuse pattern 140. At least one of the first fuse pattern 130 and the second fuse pattern 140 is undercut under the first insulating layer 150.

The conductive particles 180 are formed between the first fuse pattern 130 and the second fuse pattern 140. The conductive particles 180 may be formed on the third insulating film 104, and specifically, may be formed in contact with the third insulating film 104. The entire conductive particle 180 may overlap the opening 155. The conductive particles 180 are illustrated as being spaced apart from the first fuse pattern 130 and the second fuse pattern 140, respectively, but are not limited thereto.

That is, the conductive particles 180 may be connected to one of the first fuse pattern 130 and the second fuse pattern 140. In this case, the fuse pattern not connected to the conductive particles 180 is undercut under the first insulating layer 150, and is spaced apart from the conductive particles 180.

The conductive particles 180 may be a metallic material introduced from the outside, or the conductive particles 180 may include, for example, a material included in the fuse patterns 130 and 140, and may further include a barrier metal film ( Materials included in 132 and 142 may also be included. For example, the conductive particles 180 repair the fuses connecting the first circuit pattern 105 and the second circuit pattern 110 to form the first fuse pattern 130 and the second fuse pattern 140. It may be a residue made.

In the semiconductor device according to the fourth exemplary embodiment, the conductive particles 180 are not protruded from the top surface of the first insulating layer 150, but the present invention is not limited thereto. That is, since the shape of the conductive particles 180 is not limited, a portion of the conductive particles 180 may protrude from the upper surface of the first insulating layer 150.

Referring to FIG. 10, the semiconductor device 40 may further include an insulating material 160 including a first portion 162 and a second portion 164. The first portion 162 of the insulating material formed between the first fuse pattern 130 and the second fuse pattern 140 through the opening 155 may surround the conductive particles 180. By the insulating material 160 surrounding the conductive particles 180, a first air gap 170 is formed between the first fuse pattern 130 and the first portion 162 of the insulating material, and the second fuse pattern ( A second air gap 175 is formed between the 140 and the first portion 162 of the insulating material. That is, the first air gap 170 is formed between the first fuse pattern 130 and the conductive particles 180, and the second air gap 175 is formed between the second fuse pattern 140 and the conductive particles 180. This can be formed.

In the semiconductor device of the present invention, the conductive particles 180 are described as being completely wrapped by the insulating material 160, but are not limited thereto. That is, some of the conductive particles 180 may be exposed by the insulating material 160. Even when the conductive particles 180 are exposed to the outside of the insulating material 160, air gaps 170 and 175 are formed between the conductive particles 180 and the fuse patterns 130 and 140.

In the semiconductor device of the present invention, it is described that the first air gap 170 and the second air gap 175 are formed on both side surfaces of the conductive particles 180, but are not limited thereto. That is, when one of the first fuse pattern 130 and the second fuse pattern 140 is undercut under the first insulating layer 150, only one of the first air gap 170 or the second air gap 175 is provided. This can be formed. Alternatively, even when both of the first fuse pattern 130 and the second fuse pattern 140 are undercut under the first insulating layer 150, a portion of the insulating material 160 is inserted into the undercut portion, whereby the first fuse pattern In contact with one of the 130 and the second fuse patterns 140, only one of the first air gap 170 or the second air gap 175 may be formed. That is, the semiconductor device 40 may include air gaps 170 and 175 formed between at least one of the first fuse pattern 130 and the conductive particles 180 and between the second fuse pattern 140 and the conductive particles 180. It may include.

A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIGS. 11 and 12. Since the present embodiment is substantially the same as the above-described second embodiment except that it includes a spacer, overlapping portions are simplified or omitted.

11 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. 12 is a diagram for explaining the semiconductor device of FIG. 11 after assembly.

Referring to FIG. 11, the semiconductor device 50 may include a first fuse pattern 130, a second fuse pattern 140, a first spacer 190, a second spacer 195, and a first insulating layer 150. do.

The first spacer 190 may be formed between the first fuse pattern 130 and the opening 155, and the second spacer 195 may be formed between the second fuse pattern 140 and the opening 155. When one of the first fuse pattern 130 and the second fuse pattern 140 is undercut, only one of the first spacer 190 and the second spacer 195 may be formed. The first spacer 190 is disposed in a space in which the first fuse pattern 130 is undercut under the first insulating layer 150, and the second spacer 195 has the second fuse pattern 140. 150 may be disposed in a space formed undercut. That is, the first spacer 190 and the second spacer 195 may be formed between the third insulating film 104 and the first insulating film 150.

As the first spacer 190 is formed, a first air gap 170 is formed between the first spacer 190 and the first fuse pattern 130, and the second spacer 195 and the second fuse pattern 140 are formed. The second air gap 175 may be formed between the two sides. In the semiconductor device according to the fifth embodiment of the present invention, the first air gap 170 and the second air gap 175 are illustrated as being formed, but are not limited thereto. When the first fuse pattern 130 and the second fuse pattern 140 are undercut to each other under the first insulating layer 150, one of the fuse patterns 130 and 140 may be one of the spacers 190 and 195. Contact with At this time, an air gap is formed between the fuse pattern and the spacer which are not in contact with each other. Therefore, the semiconductor device 50 including the first spacer 190 and the second spacer 195 may include at least one of the first air gap 170 and the second air gap 175 formed under the first insulating layer 150. It may include one.

The first spacer 190 and the second spacer may include an insulating material, for example. Specifically, the first spacer 190 and the second spacer 195 include photosensitive polyamide (PSPI; Photo Sensitive Polyimide), polyamide (PI, Polyimide), photosensitive polyhydroxystyrene, and the like. It may be, but is not limited thereto. In the manufacturing process, since the first spacer 190 and the second spacer 195 may be formed after the undercut is formed under the first insulating layer 150, the first spacer 190 and the second spacer 195 may be formed. The flowable insulating material may be formed by curing.

Referring to FIG. 12, the semiconductor device 50 may further include an insulating material 160 including a first portion 162 and a second portion 164. The first portion 162 of the insulating material may be formed between the first spacer 190 and the second spacer 195 through the opening 155. The first spacer 190 and the second spacer 195 are formed in contact with the insulating material 160.

In other words, a first spacer 190 is formed between the first fuse pattern 130 and the insulating material 160, and a second spacer 195 is formed between the second fuse pattern 140 and the insulating material 160. Can be formed. Since one of the first spacer 190 and the second spacer 195 may be formed, between the first fuse pattern 130 and the insulating material 160 and between the second fuse pattern 140 and the insulating material 160. Spacers 190 and 195 may be formed in at least one of the spaces therebetween.

A first air gap 170 is formed between the first fuse pattern 130 and the first portion 162 of the insulating material, and between the second fuse pattern 140 and the first portion 162 of the insulating material. 2 air gaps 175 are formed. In other words, the first air gap 170 may be formed between the first fuse pattern 130 and the first spacer 190, and the second air gap 175 may include the second fuse pattern 140 and the second spacer ( 195).

A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIGS. 13 to 15.

13 is a diagram for describing a semiconductor device according to example embodiments of the present inventive concepts. 14 is a plan view of FIG. 13. FIG. 15 is a diagram for describing the semiconductor device of FIG. 13 after assembly. FIG.

Referring to FIG. 13, the semiconductor device 60 may include a substrate 100, a first metal wire 120, a second metal wire 122, a first fuse pattern 130, a second fuse pattern 140, and a second material. One insulating film 150 is included.

The first circuit pattern 105 and the second circuit pattern 110 may be formed on the substrate 100. The first metal wire 120 and the second metal wire 122 may be formed on the second insulating layer 102, and may be electrically connected to the first circuit pattern 105 and the second circuit pattern 110, respectively. In addition, the first fuse pattern 130 and the second fuse pattern 140 are formed on the second insulating film 102, respectively, and are electrically connected to the first metal wire 120 and the second metal wire 122, respectively. do. That is, the first metal wire 120, the second metal wire 122, the first fuse pattern 130, and the second fuse pattern 140 are all formed on the second insulating layer 102. Specifically, the first metal wiring 120, the second metal wiring 122, the first fuse pattern 130, and the second fuse pattern 140 are each spaced apart from the substrate 100 by the same distance, and thus, the second insulating film. Can be formed on 102.

This is a difference from the first to fifth embodiments of the present invention described above. In the first to fifth embodiments of the present invention, the fuse patterns 130 and 140 and the first and second metal wires 120 and 122 are formed at different distances from the substrate 100. However, in the sixth exemplary embodiment of the present invention, the fuse patterns 130 and 140 and the first metal wire 120 and the second metal wire 122 are separated from the substrate 100 by the same distance.

The first insulating layer 150 is formed on the first and second metal wires 120 and 122, the first fuse pattern 130, and the second fuse pattern 140. The first insulating layer 150 includes an opening 155 formed between the first fuse pattern 130 and the second fuse pattern 140. Since the relationship between the component, the opening 155, and the fuse patterns 130 and 140 of the semiconductor device 60 overlaps with the above-described embodiment, a description thereof will be omitted below.

Referring to FIG. 14, the first fuse pattern 130 and the first metal wire 120 are connected, and the second fuse pattern 140 and the second metal wire 122 are connected. An opening 155 formed in the first insulating layer 150 is disposed between the first fuse pattern 130 and the second fuse pattern 140.

An area 170a in which the first fuse pattern 130 is undercut is positioned between the opening 155 and the first fuse pattern 130, and a second fuse pattern is formed between the opening 155 and the second fuse pattern 140. An area 175a undercut 140 is positioned.

In the semiconductor device 60 according to the sixth embodiment of the present invention, the first fuse pattern 130 is directly connected to the first metal wire 120, and the second fuse pattern 140 is the second metal wire 122. Is shown to be directly connected to, but is not limited thereto.

Referring to FIG. 15, the semiconductor device 60 may further include an insulating material 160 including a first portion 162 and a second portion 164. The insulating material 160 is formed between the first fuse pattern 130 and the second fuse pattern 140. A first air gap 170 is formed between the first fuse pattern 130 and the insulating material 160, and a second air gap 175 is formed between the second fuse pattern 140 and the insulating material 160. do.

16 is a block diagram of a memory card including a semiconductor device according to example embodiments.

Referring to FIG. 16, a memory 1210 including a semiconductor device according to various embodiments of the present disclosure may be employed in a memory card 1200. The memory card 1200 may include a memory controller 1220 that controls data exchange between the host 1230 and the memory 1210. The SRAM 1221 may be used as an operating memory of the central processing unit 1222. The host interface 1223 may include a protocol for the host 1230 to access the memory card 1200 and exchange data. The error correction code 1224 may detect and correct an error in data read from the memory 1210. The memory interface 1225 may interface with the memory 1210. The CPU 1222 may perform an overall control operation related to data exchange of the memory controller 1220.

17 is a block diagram of an information processing system using a semiconductor device according to example embodiments.

Referring to FIG. 17, the information processing system 1300 may include a memory system 1310 including a semiconductor device according to various embodiments of the present disclosure. The information processing system 1300 may include a memory system 1310, a modem 1320, a central processing unit 1330, a RAM 1340, and a user interface 1350, electrically connected to the system bus 1360. Can be. The memory system 1310 may include a memory 1311 and a memory controller 1312, and may have substantially the same configuration as the memory card 1200 illustrated in FIG. 9. Data processed by the central processing unit 1330 or data received from an external device may be stored in the memory system 1310. The information processing system 1300 may be applied to memory cards, SSDs, camera image sensors, and various other chipsets. For example, the memory system 1310 may be configured such that an SSD is employed, and in this case, the information processing system 1300 may process a large amount of data stably and reliably.

18 is a block diagram of an electronic device including a semiconductor device according to some example embodiments of the inventive concepts.

Referring to FIG. 18, the electronic device 1400 may include a semiconductor device manufactured according to various embodiments of the present disclosure. The electronic device 1400 may be used in a wireless communication device (eg, PDA, notebook, portable computer, web tablet, cordless phone, and / or wireless digital music player) or various devices that transmit and receive information in a wireless communication environment. have.

The electronic device 1400 may include a controller 1410, an input / output device 1420, a memory 1430, and a wireless interface 1440. The memory 1430 may include a semiconductor device manufactured according to various embodiments of the present disclosure. The controller 1410 may include a microprocessor, a digital signal processor, or a similar processor. The memory 1430 may be used to store a command (or user data) processed by the controller 1410. The air interface 1440 may be used to exchange data over a wireless data network. The air interface 1440 may include an antenna and / or a wireless transceiver. The electronic device 1400 may use, for example, a third generation communication system protocol such as CDMA, GSM, NADC, E-TDMA, WCDMA, CDMA2000.

Although embodiments of the present invention have been described above with reference to the accompanying drawings, those skilled in the art to which the present invention pertains may implement the present invention in other specific forms without changing the technical spirit or essential features thereof. I can understand that. Therefore, it should be understood that the embodiments described above are exemplary in all respects and not restrictive.

100: substrate 105, 110: circuit pattern
120, 122: metal wiring 125, 127: via
130 and 140: fuse patterns 132 and 142: barrier metal film
150: insulating film 155: opening
160: insulating material 170, 175: air gap
180: conductive particles 190, 195: spacer

Claims

Board;
A first fuse pattern and a second fuse pattern formed on the substrate, the first fuse pattern and the second fuse pattern spaced apart from each other by a first width;
A first insulating film formed on the first fuse pattern and the second fuse pattern, the first insulating film including an opening having a second width smaller than the first width;
An insulating material formed between the first fuse pattern and the second fuse pattern; And
And an air gap formed between at least one of the first fuse pattern, the first insulating film, and the insulating material, and at least one of the second fuse pattern, the first insulating film, and the insulating material.

According to claim 1,
And at least one of the first fuse pattern and the second fuse pattern is undercut under the first insulating layer.

According to claim 1,
And the opening is non-overlapping with at least one of the first fuse pattern and the second fuse pattern.

delete

According to claim 1,
The air gap includes a first air gap and a second air gap,
The first air gap is formed between the first fuse pattern and the insulating material, and the second air gap is formed between the second fuse pattern and the insulating material.

According to claim 1,
A second insulating layer formed under the first fuse pattern and the second fuse pattern;
And the second insulating layer includes a trench overlapping the opening.

According to claim 1,
The semiconductor device further comprises conductive particles formed between the first fuse pattern and the second fuse pattern.

The method of claim 8,
And an air gap formed between the first fuse pattern and the conductive particles and between the second fuse pattern and the conductive particles.

According to claim 1,
And a spacer formed between at least one of the first fuse pattern and the opening and between the second fuse pattern and the opening.

The method of claim 10,
The spacer includes a first spacer and a second spacer,
Further comprising a first air gap formed between the first spacer and the first fuse pattern,
And a second air gap formed between the second spacer and the second fuse pattern.

According to claim 1,
Further comprising a first metal wiring and a second metal wiring formed under the first fuse pattern and the second fuse pattern,
And the first metal wire is electrically connected to the first fuse pattern through a first via, and the second metal wire is electrically connected to the second fuse pattern through a second via.

According to claim 1,
A first metal wire electrically connected to the first fuse pattern, and a second metal wire electrically connected to the second fuse pattern;
The first fuse pattern, the second fuse pattern, the first metal wiring, and the second metal wiring are formed to be spaced apart from the substrate by the same distance.

According to claim 1,
The method may further include a first circuit pattern and a second circuit pattern formed under the first fuse pattern and the second fuse pattern.
The first fuse pattern is electrically connected to the first circuit pattern, and the second fuse pattern is electrically connected to the second circuit pattern.

Board;
A first fuse pattern and a second fuse pattern formed on the substrate and spaced apart from each other;
A first insulating layer formed on the first fuse pattern and the second fuse pattern, the first insulating layer including an opening formed between the first fuse pattern and the second fuse pattern;
An insulating material formed between the first fuse pattern and the second fuse pattern; And
And an air gap formed between at least one of the first fuse pattern, the first insulating film, and the insulating material, and at least one of the second fuse pattern, the first insulating film, and the insulating material.

The method of claim 15,
The width of the first fuse pattern and the second fuse pattern is greater than the width of the opening.

The method of claim 15,
The air gap includes a first air gap and a second air gap,
The first air gap is formed between the first fuse pattern and the insulating material, and the second air gap is formed between the second fuse pattern and the insulating material.

The method of claim 15,
A second insulating layer formed under the first fuse pattern and the second fuse pattern;
And the second insulating layer includes a trench overlapping the opening.

The method of claim 15,
Further comprising conductive particles formed between the first fuse pattern and the second fuse pattern,
And the conductive particles are surrounded by the insulating material.

Board;
A first fuse pattern and a second fuse pattern formed on the substrate and spaced apart from each other;
An insulating layer formed on the first fuse pattern and the second fuse pattern and including an opening formed between the first fuse pattern and the second fuse pattern; And
It includes an insulating material formed between the first fuse pattern and the second fuse pattern,
At least one of the first fuse pattern and the second fuse pattern is undercut under the insulating film to define an air gap together with the insulating film and the insulating material.