KR101972167B1 - Semiconductor memory device and operating method thereof - Google Patents

Abstract

The present invention relates to a semiconductor memory device. A method of operating a semiconductor memory device according to an embodiment of the present invention includes the steps of: during an erase voltage applied to a bulk region corresponding to a selected memory block, rising until a voltage level is reached at a word line connected to the selected memory block And applying a word line voltage.

Description

Technical Field [0001] The present invention relates to a semiconductor memory device and a method of operating the same,

The present invention relates to a semiconductor memory device.

Semiconductor memory is a memory device implemented using semiconductors such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP) Semiconductor memory is divided into volatile memory and nonvolatile memory.

The volatile memory is a memory device in which the stored data is lost when the power supply is interrupted. Volatile memories include SRAM (Static RAM), DRAM (Dynamic RAM), and SDRAM (Synchronous DRAM). A nonvolatile memory is a memory device that retains data that has been stored even when the power supply is turned off. The non-volatile memory includes a ROM (Read Only Memory), a PROM (Programmable ROM), an EPROM (Electrically Programmable ROM), an EEPROM (Electrically Erasable and Programmable ROM), a flash memory, a PRAM RRAM (Resistive RAM), and FRAM (Ferroelectric RAM). Flash memory is divided into NOR type and NOR type.

A high voltage is applied to the bulk region of the memory cells in the erasing operation of the semiconductor memory device, for example, the flash memory device. Due to such a high voltage, the memory cells of the semiconductor memory device deteriorate as the erase operation is repeated.

An embodiment of the present invention is intended to reduce deterioration of memory cells of a semiconductor memory device.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes applying an erase voltage to a bulk region corresponding to a selected memory block; And applying a word line voltage that rises until a certain voltage level is reached in the word lines connected to the selected memory block while the erase voltage is applied.

In an embodiment, the word line voltage rises together when the erase voltage rises.

As an embodiment, the rising slope of the word line voltage may be less than the rising slope of the erase voltage.

In an embodiment, the particular voltage level may be less than the target voltage level of the erase voltage.

Another aspect of the present invention relates to a semiconductor memory device. A semiconductor memory device according to an embodiment of the present invention includes: a memory cell array including a plurality of memory blocks located on a bulk region; And applying an erase voltage to the bulk region and applying a word line voltage rising until a voltage level is reached at a word line of a selected one of the plurality of memory blocks while the erase voltage is applied, Lt; / RTI >

In an embodiment, the word line voltage rises together when the erase voltage rises.

As an embodiment, the rising slope of the word line voltage may be less than the rising slope of the erase voltage.

In an embodiment, the particular voltage level may be less than the target voltage level of the erase voltage.

According to the embodiment of the present invention, deterioration of memory cells of the semiconductor memory device is reduced.

BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the drawings recited in the Detailed Description of the Invention, a brief description of each drawing is provided below.
1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.
FIG. 2 is a circuit diagram showing one of the plurality of memory blocks of FIG. 1. FIG.
3 is a cross-sectional view of one of the memory cells of FIG.
4 is a table showing the voltages applied to the row lines and the bulk region in the erase operation.
5 is a graph showing an erase voltage and a word line voltage according to an embodiment of the present invention.
6 is a graph showing an erase voltage and a word line voltage according to another embodiment of the present invention.
7 is a graph showing an erase voltage and a word line voltage according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish it, will be described with reference to the embodiments described in detail below with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. The embodiments are provided so that those skilled in the art can easily carry out the technical idea of the present invention to those skilled in the art.

Throughout the specification, when a part is referred to as being "connected" to another part, it includes not only "directly connected" but also "indirectly connected" . Throughout the specification, when an element is referred to as " comprising ", it means that it can include other elements as well, without excluding other elements unless specifically stated otherwise.

1 is a block diagram showing a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device 100 includes a memory cell array 110 and peripheral circuits 120 for driving the memory cell array 110.

The memory cell array 110 is connected to the address decoder 121 via the row lines RL and to the read and write circuit 123 via the bit lines BL. The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz include a plurality of memory cells. In an exemplary embodiment, the plurality of memory cells are non-volatile memory cells. In an exemplary embodiment, each of the plurality of memory cells may be a single level cell or a multi level cell.

The peripheral circuit 120 drives the memory cell array 110. The peripheral circuit 120 includes an address decoder 121, a voltage generator 122, a read and write circuit 123 and control logic 124.

The address decoder 121 is connected to the memory cell array 110 via the row lines RL. The row lines RL include drain select lines, word lines, source select lines, and a common source line. The address decoder 121 is configured to operate in response to control of the control logic 124. The address decoder 121 receives an address ADDR from an input / output buffer (not shown) in the external or semiconductor memory device 100.

The address decoder 121 is configured to decode the block address of the received address ADDR. The address decoder 121 selects at least one memory block according to the decoded block address.

In the program operation and the read operation, the address decoder 121 is configured to decode the row address of the received address ADDR. The address decoder 121 will select one of the word lines according to the decoded row address. The address decoder 121 will decode the column address of the received address ADDR and transmit the decoded column address Yi to the read and write circuit 123, for example during a read operation.

In an exemplary embodiment, the address decoder 121 may include a block decoder, a row decoder, a column decoder, an address buffer, and so on.

The voltage generator 122 is configured to generate a plurality of voltages using the power supply voltage supplied to the semiconductor memory device 100. The voltage generator 122 operates in response to control of the control logic 124. In an exemplary embodiment, the voltage generator 122 includes a plurality of pumping capacitors, and may selectively activate a plurality of pumping capacitors to generate a plurality of voltages.

In an erase operation, the voltage generator 122 is configured to generate an erase voltage Vers to be applied to the bulk region of the memory cell array 110, and a word line voltage Vwl to be applied to the word lines.

In the erase operation, the erase voltage Vers generated in the voltage generator 122 is applied to the bulk region of the memory cell array 110. When the erase voltage Vers is applied to the bulk region, the address decoder 121 applies the word line voltage Vwl provided from the voltage generator 122 to the word lines connected to the selected memory block, Thereby flaoting the connected word lines WL.

According to an embodiment of the present invention, the word line voltage Vwl is a positive voltage. The word line voltage Vwl rises until a specific voltage level is reached while the erasing voltage Vers is applied. At this time, the word line voltage Vwl may rise together when the erase voltage Vers rises. This will be described in more detail with reference to Figures 5-7.

The read and write circuit 123 is connected to the plurality of memory blocks BLK1 to BLKz via the bit lines BL. The read and write circuit 123 operates in response to control of the control logic 124.

In the program operation and the read operation, the read and write circuit 123 exchanges data (DATA) with the input / output buffer (not shown) of the external or semiconductor memory device 100. At the time of programming, the read and write circuit 123 receives the data (DATA) and programs the received data (DATA) into the memory cells of the selected word line. In a read operation, the read and write circuit 130 reads data from the memory cells of the selected word line and outputs data (DATA) corresponding to the decoded column address Yi in the read data.

As an example embodiment, the read and write circuitry 130 may include page buffers (or page registers), column select circuitry, and the like.

The control logic 124 is coupled to an address decoder 121, a voltage generator 122 and a read and write circuit 123. The control logic 124 receives the control signal CTRL from the input or output buffer (not shown) of the external or semiconductor memory device 100. The control logic 124 is configured to control all operations of the semiconductor memory device 100 in response to the control signal CTRL.

The semiconductor memory device 100 may further include an input / output buffer (not shown). The input / output buffer will operate in response to control of the control logic 124. The input / output buffer will receive the control signal CTRL and address ADDR from the outside and deliver the received control signal CTRL and address ADDR to the control logic 124 and address decoder 121, respectively. The input / output buffer may be configured to transfer data (DATA) from the outside to the read / write circuit 123 and to transfer the data (DATA) from the read / write circuit 123 to the outside.

As an exemplary embodiment, the semiconductor memory device 100 may be a flash memory device.

2 is a circuit diagram showing one of the plurality of memory blocks BLK1 to BLKz (BLK1) of FIG.

Referring to FIGS. 1 and 2, the first memory block BLK1 includes a plurality of memory cells. The memory cells arranged in one column form one cell string. One cell string includes a source select transistor (SST), first to nth memory cells (M1 to Mn), and a drain select transistor (DST).

One memory block BLK1 is connected to the address decoder 121 via the common source line CSL, the source select line SSL, the first through the n th word lines WL1 through WLn, and the drain select line DSL. . The row lines RL described with reference to FIG. 1 are the same as the common source line CSL, the source select line SSL, the first to the nth word lines WL1 to WLn, and the drain select line DSL ). Source select transistors (e.g., SST) are connected to a source select line (SSL). In each word line, memory cells arranged in the row direction are connected. A drain select transistor DST is connected to the drain select line DSL. The common source line CSL is commonly connected to the plurality of memory blocks BLK1 to BLKz. One memory block BLK1 is connected to the first to m-th bit lines BL1 to BLm. Each bit line is connected to each cell string. That is, memory cells arranged in the column direction are connected to each bit line.

The first to m-th bit lines BL1 to BLm may be commonly connected to the first to z-th memory blocks BLK1 to BLKz.

The memory cells connected to one word line constitute at least one page. The program operation and the read operation of the semiconductor memory device 100 may be performed page by page. The erase operation of the semiconductor memory device 100 may be performed on a memory block basis.

3 is a cross-sectional view of any one of the memory cells M1 to Mn of FIG.

3, the third memory cell M3 includes a corresponding bulk region 210, n well regions 220 and 230 disposed in the bulk region 210 and doped with n-type conductivity dopants, And a floating gate 240 and a control gate 250 sequentially disposed on the bulk region 210. A tunnel insulating layer (TIL) is disposed between the bulk region 210 and the floating gate 240. The control gate 250 is connected to the third word line WL3. The bulk region 210 may be a region doped with a p-type dopant. For example, the memory cell array 110 (see FIG. 1) may be formed in a triple well structure, and the bulk region 210 may be included in a pocket p-well.

A plurality of electrons are trapped in the floating gate 240 according to the program state. 3, the word line voltage Vwl is applied to the control gate 250 and the erase voltage Vers is applied to the bulk region 210 so that electrons of the floating gate 240 And moves to the bulk region 210. The erase voltage Vers will rise from, for example, the ground voltage to reach the target voltage level. The target voltage level of the erase voltage Vers will be a high voltage (e.g., 20V).

It is assumed that the word line voltage Vwl is the ground voltage and the erase voltage Vers gently rises from the ground voltage to reach the target voltage level. Electrons of the floating gate 240 move to the bulk region 210 through the tunnel insulating film TIL not only at the time when the erase voltage Vers reaches the target voltage level but also before the erase voltage Vers reaches the target voltage level will be. Since the erase voltage Vers gently rises, the amount of current flowing per unit time through the tunnel insulating film TIL will be relatively small. The stress induced in the tunnel insulating film (TIL) will also be relatively small. The electric field induced in the tunnel insulating film (TIL) will also be relatively small. However, in this case, since the erase voltage Vers reaches the target voltage level for a long time, the erase operation speed will increase.

It is assumed that the word line voltage Vwl is the ground voltage and the erase voltage Vers rises sharply from the ground voltage to reach the target voltage level. That is, the time at which the erase voltage Vers reaches the target voltage level from the ground voltage will be relatively short. The electrons of the floating gate 240 will move abruptly to the bulk region 210 through the tunnel insulating film TIL. When the erase voltage Vers rapidly increases, the amount of current flowing per unit time through the tunnel insulating film TIL will be relatively large. The stress induced in the tunnel insulating film (TIL) will be relatively large. The electric field induced in the tunnel insulating film (TIL) will be relatively large. Therefore, the third memory cell M3 will easily deteriorate. However, in this case, since the time for which the erase voltage Vers reaches the target voltage level is short, the erase operation speed will be reduced.

As a result, the erase operation speed is improved as the erase voltage Vers rapidly rises, while the memory cell M3 will easily deteriorate.

According to the embodiment of the present invention, while the erase voltage Vers is applied, the word line voltage Vw1 applied to the word lines WL1 to WLn (see FIG. 2) rises until a specific voltage level is reached . Even if the erase voltage Vers rises abruptly, the word line voltage Vwl also increases together, so that the stress caused in the memory cells can be reduced. The rising word line voltage Vwl compensates for the erasing voltage Vers which rises sharply. In addition, the erase operation speed can be improved when the erase voltage Vers rises sharply. As a result, according to the embodiment of the present invention, deterioration of memory cells due to the erase operation is reduced, and erase operation speed is improved.

4 is a table showing the voltages applied to the row lines (DSL, WL1 to WLn, SSL) and the bulk region in the erase operation.

1, 2, and 4, an erase voltage Vers is applied to the bulk region of the memory cell array 110. FIG. The word line voltage Vw1 is applied to the first to nth word lines WL1 to WLn. A selection voltage Vs is applied to the source selection line SSL and the drain selection line DSL. For example, the selection voltage Vs may be lower than the erasing voltage Vers and higher than the word line voltage Vwl. As another embodiment, the source select line (SSL) and the drain select line (DSL) can be floated without being supplied with the selection voltage (Vs). In addition, it will be appreciated that the source select line (SSL) and the drain select line (DSL) can be driven in a variety of ways.

5 is a graph showing an erase voltage Vers and a word line voltage Vwl according to an embodiment of the present invention. 6 is a graph showing an erase voltage Vers and a word line voltage Vwl2 according to another embodiment of the present invention. 7 is a graph showing an erase voltage Vers and a word line voltage Vw13 in accordance with another embodiment of the present invention.

Referring first to FIG. 5, first, the erase voltage Vers and the word line voltage Vwl are maintained at the ground voltage. At the first time t1, the erase voltage Vers begins to rise. Then, the word line voltage Vwl rises together when the erase voltage Vers rises. As an exemplary embodiment, the rising slope b of the word line voltage Vwl may be less than the rising slope a of the erasing voltage Vers.

At the second time t2, the erase voltage Vers reaches the first voltage level V1. The first voltage level V1 corresponds to the target voltage level. Thereafter, the erase voltage Vers is maintained at the first voltage level V1. The word line voltage Vwl reaches the second voltage level V2 at the second time t2. After that, the word lines WL1 to WLn (see FIG. 2) are discharged and the word line voltage Vw1 decreases.

In an exemplary embodiment, the erase voltage Vers and the word line voltage Vwl reach the first voltage level V1 and the second voltage level V2, respectively, at the same time t2, as shown in Fig. 5 . As an exemplary embodiment, the word line voltage Vwl may be discharged when the erase voltage Vers is maintained at the first voltage level Vl, as shown in Fig. The maximum value of the difference between the voltages applied to the bulk region (e. G., 210 in FIG. 3) and the control gate 250 of one memory cell (e.g., M3 in FIG. 3) The time point at which the word line voltage Vw1 decreases to reach the ground voltage, not at the time point when the word line voltage Vw1 reaches V1.

At the third time t3, the erase voltage Vers will decrease. In an exemplary embodiment, after the erase voltage Vers has decreased to reach the ground voltage, a verify operation will be performed to determine whether the erase has been normally performed.

According to an embodiment of the present invention, in the erase operation, the word line voltage Vwl rises until it reaches a certain voltage level V2 and is discharged. Thus, the erasing voltage Vers will prevent excessive stress from being caused to the memory cells. Thus, the deterioration of the memory cells due to the erase operation will be reduced.

On the other hand, the embodiment of the present invention is not limited to the case where the erase voltage Vers and the word line voltage Vwl reach the first voltage level V1 and the second voltage level V2 at the same time t2, respectively.

Referring to Fig. 6, the word line voltage Vwl2 reaches the third voltage level V3 at the second time t2. And the erase voltage Vers reaches the first voltage level V1 at the third time t3. That is, the word line voltage Vwl2 reaches the third voltage level V3 before the erase voltage Vers reaches the target voltage level V1, and the word line voltage Vwl2 may be discharged.

Referring next to FIG. 7, the erase voltage Vers reaches the first voltage level V1 at a second time t2. And the word line voltage Vw13 reaches the fourth voltage level V4 at the third time t3. That is, after the erase voltage Vers reaches the target voltage level V1, the word line voltage Vw13 reaches the fourth voltage level V4 and the word line voltage Vw13 can be discharged.

According to an embodiment of the present invention, the word line voltage rises until it reaches a certain voltage level and then is discharged. Thereby preventing excessive stress on the memory cells due to the erase voltage of the high voltage. Thus, the deterioration of the memory cells will be reduced.

While the invention has been shown and described with reference to certain preferred embodiments thereof, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by the equivalents of the claims of the present invention as well as the claims of the following.

110: memory cell array 120: peripheral circuit
121: address decoder 122: voltage generator
123: read and write circuit 124: control logic
210: bulk region 220, 230: n-well regions
240: floating gate 250: control gate
Vers: Erase voltage Vwl: Word line voltage

Claims (14)

A method of operating a semiconductor memory device comprising:
Applying an erase voltage to a bulk region corresponding to the selected memory block;
And applying a word line voltage that rises until a particular voltage level is reached while the erase voltage is applied to word lines connected to the selected memory block. The method according to claim 1,
Wherein the word line voltage rises together when the erase voltage rises. The method according to claim 1,
Wherein the rising slope of the word line voltage is less than the rising slope of the erase voltage. The method according to claim 1,
Wherein the specific voltage level is less than the target voltage level of the erase voltage. The method according to claim 1,
Wherein the word line voltage is discharged after reaching the specified voltage level while the erase voltage is applied. 6. The method of claim 5,
Wherein the word line voltage is discharged when the erase voltage rises to a target voltage level. The method according to claim 1,
Wherein the word line voltage reaches the particular voltage level when the erase voltage rises to reach a target voltage level. The method according to claim 1,
Wherein the word line voltage reaches the specific voltage level after the erase voltage rises to reach a target voltage level. The method according to claim 1,
Wherein the erase voltage reaches a target voltage level after the word line voltage reaches the particular voltage level. A memory cell array including a plurality of memory blocks located on a bulk region; And
Applying an erase voltage to the bulk region and applying a word line voltage rising until a specific voltage level is reached while the erase voltage is applied to word lines of a selected one of the plurality of memory blocks A semiconductor memory device comprising a peripheral circuit. 11. The method of claim 10,
And the word line voltage rises together when the erase voltage rises. 11. The method of claim 10,
Wherein a rising ramp of the word line voltage is smaller than a rising ramp of the erase voltage. 11. The method of claim 10,
Wherein the specific voltage level is smaller than a target voltage level of the erase voltage. 11. The method of claim 10,
And the word line voltage is discharged after reaching the specific voltage level.

Images