KR101936368B1 - Display device and method of fabricating the same - Google Patents

Abstract

The display device and the method of manufacturing the same according to the present invention are designed in a dual link structure for a narrow bezel so that the line width of the inclined wiring portion in which the link wiring is inclined is designed differently according to the specific resistance of each link wiring A first substrate divided into a display region and a non-display region disposed around the display region for improving image defects due to a resistance difference between neighboring link wirings without increasing the size of the bezel; A plurality of subpixels arranged in a matrix form in the display region and defined by intersecting a plurality of data lines and gate lines; A data driver and a gate driver arranged in the non-display area to drive data lines and gate lines of the subpixels; A link portion disposed in the non-display region, the link portion being divided into a vertical wiring portion arranged in a direction perpendicular to the data line and a sloped wiring portion extending from the vertical wiring portion toward a data line and inclined; A first data link line formed in the same layer as the data line and a second data link line formed in the same layer as the gate line; A data link wiring line formed by a second data link line formed; And a second substrate bonded to the first substrate, wherein the first data link wiring and the second data link wiring each have a different line width from the sloped wiring part to the vertical wiring part.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device using a dual link structure for implementing a narrow bezel and a method of manufacturing the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as a liquid crystal display (LCD), an organic light emitting display (OLED), and an electrophoretic display (EPD) has been increasing.

Such a display device is used in various fields such as a computer such as a notebook computer, a cellular phone, and the like in the field of consumer electronics such as a television (TV) and a video.

Hereinafter, the display device will be described in detail with reference to the drawings.

1 is a plan view schematically showing a general display device.

Referring to the drawings, the display device 10 described above includes a display region 20 in which a plurality of subpixels (not shown) arranged in a matrix are formed, and a display region 20 disposed around the display region 20, A non-display area in which the driving unit is located.

The driving unit includes a timing driver (not shown), a data driver 31 and a gate driver 32. At this time, the data driver 31 and the gate driver 32 are formed on a panel of the display device 10, and the timing driver is formed on a flexible circuit board (not shown) connected to the panel.

The structure of the general display device 10 configured as above is suitable for application to a landscape display mode in which the width of the screen in the horizontal direction is larger than the height in the vertical direction. However, It is considered that it is not suitable to apply to a portrait display mode in which a lot of information is displayed during use of the apparatus, for example, when a plurality of text files are opened and worked.

The general display device 10 includes a data driver 31 for applying a data signal to each data line (not shown) of a plurality of subpixels, Wiring 26 is required. As a result, the number of the data link wiring lines 26 is increased by the number of data lines required as the resolution increases, and the bezel width w0 of the display device 10 is increased. There is a need to find ways to improve.

Reference numeral 27 denotes a gate link wiring for applying a gate signal to each gate line of a plurality of subpixels. In the same manner, the number of gate line wirings 27 is increased by the number of necessary gate lines as the resolution increases.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and it is an object of the present invention to provide a display device which realizes a structure suitable for a vertical display mode and implements a narrow bezel by applying a dual link structure, The purpose is to provide.

Another object of the present invention is to provide a display device and a method of manufacturing the display device in which the resistance difference between neighboring link wirings is reduced in the dual link design.

Other objects and features of the present invention will be described in the following description of the invention and the claims.

According to an aspect of the present invention, there is provided a display device including a first substrate divided into a display region and a non-display region disposed around the display region; A plurality of subpixels arranged in a matrix form in the display region and defined by intersecting a plurality of data lines and gate lines; A data driver and a gate driver arranged in the non-display area to drive data lines and gate lines of the subpixels; A link portion disposed in the non-display region, the link portion being divided into a vertical wiring portion arranged in a direction perpendicular to the data line and a sloped wiring portion extending from the vertical wiring portion toward a data line and inclined; A first data link line formed in the same layer as the data line and a second data link line formed in the same layer as the gate line; A data link wiring line formed by a second data link line formed; And a second substrate bonded to the first substrate, wherein the first data link wiring and the second data link wiring each have a different line width from the sloped wiring part to the vertical wiring part.

In this case, the first data link wiring and the second data link wiring are alternately arranged according to the order of the data lines.

The line width of each of the first data link wiring and the second data link wiring is determined in consideration of a difference in resistivity between the first data link wiring and the second data link wiring.

In this case, if the specific resistance of the second data link wiring is larger than the specific resistance of the first data link wiring, the second data link wiring has a larger line width than the first data link wiring.

In this case, the second data link wiring has a line width equal to that of the first data link wiring in the vertical wiring portion, but has a line width larger than that of the first data link wiring in the inclined wiring portion.

The sub-pixel is divided into an upper sub-pixel and a lower sub-pixel located at the upper and lower portions of the display region, respectively. The data driver supplies data signals to the data lines of the upper sub- And a left data driver for applying a data signal to a data line of the lower sub-pixel through a data driver and a left data link wiring line.

In this case, the left and right data driver and gate driver are disposed in the driver on the lower side of the display area.

The left and right data link lines are divided into first left and right data link lines formed on the same layer as the data lines and second left and right data link lines formed on the same layer as the gate lines .

If the resistances of the second left and right data link wires are larger than the resistances of the first left and right data link wires, the second left and right data link wires are connected to the first left and right data link wires And has a large line width.

At this time, the second left and right data link wirings have the same line width as the first left and right data link wirings in the vertical wiring portion, while the sloped wiring portions have a larger line width than the first left and right data link wirings .

A manufacturing method of a display device of the present invention includes: providing a first substrate divided into a display area and a non-display area disposed around the display area; Forming a plurality of subpixels in a matrix form in the display area, the plurality of subpixels defining a plurality of data lines and gate lines crossing each other; Forming a data driver and a gate driver for driving the data lines and the gate lines of the subpixel in the non-display area; Forming a vertical wiring part formed in the non-display area in a direction perpendicular to the data line, and a link part extending in a vertical direction to the data line and separated from the vertical wiring part by a sloped wiring part arranged obliquely; A first data link line formed in the same layer as the data line and a second data line line formed in the same layer as the gate line and a second data link line formed in the same layer as the data line, Forming a data link wiring that is divided into data link wiring; And bonding the first substrate and the second substrate, wherein the first data link wiring and the second data link wiring each have a line width different from that of the vertical wiring portion in the inclined wiring portion .

In this case, the first data link wiring and the second data link wiring are alternately formed in the order of the data lines.

At this time, the line width of each of the first data link wiring and the second data link wiring is determined in consideration of a difference in resistivity between the first data link wiring and the second data link wiring.

In this case, if the specific resistance of the second data link wiring is larger than the specific resistance of the first data link wiring, the second data link wiring is formed to have a larger line width than the first data link wiring.

In this case, the second data link wiring is formed to have a line width equal to that of the first data link wiring in the vertical wiring portion, but to have a larger line width in the inclined wiring portion than the first data link wiring .

The sub-pixel is divided into an upper sub-pixel and a lower sub-pixel located at the upper and lower portions of the display region, respectively. The data driver supplies data signals to the data lines of the upper sub- And a left data driver for applying a data signal to a data line of the lower sub-pixel through a data driver and a left data link wiring line.

In this case, the left and right data driver and gate driver are formed in the driver on the lower side of the display area.

In this case, the left and right data link lines are formed so as to be divided into first left and right data link lines formed in the same layer as the data line, and second left and right data link lines formed in the same layer as the gate line .

If the resistances of the second left and right data link wires are larger than the resistances of the first left and right data link wires, the second left and right data link wires are connected to the first left and right data link wires And has a large line width.

At this time, the second left and right data link wirings have the same line width as the first left and right data link wirings in the vertical wiring portion, while the sloped wiring portions have a larger line width than the first left and right data link wirings Is formed.

As described above, according to the display device and the manufacturing method thereof according to the present invention, in the dual-link structure for the inner bezel, the line width of the inclined wiring portion in which the link wiring is inclined is designed differently according to the specific resistance of each link wiring, It is possible to improve the image defect due to the resistance difference between the neighboring link wirings without increasing the size.

1 is a plan view schematically showing a general display device;
2 is a plan view schematically showing a display device according to a first embodiment of the present invention;
FIG. 3 is a schematic view showing a part of a cross section of a link portion according to an AA line in the display device according to the first embodiment of the present invention shown in FIG. 2;
4 is a plan view schematically showing a display device according to a second embodiment of the present invention.
5 is a view schematically showing a part of a cross section of a link portion according to a BB line in the display device according to the second embodiment of the present invention shown in FIG.
FIGS. 6A and 6B are enlarged plan views of a part of a link portion in the display device according to the second embodiment of the present invention shown in FIG. 4; FIG.
7 is an enlarged plan view showing a part of a link wiring in a vertical wiring portion and a sloped wiring portion in the display device according to the second embodiment of the present invention shown in FIG.
8 is a plan view schematically showing a display device according to a third embodiment of the present invention.
FIGS. 9A and 9B are enlarged plan views of a part of a link portion in another display device according to a third embodiment of the present invention shown in FIG. 8; FIG.
10 is an enlarged plan view showing a part of a link wiring in a vertical wiring portion and a sloped wiring portion in another display device according to the third embodiment of the present invention shown in FIG.
11A to 11E are sectional views sequentially showing a manufacturing process of another display device according to the third embodiment of the present invention;
12 is a cross-sectional view schematically showing a structure of a liquid crystal display device according to the present invention.
13 is a cross-sectional view schematically showing a structure of an electrophoretic display device according to the present invention.

Hereinafter, preferred embodiments of a display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

2 is a plan view schematically showing a display device according to a first embodiment of the present invention.

3 is a view schematically showing a part of a cross section of a link portion taken along the line A-A in the display device according to the first embodiment of the present invention shown in FIG.

The display device 100 according to the first embodiment of the present invention includes a display region 120 in which a plurality of subpixels (not shown) are arranged in a matrix, And a non-display region in which a driving unit for driving the sub-pixel is located.

The display device 100 according to the first embodiment of the present invention is designed to have a structure suitable for application to a portrait display mode in which the vertical height of the screen is larger than the width of the horizontal direction . The vertical display mode is suitable for a case where a large number of text files are opened and operated, for example, a job requiring a large amount of information to be displayed during use of a mobile device such as a cellular phone or an e-book.

The driving unit includes a timing driver (not shown), data drivers 131L and 131R, a gate driver 132, and the like. The data drivers 131L and 131R and the gate driver 132 may be formed on a panel of the display device 100 and the timing driver may be formed on a flexible circuit board (not shown) connected to the panel. However, the present invention is not limited thereto.

The data drivers 131L and 131R include a left data driver 131L for applying a data signal to a lower sub pixel based on the center of the pixel part 120 and a right data driver 131L for applying a data signal to the upper sub pixel, And a driving unit 131R. However, the present invention is not limited thereto. The left data driver 131L may apply a data signal to the upper sub-pixel and the right data driver 131R may apply a data signal to the lower sub-pixel. In addition, the present invention may include one data driver to apply a data signal sequentially to all the sub-pixels of the pixel portion through the data driver.

At this time, the display device 100 includes a flat panel display device such as a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device.

Although not shown in detail in the drawings, the panel of the display device 100 includes a color filter substrate, which is a first substrate, and an array substrate 110, which is a second substrate, And a liquid crystal layer formed between the color filter substrate and the array substrate 110.

At this time, the color filter substrate may include a black matrix for separating the sub-color filter from the color filter composed of red, green, and blue sub-color filters and blocking light transmitted through the liquid crystal layer, And an overcoat layer formed on the top.

A gate line and a data line are vertically and horizontally arranged on the array substrate 110 to define a pixel region. A thin film transistor, which is a switching element, is formed in a crossing region of the gate line and the data line, that is, in a TFT region.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The thin film transistor includes a gate insulating film 115a for insulation between the gate electrode and the source / drain electrode, and a conductive channel between the source electrode and the drain electrode by a gate voltage supplied to the gate electrode Lt; / RTI > In addition, the thin film transistor includes a protective film 115b for insulation between the source / drain electrode and the pixel electrode.

The display device 100 according to the first embodiment of the present invention configured as described above includes a plurality of data link wirings 126L and 126R corresponding to the data lines for applying data signals to the respective data lines of the plurality of subpixels ). In addition, the display device 100 according to the first embodiment of the present invention requires a number of gate link wirings 127 corresponding to the gate lines in order to apply a gate signal to each gate line of a plurality of subpixels Do.

The data link wirings 126L and 126R and the gate link wirings 127 connect signals from the data drivers 131L and 131R and the gate driver 132 to the data lines and the gate lines of the display unit 120 And is disposed at an outer periphery of the pixel portion 120 to determine a bezel width w1.

At this time, the data link lines 126L and 126R are connected to the left data link line 126L and the right data driver 131R for applying a data signal to the data line of the lower sub-pixel through the left data driver 131L, And a right data link wiring 126R for applying a data signal to the data line of the upper sub-pixel. However, the present invention is not limited thereto. The left data link line 126L applies a data signal to the data line of the upper sub pixel through the left data driver 131L while the right data link line 126R applies the data signal to the data line of the upper sub pixel through the right data driver 131R And to apply the data signal to the data line of the lower sub-pixel. For example, when one data driver is provided as described above, the data link line may be disposed only on one side of the panel, and the data link line may be connected to the data line of the sub pixel of the pixel unit through the data driver. The data signal is applied.

In the display device 100 according to the first embodiment of the present invention configured as described above, the data drivers 131L and 131R and the gate driver 132 are disposed at the same positions, for example, below the pixel portion 120 The bezel width w1 on the left and right sides of the panel is reduced as compared with the conventional case while the bezels on the left and right sides have substantially the same width. However, the present invention is not limited thereto.

However, as the resolution increases, the number of data link lines increases by the number of data lines required. However, in the case of the first embodiment of the present invention, it is insufficient to fundamentally solve the problem. That is, in order to manufacture a slim panel, a narrow bezel width should be realized with the same resolution. Data link wiring is usually formed in one layer, and the minimum line pitch (p ) Is determined according to the TFT process capability.

Thus, by applying the dual link structure in which the data link wiring is formed not only in the data wiring layer (the layer where the data wiring is formed) but also in the gate wiring layer (the layer in which the gate wiring is formed), the same number of data- The width of the bezel of the display device can be drastically reduced. The second embodiment of the present invention will now be described in detail.

4 is a plan view schematically showing a display device according to a second embodiment of the present invention.

5 is a view schematically showing a part of a cross section of a link portion along a line B-B in the display device according to the second embodiment of the present invention shown in FIG.

At this time, the display device according to the second embodiment of the present invention has substantially the same constituent elements as those of the first embodiment of the present invention, except that the data link wiring has a dual link structure.

6A and 6B are enlarged plan views of a portion of the link portion in the display device according to the second embodiment of the present invention shown in FIG. 6A is an enlarged view of a portion L of the link portion located on the left side of the panel, and FIG. 6B is an enlarged view of a portion R of the link portion located on the right side of the panel.

7 is an enlarged plan view showing a part of a link wiring in the vertical wiring portion and the inclined wiring portion in the display device according to the second embodiment of the present invention shown in FIG.

In this case, the vertical wiring part indicates a link part area in which the data link wiring is arranged in a direction perpendicular to the data driver, and the inclined wiring part has a link part area in which the data link wiring of the vertical wiring part extends toward the pixel part and is inclined .

The display device 200 according to the second embodiment of the present invention includes a display area 220 in which a plurality of sub pixels (not shown) are arranged in a matrix, And a non-display region in which a driving unit for driving the sub-pixel is located.

Here, the display device 200 according to the second embodiment of the present invention is designed to have a structure suitable for application to the vertical display mode in the same manner as the display device according to the first embodiment of the present invention described above.

The driving unit includes a timing driver (not shown), data drivers 231L and 231R, a gate driver 232, and the like. The data drivers 231L and 231R and the gate driver 232 may be formed on a panel of the display device 200 and the timing driver may be formed on a flexible circuit board (not shown) connected to the panel. However, the present invention is not limited thereto.

The data drivers 231L and 231R include a left data driver 231L for applying a data signal to the lower sub-pixel with reference to the center of the pixel unit 220 and a right data driver 231L for applying a data signal to the upper sub- And a driving unit 231R. However, the present invention is not limited thereto. The left data driver 231L applies a data signal to the upper sub-pixel while the right data driver 231R applies a data signal to the lower sub-pixel. In addition, the present invention may include one data driver to apply a data signal sequentially to all the sub-pixels of the pixel portion through the data driver.

At this time, the display device 200 includes a flat panel display device such as a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device.

Although not shown in detail in the drawings, the panel of the display device 200 includes a color filter substrate, which is a first substrate, and an array substrate 210, which is a second substrate, And a liquid crystal layer formed between the color filter substrate and the array substrate 210.

At this time, the color filter substrate may include a black matrix for separating the sub-color filter from the color filter composed of red, green, and blue sub-color filters and blocking light transmitted through the liquid crystal layer, And an overcoat layer formed on the top.

A gate line and a data line are vertically and horizontally arranged on the array substrate 210 to define a pixel region. A thin film transistor, which is a switching element, is formed in a crossing region of the gate line and the data line, that is, a TFT region.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The thin film transistor includes a gate insulating layer 215a for insulation between the gate electrode and the source / drain electrode, and an active layer 215b for forming a conduction channel between the source electrode and the drain electrode by a gate voltage supplied to the gate electrode. . In addition, the thin film transistor includes a protective film 215b for insulation between the source / drain electrode and the pixel electrode.

The display device 200 according to the second embodiment of the present invention has the same number of data link lines 226L ', 226L', and 226L 'corresponding to the data lines in order to apply data signals to the respective data lines of the plurality of sub- 226L ", 226R ', 226R " In addition, in the display device 200 according to the second embodiment of the present invention, in order to apply a gate signal to each gate line of a plurality of sub-pixels, gate line wiring lines 227 corresponding to the number of gate lines are required Do.

The data link lines 226L ', 226L ", 226R', and 226R" are connected to the left data link lines 226L 'and 226L' for applying data signals to the data lines of the lower sub-pixels through the left data driver 231L, 226L "for applying data signals to the data lines of the upper sub-pixel through the right data driver 231R, and right data link lines 226R ', 226R" for applying data signals to the data lines of the upper sub-pixel through the right data driver 231R. However, the present invention is not limited thereto. The left data link lines 226L 'and 226L "apply data signals to the data lines of the upper sub-pixel through the left data driver 231L while the right data link lines 226R' and 226R" And the data signal may be applied to the data line of the lower sub-pixel through the right data driver 231R. For example, when one data driver is provided as described above, the data link line may be disposed only on one side of the panel, and the data link line may be connected to the data line of the sub pixel of the pixel unit through the data driver. The data signal is applied.

The left data link wirings 226L 'and 226L "include first left data link wirings 226L' formed in a data wiring layer in which data wirings (i.e., source electrodes, drain electrodes, data lines, And a second left data link wiring 226L "formed in a gate wiring layer on which gate wirings (i.e., gate electrodes and gate lines, etc.) are formed. The right data link wirings 226R 'and 226R "are connected to the first right data link wirings 226R' formed on the data wiring layer and the second right data link wirings 226R" .

In the display device 200 according to the second embodiment of the present invention, the data drivers 231L and 231R and the gate driver 232 are disposed at the same positions, for example, on the lower side of the pixel portion 220 The bezel width w2 on the left and right sides of the panel is reduced as compared with the conventional case while the bezels on the left and right sides have substantially the same width, Mode. However, the present invention is not limited thereto.

In addition, the display device 200 according to the second embodiment of the present invention has a dual-link structure in which not only a data wiring layer but also a data wiring wiring 226L ', 226L ", 226R', 226R" The same number of data link wires 226L ', 226L ", 226R', and 226R" can be designed in a link portion having a width smaller than that of the conventional one, so that the bezel width w2 is smaller than the bezel width w2 in the first embodiment . In other words, in the case of the second embodiment of the present invention, compared with the case of the first embodiment of the present invention in which the data link wiring is formed in one layer, different layers, specifically the data wiring layer and the gate wiring layer, 226L ", 226R ', 226R" by forming right data link wires 226L', 226R 'and second left and right data link wires 226L ", 226R" And the same number of data link wires 226L ', 226L ", 226R', and 226R "can be designed in a link portion having a width smaller than that of the conventional one.

However, the dual link structure using the two layers has a problem in that the distance between the two layers, that is, the first left and right data link wires 226L 'and 226R' and the second left and right data link wires 226L " The wiring widths of the first left and right data link wirings 226L 'and 226R' and the second left and right data link wirings 226L 'and 226R' should be determined in consideration of the resistance difference.

This is because when the difference in resistance between the first left and right data link wires 226L 'and 226R' and the second left and right data link wires 226L "and 226R" is large, distortion occurs in the signal, . Particularly, when the conductive materials constituting the two layers are different kinds of materials, the resistivities are different from each other. Therefore, when the same line width is designed, the signal distortion is larger.

In order to avoid such a problem, in the case of the second embodiment of the present invention, the linewidth is controlled by the ratio of the resistances between the two materials. For example, the conductive material of the gate wiring layer, that is, the second left and right data link wires 226L 226R ") is greater than the resistivity of the conductive material of the data wiring layer, i.e., the first left and right data link wiring lines 226L 'and 226R', the second left and right data link The wiring lines 226L "and 226R" are designed to have a larger line width than the first left and right data link wiring lines 226L 'and 226R'.

At this time, for example, the second left and right data link wires 226L " and 226R "are connected to the first left and right data link wires 226L 'and 226R' It is possible to design such that the line width is larger than the line width. However, in this case, the width of the bezel is increased by an increase in the line width of the second left and right data link wires 226L "and 226R" in the vertical wiring portion.

However, the present invention is not limited to this. In the vertical wiring portion for determining the bezel width, the line width of the data link wiring is designed to be the same, and in the sloped wiring portion having no influence on the bezel width, So that the resistance of the entire data link wiring can be compensated. This will be described in detail in the following third embodiment of the present invention.

8 is a plan view schematically showing a display device according to a third embodiment of the present invention.

The display device according to the third embodiment of the present invention is substantially the same as the second embodiment of the present invention except for the configuration of the data link wiring.

9A and 9B are enlarged plan views showing a part of the link portion in the display device according to the third embodiment of the present invention shown in FIG. 8A is an enlarged view of a portion of the link portion located on the left side of the panel, and FIG. 8B is an enlarged view of a portion of the link portion located on the right side of the panel, have.

10 is an enlarged plan view showing a part of the link wiring in the vertical wiring portion and the inclined wiring portion in the display device according to the third embodiment of the present invention shown in FIG. In this case, as described above, the vertical wiring part indicates a link part area where the data link wiring is arranged in a direction perpendicular to the data driver, and the inclined wiring part is arranged such that the data link wiring of the vertical wiring part extends toward the pixel part and is inclined Indicates a link sub area.

The display device 300 according to the third embodiment of the present invention includes a display region 320 in which a plurality of subpixels (not shown) are arranged in a matrix, And a non-display region in which a driving unit for driving the sub-pixel is located.

In this case, the display device 300 according to the third embodiment of the present invention is designed to have a structure suitable for application to the vertical display mode in the same manner as the display devices according to the first and second embodiments of the present invention.

The driving unit includes a timing driver (not shown), data drivers 331L and 331R, a gate driver 332, and a level shifter (not shown). The data drivers 331L and 331R and the gate driver 332 are formed on a panel of the display device 300. The timing driver may be formed on a flexible circuit board (not shown) An external system substrate connected to the substrate, or the like. However, the present invention is not limited thereto, and the timing driver may be formed together in the data drivers 331L and 331R.

The driving unit is mounted on a panel in the form of an integrated circuit (IC), and a flexible circuit board is attached to the panel. At this time, the panel and the flexible circuit board may be attached by an anisotropic conductive film (ACF).

The data driver 331L and 331R may include a left data driver 331L for applying a data signal to the lower sub-pixel with reference to the center of the pixel portion 320, And a right data driver 331R for applying a data signal to sub-pixels of the sub-pixel. However, the present invention is not limited thereto. The left data driver 331L may apply a data signal to the upper sub-pixel and the right data driver 331R may apply a data signal to the lower sub-pixel. In addition, the present invention may include one data driver to apply a data signal sequentially to all the sub-pixels of the pixel portion through the data driver.

At this time, the display device 300 includes a flat panel display device such as a liquid crystal display device, an organic light emitting display device, and an electrophoretic display device.

Although not shown in detail in the drawings, the panel of the display device 300 includes a color filter substrate, which is a first substrate, and an array substrate 310, which is a second substrate, And a liquid crystal layer formed between the color filter substrate and the array substrate 310.

At this time, the color filter substrate may include a black matrix for separating the sub-color filter from the color filter composed of red, green, and blue sub-color filters and blocking light transmitted through the liquid crystal layer, And an overcoat layer formed on the top.

A gate line and a data line are vertically and horizontally arranged on the array substrate 310 to define a pixel region. A thin film transistor, which is a switching element, is formed in a crossing region of the gate line and the data line, that is, a TFT region.

In order to apply a data signal to each data line of a plurality of subpixels, the display device 300 according to the third embodiment of the present invention has the same number of data link lines 326L ' 326L ", 326R ", and 326R " In addition, in the display device 300 according to the third embodiment of the present invention, in order to apply a gate signal to each gate line of a plurality of sub-pixels, gate line wirings 327 corresponding to the number of gate lines are required Do.

The data link lines 326L ', 326L ", 326R', and 326R" are connected to the data lines of the lower sub-pixels through the left data driver 331L in the same manner as in the second embodiment of the present invention, 326L "for applying a data signal to the data line of the upper sub-pixel through the right data driver 331R and the left data link lines 326L 'and 326L " . However, the present invention is not limited thereto. The left data link lines 326L 'and 326L "apply data signals to the data lines of the upper sub-pixel through the left data driver 331L while the right data link lines 326R' and 326R" And the data signal may be applied to the data line of the lower sub-pixel through the right data driver 331R. For example, when one data driver is provided as described above, the data link line may be disposed only on one side of the panel, and the data link line may be connected to the data line of the sub pixel of the pixel unit through the data driver. The data signal is applied.

The left data link wirings 326L 'and 326L "include first left data link wirings 326L' formed in a data wiring layer in which data wirings (i.e., source electrodes, drain electrodes, data lines, And a second left data link wiring 326L "formed in the gate wiring layer in which the gate wiring (that is, the gate electrode and the gate line and the like) is formed. The right data link lines 326R 'and 326R' 'are connected to the first right data link line 326R' formed in the data line layer and the second right data line line 326R '' formed in the gate line layer. .

In the display device 200 according to the third embodiment of the present invention, the data drivers 331L and 331R and the gate driver 332 are disposed at the same positions, for example, in the same manner as the second embodiment of the present invention The bezel width w3 at the left and right sides of the panel is reduced as compared with the conventional case by disposing the bezel on the lower side of the pixel portion 320 as shown in the figure, It is suitable for the vertical display mode as in the first and second embodiments of the present invention. However, the present invention is not limited thereto.

In addition, the display device 300 according to the third embodiment of the present invention includes the data wiring lines 326L ', 326L', 326R 326L ", 326R ', 326R") can be designed in a link portion having a width smaller than that of the conventional one, so that the width of the bezel (326R', 326R ' w3 are reduced compared to the first embodiment of the present invention. In other words, in the case of the third embodiment of the present invention, compared with the case of the first embodiment of the present invention in which the data link wiring is formed in one layer, different layers, specifically the data wiring layer and the gate wiring layer, 326L ", 326R ', 326R" by forming right data link wires 326L', 326R 'and second left and right data link wires 326L ", 326R" So that the same number of data link wires 326L ', 326L ", 326R', and 326R" can be designed in a link portion having a width smaller than that of the conventional one.

However, the dual-link structure using the two layers has a problem in that the distance between the two layers, that is, the first left and right data link wires 326L 'and 326R' and the second left and right data link wires 326L " The wiring widths of the first left and right data link wirings 326L 'and 326R' and the second left and right data link wirings 326L 'and 326R' should be determined in consideration of the resistance difference.

This is because when the resistance difference between the first left and right data link wires 326L 'and 326R' and the second left and right data link wires 326L "and 326R" is large, distortion occurs in the signal, . Particularly, when the conductive materials constituting the two layers are different kinds of materials, the resistivities are different from each other. Therefore, when the same line width is designed, the signal distortion is larger.

In order to avoid such a problem, in the case of the third embodiment of the present invention, the linewidth is controlled by the ratio of the resistances between two materials. For example, the conductive material of the gate wiring layer, that is, the second left and right data link wires 326L 326R ") is greater than the resistivity of the conductive material of the data wiring layer, that is, the first left and right data link wires 326L 'and 326R', the second left and right data links The wiring lines 326L "and 326R" are designed to have a larger line width than the first left and right data link wiring lines 326L 'and 326R'.

In the case of the third embodiment of the present invention, the second left and right data link wires 326L "and 326R" are formed only in the oblique wiring portions which do not affect the bezel width, unlike the second embodiment of the present invention described above. 326L ", 326R ', and 326R' in the vertical wiring portion for determining the bezel width while the data wiring wirings 326L 'and 326R' are designed to have a larger width than the first left and right data link wirings 326L 'and 326R' Quot;) are designed to have the same line width. Accordingly, the minimum space occupied by one data link wiring 326L ', 326L ", 326R', and 326R '' can be reduced more than that of the second embodiment of the present invention described above, so that the same number of data link wiring lines 326L ' 326L ", 326R ', and 326R ") can be designed in a link portion having a smaller width.

In the above embodiments, only the data link wiring is described, but the present invention is not limited thereto. In this case, if the resistivity of the second left and right gate link wiring is larger than the resistivity of the first left and right gate link wiring, then the present invention is applicable to a case where the gate wiring wiring has a dual- The left and right gate link wirings can be designed to have a larger line width than the first left and right gate link wirings.

Hereinafter, a manufacturing method of the display device constructed as above will be described in detail with reference to the drawings.

FIGS. 11A to 11E are cross-sectional views sequentially showing a manufacturing process of a display device according to a third embodiment of the present invention. In FIGS. 11A to 11E, the steps of manufacturing the array substrate for a liquid crystal display of the vertical wiring portion and the sloped wiring portion of the TFT region and the link portion of the pixel portion For example.

Here, for convenience of explanation, FIGS. 11A to 11E show the steps of manufacturing the vertical wiring portion and the inclined wiring portion of the link portion located on the left side of the panel, for example, the array substrate for a liquid crystal display device. However, the present invention is not limited thereto, and the present invention is also applicable to a case where a data link wiring is formed only on one side of a panel.

A gate electrode 321 and a gate line (not shown) are formed in a pixel portion of an array substrate 310 made of a transparent insulating material such as glass, The second left data link wiring 326L 'and the second right data link wiring (not shown) of the gate wiring layer are formed.

In this case, the gate electrode 321, the gate line, the second left data link wiring 326L 'and the second right data link wiring are formed by sequentially depositing a first conductive film on the entire surface of the array substrate 310 and then performing a photolithography process (A first mask process).

The first conductive layer may include at least one selected from the group consisting of aluminum (Al), aluminum alloy (Al alloy), tungsten (W), copper (Cu), chromium (Cr), molybdenum Or a low-resistance opaque conductive material such as an alloy or the like. The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

11B, a gate insulating film (not shown) is formed on the entire surface of the array substrate 310 on which the gate electrode 221, the gate line, the second left data link wiring 326L 'and the second right data link wiring are formed, 315a, amorphous silicon thin film and n + amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 324 made of the amorphous silicon thin film in the TFT region of the array substrate 310 do.

At this time, an n + amorphous silicon thin film pattern 325 patterned in substantially the same shape as the active layer 324 is formed on the active layer 324.

Next, as shown in FIG. 11C, a second conductive layer is formed on the entire surface of the array substrate 310 on which the active layer 324 and the n + amorphous silicon thin film pattern 325 are formed. The second conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, an aluminum alloy, tungsten, copper, chromium, molybdenum, or a molybdenum alloy. The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the second conductive film are selectively removed through a photolithography process (a third mask process), thereby forming the source electrode 322 and the drain electrode 322, which are the second conductive film, on the active layer 324, (323).

At this time, a data line (not shown) made of the second conductive film is formed in the data line region of the array substrate 310 through the third mask process, and a data line The first left data link wiring 326L "and the first right data link wiring (not shown) of the data wiring layer made of the conductive film are formed.

The first left and right data link wirings 326L 'and the second left and right data link wirings 326L "are formed alternately in the order of the data lines. In this case, for example, And the even-numbered data lines may be connected to the first left and right data link wirings 326L '. The odd-numbered data lines are connected to the second left and right data link wirings 326L ", and the even-numbered data lines are connected to the first left and right data link wirings 326L ' Numbered data line is connected to the first left data link line 326L 'and the second right data link line, and the even-numbered data line is connected to the second left data line line 326L ") and the first right data link wiring.

At this time, on the active layer 324, an ohmic contact layer 322 is formed of the n + amorphous silicon thin film and ohmic-contacted between the source / drain region of the active layer 324 and the source / drain electrodes 322 and 323. (325n) is formed.

Here, the active layer 324 and the data lines, that is, the source electrode 322, the drain electrode 323, the data line, the first left data link wiring 326L "and the first right data link wiring are subjected to two mask processes However, the present invention is not limited thereto. The active layer 324 and the data line may be formed by a single mask (not shown) by using diffraction exposure or half tone exposure, And the like.

11D, the front surface of the array substrate 310 on which the source / drain electrodes 322 and 323, the data line, the first left data link wiring 326L "and the first right data link wiring are formed is formed A protective film 315b is formed.

Then, the protective film 315b is selectively removed through a photolithography process (a fourth mask process) to form a contact hole 340 for exposing a part of the drain electrode 323 to the pixel portion of the array substrate 310 Respectively.

Next, as shown in FIG. 11E, a third conductive film made of a transparent conductive material is formed on the entire surface of the array substrate 310 on which the protective film 315b is formed, and then, using a photolithography process (fifth mask process) A pixel electrode 318 electrically connected to the drain electrode 323 through the contact hole 340 is formed in the pixel portion of the array substrate 310. [

The array substrate 310 configured as described above is adhered to the color filter substrate (not shown) by a sealant formed on the outer periphery of the image display region. At this time, the color filter substrate is provided with the thin film transistor, the gate line, A black matrix for preventing light from leaking, and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the array substrate 310 are attached to each other through a cemented key formed on the color filter substrate or the array substrate.

As described above, the present invention can be applied not only to liquid crystal display devices but also to other display devices manufactured using thin film transistors, for example, organic light emitting display devices and electrophoretic display devices.

12 is a cross-sectional view schematically showing a structure of a liquid crystal display device according to the present invention.

As shown in the figure, a liquid crystal display device 400 according to the present invention includes an array substrate 460, a color filter substrate 480, and a liquid crystal layer 490 interposed therebetween.

The array substrate 460 includes a gate line (not shown) and a data line (not shown) formed on the lower substrate 410 so as to cross each other with the gate insulating film 415a therebetween, a thin film And a pixel electrode 418 formed in a unit pixel defined in a crossing region of the transistor TFT and the gate line and the data line and electrically connected to the thin film transistor TFT.

At this time, the lower substrate 410 may be made of plastic having flexibility properties, and may be formed of, for example, polyacrylate, polyethylene ether phthalate, polyethylene naphthalate, polycarbonate, polyarylate, polyetherimide, And the like.

The thin film transistor TFT is superimposed on the gate electrode 421 to which the gate signal is supplied, the source electrode 422 connected to the data line, the drain electrode 423 connected to the pixel electrode 418, and the gate electrode 421 And a semiconductor layer 424 which forms a channel between the source electrode 422 and the drain electrode 423. [

The semiconductor layer 424 is formed to overlap with the source electrode 422 and the drain electrode 423 and further includes a channel portion between the source electrode 422 and the drain electrode 423. [ A source electrode 422 and a drain electrode 423 are formed on the semiconductor layer 424 and an ohmic contact layer 425n is formed for the ohmic contact.

The pixel electrode 418 is in contact with the drain electrode 423 through the contact hole that exposes the drain electrode 423 through the protective film 415b protecting the thin film transistor TFT.

The color filter substrate 480 disposed opposite to the array substrate 460 includes a black matrix 407 on the upper substrate 401, a color filter 406 located between the black matrix 407, a black matrix 407, An overcoat layer 405 covering the color filter 406 and a common electrode 408 located on the overcoat layer 405. [

At this time, the upper substrate 401 may be made of a flexible plastic like the lower substrate 410 described above.

The black matrix 407 may be made of an opaque organic material or an opaque metal to prevent light from being transmitted through an area where the liquid crystal layer 490 can not be controlled.

The overcoat layer 405 may be formed of a transparent organic material for protecting the color filter 406 and for good step coverage of the common electrode 408. The common electrode 408 is formed of a transparent metal such as indium-tin-oxide (ITO), indium-zinc-oxide (IZO) or the like and functions to apply a common voltage to the liquid crystal layer 490.

The liquid crystal layer 490 may be positioned between the display device array substrate 460 and the color filter substrate 480 as described above.

13 is a cross-sectional view schematically showing the structure of an electrophoretic display device according to the present invention.

As shown in the figure, an electrophoretic display device 500 according to the present invention includes an array substrate 560 and an opposite substrate 580.

The array substrate 560 includes a gate line (not shown) and a data line (not shown) formed on the lower substrate 510 so as to cross each other with a gate insulating film 515 interposed therebetween, a thin film And a pixel electrode 518 formed in a unit pixel defined in a crossing region of the gate line and the data line and electrically connected to the thin film transistor TFT.

At this time, the lower substrate 510 may be made of plastic having a flexible nature, and may be formed of, for example, polyacrylate, polyethylene ether phthalate, polyethylene naphthalate, polycarbonate, polyarylate, polyetherimide, polyether sulfone, , And the like.

The thin film transistor TFT is overlapped with the gate electrode 521 to which the gate signal is supplied, the source electrode 522 connected to the data line, the drain electrode 523 connected to the pixel electrode 518, and the gate electrode 521 And a semiconductor layer 524 that forms a channel between the source electrode 522 and the drain electrode 523. [

Here, the gate electrode 521 may be formed of, for example, aluminum (Al), copper (Cu), silver (Ag), molybdenum (Mo), chromium (Cr), titanium (Ti), tantalum And the like.

In addition, the gate electrode 521 may have a double-layer structure including two conductive films (not shown) having different physical properties. One of the conductive films may be formed of a metal having a low resistivity such as aluminum (or an alloy thereof), silver (or an alloy thereof), copper (or an alloy thereof), or the like, so as to reduce signal delay or voltage drop of the gate electrode 521. [ Alloy) or the like. The other conductive film may be made of a material having excellent contact properties with indium tin oxide (ITO), indium zinc oxide (IZO), or the like, for example, molybdenum, chromium, titanium, tantalum, or an alloy thereof. However, the present invention is not limited thereto, and the gate electrode 521 may be made of various metals and conductors. It is not limited to a bilayer structure, and may have a multilayer structure of three or more layers.

On the gate electrode 521, a gate insulating film 515a is formed. At this time, the gate insulating film 515a may be formed of an inorganic insulating film such as a silicon nitride film (SiNx), a silicon oxide film (SiO ₂ ), or a high dielectric oxide film such as hafnium (Hf) oxide or aluminum oxide.

The source electrode 522 and the drain electrode 523 may be formed of a material such as Al, Cu, Ag, Mo, Cr, Ti, Or alloys thereof, and the like. The source electrode 522 and the drain electrode 523 may have a double-layer structure or a triple-layer structure including two conductive layers (not shown) having different physical properties. However, the present invention is not limited thereto, and the source electrode 522 and the drain electrode 523 may have a multi-layer structure including various metals and conductors.

The semiconductor layer 524 is formed so as to overlap with the source electrode 522 and the drain electrode 523 and further includes a channel portion between the source electrode 522 and the drain electrode 523. [ A source electrode 522 and a drain electrode 523 may be formed on the semiconductor layer 524 and an ohmic contact layer 525n may be further formed for ohmic contact.

The pixel electrode 518 is in contact with the drain electrode 523 through the contact hole that exposes the drain electrode 523 through the protective film 515b protecting the thin film transistor TFT.

The counter substrate 580 disposed opposite to the array substrate 560 includes a common electrode 508 formed on the upper substrate 501 and an electrophoretic film 590 disposed on the common electrode 508.

At this time, the upper substrate 501 may be made of a flexible plastic like the lower substrate 510 described above.

The electrophoretic film 590 is composed of a capsule 592 containing charge pigment particles and upper and lower protective layers 509 and 519 located above and below the capsule 592 and a capsule 592, And a color filter 516 between the upper protective layer 519 and the lower protective layer 519.

Capsule 592 includes black dye particles 592a responsive to a positive voltage, white dye particles 592b responsive to a negative voltage, and solvent 592c.

The upper and lower protective layers 509 and 519 serve to block the flow of the spherical capsule 592 and to protect the capsule 592. The upper and lower protective layers 509 and 519 may be made of flexible plastic, easily bendable base film, or metal having flexibility.

The electrophoretic display device having such a configuration can be provided with a color filter 516 to realize color. In addition, flexibility can be maintained by using the upper substrate 501 having flexibility, which is not an upper glass substrate in the flat panel display panel.

Then, the array substrate 560 and the counter substrate 580 are bonded together by the lamination process using the adhesive 515c.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100, 200, 300: Display device 110, 210, 310:
120, 220,
126L, 226L ', 326L ": Left data link wiring
126R, 226R ', 226R ": Right data link wiring
131L, 231L, 331L, 131R, 231R, 331R:
132, 232,

Claims (21)

A first substrate divided into a display region and a non-display region disposed around the display region;
A plurality of subpixels arranged in a matrix form in the display region and defined by intersecting a plurality of data lines and gate lines;
A data driver and a gate driver arranged in the non-display area to drive data lines and gate lines of the subpixels;
A link portion disposed in the non-display region, the link portion being divided into a vertical wiring portion arranged in a direction perpendicular to the data line and a sloped wiring portion extending from the vertical wiring portion toward a data line and inclined;
A first data link line formed in the same layer as the data line and a second data link line formed in the same layer as the gate line; A data link wiring line formed by a second data link line formed; And
And a second substrate bonded to the first substrate,
And the second data link wiring has a line width larger than that of the vertical wiring portion in the inclined wiring portion. The display device according to claim 1, wherein the first data link wiring and the second data link wiring are alternately arranged in the order of the data lines. The display device according to claim 1, wherein a line width of each of the first data link wiring and the second data link wiring is determined in consideration of a difference in resistivity between the first data link wiring and the second data link wiring. The display device according to claim 3, wherein, in the inclined wiring portion, the second data link wiring has a larger line width than the first data link wiring. The display device according to claim 4, wherein the second data link wiring has the same line width as the first data link wiring in the vertical wiring part. The display device according to claim 1, wherein the subpixel is divided into an upper subpixel and a lower subpixel located at upper and lower portions of the display region, and the data driver is connected to the data line of the upper subpixel And a left data driver for applying a data signal to a data line of the lower sub-pixel through a left data link line and a right data driver for applying a data signal. 7. The display device according to claim 6, wherein the left and right data drivers and the gate driver are disposed in a driver on a lower side of the display area. delete delete delete Providing a first substrate, the first substrate being divided into a display region and a non-display region disposed around the display region;
Forming a plurality of subpixels in a matrix form in the display area, the plurality of subpixels defining a plurality of data lines and gate lines crossing each other;
Forming a data driver and a gate driver for driving the data lines and the gate lines of the subpixel in the non-display area;
A first data link line formed in the same layer as the data line and a second data line line formed in the same layer as the gate line and a second data link line formed in the same layer as the data line, Forming a data link wiring that is divided into data link wiring; And
And bonding the first substrate and the second substrate,
Wherein the second data link wiring includes a vertical wiring portion arranged in a direction perpendicular to the data line and a sloped wiring portion extending from the vertical wiring portion toward a data line and inclined,
And the second data link wiring has a line width larger than that of the vertical wiring portion in the inclined wiring portion. 12. The method according to claim 11, wherein the first data link wiring and the second data link wiring are alternately formed in the order of the data lines. The display device according to claim 12, characterized in that a line width of each of the first data link wiring and the second data link wiring is determined in consideration of a difference in resistivity between the first data link wiring and the second data link wiring ≪ / RTI > 14. The manufacturing method of a display device according to claim 13, wherein in the inclined wiring portion, the second data link wiring is formed to have a larger line width than the first data link wiring. 15. The manufacturing method of a display device according to claim 14, wherein the second data link wiring is formed so as to have the same line width as the first data link wiring in the vertical wiring part. The display device according to claim 11, wherein the subpixel is divided into an upper subpixel and a lower subpixel located at upper and lower portions of the display region, and the data driver is connected to the data line of the upper subpixel And a left data driver for applying a data signal to a data line of the lower sub-pixel through a left data link wiring and a right data driver for applying a data signal. The method of manufacturing a display device according to claim 16, wherein the left and right data driver and gate driver are formed in a driver on a lower side of the display area. delete delete delete A substrate divided into a display area and first and second non-display areas arranged around two adjacent sides of the display area;
A plurality of first signal lines and a plurality of second signal lines arranged in the display region and intersecting with each other to define a plurality of subpixels;
A first and a second driver arranged in the first non-display area and connected to the first and second signal lines, respectively;
And a sloped wiring part connected to the first driving part and each extending to the second non-display area and a sloped wiring part extending from the vertical wiring part to the display area and connected to two of the first signal lines, respectively 1 and a second link wiring,
Wherein the line widths of the first and second link wirings in the vertical wiring portion are the same and the line widths of the first and second link wirings in the inclined wiring portion are different from each other.

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