KR101934016B1 - Pulse driver and method for driving the same - Google Patents

Abstract

According to an embodiment of the present invention, a pulse driver comprises: a first stage receiving a first input pulse, and outputting an output pulse by being connected to or disconnected from a second stage according to a level of the first input pulse; and the second stage to an n^th stage (n is a natural number greater than or equal to two) receiving power, receiving a k^th input pulse from a k^th stage (k is a natural number between two and n), and enabling an m^th stage to be connected to or disconnected from an (m+1)^th stage according to a level of an m^th input pulse (m is a natural number between two and (n-1)). The output pulse is output by processing the power according to a connection state among the stages.

Description

[0001] Pulse driver and method for driving same [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse driver and a driving method thereof, and more particularly, to a pulse driver capable of adjusting the level of an output pulse with low power and a driving method thereof.

1 shows the configuration of a conventional pulse driver.

The pulse driver is a device for outputting a pulse of a constant level. Referring to FIG. 1, a conventional pulse driver includes a plurality of level converters LC1 and LC2 connected in a cascade manner to receive a clock signal CLK _in and adjust a level thereof, And a load capacitor C _load for charging the level-adjusted clock signal and outputting it as an output pulse CLK _out .

However, in the conventional pulse driver, not only the common power sources V _{dd and I O} inputted to the level converters LC1 and LC2 but also the high voltage additional power sources V _{dd and HV} ) Is also required. Accordingly, the conventional pulse driver generates an output pulse (CLK _out ), which has a problem in that power consumption is considerably large.

In addition, the conventional pulse driver is a method of outputting the output pulse CLK _out of a constant level. Accordingly, the conventional pulse driver can not be applied when the level of the output pulse CLK _out needs to be adjusted according to various situations.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a pulse driver and a driving method thereof that can output pulses at a low power and adjust the level as needed.

It is to be understood, however, that the present invention is not limited to the above-mentioned problems, and other problems that are not mentioned can be clearly understood by those skilled in the art from the following description.

According to an aspect of the present invention, there is provided a pulse driver including: (1) a first input pulse receiving unit, connected to a second stage according to a level of a first input pulse, (M is an integer of 2 to n (n is an integer equal to or greater than 2), and the mth input pulse is input in a kth stage (where k is a natural number between 2 and n) 1) stages (n is a natural number of 2 or more) in which the m-th stage is connected to or disconnected from the (m + 1) -th stage in accordance with the level of the first stage And outputs the power as an output pulse.

The second stage to the n-th stage may respectively charge the input power source. At this time, the first stage can output the output pulse having a level higher than that of the power source by using the power charged in the second stage to the n-th stage as an output pulse according to the connection between the stages.

The pulse driver according to an embodiment of the present invention is sequentially connected from the first stage to the n-th stage, and the level of the output pulse is gradually increased. After the n-th stage to the first stage are connected, To the first stage, and the level of the output pulse gradually decreases.

A pulse driver according to an exemplary embodiment of the present invention is a pulse driver in which, when a specific input pulse has a low signal level, stages related to the input pulse are connected to each other, and a specific input pulse has a high signal level The stages related to the input pulse are disconnected.

The pulse driver according to an embodiment of the present invention has a low signal level sequentially from the first input pulse to the n th input pulse and then sequentially outputs a high signal level from the n th input pulse to the first input pulse I have.

The pulse driver according to an embodiment of the present invention includes: (1) a clock generator for generating a clock signal; (2) a clock generator for performing a delay operation on a clock signal, (3) a first delay pulse to an (n) -th delay pulse to generate a first to n-th reverse pulse, wherein the i-th reverse pulse (I is a natural number between 1 and n) is an inverting part having a falling point at the rising point of the i-th delay pulse and a rising point at the falling point of the (n + 1-i) th delay pulse, N-th input pulse to the n-th input pulse by changing the level of the n-th inverted pulse to the n-th inverted pulse.

In the power source, the (k-1) th power source is input to the k-th stage, and the n-th power source is further input to the n-th stage, and the n-th stage is connected to the n-th power source or disconnected according to the level of the n-th input pulse.

The power source may be a common voltage source.

The first stage includes: (1) a load capacitor (C _load ) connected to a reference end to output an output pulse, (2) a load capacitor connected between one end of the load capacitor (C _load ) Type switch element M _N1 for switching between the one end of the load capacitor C _load and the first node V _1P of the first stage in accordance with the first input pulse, (M _P1 ).

The k-th stage includes: (1) a k-1 capacitor C _Sk-1 whose other end is connected to a k-th segment V _kP ; (2) a k-1 capacitor C _{Sk- first} switch element of the n-type to switch between the one end and the reference terminal _{of) (M Nk), (3} ) the one end and the k + 1 stage of the first k-1 capacitor (C _Sk-1) according to k input pulse the k + 1 node (V _{k + 1P),} but switching between the case in which k is n, the switch element of the p-type for switching between the one end and the power of the n-th capacitor (C _Sn) in accordance with the n input pulse (M _Pk), (4) the reference end and the switching element (switching element in accordance with the switch element (M _NSk), (5) of the n-type for switching between the gate k-th input pulse of M _PDk) according to k input pulse (M _NSk ) and the switching element (p-type for switching between a power supply and the k-th node (V _kP) in accordance with the signal input to the gate switching element (M _PSk), (6) a p-type for switching between the gate of M _PDk) A switch element M _PDk may be included. have.

The method of driving a pulse driver according to an embodiment of the present invention includes driving the pulse driver that processes the power source according to whether the stages are connected or not and outputs the pulse as an output pulse, The method includes the steps of (a) inputting an input pulse to each stage, and (b) adjusting whether or not to connect each stage according to an input pulse.

Wherein the step (b) comprises the steps of sequentially connecting the first stage to the n-th stage and outputting an output pulse whose level gradually rises, and after the n-th stage to the first stage are connected, And outputting an output pulse whose level is gradually lowered by sequentially disconnecting from the stage to the first stage.

In the step (b), when a specific input pulse has a low signal level, it connects between stages related to the input pulse, and when a specific input pulse has a high signal level Disconnection between the stages associated with the input pulse.

In the step (a), input pulses are sequentially input from the first input pulse to the n-th input pulse so as to have a low signal level, and then sequentially from the n-th input pulse to the first input pulse are high ) ≪ / RTI > signal level.

The pulse driver and the driving method according to an embodiment of the present invention configured as described above are capable of outputting an output pulse with a low power and adjusting the level of the pulse according to necessity so that it can be applied to various devices. There is an advantage that high efficiency energy performance can be provided when applied to devices requiring high output power pulses.

1 shows the configuration of a conventional pulse driver.
2 is a circuit diagram of a driving unit in a pulse driver according to an embodiment of the present invention.
3 shows a timing diagram of a driver in a pulse driver according to an embodiment of the present invention.
4 shows an overall configuration of a pulse driver according to an embodiment of the present invention.
5 shows an example of a clock signal CLK _in , a delay pulse P _Dk and an inversion pulse P _Lk in the pulse driver according to the embodiment of the present invention.
6 illustrates a method of driving a pulse driver according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings, . In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Furthermore, terms used herein are for the purpose of illustrating embodiments and are not intended to limit the present invention. In this specification, the singular forms include plural forms as the case may be, unless the context clearly indicates otherwise. The terms "comprises", "having", "having", or "having" as used herein do not exclude the presence or addition of one or more other elements other than the named element.

In this specification, the expressions " or ", " at least one ", etc. may denote one of the words listed together, or may represent a combination of two or more. For example, " A or B ", " at least one of A and B " may include only one of A or B, and may include both A and B.

In the present description, for example, the description may not exactly match the information presented, such as a cited property, a variable, or a value, and may be different from the tolerance, measurement error, The invention should not be limited to the embodiments of the invention in accordance with the various embodiments of the present invention.

In this specification, when an element is referred to as being "connected" or "connected" to another element, it may be directly connected or connected to the other element, but other elements It should be understood that it may exist. On the other hand, when an element is referred to as being "directly connected" or "directly connected" to another element, it should be understood that there are no other elements in between.

Unless defined otherwise, all terms used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. In addition, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 2 shows a circuit diagram of a driver in a pulse driver according to an embodiment of the present invention, and FIG. 3 shows a timing diagram of a driver in a pulse driver according to an embodiment of the present invention. 4 is a diagram illustrating the overall configuration of a pulse driver according to an embodiment of the present invention. FIG. 5 is a circuit diagram illustrating a pulse driver according to an exemplary embodiment of the present invention, in which a clock signal CLK _in , a delay pulse P _Dk , _{Shows an} example of the pulse P _Lk .

4, the pulse driver according to the exemplary embodiment of the present invention outputs an output pulse CLK _out and adjusts the output level of the output pulse CLK _out . The pulse driver includes a clock generating unit (not shown), a delay unit 10 An inverting unit 20, a level converter 30, and a driving unit 40. As shown in FIG. At this time, the pulse driver according to an embodiment of the present invention includes a driver 40 as an essential constitution. Accordingly, the driving unit 40 will be described first, and the rest of the configuration will be described.

The drive section 40 is comprising a first stage (ST ₁₎ to the n-th stage (ST _n) (where, n is a natural number of 2 or more) as shown in FIG. For convenience of explanation, FIG. 2 and FIG. 3 have been shown in the case where n is 3, but the present invention is not limited thereto.

A first stage (ST ₁₎ is an output stage, the first input pulse (P _H1) the input batdoe, the first input pulse and the second connection and the stage (ST ₂₎ or disconnection in accordance with a level of (P _H1) output pulse (CLK _out ).

The second stage (ST ₂₎ to n-th stages (ST _n) is batdoe input to each of the first input pulse (P _H1) to the n input pulse (P _Hn) and the power supply _{(V dd1, IO ... V ddn} , IO) a first input pulse (P _H1) to the n input pulse is filled accepted in accordance with a level of (P _Hn) input power (V _{dd1, IO} ... V _{ddn, IO),} and whether the crystal connected to each other that the charging power source To the first stage ST1. That is, the k-th stage ST _k (where k is a natural number between 2 and n) receives the k-th input pulse PH _k . Particularly, the m-th stage ST _m (where m is a natural number between 2 and n-1) is connected to the ( _{m + 1} ) th stage ST _{m + 1} according to the level of the _m -th input pulse PH _m It is disconnected. For example, referring to FIG. 2, the second stage ST ₂ receives a second input pulse PH ₂ , and is connected to or disconnected from the third stage ST ₃ according to the level.

It is preferable that the power sources V _{dd1 , Io} ... V _{ddn, IO} are the common voltages for supplying the same voltage to the stages ST ₁ , ..., ST _n , but they are not limited thereto and may be different voltage sources. However, to the to the 3 and 4 for convenience of description to describe that the power (V _dd1, V ... _{ddn IO, IO)} common voltage source (V _{dd, IO).}

On the other hand, the driving unit 40 processes the power sources V _{dd and I 0} input to the respective stages according to whether the stages ST _{1 to} ST _n are connected or not, and outputs the processed power V _{dd and IO} as an output pulse CLK _out . At this time, processing power (V _{dd, IO)} which is input to each stage for outputting the output pulse (CLK _out), the second stage (ST ₂₎ to n-th stages (ST _n) is the power inputted to their respective charging the (V _{dd, IO),} and a first stage (ST ₁₎ to the second stage (ST ₂₎ to n-th stages (ST _n) according to the connection or between the individual stages (ST _1, ... ST _n) a power supply (V _{dd, IO)} filled in and outputs the output pulse (CLK _out). Accordingly, as shown in FIG. 3, the output pulse CLK _out may have a value of a level higher than that of the power source (V _{dd, IO} ).

That is, the driving unit 40 can sequentially increase the level of the output pulse CLK _out by sequentially connecting the first stage ST ₁ to the n-th stage ST _n . For example, referring to FIG. 2, the first stage ST ₁ to the n-th stage ST _n are initially disconnected from each other, and the level of the output pulse CLK _out is maintained at the lowest level. Thereafter, the first stage ST ₁ and the second stage ST ₂ are connected to each other, so that the level of the output pulse CLK _out rises slightly. Then, the first and the stage (ST ₁₎ and the second stage (ST ₂₎ while the maintaining connection of the second stage (ST ₂₎ with added between the third stage (ST ₂₎ connected, so that an output pulse ( CLK _out is slightly increased. In this way, according to the progress in turn connected between each stage _{(ST 1, ... ST n)} , the output pulses (CLK _out) is as to its level is gradually increased to a large level value than the power supply (V _{dd, IO)} . In particular, when all of the first stage ST ₁ to the n-th stage ST _n are connected, the level of the output pulse CLK _out becomes the maximum.

After the n-th stage ST _n to the first stage ST ₁ are connected, the driving unit 40 sequentially disconnects the _n- th stage ST _n to the first stage ST ₁ to generate the output pulse CLK _out Can be gradually lowered. For example, referring to FIG. 2, after all of the first stage (ST ₁ ) to the third stage (ST ₃ ) are connected, the third stage (ST ₂ ) and the second stage (ST ₂ ) , So that the level of the output pulse CLK _out is slightly lowered. Then, the third, and between the stage (ST ₂₎ and the second stage while a break of (ST ₂₎ retained second stage (ST ₂₎ and the first stage (ST ₁₎ additional disconnection, so that the output pulse ( CLK _out is slightly lowered. Thus, as the disconnection between the stages ST _{1 through} ST _n progresses in order, the level of the output pulse CLK _out gradually decreases, and finally, the output pulse CLK _out can have the lowest level value.

On the other hand, when the specific input pulse PH _i (i is a natural number between 1 and n) has a low signal level, the driving unit 40 connects the stages related to the input pulse to each other, If the input pulse (PH _i) having a high (high) level signal, it may be configured such that disconnection stage related to the input pulse (hereinafter referred to as "first case" hereinafter referred to). At this time, a stage associated with a particular input pulse (PH _i) are means the stage whether a particular input pulse (PH _i) connected to each other by a determined or disconnected. That is, the related stage of the k-th input pulse PH _k is the k-th stage ST _k and the ( _{k + 1} ) _th stage ST _{k + 1} .

However, the present invention is not limited to the first case, and the opposite case (hereinafter referred to as " second case "). In this case, the second case means that, when a particular input pulse has a high signal level, the stages associated with the input pulse are connected to each other, and when a particular input pulse has a low signal level, It means that the driving unit 40 is configured so that the stages related to the input pulse are disconnected. 2 to 5 show that the driving unit 40 is configured as the first case.

According to the first case, as shown in FIG. 3, the input pulses P _H1 ... P _Hn are all kept at the high signal level at first, and then the first input pulses P _H1 , after the up pulse (P _Hn) with a (low) level signal to turn, the n input pulse has a high (high) level signal from the (P _Hn) in turn to the first input pulse (P _H1). For example, when n is 3, the first input pulse (P _H1 ), the second input pulse (P _H2 ), and the third input pulse (P _H3 ) Signal level and thereafter changes from the low signal level to the high signal level in the order of the third input pulse P _H3 , the second input pulse P _H2 and the first input pulse P _H1 Change.

Conversely, according to the second case, the input pulses P _H1 ... P _Hn are maintained at the first low signal level, and the first input pulse P _H1 to the n th input pulse P _Hn The input signal from the nth input pulse P _Hn to the first input pulse P _H1 in turn has a low signal level.

Referring to FIG. 2, a detailed circuit configuration of the first stage ST ₁ and the k-th stage ST _k for the first case will be described below.

That is, the first stage ST ₁ includes a load capacitor C _load , an n-type switch element M _N1 , and a p-type switch element M _P1 , respectively.

The load capacitor C _load is a capacitor for outputting an output pulse CLK _out , one end of which is connected to the switch element M _N1 and the other end of which is connected to the reference end. At this time, the load capacitor C _load supplies the power source V _{dd, IO} charged in each of the stages ST ₁ , ..., ST _n to the output pulse CLK _out in accordance with the level of the first input pulse P _H1 Can be output.

The switch element M _N1 may switch between one end of the load capacitor C _load and the reference end according to the first input pulse P _H1 . At this time, the reference terminal supplies a voltage having a level lower than that of the power sources (V _{dd, I O} ), and may be ground (GND). For example, the switch element M _N1 may be an n-type MOSFET. That is, when the first input pulse P _H1 is at a high signal level, the switch element M _N1 turns on between the one end of the load capacitor C _load and the reference end, and the first input pulse P _H1 ) is at a low signal level, it turns off between the one end of the _load capacitor C _load and the reference end.

The switch element M _P1 can switch between one end of the load capacitor C _load and the first node V _1P of the first stage in accordance with the first input pulse P _H1 . For example, the switch element M _P1 may be an n-type MOSFET. That is, when the first input pulse P _H1 is at a high signal level, the switch element M _P1 is turned off between the one end of the _load capacitor C _load and the first node V _1P of the first stage And turns on between one end of the _load capacitor C _load and the first node V _1P of the first stage when the first input pulse P _H1 is at a low signal level.

The k-th stage (ST _k) is a switch element (M _Nk), switch element (M _Pk), the switching element (M _NSk) of the n-type of p-type of the k-1 capacitor (C _Sk-1), n-type, a p-type switch element M _PSk , and a p-type switch element M _PDk , respectively.

The k-1 capacitor (C _Sk-1) is a capacitors for power charging, one end is connected with a switch element (M _Nk) and the other end is connected to the k-th node (V _kP), the k-th input pulse (P _Hk) 1 power source (V _{ddk-1, IO} ) according to the level of the (k-1) th power source.

The switch element M _Nk may switch between one end of the k-1 capacitor C _Sk-1 and the reference end in accordance with the k-th input pulse P _Hk . For example, the switch element M _Nk may be an n-type MOSFET. That is, when the k-th input pulse P _Hk is at a high signal level, the switch element M _Nk turns on between the one end of the ( _k-1 ) th capacitor C _Sk-1 and the reference end, and turns off between the one end of the ( _k-1 ) th capacitor C _Sk-1 and the reference node when the k input pulse P _Hk is at a low signal level.

The switch element M _Pk is connected to one terminal of the k-1 capacitor C _Sk-1 and the ( _{k + 1} ) th terminal V k of the ( _{k + 1} ) _th stage ST _{k + 1} according to the k input pulse P _Hk . _the switching between one end of the n-th capacitor C _Sn and the n-th power source Vdd _{n, IO} may be switched according to the n-th input pulse P _Hn when k is n . For example, the switch element M _Pk may be a p-type MOSFET. That is, the switch element (M _Pk) is the k-th input pulse (P _Hk) is high (high) once the first k + 1 stages (ST _{k + 1)} of the signal level if the k-1 capacitor (C _Sk-1) (K + 1) of the (k + 1) _-th capacitor C _Sk-1 when the k-th input pulse is at the low signal level, And turns on between the ( _{k + 1} ) _th stage (V _{k +} 1 P) of the stage ST _{k + 1} . However, if k is n, the switching element M _Pk is turned on when one end of the n-th capacitor C _Sn and the n-th power supply V _{ddn, IO} are _{turned on,} if the n-th input pulse P _Hn is at a high signal level. And turns on one end of the n-th capacitor C _Sn and the n-th power source V _{ddn, IO} when the n-th input pulse P _Hn is at a low signal level.

The switch element M _NSk can switch between the reference end and the gate of the switch element M _PDk in accordance with the k-th input pulse P _Hk . For example, the switch element M _NSk may be an n-type MOSFET. That is, the switch element (M _NSk) is the k-th input pulse (P _Hk) is high (high) signal level when the reference end and the switch elements turned on (on) between the gate of the (M _PDk) and, the k input pulse (P _Hk Off between the reference end and the gate of the switch element M _PDk .

Switch elements (M _PSk) may switch between the gate of the switching element (M _NSk) and switch element (M _PDk) according to the k-th input pulse (P _Hk). For example, the switch element M _PSk may be a p-type MOSFET. That is, the switch element (M _PSk) are the k-th input pulse (P _Hk) that is high (high) signal level switching element (M _NSk) and a switch element turned off through the gate (off) of the (M _PDk) and, the k input turns on (on) between the gate of the pulse (P _Hk) is equal to (low) level signal switch element (M _NSk) and switch element (M _PDk).

The switch element M _PDk may switch between the k-th power supply (V _{dd, I o} ) and the k-th node (V _kP ) according to a signal input to its gate. For example, the switch element M _PDk may be a p-type MOSFET. That is, when the signal input to the gate of the switch element M _PDk is at a high signal level, the switch element M _PDk turns off between the k-th power supply V _{dd, I o} and the k-th node V _kP , The voltage between the k-th power source V _{dd, I o} and the k-th node V _kP is turned on.

On the other hand, in the specific circuit configuration of the first stage ST ₁ and the k-th stage ST _k for the second case, the respective switch elements of the first case are opposite in type, that is, the n- And the p-type switch element is the same as the first case except that it is changed to the n-type switch element.

Hereinafter, with reference to FIG. 2 and FIG. 3, the detailed operation of the first case of each circuit (when n is 3) of the driving unit 40 will be described in more detail. However, for convenience of explanation, the switch elements of each stage ST ₁ , ... ST _n are indicated by their symbols.

First, as the first input pulse P _H1 to the third input pulse P _H3 all have a high signal level, the interval between the first stage ST ₁ and the third stage ST ₃ is All are disconnected. That is, in the first stage ST ₁ , M _N1 is turned on and M _P1 is turned off, so that the first stage ST ₁ and the second stage ST ₂ are disconnected. In the second stage ST ₂ , M _N2 is turned on and M _P2 is turned off, and the second stage ST ₂ and the third stage ST ₃ are also disconnected. In the third stage ST ₃ , M _N3 is turned on and M _P3 is turned off so that the third stage ST ₃ and the third power source V _{dd3 and IO} are also disconnected . At this time, M _NS2 and M _NS3 are turned on and M _PD2 and M _PD3 are turned on so that the first power source V _{dd1 and Io} are connected to the first node 1P and the second power V _{dd2, IO)} connected to the second node (2P), and, thus, C _s1 first power supply (V _{dd1, IO)} is charged, the charge of the second power supply (V _{dd2, IO)} to C _s2.

Thereafter, as only the first input pulse P _H1 has a low signal level, the first stage ST ₁ and the second stage ST ₂ are connected, and the second stage ST ₂ is connected, And the third stage (ST ₃ ). That is, in the first stage ST ₁ , M _N1 is turned off and M _P1 is turned on, so that the first stage ST ₁ and the second stage ST ₂ are connected. Accordingly, the voltage of the first power source (V _{dd1, IO} ) charged in C _s1 is output to C _load , and the level of CLK _out rises by the voltage of the first power source (V _{dd2, IO} ).

Thereafter, the connection between the first stage ST ₁ and the second stage ST ₂ , as the first input pulse P _H1 and the second input pulse P _H2 have a low signal level, retained and, the second connection may be added between the stage (ST ₂₎ and the third stage (ST _3). That is, in the second stage ST ₂ , M _N2 is turned off and M _P2 is turned on, so that the second stage ST ₂ and the third stage ST ₃ are additionally connected. Accordingly, the voltage of the second power supply (V _{dd2, IO)} filled in the C _s2 as the output level of the CLK to the _load C _out is more raised by the voltage of the second power supply (V _{dd2, IO).}

Thereafter, as the first input pulse P _H1 to the third input pulse P _H3 all have a low signal level, the connection between the first stage ST ₁ and the second stage ST ₂ The connection between the second stage ST ₂ and the third stage ST ₃ is maintained and the third stage ST ₃ is further connected between the third power source V _{dd3 and IO} . That is, in the third stage ST ₃ , M _N3 is turned off and M _P3 is turned on so that the third stage ST ₃ and the third power source V _dd3, do. Accordingly, the voltage of the third power source (V _{dd3, Io} ) is also output to the C _load , and the level of the CLK _out further rises by the voltage of the third power source (V _{dd3, IO} ).

On the other hand, the process of sequentially disconnecting from the _n- th stage ST _n to the first stage ST ₁ after all of the n-th stage ST _n to the first stage ST ₁ are connected is the reverse process of the above-described process , And a description thereof will be omitted.

Next, the remaining configuration of the pulse driver according to the embodiment of the present invention will be described with reference to FIGS. 4 and 5. FIG.

A clock generator (not shown) generates an input pulse (CLK _in ) and may be a conventional clock generator.

The delay unit 10 performs a delay operation on the clock signal CLK _in generated by the clock generating unit to generate the first delay pulse _PD1 to the n-th delay pulse _PDn . At this time, the first delay pulse _PD1 to the n-th delay pulse _PDn have different rising points, and the rising points of the first delay pulse _PD1 to the n-th delay pulse _PDn It is as slow as it is. For example, the delay unit 10 may be implemented using a plurality of buffers.

Inverting (20) generates a first delay pulse (P _D1) and to process the n-th delayed pulse (P _Dn), a first inversion pulse (P _L1) to n-th inversion pulse (P _Ln). At this time, the i-th reverse pulse P _Li (i is a natural number between 1 and n) has its falling time at the rising time point of the i-th delay pulse P _Di , and the (n + P _{D (n + 1-i)} ). For example, referring to FIG. 5, when n is 4, the first inverted pulse P _L1 has its falling point at the rising point of the first delay pulse P _D1 , and the fourth inverted pulse P _DL ) At the time of the descent.

The level converter 30 changes the level of the first inverted pulse P _L1 to the n th inverted pulse P _Ln to generate the first input pulse P _H1 through the n th input pulse P _Hn . At this time, the level converter 30 can further raise the level of the first inverted pulse P _L1 to the nth inverted pulse P _Ln . For example, the level converter 30 may be implemented using a plurality of amplifiers and switch elements.

Hereinafter, a driving method of a pulse driver according to an embodiment of the present invention will be described.

6 illustrates a method of driving a pulse driver according to an embodiment of the present invention.

The method of driving a pulse driver according to an embodiment of the present invention includes steps S10 and S20 as shown in FIG. However, since the pulse driver and its configuration have been described above with reference to FIGS. 1 to 5, a description thereof will be omitted herein.

Step S10 is an input step of inputting an input pulse to each stage. At this time, in step S10, input pulses are sequentially inputted from the first input pulse to the n-th input pulse so as to have a low signal level, and then, from the n-th input pulse to the first input pulse And inputting the input pulses so as to have a high signal level in turn. In step S10, input pulses are sequentially input from the first input pulse to the n-th input pulse so as to have a high signal level, and then, from the n-th input pulse to the first input pulse And inputting the input pulses so as to have a low signal level in turn.

Step S20 is a stage connecting step, which controls the connection between the stages according to the input pulse. In this case, step S20 is a step of sequentially connecting the first stage to the n-th stage and outputting an output pulse whose level gradually rises. After the n-th stage to the first stage are connected, And sequentially outputting an output pulse whose level gradually drops.

Step S20 connects between stages related to the input pulse when a particular input pulse has a low signal level, and when a particular input pulse has a high signal level And disconnection between stages associated with the input pulse. In addition, step S20 includes connecting, in accordance with the second case, the stages associated with the input pulse when a particular input pulse has a high signal level, and when a particular input pulse is at a low signal level And disconnection between the stages associated with the input pulse in the case of the input pulse.

Although the present invention has been described in connection with certain exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Therefore, the scope of the present invention should not be limited to the embodiments described, but should be determined by the scope of the following claims and equivalents thereof.

10: delay unit 20:
30, LC _X : level converter 40: driving unit
C _load : load capacitor C _Sk-1 : k-1 capacitor
DC-DC: DC converter M _NX , M _NSX : n-type switch element
M _PX , M _PSX , M _PDX : p-type switch element ST _i : i th stage

Claims (13)

A first stage which receives a first input pulse and is connected to or disconnected from a second stage according to a level of a first input pulse and outputs an output pulse; And
Receives a k-th input pulse at a k-th stage (where k is a natural number between 2 and n), receives an input pulse at an m-th input pulse (m is a natural number between 2 and n-1) Second stage to n-th stage (where n is a natural number of 2 or more) in which the m-th stage is connected to or disconnected from the m + 1-th stage,
The power source is processed according to whether or not the stages are connected to each other to output an output pulse,
When a particular input pulse has a low signal level, the stages associated with that input pulse are connected together,
And when the specific input pulse has a high signal level, the stages related to the input pulse are disconnected. The method according to claim 1,
And the second stage to the n-th stage respectively charge the input power source,
Wherein the first stage is capable of outputting an output pulse having a level higher than that of the power source by using the power charged in the second stage to the nth stage as an output pulse according to whether or not the connection between the stages is connected. The method according to claim 1,
The level of the output pulse gradually increases from the first stage to the n-th stage,
And the level of the output pulse is gradually lowered while being disconnected from the n-th stage to the first stage in succession after the n-th stage to the first stage are connected. delete The method according to claim 1,
Wherein the pulse driver has a low signal level sequentially from a first input pulse to an n th input pulse, and then has a high signal level sequentially from an n th input pulse to a first input pulse. 6. The method of claim 5,
A clock generator for generating a clock signal;
A delay unit for performing a delay operation on the clock signal to generate first to n-th delay pulses having different rising points and rising points in the order of the rising points;
The first to n-th reverse pulses are generated by processing the first delay pulse to the n-th delay pulse, wherein the i-th reverse pulse (i is a natural number between 1 and n) And a rising point at a falling point of the (n + 1-i) -th delay pulse; And
And a level converter for changing levels of the first to n < th > inversion pulses to generate first to n < th > input pulses. A first stage which receives a first input pulse and is connected to or disconnected from a second stage according to a level of a first input pulse and outputs an output pulse; And
Receives a k-th input pulse at a k-th stage (where k is a natural number between 2 and n), receives an input pulse at an m-th input pulse (m is a natural number between 2 and n-1) Second stage to n-th stage (where n is a natural number of 2 or more) in which the m-th stage is connected to or disconnected from the m + 1-th stage,
The power source is processed according to whether or not the stages are connected to each other to output an output pulse,
The k-th power is input to the k-th stage and the n-th power is further input to the n-th stage,
And the n-th stage is connected to or disconnected from the n-th power supply according to the level of the n-th input pulse. The method according to claim 1,
Wherein the power source is a common voltage source. A first stage which receives a first input pulse and is connected to or disconnected from a second stage according to a level of a first input pulse and outputs an output pulse; And
Receives a k-th input pulse at a k-th stage (where k is a natural number between 2 and n), receives an input pulse at an m-th input pulse (m is a natural number between 2 and n-1) Second stage to n-th stage (where n is a natural number of 2 or more) in which the m-th stage is connected to or disconnected from the m + 1-th stage,
The power source is processed according to whether or not the stages are connected to each other to output an output pulse,
The first stage includes:
A load capacitor (C _load ) whose other end is connected to a reference end to output an output pulse;
An n-type switch element M _N1 for switching between one end of the load capacitor C _load and the reference _node in accordance with the first input pulse; And
And a p-type switch element M _P1 for switching between one end of the load capacitor C _load and the first node V _1P of the first stage in accordance with the first input pulse,
The k < th >
A k-1 capacitor (C _Sk-1 ) whose other end is connected to the k-th node (V _kP );
An n-type switch element M _Nk for switching between one end of the ( _k-1 ) th capacitor C _Sk-1 and the reference terminal according to the k-th input pulse;
According to the k input pulse, but switching between the k-1 capacitor (C _Sk-1) one and a k + 1 the k + 1 node (V _{k + 1P)} of the stage, if the k is n, the first n A p-type switch element (M _Pk ) for switching between one end of the n-th capacitor (C _Sn ) and the power supply according to an input pulse;
The reference end and the switching element switch device _(NSk M) of n-type for switching between the gate of the (M _PDk) according to k input pulse;
The switch element (M _NSk) and the switching element switch device of the p-type for switching between the gate of the (M _PDk) (M _PSk) according to k input pulse; And
A p-type switch element M _PDk for switching between a power supply and a k-th node (V _kP ) according to a signal input to the gate;
And a pulse driver. A first stage which receives a first input pulse and is connected to or disconnected from a second stage according to a level of a first input pulse and outputs an output pulse; M stage is connected to or disconnected from the (m + 1) th stage according to the level of the m-th input pulse (where m is a natural number between 2 and n-1) A driving method of a pulse driver that includes an n-th stage (where n is a natural number of 2 or more), processes the power supply according to whether the stages are connected to each other,
(a) inputting an input pulse to each stage; And
(b) adjusting the connection between the stages according to the input pulse,
The step (b)
When a specific input pulse has a low signal level, connects between stages related to the input pulse, and when a specific input pulse has a high signal level, Further comprising the step of disconnecting the pulse driver. 11. The method of claim 10,
The step (b)
Outputting an output pulse whose level gradually increases by sequentially connecting the first stage to the n-th stage; And
And outputting an output pulse whose level gradually decreases after sequentially connecting the n-th stage to the first stage, after the n-th stage to the first stage are connected to each other. Driving method. delete 11. The method of claim 10,
The step (a)
The input pulses are sequentially inputted from the first input pulse to the nth input pulse so as to have a low signal level and then input from the nth input pulse to the first input pulse are sequentially inputted to have a high signal level Further comprising the step of inputting pulses.

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