KR101928421B1 - Method for manufacturing perpendicularity laminating chip and multi chip package and Apparatus for multi chip package - Google Patents

Abstract

According to one embodiment of the present invention, a method of manufacturing a chip for vertical lamination capable of improving electrical conductivity between chips for vertical lamination may comprise: a first conductor forming process of forming a first conductor whose surface is exposed by being buried in a substrate with an inverted triangular structure widening from an upper surface to a lower portion of the substrate; a second conductor forming process of forming a second conductor buried in a vertical structure on the upper surface of the first conductor to expose a surface of the second conductor; a connection protruding body forming process of forming a connection protruding body of a conductive material having a protruding shape on a surface of the second conductor; and a substrate lower surface exposing process of exposing a lower surface of the substrate in any one method of grinding, polishing, and etching so that a bottom surface of the first conductor is exposed to the outside.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a vertical multi-chip package, a multi-chip package,

The present invention relates to a chip for vertical stacking, a method for manufacturing a multi-chip package, and a multi-chip package, and a method and apparatus for manufacturing a multi-chip package using the same.

Current electronic systems mostly consist of several integrated circuits or components, each of which performs one or more functions. For example, a computer includes one or more microprocessors and some memory circuits. Usually, each integrated circuit corresponds to an electronic chip in its package. For example, the integrated circuits are plugged or soldered into the printed circuit board 10 (PCB) connecting the integrated circuits.

In recent years, three-dimensional (3D) vertical stacking schemes have been used in which chips are stacked and connected by vertical interconnections to the material of the chip, respectively, and electrically connect the bottom surface and the top surface of the chip . Thus, the resulting stack may include several layers or strata of active components or chips to implement a multi chip package (MCP).

A multi-chip package (MCP) is a package chip composed of a plurality of chips, which can combine necessary memories according to application products and contributes to space efficiency of mobile devices such as mobile phones.

A 3D stacking scheme, which is one of the methods of manufacturing MCP, stacks a plurality of chips in a vertical direction and interconnects the plurality of chips using through silicon vias (TSV). That is, since the MCP by the method of stacking in the three-dimensional stacking manner does not require a metal wire for interconnecting the chips, the MCP can be miniaturized, increased in speed and lowered in power,

However, when a failure occurs in the TSV of the MCP, the input / output line which is implemented in each of the chips and forms an electrical transmission path between the at least two chips may also fail, resulting in defective MCP.

Korean Patent Publication No. 10-1999-0030081

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and it is an object of the present invention to provide a chip fabrication method and a multichip package fabrication method capable of improving electrical conductivity between vertically stacking chips.

A first conductor forming step of forming a first conductor whose surface is exposed by being buried in a substrate with an inverted triangular structure that widens from the upper surface to the lower portion of the substrate; A second conductor forming step of forming a second conductor buried in a vertical structure on an upper surface of the first conductor to expose a surface thereof; A connection pour gas forming step of forming a connecting pour body of a conductive material having a protruding shape on the surface of the second conductor; And exposing the lower surface of the substrate in any one of grinding, polishing, and etching so that the bottom surface of the first conductor is exposed to the outside.

The forming of the first conductor may include forming an insulating groove having an inverted triangular groove that widens from the upper surface of the substrate toward the lower side, Insulator filling process of filling the inside of the insulating groove with an insulator; A first conductor groove forming step of forming a first conductor groove, which is an inverted triangular groove, which is widened from an upper surface of the insulator to a lower portion; And a first conductor filling step of filling the inside of the first conductor groove with a first conductor made of a conductive material.

In the insulating groove forming process, the patterned pattern surface is exposed to the outside on the upper surface of the substrate, and the insulating groove is formed over the pattern surface and the substrate.

The first conductive groove forming process may include forming a first conductive groove such that a side wall of a first conductive groove having an inverted triangular shape is surrounded by an insulator.

And forming a ring-shaped groove in the lower interface of the first conductor and the insulator after the lower surface of the substrate is exposed.

The second conductor formation process includes: forming a second conductor groove in a vertical structure in the first conductor; And a second conductor filling process of filling the inside of the second conductor groove with a second conductor of a conductive material.

And the second conductor is implemented as a conductor having a higher conductivity than the conductivity of the first conductor.

The connecting pawl body may have a circular spherical shape having a curvature.

The connecting pawl body may have a columnar shape in which the upper surface of the connecting pawl body is a horizontal plane.

The method of manufacturing a multi-chip package according to the present invention includes the steps of forming a first conductor having an inverted triangular structure that widens from a top surface of a first substrate toward a bottom, Forming a first pillar-shaped conductor of a protruding conductive material on the surface of the first conductor, forming a first pillar-shaped conductor of a conductive material on the surface of the first conductor, A first chip fabrication process for vertically stacking the first chip for vertical stacking through a process of grinding, polishing and etching the lower surface of the first substrate so as to expose the first chip; Forming a second-1 conductor having an inverted triangular shape that widens from the upper surface of the second substrate toward the lower portion, forming a second-2 conductor having a vertical structure in the second-1 conductor, A step of forming a connection second pillar body of a protruding conductive material on the surface of the second-2 conductor and a step of grinding the lower surface of the second substrate so as to expose the bottom surface of the second- Polishing, and etching; a second chip for vertically stacking a chip for vertical stacking; And a laminating step of laminating the lower surface of the first conductor of the vertically stacking first chip and the upper surface of the connecting second pillar body of the vertically stacking second chip.

Further, the multi-chip package of the present invention is manufactured by combining the lower surface of the first conductor of the first chip for vertical stacking with the upper surface of the second pillar body of the second chip for vertical stacking manufactured through claim 10 .

According to the embodiment of the present invention, the electrical conductance can be improved by making the conductor double structure. In addition, a conductive body can be formed on the conductor and electrically connected with other adjacent chips to improve the conductivity. In addition, most of the work for chip stacking can be carried out only by processing at the normal chip surface and vertical pattern side for the vertical stacking, which simplifies the process.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a flowchart illustrating a process for fabricating a vertical stacking chip according to an embodiment of the present invention. FIG.
FIG. 2 is a diagram illustrating a fabrication sequence of a vertical stacking chip according to an embodiment of the present invention. FIG.
3 is a flowchart illustrating a process of fabricating a multi-chip package in which two vertical stacking chips are vertically stacked according to an embodiment of the present invention.
FIG. 4 is a view illustrating a multi-chip package in which two vertically stacked chips are vertically stacked according to an embodiment of the present invention.
5 illustrates an example of a multi-chip package in which two or more N stacking chips are vertically stacked according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to achieve them, will be apparent from the following detailed description of embodiments thereof taken in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. And the present invention is only defined by the scope of the claims. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

FIG. 1 is a flow chart illustrating a process of fabricating a vertical stacking chip according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating a fabrication sequence of a vertical stacking chip according to an embodiment of the present invention.

In the following description, individual chips used in a multi-chip package (MCP) in which a plurality of chips are vertically stacked will be referred to as vertical stacking chips.

As shown in FIG. 1, the method for fabricating a vertical stacking chip according to the present invention includes forming a substrate 10 (S110), forming a first conductor (S120), forming a second conductor (S130) A process S140, and a substrate lower surface exposure process S150. Further, it may further include an additional insulation formation process (S160).

First, the substrate 10 is prepared (S110). The substrate 10 is formed on the substrate 10 with a patterned patterned surface patterned with metal, as shown in Fig.

The first conductor forming process S120 is a process of forming a first conductor 12 having a surface exposed by being buried in the substrate 10 with an inverted triangular structure that widens from the upper surface to the lower portion of the substrate 10 .

The first conductor forming step S120 may include an insulating groove forming step S121, an insulator filling step S122, a first conductor groove forming step S123, and a first conductor filling step S124.

In detail, when the patterned substrate 10 is provided, it has an insulating groove forming process S121. The insulating groove forming process S121 is a process of forming an insulating trench 11h having grooves of an inverted triangle shape that widens from the upper surface of the substrate 10 toward the lower portion as shown in Fig. 2 (b). Therefore, the insulating groove 11h having a small hole entrance and a wide groove inside can be formed. Therefore, only a small area of the chip surface may be used. The formation of the insulating trench can be formed by giving an angle to the laser, changing the focus, and chemical treatment so as to expand from the upper surface of the substrate 10 toward the lower portion. In the insulating groove forming process S121, the patterned pattern surface P is exposed to the outside on the upper surface of the substrate 10, and the insulating trench 11h is formed on the pattern surface P and the substrate 10 . Thus, the insulating trenches 11h are exposed at the top.

After the insulating groove forming process S121, the insulator filling process S122 is performed. The insulator filling process (S122) is a process of filling the insulator 11h with the insulator 11 as shown in Fig. 2 (c). That is, the inside of the insulating trench 11h is filled with the insulator 11. Here, the insulator 11 can be used as long as it is a material that cuts off the electric conductivity.

After the insulator filling process S122, the first conductor groove forming process S123 is performed. As shown in FIG. 2D, the first conductive groove forming process S123 is a reverse oval-shaped groove-like process that spreads from the upper surface of the insulator 11 toward the lower portion. The first conductor groove forming process forms the first conductor groove 12h so that the side wall of the first conductor groove 12h having the inverted triangular shape is surrounded by the insulator 11. This is for the purpose of enhancing the insulation surrounding the first conductor 12. To do this, drill some of the insulating material. Or angle to the perforated laser, focus change and chemical treatment.

After the first conductor groove forming process (S123), the first conductor filling process (S124) is performed. The first conductor filling process S124 is a process of filling the interior of the first conductor groove 12h with the first conductor 12 made of a conductive material as shown in Fig. 2 (e).

Meanwhile, the second conductor formation process (S130) is a process of forming the second conductor 13, which is buried in a vertical structure on the upper surface of the first conductor 12 to expose the surface. To this end, the second conductor formation process (S130) has a second conductor groove forming process (S131) and a second conductor filling process (S132).

The second conductor groove forming process S131 is a process of forming a second conductor groove 13h having a vertical structure in the first conductor 12 as shown in FIG. 2 (f). The filled first conductor 12 may be drilled as a vertical structure to form the second conductor groove 13h.

A second conductor filling process for filling the inside of the second conductor groove 13h with the second conductor 13 made of a conductive material as shown in FIG. 2 (g) after the second conductor groove forming process (S131) S132).

Here, the second conductor 13 is filled with a conductor having a conductivity higher than that of the first conductor 12. This is because a connecting pawl body 14 to be described later is formed on the upper surface of the second conductor 13 so that the coupling area between the second conductor 13 and the connecting pawl body 14 is small, 14) and the second conductor (13). The second conductor 13 may be formed by further inserting a high-performance core material such as copper and gold to improve the conductivity.

On the other hand, as shown in FIG. 2 (h) after the second conductor formation process (S130), the connecting stone (14) is formed on the surface of the second conductor (13) And a gas formation process (S140). The connecting pawl body 14 is a connecting body that is coupled to the lower surface of the second conductor 13 of another vertically stacking chip as will be described later.

To this end, the connecting pawl body 14 may have a spherical shape with a curvature. However, when the connecting pawl body 14 has a spherical shape, the bonding strength may be deteriorated when bonding with the lower surface of the second conductor 13 of another vertical stacking chip, thereby deteriorating the electrical conductivity. Accordingly, the present invention can be embodied in the form of a connecting pawl body 14 having a cylindrical shape whose upper surface is a horizontal plane. Therefore, the upper surface of the connecting pillar body 14 is in a horizontal plane, so that the bonding force is improved when bonding with the lower surface of the second conductor 13 of the adjacent vertical stacking chip, and the electrical conductivity can be improved.

The bottom surface of the substrate 10 is ground, polished, and etched so that the bottom surface of the first conductor 12 is exposed to the outside, as shown in FIG. 2 (i) (S150) of exposing the lower surface of the substrate in any one of the following processes. This is to grind unwanted backsides for lightweight chips, at which time the bottom surface of the first conductor 12 embodied within the chip is exposed.

An additional insulation formation process (S150) is performed so that the lower interface of the first conductor 12 and the insulator 11 is formed in a ring-shaped groove as shown in FIG. 2 (j) S160). This means that the first conductor 12 is cleaned or gently melted to secure additional insulation.

Meanwhile, the first conductor forming process S120, the second conductor forming process S130, the connecting pouring process S140, the bottom surface exposure process S150, and the additional insulation forming process S160), a single vertical stacking chip can be manufactured. A plurality of such vertical stacking chips can be stacked to produce a multi-chip package (MCP). 3 to 5 will be described below in detail.

FIG. 3 is a flow chart illustrating a process for fabricating a multi-chip package in which two vertically stacked chips are vertically stacked according to an embodiment of the present invention. FIG. 4 is a cross- 5 is a view illustrating an example of a multi-chip package in which two or more N stacking chips are vertically stacked according to an embodiment of the present invention .

3, the process of fabricating a multichip package of the present invention includes a first chip fabrication process (S310) for vertical stacking, a second chip fabrication process (S320) for vertical stacking, and a stacking process (S330) .

The first chip fabrication process (S310) for vertically stacking includes a process (S311) of forming a first conductor (12a) having an inverted triangular structure that widens from the upper surface of the first substrate (10) , Forming a first conductor (13a) having a vertical structure on the first conductor (S312), a step (S312) of forming a second conductor (13a) having a vertical structure on the first conductor, (S313) of forming a first conductor (14a) on the lower surface of the first conductor (10) and a lower surface of the first substrate (10) so that the bottom surface of the first conductor is exposed to the outside And a first chip (chip 1) for vertical stacking is manufactured through a step S314.

The second chip fabrication process (S320) for vertical stacking may further include a process (S321) of forming a second-first conductor 12b having an inverted triangular cross-sectional structure that widens from the upper surface of the second substrate 10 toward the lower side, A step (S322) of forming a second-2 conductor (13b) having a vertical structure on the second-type conductor (12b), a step The lower surface of the second substrate 10 is ground, polished, and etched so that the bottom surface of the second-1 conductor 12b is exposed to the outside (S323) of forming the second pillar body 14b (S324) of fabricating a second chip for vertical stacking (Chip2) through a process of exposing and exposing in any one manner. Therefore, as shown in FIG. 4 (a), a first chip (chip 1) for vertical stacking and a second chip (chip 2) for vertical stacking can be manufactured.

4 (b), the lamination process is carried out in such a manner that the lower surface of the first conductor 12a of the first chip for vertical stacking (chip1) and the second connecting stone of the second chip for vertical stacking (chip2) To be combined with the upper surface of the base 14b. Accordingly, the first chip for vertical stacking and the second chip for vertical stacking are vertically stacked to form a multi-chip package (MCP).

In this multi-chip package, two vertical stacking chips are vertically stacked, but as shown in FIG. 5, N vertical stacking chips are vertically stacked in order to form N vertical stacking chips It is obvious that a multi-chip package (MCP) having a plurality of chips can be fabricated.

The embodiments of the present invention described above are selected and presented in order to assist those of ordinary skill in the art from among various possible examples. The technical idea of the present invention is not necessarily limited to or limited to these embodiments Various changes, modifications, and other equivalent embodiments are possible without departing from the spirit of the present invention.

S120: First conductor formation process
S130: Second conductor formation process
S140: Connection process
S150: Substrate lower surface exposure process
S160: Additional insulation formation process

Claims (8)

A first conductor forming step of forming a first conductor having a surface exposed by being buried in a substrate with an inverted triangular structure that widens from an upper surface to a lower portion of the substrate;
A second conductor forming step of forming a second conductor buried in a vertical structure on an upper surface of the first conductor to expose a surface thereof;
A connection pour gas forming step of forming a connecting pour body of a conductive material having a protruding shape on the surface of the second conductor; And
And exposing the lower surface of the substrate in any one of grinding, polishing, and etching so that the bottom surface of the first conductor is exposed to the outside,
The first conductor forming process includes:
An insulating groove forming step of forming an insulating groove having an inverted triangular shape that is widened from the upper surface of the substrate to the lower side; Insulator filling process of filling the inside of the insulating groove with an insulator; A first conductor groove forming step of forming a first conductor groove, which is an inverted triangular groove, which is widened from an upper surface of the insulator to a lower portion; And a first conductor filling step of filling the inside of the first conductor groove with a first conductor of a conductive material,
The insulating groove forming process and the first conductive groove forming process are performed such that an angle is given to the laser so as to be widened from the upper surface of the substrate toward the lower portion,
The second conductor formation process may include:
A second conductor groove forming step of forming a second conductor groove perpendicular to the first conductor; And a second conductor filling step of filling the inside of the second conductor groove with a second conductor of a conductive material, wherein the second conductor is implemented as a conductor having higher conductivity than the conductivity of the first conductor, 2 conductor further inserts a core material composed of copper or gold,
Wherein the connecting pawl body has a columnar shape in which the upper surface is a horizontal plane.
delete The method according to claim 1,
Wherein the patterned pattern surface is exposed to the outside on the upper surface of the substrate, and the insulating groove is formed across the pattern surface and the substrate.



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