KR101901506B1 - Light emitting transistor and method of fabricating the same - Google Patents

Abstract

The present invention relates to a light emitting transistor and a method of manufacturing the same. According to an embodiment of the present invention, there is provided a liquid crystal display comprising: a first electrode; A P-type semiconductor electrically connected to the first electrode and having a first surface and a second surface opposite to each other; A gate electrode including an insulating film bonded to the first surface of the P-type semiconductor; An N-type semiconductor forming a PN junction with the second surface of the P-type semiconductor; And a second electrode electrically connected to the N-type semiconductor, wherein the gate electrode including the insulating film controls at least one of a hole concentration and a Fermi level of the P-type semiconductor by applying an electric field to the P- A light emitting transistor can be provided.

Description

[0001] LIGHT EMITTING TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME [0002]

The present invention relates to a light emitting device, and more particularly, to an inorganic light emitting transistor and a method of manufacturing the same.

Because nanomaterials have excellent electrical and optical properties, they can be used in field-effect transistors (FETs), photo sensors, photovoltaic cells, biosensors and light-emitting diodes : LED) are used as materials for semiconductor devices. Particularly, light emitting diodes based on nanomaterials are very attractive for use in optoelectronics because of their low cost and high efficiency. However, at a specific bias, the emission intensity of a conventional PN junction light-emitting diode is affected by the characteristics of the nanomaterial and the device configuration. When a nanomaterial having a broad band gap relative to other materials is applied, the device must operate at a high forward bias due to Ohmic losses, which may degrade device efficiency.

Since the concentration and mobility of holes are generally lower than the concentration and mobility of holes, holes and electrons are efficiently recombined to generate spontaneous light emission. It can be difficult. Thus, control over the space where electron-hole recombination takes place is an important requirement in the design of materials for light-emitting diodes.

However, the conventional PN junction light emitting diode can not control the amount of generated bias, so that the emission intensity can not be modulated by itself. This limitation requires a field-effect transistor switch for every pixel unit of an active-matrix organic light-emitting diode (OLED) display device, thereby complicating the manufacturing process and structure of the device .

SUMMARY OF THE INVENTION The present invention provides a light emitting transistor which can control the space where electron-hole recombination takes place, and which has a simple manufacturing process and structure of a device capable of a self-switching operation.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting transistor having the above-described advantages.

According to an embodiment of the present invention, there is provided a liquid crystal display comprising: a first electrode; A P-type semiconductor electrically connected to the first electrode and having a first surface and a second surface opposite to each other; A gate electrode including an insulating film bonded to the first surface of the P-type semiconductor; An N-type semiconductor forming a PN junction with the second surface of the P-type semiconductor; And a second electrode electrically connected to the N-type semiconductor, wherein the gate electrode including the insulating film is formed by applying an electric field to the P-type semiconductor to form at least one of a hole concentration and a Fermi level A light emitting transistor that controls one transistor can be provided. Wherein the P-type semiconductor includes at least one p-type porous Si nanowires (PoSiNWs) having a direct bandgap characteristic, and the N-type semiconductor is at least one selected from the group consisting of N-type zinc oxide : &Lt; / RTI > ZnO) nanotubes. The aspect ratio of the porous silicon nanowire is in the range of 700 to 813, and the P-type porous silicon nanowire may have a single crystal preferentially oriented in the <100> direction. Wherein the P-type porous silicon nanowire has at least two sub-peaks at a single peak in the visible light range of 300 nm to 800 nm in the center of the photon energy in the range of 1.5 eV to 3.5 eV micro-photoluminescence (μ-PL) spectrum that is deconvoluted with a sub-peak. A quantum confinement effect (QCE) can be generated on the surface of the P-type porous silicon nanowire due to nano-sized surface roughness and porosity. Wherein the N-type zinc oxide nano-thin film has a thickness within a range of 90 nm to 120 nm, and the zinc oxide nano-thin film has two peaks corresponding to an ultraviolet ray region and a red series region in a visible light region in a range of 300 nm to 800 nm , And a microphotoluminescence spectrum in which the peak corresponding to the red series region is deconvoluted into at least two or more sub-peaks centered on photon energies in the range of 1.5 eV to 3.5 eV. When a negative electric field is applied to the P-type semiconductor, the potential energy difference increases at the junction between the P-type semiconductor and the N-type semiconductor, and the Fermi level of the P-type semiconductor reaches the conduction band edge, Type semiconductor, the amount of carriers to be transferred is increased, and when a positive electric field is applied to the P-type semiconductor, a potential energy difference at the junction between the P-type semiconductor and the N-type semiconductor decreases, The Fermi level of the P-type semiconductor moves to the valence band edge, and the amount of the carrier to be transferred can be reduced. And the peak corresponding to the red series region may have an electroluminescence (EL) spectrum deconvoluted into at least two or more sub-peaks centered on photon energies in the range of 1.5 eV to 3.0 eV. The gate electrode may comprise a heavily doped P-type (p ++) silicon (Si) substrate having a thermally grown silicon dioxide (SiO ₂ ) layer. The PN junction between the P-type semiconductor and the N-type semiconductor may have at least some amorphous phase that generates a microphotoluminescence emission peak. The N-type zinc oxide nanotubes can be formed by a combination of a zinc interstitial site (Zn _i ), an expanded zinc interstitial site (ex-Zn _i ), an oxygen vacancy (V _o ) and a transitionable energy level of at least one of the oxygen interstitial sites (O _i ) (the expression is modified to increase the right range).

According to another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a substrate; Forming at least one first electrode on the substrate and at least one dummy electrode spaced apart from the at least one first electrode; Forming a P-type semiconductor across the at least one first electrode and the at least one dummy electrode; Forming an N-type semiconductor on the P-type semiconductor formed; And forming a second electrode on the formed N-type semiconductor. The P-type semiconductor may be formed by dielectrophoresis (DEP) alignment using the at least one first electrode and the at least one dummy electrode. The forming of the second electrode may include: patterning the second electrode on the N-type semiconductor formed; Forming an etching mask on the patterned second electrode; Etching a portion of the N-type semiconductor in a region other than the N-type semiconductor at the bottom of the second electrode using the etching mask; And removing the etch mask. The P-type semiconductor may include at least one P-type porous silicon nanowire having a direct bandgap characteristic, and the N-type semiconductor may include an N-type zinc oxide nano-thin film. The P-type porous silicon nanowire can be formed by a metal-catalyst-assisted chemical (PECVD) process from a P-type silicon wafer doped with a dopant such as boron having a resistivity within a range of 1 Ωcm to 10 Ωcm etching: MCE) process.

According to an embodiment of the present invention, the light emitting transistor has a structure of a gate electrode including an insulating film for controlling at least one of a hole concentration and a Fermi level of a p-type semiconductor by applying an electric field to the p-type semiconductor, And a light emitting transistor having a simple manufacturing process and structure of a device capable of self-switching operation can be provided.

According to still another embodiment of the present invention, a method of manufacturing a light emitting transistor having the above-described advantages can be provided.

FIGS. 1A to 1D are cross-sectional views of a light emitting transistor according to one embodiment of the present invention, and FIG. 1E is a perspective view of a light emitting transistor according to an embodiment of the present invention.
2A and 2B are a cross-sectional view and a perspective view, respectively, of a light emitting transistor according to another embodiment of the present invention.
3A is a scanning electron microscope image of a P-type porous silicon nanowire in a light emitting transistor according to an embodiment of the present invention.
FIG. 3B is a transmission electron microscope image showing the rough surface of a P-type porous silicon nanowire in a light emitting transistor according to an embodiment of the present invention. FIG.
3C is a transmission electron microscope image showing the degree of solidification of the P-type porous silicon nanowire in the light emitting transistor according to an embodiment of the present invention.
FIG. 3D is a microphotoluminescence spectrum of a P-type porous silicon nanowire in a light emitting transistor according to an embodiment of the present invention.
FIG. 4A is a scanning electron microscope image showing a structure having an aluminum electrode / N-type zinc oxide nano-thin film / P-type porous silicon nanowire / gold electrode in a light emitting transistor according to an embodiment of the present invention.
FIG. 4B is a transmission electron microscope image showing the interface between the N-type zinc oxide nanofiltration film and the P-type porous silicon nanowire in the light emitting transistor according to an embodiment of the present invention.
4C is a microphotoluminescence spectrum of an N-type zinc oxide nanotube film formed on a P-type porous silicon nanowire in a light emitting transistor according to an embodiment of the present invention.
FIG. 5 is a graph showing IV characteristics of a light emitting transistor including an N-type zinc oxide nanotube film formed on a P-type porous silicon nanowire according to an embodiment of the present invention.
6A and 6B are energy band diagrams of a light emitting transistor according to a gate voltage according to an embodiment of the present invention.
7A and 7B are electro-luminescence spectra of a light emitting transistor according to an embodiment of the present invention.
8A and 8B are energy band diagrams of a light emitting transistor before and after a PN junction according to an embodiment of the present invention.
9 is a view illustrating a method of manufacturing a light emitting transistor according to an embodiment of the present invention.
10A is an optical microscope image showing a PN junction between an N-type zinc oxide nanofiltration film and a P-type porous silicon nanowire in a light emitting transistor according to an embodiment of the present invention.
Figures 10b-h are orange-red emission images within the light emitting transistor.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

The embodiments of the present invention are described in order to more fully explain the present invention to those skilled in the art, and the following embodiments may be modified into various other forms, It is not limited to the embodiment. Rather, these embodiments are provided so that this disclosure will be more faithful and complete, and will fully convey the scope of the invention to those skilled in the art.

Like numbers refer to like elements in the drawings. Also, as used herein, the term "and / or" includes any and all combinations of any of the listed items.

The terms used herein are used to illustrate the embodiments and are not intended to limit the scope of the invention. Also, although described in the singular, unless the context clearly indicates a singular form, the singular forms may include plural forms. Also, the terms "comprise" and / or "comprising" used herein should be interpreted as referring to the presence of stated shapes, numbers, steps, operations, elements, elements and / And does not exclude the presence or addition of other features, numbers, operations, elements, elements, and / or groups.

Reference herein to a layer formed "on" a substrate or other layer refers to a layer formed directly on top of the substrate or other layer, or may be formed on intermediate or intermediate layers formed on the substrate or other layer Layer. &Lt; / RTI &gt; It will also be appreciated by those skilled in the art that structures or shapes that are "adjacent" to other features may have portions that overlap or are disposed below the adjacent features.

As used herein, the terms "below," "above," "upper," "lower," "horizontal," or " May be used to describe the relationship of one constituent member, layer or regions with other constituent members, layers or regions, as shown in the Figures. It is to be understood that these terms encompass not only the directions indicated in the Figures but also the other directions of the devices.

In the following, embodiments of the present invention will be described with reference to cross-sectional views schematically illustrating ideal embodiments (and intermediate structures) of the present invention. In these figures, for example, the size and shape of the members may be exaggerated for convenience and clarity of explanation, and in actual implementation, variations of the illustrated shape may be expected. Accordingly, embodiments of the present invention should not be construed as limited to any particular shape of the regions shown herein. In addition, reference numerals of members in the drawings refer to the same members throughout the drawings.

FIGS. 1A to 1D are cross-sectional views of a light emitting transistor according to one embodiment of the present invention, and FIG. 1E is a perspective view of a light emitting transistor according to an embodiment of the present invention.

1A, a light emitting transistor 100 includes a first electrode E1, a P-type semiconductor P electrically connected to the first electrode E1 and having first and second surfaces facing each other, A gate electrode S1 including an insulating film bonded to a first surface of the P-type semiconductor P, an N-type semiconductor N and an N-type semiconductor N forming a PN junction with the second surface of the P- And a second electrode (E2) electrically connected to the first electrode (N).

The P-type semiconductor P may include at least one P-type porous silicon nanowire P having a direct bandgap characteristic and the N-type semiconductor N may include an N-type zinc oxide nano-thin film N . The aspect ratio of the P-type porous silicon nanowire (P) is in the range of 700 to 813, and the P-type porous silicon nanowire (P) may have a single crystal preferentially oriented in the <100> direction. In addition, the surface of the P-type porous silicon nanowire (P) may have a quantum confinement effect due to the nano-sized surface roughness and porosity.

The P-type porous silicon nanowire (P) is characterized in that, in the visible light region in the range of 300 nm to 800 nm, a single peak is deconvoluted into at least two or more sub-peaks centered on photon energies in the range of 1.5 eV to 3.5 eV And can have a micro-optical luminescence spectrum. For example, in the microphotoluminescence spectrum of the P-type porous silicon nanowire (P) to be described later, a wide range of single peaks has four sub-peaks centered on photon energies of 1.84 eV, 2.13 eV, 2.41 eV and 2.97 eV, It can be rode deconvolution. The sub-peaks may be caused by the formation of energy levels between the bandgaps of the material due to defects or impurities. In other words, when measuring micro-optical luminescence, electrons can be excited by an energy source (for example, a laser source), and then the electrons can be relaxed to confirm the energy difference. Sub-peaks may appear by an excitation relaxation process through the energy level (due to defects or impurities) between the conduction band and the valence band, rather than the excitation-relaxation (bandgap) of the electrons through. Therefore, energy levels generated by defects or impurities can be identified through the deconvoluted sub-peaks.

The thickness of the N-type zinc oxide nano-thin film (N) formed on the P-type porous silicon nanowire (P) is in the range of 90 nm to 120 nm, and the ultraviolet region and the red region And can have two peaks corresponding to the region. At this time, the peak corresponding to the red series region may have a microphotoluminescence spectrum deconvoluted into at least two or more sub-peaks at the centers of photon energies in the range of 1.5 eV to 3.5 eV. For example, in the microphotoluminescence spectra of the N-type zinc oxide nano-thin film (N) formed on the P-type porous silicon nanowire (P), the broad spectrum of the red series region is 1.72 eV, 1.85 eV and 2.0 eV Can be deconvoluted into three sub-peaks corresponding to photon energy. In addition, the light emitting transistor 100 may have an electroluminescence spectrum in which the peak corresponding to the red series region is deconvoluted into at least two or more sub-peaks centered on photon energies in the range of 1.5 eV to 3.0 eV.

The gate electrode S1 including the insulating film may be composed of a heavily doped P-type silicon substrate having a thermally grown silicon oxide layer. The silicon oxide layer is used as an insulating film of the gate electrode S1, and a heavily doped P-type silicon substrate can be used as a gate electrode. The P-type silicon substrate is exemplary, and in another embodiment, a heavily doped N-type silicon substrate may be used as the gate electrode S1.

In another embodiment of the present invention, the gate electrode S1 including the insulating film may be formed of an insulating ceramic, a semiconductor, an insulating polymer, or a structure having a conductive material layer as a gate electrode and an insulating film formed on the conductive material layer on an insulated metal substrate Lt; / RTI &gt; In some embodiments, the conductive material layer may be a metal thin film, a conductive metal oxide thin film, a doped semiconductor layer, or a conductive nanowire laminate.

The metal thin film may be formed of a metal such as gold (Au), silver (Ag), platinum (Pt), palladium (Pd), aluminum (Al) or an alloy thereof. The transparent conductive metal oxide thin film may be at least one selected from the group consisting of indium tin oxide (ITO), fluorine doped tin oxide (FTO), aluminum doped zinc oxide (AZO) May be a transparent conductive oxide (TCO) such as gallium doped zinc oxide (GZO) or boron doped zinc oxide (BZO). However, the metal oxide thin film in the present invention is not limited thereto. The conductive nanowire laminate may be a metal such as gold, silver, platinum, palladium, aluminum, copper, or an alloy thereof, and the nanowire may be a nanowire, a nanotube, or a nanorod.

The insulating layer formed on the conductive material may include at least one of silicon oxide (SiO ₂ ), silicon oxynitride (SiON), silicon nitride (Si ₃ N ₄ ), silicon oxycarbide (SiOC) (Al ₂ O ₃ ), hafnium oxide (HfO ₂ ), zirconium oxide (ZrO ₂ ), yttrium oxide (Y ₂ O ₃ ), silicon oxide ), Tantalum oxide (Ta ₂ O ₅ ), titanium oxide (TiO ₂ ), lanthanum oxide (La ₂ O ₃ ).

The gate electrode S1 including the insulating film may be formed by applying an electric field to the P-type semiconductor P so that the hole concentration of the P-type semiconductor P and the Fermi level At least one can be controlled. For example, when a negative electric field is applied to the P-type semiconductor P through the gate electrode S1 including the insulating film, the Fermi level of the P-type semiconductor P shifts to the conduction band edge, ) And the N-type semiconductor N, the amount of the carrier to be transferred can be increased. On the other hand, when a positive electric field is applied to the P-type semiconductor P through the gate electrode S1 including the insulating film, the Fermi level of the P-type semiconductor P shifts to the valence band edge, P) and the N-type semiconductor N can be reduced, so that the amount of carrier to be transferred can be reduced.

In one embodiment of the present invention, one of the two first electrodes E1 is a dummy electrode, which uses a dielectrophoretic wave to be described later to cause the P-type semiconductor P to be sandwiched between the first electrodes E1 And the light emitting transistor 100 is not used for light emission.

1A, the P-type semiconductor P is aligned across the two first electrodes E1, and the P-type semiconductor P is formed by the thickness of the first electrode E1, A space V1 may be formed between the electrodes S1. The space V1 between the P-type semiconductor P and the gate electrode S1 including the insulating film may be filled with the material of the N-type semiconductor N (for example, zinc oxide).

In another embodiment of the present invention, as shown in FIG. 1B, the P-type semiconductor P is formed on the gate electrode S1 including the insulating film without the space V1 between the P- May be formed on the surface of the substrate S1. In addition, a part of the P-type semiconductor P electrically connected to the first electrode E1 may be formed on the surface of the first electrode E1.

In another embodiment of the present invention, as shown in FIG. 1C, the P-type semiconductor P is formed on the gate electrode S1 including the insulating film without the space V1 between the P- And may be formed on the surface of the electrode S1. 1B shows a state in which a part of the P-type semiconductor P is formed on the first electrode E1 and is electrically connected to the first electrode E1, The ends can be electrically connected.

In one embodiment of the present invention, the light emitting transistor 100 includes an N-type zinc oxide nano-thin film (N) / P-type porous silicon nanowire (P) as an inorganic nano light- .

1D, an inorganic nano-luminescent transistor composed of a P-type porous silicon nanowire (P) and an N-type zinc oxide nano-thin film (N) is formed on a heavily doped P-type silicon substrate having a thermally grown silicon oxide layer . The heavily doped P-type silicon substrate having the thermally grown silicon oxide layer can be used as a gate electrode including an insulating film.

In the present invention, it is possible to control the hole concentration and the Fermi level of a P-type nano material (for example, a P-type porous silicon nano wire (P)) by using an electric field generated by applying a voltage to a gate electrode An inorganic nano-luminescent transistor may be provided. This allows the inorganic nano-luminescent transistor to emit light as well as self-switching characteristics as compared with the conventional light-emitting transistor.

Further, in the case of the P-type material, the porous silicon nanowire (P) exhibiting the bandgap characteristic directly at the nanoscale due to the quantum confinement effect can be synthesized by chemical etching with a metal catalyst as an auxiliary, A patterned N-type zinc oxide nanotube film (N) having a wide band gap of about 3.25 eV can be deposited on the P-type porous silicon nanowire (P). Finally, an inorganic nano-luminescent transistor composed of an N-type zinc oxide nanotube (N) / P-type porous silicon nanowire (P) is grown on a heavily doped P-type silicon substrate with a thermally grown 300 nm thick silicon oxide layer As shown in FIG.

The luminescence characteristics of the self-switchable device through the modulation of the Fermi level of the P-type porous silicon nanowire (P) will be described with reference to FIGS. 3A to 8B described later. For example, the I-V characteristic curve of the light-emitting transistor and the micro-optical luminescence or electroluminescence luminescence characteristics can be analyzed as a function of the gate voltage (Vg). As the gate voltage varies within a range of 0 V to -20 V, the current level and emission intensity of the red (orange-red) region are compared with the current level and emission intensity at the gate voltage of 0 V, With a forward bias of 20 V, up to 3 times and 2 times, respectively. On the other hand, as the gate voltage approaches 10 V, the current level decreases, the emission intensity decreases, and then finally switches off. This result is due to the modulation of the Fermi level of the P-type porous silicon nanowire (P) and the built-in potential barrier at the PN junction due to the electric field generated by applying a voltage to the gate electrode.

In another embodiment of the present invention, the light emitting transistor may be arranged in an array, as in Fig. For example, the light emitting transistor may be configured as a horizontal or vertical tile, but the present invention is not limited thereto.

Referring to FIG. 1E, a PN junction may be formed in proportion to the array size of the light emitting transistor. For example, 3? Three PN junctions may be formed in the light emitting transistor having one array size.

The P-type semiconductor (P) material in FIGS. 1A to 1E is based on a nanowire shape instead of a thin film shape, but the present invention is not limited thereto. For example, the P-type semiconductor (P) material of FIGS. 2A and 2B may have a thin film form like an N-type semiconductor (N) material.

2A and 2B are a cross-sectional view and a perspective view, respectively, of a light emitting transistor according to another embodiment of the present invention.

2A and 2B, a P-type semiconductor film P is formed on a gate electrode S1 including an insulating film, and an N-type semiconductor film N is formed on a P-type semiconductor film P . Here, a PN junction may be formed between the P-type semiconductor film (P) and the N-type semiconductor film (N). An electrode may be formed to implant carriers (e.g., electrons and holes) into the P-type semiconductor film P and the N-type semiconductor film N, respectively. For example, the first electrode E1 may be formed on the P-type semiconductor film P together with the N-type semiconductor film N, and the second electrode E2 may be formed on the N-type semiconductor film N . At this time, since the N-type semiconductor film N and the first electrode E1 are formed on the same P-type semiconductor film P, the N-type semiconductor film N and the first electrode E1 are formed on the same P- May be spaced apart from each other by a gap interval.

3A is a scanning electron microscope (SEM) image of a P-type porous silicon nanowire P in a light emitting transistor according to an embodiment of the present invention, and FIG. 3B is a scanning electron microscope FIG. 3C is a transmission electron microscope (TEM) image showing the rough surface of the P-type porous silicon nanowire P in the light emitting transistor according to an embodiment of the present invention. FIG. ), Which is a transmission electron microscope image. FIG. 3D is a microphotoluminescence spectrum of a P-type porous silicon nanowire (P) in a light emitting transistor according to an embodiment of the present invention.

3A to 3C, the length of the P-type porous silicon nanowire P is in the range of 70 to 130 mu m, the diameter is in the range of 100 to 160 nm, and the aspect ratio is in the range of 700 to 813. In one embodiment of the present invention, the average length and diameter of the P-type porous silicon nanowire (P) may be 100 탆 and 130 ㎚, respectively.

Due to the small diameter of the P-type porous silicon nanowire (P) and the high aspect ratio of about 770, the P-type porous silicon nanowire (P) can be bent like a hair and can be formed into a honeycomb structure have. Further, the surface of the P-type porous silicon nanowire (P) is very rough and may have a single crystal preferentially oriented in the <100> direction.

In general, the bandgap of bulk silicon is about 1.1 eV and can emit light having a wavelength centered at a wavelength of about 1130 nm in the infrared region of the room temperature micro-optical luminescence spectrum. When the diameter of the silicon nanowire is less than 5 nm, the silicon bandgap of the nanowire structure can be extended to about 3.5 eV (at a diameter of about 1.3 nm) due to the quantum confinement effect in the conduction band and the valence band, The center of the spectrum can be moved to the visible ray region. Therefore, the P-type porous silicon nanowire (P) has an average diameter of 130 nm, so that the band gap expansion is not expected. However, due to the nano-sized surface roughness and porosity, .

Referring to FIG. 3D, the micro-optical luminescence spectrum of the porous silicon nanowire (P) appears throughout the visible light region. This broad range of single peaks can be deconvoluted into four sub-peaks centered on photon energies of 1.84 eV, 2.13 eV, 2.41 eV, and 2.97 eV, which can be attributed to the quantum confinement effect of nanocrystals on the surface of porous silicon nanowires Can be attributed. In particular, light emission at 2.97 eV is due to the oxidized structure and may be due to contaminated or defective SiOx. In addition, other light emissions (e.g., 1.84 eV, 2.13 eV, 2.41 eV) are catalyzed by chemical termination of the surface of the P-type porous silicon nanowire (P) by SiFxHy during a chemical- . &Lt; / RTI &gt;

4A is a scanning electron microscope image showing a structure having an aluminum electrode / N-type zinc oxide nanotube (N) / P-type porous silicon nanowire (P) / gold electrode in a light emitting transistor according to an embodiment of the present invention 4b is a transmission electron microscope image showing the interface between the N-type zinc oxide nanofiber N and the P-type porous silicon nanowire P in the light emitting transistor according to an embodiment of the present invention, Is a microphotoluminescence spectrum of an N-type zinc oxide nano-thin film (N) formed on a P-type porous silicon nanowire (P) in a light emitting transistor according to an embodiment of the present invention.

Using the porous silicon nano wire P as a p-type semiconductor, the light emitting transistor 100 can be manufactured in six steps as shown in FIG. 9 described later. Typically, since the majority carriers of the P type material and the N type material are different (for example, P type - hole, N type - electron), the carrier concentration is the electric field generated by applying a voltage to the gate electrode Lt; RTI ID = 0.0 &gt; modulated by &lt; / RTI &gt; Therefore, in order to control the performance of the PN junction-based device by an electric field generated by applying a voltage to the gate electrode, one of the P-type or N-type material is mainly influenced by an electric field generated by applying a voltage to the gate electrode And the like. For this, a laminated structure composed of an N-type zinc oxide nano-thin film (N) is designed on a P-type porous silicon nanowire (P), and the light emitting transistor 100 according to an embodiment of the present invention includes a P- Doped P-type silicon substrate (as the lower gate electrode) having a thermally grown silicon oxide layer (as gate insulator) approximately 300 nm thick, which acts as a control gate for the modulation of the Fermi level of the substrate P .

Referring to FIG. 4A, a P-type porous silicon nanowire (P) is formed of N-type zinc oxide (P), which is vertically aligned between a gold electrode and an aluminum electrode and is patterned by a hydrochloric acid (HCl) vapor etching process The nanofilm N may be formed on a heavily doped P-type silicon substrate comprising a P-type porous silicon nanowire (P) and a silicon oxide layer. Here, in order to determine the interface between the N-type zinc oxide nanofiber N and the P-type porous silicon nanowire P, the cross section of the rectangular region in FIG. 4A was analyzed by transmission electron microscope, and the result is shown in FIG.

4B, region A is a body of P-type porous silicon nanowire (P) exhibiting monocrystallinity, region B is a body of P-type porous silicon nanowire (P) and P-type porous silicon nanowire And the interface between the deposited N-type zinc oxide nano-thin film (N). Partial crystalline properties appear in the region B, and some amorphous phase, which is believed to be oxidized silicon, may be present at 2.97 eV in Fig. 3 D above, resulting in micro-optical luminescence emission peaks. In region C, the N-type zinc oxide nanotube (N) deposited on the P-type porous silicon nanowire (P) and the P-type porous silicon nanowire (P) Is used as a template for N-type zinc oxide nanofiltration (N) deposition, it can exhibit polycrystalline properties even when deposited at about 300 ° C.

Referring to FIG. 4C, the microphotoluminescence spectra of the N-type zinc oxide nanotubes (N) deposited on the P-type porous silicon nanowire (P) obtained at room temperature are shown in an ultraviolet region and a red (orange) Respectively. In the former, the first peak appearing in the ultraviolet region is generated from the NBE (near band edge) of the N-type zinc oxide nanotube film (N), and the latter (i.e., the peak appearing in the red series region) (DLE) of the signal (N). The NBE is light emission by free exciton emission, and the DLE may be light emission by defect.

In addition, the broad spectrum of the red series region can be deconvoluted into three sub-peaks corresponding to photonic energies of 1.72 eV, 1.85 eV and 2.0 eV, respectively. Emission at 2.0 eV can be due to recombination between the electrons of the interstitial zinc and the holes of the interstitial oxygen. Furthermore, other emissions at 1.72 eV and 1.85 eV can be attributed to recombination between extended interstitial zinc and oxygen depletion and recombination between extended interstitial zinc and interstitial oxygen, respectively.

5 is a graph showing the IV characteristics of the light emitting transistor 100 including the N-type zinc oxide nano-thin film N formed on the P-type porous silicon nanowire P according to the embodiment of the present invention, And 6B are energy band diagrams of the light emitting transistor 100 according to the gate voltage according to an embodiment of the present invention. Here, the light emitting transistor has a structure including a source, a drain, a gate, and a PN junction.

Referring to FIG. 5, in the voltage VAu-Al between the gold electrode and the aluminum electrode, the drain current I increases exponentially with the forward bias and is maintained almost at zero at the reverse bias . As the contact between the gold electrode / P-type porous silicon nanowire (P) and the aluminum electrode / N-type zinc oxide nano-thin film (N) exhibits excellent ohmic behavior, (P) and the N-type zinc oxide nanotube film (N). Further, for various gate voltage values in the range of 10 V to -20 V, the drain current level may increase with the negative gate voltage at the forward bias. This means that the gate voltage can affect the Fermi level of the P-type porous silicon nanowire (P) rather than the Fermi level of the N-type zinc oxide nanotube (N). If the gate voltage controls the Fermi level of the N-type zinc oxide nano-thin film (N) on the P-type porous silicon nanowire (P), the conduction band edge of the N-type zinc oxide nano thin film (N) It may be far from the Fermi level. Electron numbers increased in the conduction band of the N-type zinc oxide nanotube (N) can be transferred to the conduction band of the P-type porous silicon nanowire (P). In the same way, the holes of the valence band of the P-type porous silicon nanowire (P) actively move to the valence band of the N-type zinc oxide nanotube film (N), resulting in an increase in current at a positive gate voltage. However, in this case, the current may not be increased while applying a positive gate voltage.

This result implies that the applied gate voltage mainly affects the Fermi level of the P-type porous silicon nanowire (P). When a negative gate voltage is applied, the valence band edge of the P-type porous silicon nanowire (P) can move away from the Fermi level. Thus, in the forward bias, the increased number of carriers can be delivered with a sharply increasing negative gate voltage. This tendency is due to the fact that the potential energy difference formed at the PN junction between the P-type porous silicon nanowire (P) and the N-type zinc oxide nanotube film (N) increases so that the turn-on voltage is approximately 11.99 V to 8.9 V And increases the current magnitude. The increase of the current magnitude can also be explained from the following PN diodes [1] and [2].

[Equation 1]

&Quot; (2) &quot;

Where J is the current density of the ideal PN junction diode, e is the electron charge, and Dp and Dn are the diffusion coefficients of the hole and electron, respectively. pn0 and np0 are the p-type semiconductor and the n-type semiconductor minority carrier concentration in the equilibrium state, V is the voltage applied to the PN junction, k and T are the Boltzmann constant and It is an absolute temperature.

Referring to FIG. 6A, as the negative gate voltage is applied higher, the Fermi level becomes closer to the conduction band edge in the P-type porous silicon nanowire (P), so that electrons in the P-type porous silicon nanowire (P) pn0) can be increased. Therefore, the current density (JS) value of the above-mentioned formula (1) and the drain current (I) observed in the I-V curve can be increased. When the negative gate voltage and the reverse bias are applied, the exp (eV / kT) term of Equation (2) can be ignored and the off current-JS can be ignored in accordance with the IV characteristic in the inset Can be large.

Referring to FIG. 6B, since the valence band edge of the P-type porous silicon nanowire P approaches the Fermi level even when the forward bias is applied at the voltage between the gold electrode and the aluminum electrode, The current magnitude can be suppressed. At the same time, by a reduction in the potential energy difference at the PN junction of the transferred carriers.

7A and 7B are electro-luminescence spectra of a light emitting transistor according to an embodiment of the present invention.

Referring to FIG. 7A, when a forward bias of 20 V and a gate voltage of -20 V are applied, an electroluminescence spectrum in which a red (orange-red) emission is observed from the light emitting transistor 100 appears. At this time, a wide single electroluminescence peak can be deconvoluted into four sub-peaks centered on photonic energies of 1.72 eV, 1.85 eV, 2.0 eV and 2.41 eV, respectively.

Referring to FIG. 7B, an electroluminescence spectrum appears at a forward bias of 20 V for different gate voltage values. The emission intensity can be increased as the gate voltage is changed from 0 V to -20 V due to the increased current amplitude described in FIGS. 6A and 6B. On the other hand, when the gate voltage changes from 0 V to 10 V, the luminescence intensity is reduced, and can eventually be turned off due to a decrease in the potential energy difference.

8A and 8B are energy band diagrams of a light emitting transistor before and after a PN junction according to an embodiment of the present invention. 8A is an energy band diagram of an N-type zinc oxide nanofiber N on a P-type porous silicon nanowire P and a P-type porous silicon nanowire P isolated before the PN junction is formed, and FIG. , And an energy band diagram of the N-type zinc oxide nanofiber N on the P-type porous silicon nanowire (P) and the P-type porous silicon nanowire (P) after the PN junction is formed.

8A, the bandgap of the P-type porous silicon nanowire (P) is not clearly defined, but due to the contamination or defects of SiOx as well as the chemical termination of the P-type porous silicon nanowire (P) surface by SiFxHy May be larger than the bandgap of bulk silicon. On the other hand, in the case of the N-type zinc oxide nano-thin film (N), deep layers can be introduced between the band gaps of the N-type zinc oxide nano-film (N) containing the transition between different charge states. Oxygen depletion and interstitial oxygen levels operating as acceptors are located at approximately 0.9 eV and 1.09 eV, respectively, than the valence band minimum, so that transition from interstitial zinc and extended interstitial zinc is 1.72 eV or 2.0 eV It is possible to generate luminescence having energy.

In addition, the above-mentioned peak at 1.84 eV from the P-type porous silicon nanowire (P) and the above-mentioned peak at 1.85 eV from the N-type zinc oxide nanotube film (N) almost overlap in the microphotoluminescence spectrum , The generation of a peak at 1.85 eV is not clear compared to the other three emission peaks. However, since the strongest peak (corresponding to the photon energy of 2.41 eV) generated in the P-type porous silicon nanowire (P) is observed at a very small intensity compared with the other three peaks of the electroluminescence spectrum, Is believed to be due to the transition between the intruded zinc and the interstitial oxygen extended in the N-type zinc oxide nanotube (N) rather than the quantum confinement effect of the P-type porous silicon nanowire (P).

FIG. 8B shows energy band diagrams and radiative recombination paths of the P-type porous silicon nanowire (P) and the N-type zinc oxide nano-thin film (N) after forming the PN junction. In the P-type porous silicon nanowire (P), electrons injected from the N-type zinc oxide nano-thin film (N) are attracted to the holes of the valence band of the modified energy band structure of the P- So that a weak green light of 2.41 eV can be generated (path 1 in FIG. 8B). As more holes are transported from the P-type porous silicon nanowire (P) to the N-type zinc oxide nanotubes (N), the interstitial zinc and interstitial oxygen, between the extended interstitial zinc and oxygen depletion, Red-orange (orange-red) light resulting from recombination between zinc and interstitial oxygen (path 2 &amp; cir &amp;

In another embodiment of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: preparing a substrate; forming at least one first electrode and at least one dummy electrode spaced apart from the at least one first electrode on the substrate; Forming a P-type semiconductor across the one electrode and the at least one dummy electrode; Forming an N-type semiconductor on the formed P-type semiconductor, and forming a second electrode on the formed N-type semiconductor. The P-type semiconductor may be formed by dielectrophoretic alignment using the at least one first electrode and the at least one dummy electrode.

The forming of the second electrode may include patterning the second electrode on the N-type semiconductor formed, forming an etching mask on the patterned second electrode, forming the second electrode using the etching mask, Etching the part of the N-type semiconductor in a region other than the N-type semiconductor of the bottom of the two electrodes, and removing the etching mask.

The P-type semiconductor includes at least one P-type porous silicon nanowire (P) having a direct bandgap characteristic, and the N-type semiconductor may include an N-type zinc oxide nano-thin film (N). The P-type porous silicon nanowire (P) can be synthesized by a chemical etching process with a metal catalyst as an auxiliary from a P-type silicon wafer doped with an impurity having a resistivity within a range of 1? Cm to 10?? Cm.

9 is a view illustrating a method of manufacturing a light emitting transistor according to an embodiment of the present invention.

Referring to FIG. 9, in a first step, a first electrode patterning and a P-type porous silicon nanowire (P) alignment may be performed. For example, a silicon substrate doped with a p-type impurity having a silicon oxide layer with a thickness of approximately 300 nm, which is first grown thermally, is doped with a piranha solution (98% H2SO4: 60% H2O2 = 3: 1 v / Min, and then sonicated in deionized water approximately twice for about 10 minutes.

A gold electrode about 100 nm thick with a gap distance of about 24 탆 can then be formed on the cleaned substrate by photolithography followed by electron beam (e-beam) deposition. For example, at least one P-type porous silicon nanowire (P) can be synthesized by a chemical etching process with a metal catalyst as an aid from a P-type silicon wafer doped with an impurity having a resistivity in the range of 1 Ωcm to 10 Ωcm have. In addition, a dielectrophoretic alignment process can be applied to connect the P-type porous silicon nanowire (P) between the gold electrodes. The prepared P-type porous silicon nanowire (P) may be dispersed in ethanol containing about 0.05% diluted hydrazine at a density of 7 × 10 8 NWs · mL ^-1 . 4 μL of the silicon nanowire dispersion solution was dropped on the gold electrode, and a direct current (DC) bias having a frequency of 1 kHz, an amplitude of 10 Vpp, and a pulse of 500 μs was supplied to the electrode for 3 seconds, One or more P-type porous silicon nanowires (P) may be vertically aligned between the gold electrodes.

In step 2, an N-type zinc oxide nanotube film (N) can be deposited. For example, radio-frequency (RF) power of 150 W, operating pressure of 5 mTorr, radio-frequency magnetron sputtering for 30 minutes at a temperature of 300 DEG C in an argon (Ar) A 120 nm thick N-type zinc oxide nanotube film (N) can be deposited on the structure of the P-type porous silicon nanowire (P) / gold electrode / substrate.

In step 3, aluminum electrode deposition and N-type zinc oxide nanotube (N) patterning may be performed. For example, aluminum electrodes of about 8 탆 width and about 100 nm thickness can be deposited on the N-type zinc oxide nano-thin film (N) by photolithography and electron beam evaporation. For the patterning of the N-type zinc oxide nano thin film (N), a vapor etching process using hydrogen chloride using photoresist (PR) as an etching mask can be performed.

In step 4, in order to protect the aluminum electrode during the etching process and to block the penetration of the hydrogen chloride vapor into the interface between the aluminum electrode and the N-type zinc oxide nano-thin film (N), a 15- Can be formed. Then, in step 5, the structure is exposed to 35% hydrogen chloride vapor for 10 seconds, and the N-type zinc oxide nanotube (N) can be etched except for the area covered by the photoresist etch mask. In step 6, the photoresist etch mask is removed by acetone and methanol to leave an aluminum electrode and a patterned N-type zinc oxide nanotube film (N) on the P-type porous silicon nanowire (P).

10A is an optical microscopy image showing a PN junction between an N-type zinc oxide nano-film (N) and a P-type porous silicon nanowire (P) in a light emitting transistor according to an embodiment of the present invention, 10b to 10h are orange-red emission images in the light emitting transistor manufactured by the manufacturing method of FIG. FIGS. 10B through 10H are luminescent images of a red series (orange-red) for different gate voltage values in the range of 10 V to -20 V. FIG. The aluminum electrode and the N-type zinc oxide nanotube film (N) are clearly defined in the P-type porous silicon nanowire (P) (see FIG. 10A). The light emitting position can coincide with the light emitting position of the junction between the P-type porous silicon nanowire (P) and the N-type zinc oxide nano-thin film (N).

Referring to FIG. 10D, red light of a visible type is generated at a gate voltage of 0 V (see FIG. 10D), and referring to FIGS. 10B to 10C, light can be switched off at a positive gate voltage have. Referring to Figs. 10E to 10H, as the absolute value of the gate voltage increases from -5 V to -20 V, the light can be intensified.

As described above, by controlling the hole concentration and the Fermi level of the P-type porous silicon nanowire (P), the P-type porous silicon nanowire (P) / N-type zinc oxide nanotube (N) 100 may be provided. Further, the light emitting transistor 100 of the present invention exhibits self-switching capable of emitting light. The P-type porous silicon nanowire (P) is synthesized by a chemical etching method with a metal catalyst as an aid, and a quantum confinement effect provides a rough and porous surface with a wider energy band of the P-type porous silicon nanowire (P) . In addition, the surface of the P-type porous silicon nanowire (P) is contaminated by SiFxHy in a chemical etching process with the aid of a metal catalyst and can be partially oxidized. This can be confirmed by a microphotoluminescence spectrum that can be deconvoluted into four sub-peaks with photon energies at 1.72 eV, 1.85 eV, 2.0 eV and 2.41 eV. The microphotoluminescence spectra of the N-type zinc oxide nanotubes (N) having the polycrystallinity grown on the P-type porous silicon nanowire (P) were measured by ultraviolet light and red light (orange- Red) can be deconvoluted into two peaks in the range. The light emitting transistor 100 is formed on the silicon substrate doped with the heavily doped p-type impurity having the thermally grown silicon oxide layer by using the p-type porous silicon nano wire (P) and the n-type zinc oxide nano thin film (N) Can be finally formed. When the forward bias is applied to the light emitting transistor 100, the IV characteristic of the PN junction diode is obtained, and the light emission of the red (orange-red) range corresponding to the deep level of the N-type zinc oxide nano- Can be observed. Further, it can be seen that the present invention controls the light emission intensity of the light emitting transistor 100 by controlling the gate voltage. This structure can easily simplify the fabrication process and the structure of the components of the display by combining the two roles of light emission and self-switching in a single device. This enables the integrated manufacture of display components that was not possible with the prior art.

In addition, when an integrated technology of a gallium nitride (GaN) based light emitting diode is developed as an active driving type organic light emitting diode display in the present invention, an active driving type inorganic light emitting display can be realized. Further, the light emitting transistor 100 of the present invention can easily control the Fermi level of the selected semiconductor to generate an improved electron-hole recombination and to modulate the turn-on voltage of the light emitting transistor 100. [

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention as defined in the appended claims. It will be clear to those who have knowledge.

E1: first electrode
P: P-type semiconductor
S1: substrate, gate electrode
N: N type semiconductor
E2: Second electrode

Claims (17)

A first electrode;
A P-type semiconductor electrically connected to the first electrode and having a first surface and a second surface opposite to each other;
An insulating film formed on the first surface of the P-type semiconductor and a gate electrode on the insulating film;
An N-type semiconductor forming a PN junction with the second surface of the P-type semiconductor; And
And a second electrode electrically connected to the N-type semiconductor,
Wherein the gate electrode controls at least one of a hole concentration and a Fermi level of the P type semiconductor by applying an electric field to the P type semiconductor,
Wherein the P-type semiconductor includes at least one P-type porous silicon nanowire having a direct bandgap characteristic, and the N-type semiconductor includes an N-type zinc oxide nanotube. The method according to claim 1,
And the N-type semiconductor is further formed between the insulating film and the first surface of the P-type semiconductor. The method according to claim 1,
Wherein the aspect ratio of the P-type porous silicon nanowire is in the range of 700 to 813. The light- The method according to claim 1,
Wherein the P-type porous silicon nanowire has a single crystal preferentially oriented in the <100> direction. The method according to claim 1,
Wherein the P-type porous silicon nanowire is a micro-optical phosphor that is deconvoluted into at least two or more sub-peaks centered on photon energy in the range of 1.5 eV to 3.5 eV in the visible light region in the range of 300 nm to 800 nm. A light emitting transistor having a ness spectrum. The method according to claim 1,
Wherein a quantum confinement effect is generated on the surface of the P-type porous silicon nanowire due to nano-sized surface roughness and porosity. The method according to claim 1,
Wherein the thickness of the N-type zinc oxide nano-thin film is within a range of 90 nm to 120 nm. The method according to claim 1,
Wherein the N-type zinc oxide thin film has two peaks corresponding to an ultraviolet ray region and a red series region in a visible light region in a range of 300 nm to 800 nm,
Wherein the peak corresponding to the red series region is deconvoluted into at least two or more sub-peaks centered on photon energies in the range of 1.5 eV to 3.5 eV. The method according to claim 1,
When a negative electric field is applied to the P-type semiconductor, the potential energy difference at the junction between the P-type semiconductor and the N-type semiconductor increases, the Fermi level of the P-type semiconductor shifts to the conduction band edge, Is increased,
When a positive electric field is applied to the P-type semiconductor, the potential energy difference at the junction between the P-type semiconductor and the N-type semiconductor decreases, the Fermi level of the P-type semiconductor moves to the valence band edge, Wherein the amount of carriers is reduced. The method according to claim 1,
Wherein the peak corresponding to the red series region is deconvoluted into at least two or more sub-peaks at the center of the photon energy in the range of 1.5 eV to 3.0 eV. The method according to claim 1,
Wherein the gate electrode comprises a heavily doped P-type silicon substrate having a thermally grown silicon oxide layer. The method according to claim 1,
Wherein the PN junction between the P-type semiconductor and the N-type semiconductor has at least some amorphous phase that generates a micro-optical luminescence emission peak. Preparing a substrate;
Forming at least one first electrode on the substrate and at least one dummy electrode spaced apart from the at least one first electrode;
Forming a P-type semiconductor across the at least one first electrode and the at least one dummy electrode;
Forming an N-type semiconductor on the P-type semiconductor formed; And
And forming a second electrode on the formed N-type semiconductor,
Wherein the P-type semiconductor includes at least one P-type porous silicon nanowire having a direct bandgap characteristic, and the N-type semiconductor includes an N-type zinc oxide nanofiltration film. 14. The method of claim 13,
Wherein the P-type semiconductor is formed by dielectrophoretic alignment using the at least one first electrode and the at least one dummy electrode. 14. The method of claim 13,
Wherein forming the second electrode comprises:
Patterning the second electrode on the formed N-type semiconductor
Forming an etch mask on the patterned second electrode;
Etching a portion of the N-type semiconductor in a region other than the N-type semiconductor at the bottom of the second electrode using the etching mask; And
And removing the etching mask. delete A first electrode; A P-type semiconductor electrically connected to the first electrode and having a first surface and a second surface opposite to each other; An insulating film formed on the first surface of the P-type semiconductor and a gate electrode on the insulating film; An N-type semiconductor forming a PN junction with the second surface of the P-type semiconductor; And a second electrode electrically connected to the N-type semiconductor,
Wherein the gate electrode controls at least one of a hole concentration and a Fermi level of the P type semiconductor by applying an electric field to the P type semiconductor,
Wherein the P-type semiconductor includes at least one P-type porous silicon nanowire having a direct band gap characteristic, and the N-type semiconductor includes a light emitting transistor including an N-type zinc oxide nano-thin film.

Images