KR101893844B1 - Display device and method of fabricating the same - Google Patents

Abstract

The display device and the manufacturing method thereof according to the present invention can be applied to a dual link structure for a narrow bezel in which a gate wiring is formed into a double layer including a conductive film which does not react to dry etching Thereby preventing damage to the gate wiring due to dry etching in forming the link portion contact hole.

Description

TECHNICAL FIELD [0001] The present invention relates to a display device and a method of manufacturing the same.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device and a method of manufacturing the same, and more particularly, to a display device using a dual link structure for implementing a narrow bezel and a method of manufacturing the same.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, the use of display devices such as a liquid crystal display (LCD), an organic light emitting display (OLED), and a plasma display panel (PDP) has been increasing.

Such a display device is used in various fields such as a computer such as a notebook computer, a cellular phone, and the like in the field of consumer electronics such as a television (TV) and a video.

Hereinafter, the display device will be described in detail with reference to the drawings.

1 is a plan view schematically showing a general display device.

Fig. 2 is an enlarged plan view of a part of the display device shown in Fig. 1. Fig. 2 is an enlarged view of an E part.

Referring to the drawings, a part of the display device 10 described above, for example, a liquid crystal display device or an organic light emitting display device, includes a pixel portion 20 in which a plurality of subpixels (not shown) And a driving unit for driving the pixels.

The driving unit includes a timing driver (not shown), a data driver 30, and the like. At this time, the data driver 30 is formed on a panel of the display device 10, and the timing driver is formed on a flexible circuit board (not shown) connected to the panel.

For reference, reference numeral 18 denotes a common line.

In the conventional display device 10 constructed as described above, the number of the corresponding line wirings 26 is required to apply the gate signal to each gate line (not shown) of the plurality of subpixels. As a result, in the general display device 10, the link wiring lines 26 are increased in accordance with the increase in the number of gate lines required, and the bezel width W of the display device 10 is increased. A solution to this problem should be sought.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a display device and a method of manufacturing the display device by implementing a narrow bezel by applying a dual link structure.

It is another object of the present invention to provide a display device and a method of manufacturing the same that prevent damages of a gate wiring due to dry etching when forming a link portion contact hole.

Other objects and features of the present invention will be described in the following description of the invention and the claims.

According to an aspect of the present invention, there is provided a display device including a first substrate divided into a pixel portion and a driving portion, a thin film transistor provided in a pixel portion of the first substrate, A gate line extending from the pixel portion, a gate insulating film provided on the gate line and the first link wiring, a second link wiring provided on the gate insulating film, a protective film provided on the second link wiring, And a link portion contact hole for exposing a part of the first link wiring, the gate line, and the second link wiring by removing a part of the protective film.
In this case, the first link interconnection may include upper first link interconnection lines and lower first interconnection interconnection lines of different conductive materials, and the upper first interconnection line may be formed of a conductive material ≪ / RTI >

In this case, each of the first contact hole and the third contact hole exposes the surfaces of the first link wiring and the gate line, and the second contact hole exposes the side surface of the second link wiring.

A first connection electrode electrically connected to the first link wiring and the gate line through the first contact hole and the third contact hole and a second connection electrode electrically connected to the second link and the gate line through the second contact hole and the third contact hole, And a second connection electrode electrically connected to the wiring and the gate line.

Wherein the first link wiring and the second link wiring are alternately formed in the order of the gate line, the first link wiring is formed in the gate wiring layer, the second link wiring is formed in the data wiring layer, , And the interval between the second link wirings is reduced.

At this time, the odd-numbered gate lines are connected to the first link wiring and the even-numbered gate lines are connected to the second link wiring.

The conductive film which does not react with the dry etching includes ITO and aluminum-neodymium.

And the second link wiring and the second connection wiring are in side contact with each other, and the first link wiring and the gate line make a surface contact with the first connection electrode.

And the gate line is composed of an upper gate line made of a conductive film which does not react with the dry etching and a lower gate line made of a low resistance conductive film.

And the first link wiring is composed of an upper first link wiring made of a conductive film which does not react with the dry etching and a lower first wiring wiring made of a low resistance conductive film.

The upper first link wiring and the upper gate line function as an etching stopper film to prevent damage to the first link wiring and the gate line due to the dry etching.
Another display device of the present invention includes a first substrate divided into a pixel portion and a driving portion, a thin film transistor provided in a pixel portion of the first substrate, a first link wiring provided in a driver of the first substrate, A gate insulating film provided on the gate line and the first link wiring, a second link wiring provided on the gate insulating film, a protective film provided on the second link wiring, a part of the gate insulating film and the protective film, A first connection electrode for connecting the first link wiring to the gate line through the link portion contact hole and a second connection wiring for connecting the first link wiring and the gate line through the link portion contact hole, And a second connection electrode connecting the second link wiring and the gate line through the link section contact hole, Wiring may each be composed of an upper first link wire and the lower first link consists of a wire, the upper first link wiring is a conductive material that does not react in the case when etching a contact hole forming portion of the link of the other conductive material.

A method of manufacturing a display device according to the present invention includes the steps of forming a thin film transistor in a pixel portion of a first substrate, forming a gate line extending in a first link wiring and a pixel portion in a driver of the first substrate, Forming a gate insulating film on the first wiring line and the first link wiring, forming a second link wiring on the gate insulating film, forming a protective film on the second link wiring, and forming a part of the gate insulating film and the protective film And forming a link portion contact hole exposing a part of the first link wiring and the gate line and the second link wiring by removing the second link wiring.
At this time, the first link interconnection is formed of upper first link interconnection and lower first interconnection interconnection of different conductive materials, and the upper first interconnection interconnection is formed of a conductive material .

At this time, the protective film and the gate insulating film are etched to form the first contact hole and the third contact hole exposing the surface of the first link wiring and the gate line, respectively, and the third contact hole and the third contact hole exposing the side surface of the second link wiring. 2 < / RTI > contact hole. ≪ RTI ID = 0.0 >

At this time, a first connection electrode electrically connecting to the first link wiring and the gate line is formed through the first contact hole and the third contact hole, respectively, and the first connection electrode is formed through the second contact hole and the third contact hole And forming a second connection electrode electrically connected to the second link wiring and the gate line.

Wherein the first link wiring and the second link wiring are alternately formed in the order of the gate line, the first link wiring is formed in the gate wiring layer, the second link wiring is formed in the data wiring layer, , And the interval between the second link wirings is reduced.

The conductive film which does not react with the dry etching includes ITO and aluminum-neodymium.

As described above, the display device and the method of manufacturing the same according to the present invention are characterized in that in the dual-link structure for the inner bezel, the gate wiring is formed as a double layer including a conductive film which does not react with the dry etching, The damage of the gate wiring due to dry etching can be prevented. As a result, the deterioration of the upper transparent electroconductive film can be suppressed and the defect can be reduced accordingly.

1 is a plan view schematically showing a general display device;
Fig. 2 is an enlarged plan view showing a part of the display device shown in Fig. 1; Fig.
3 is a plan view schematically showing a display device according to the first embodiment of the present invention.
FIG. 4 is an enlarged plan view showing a part of a display device according to the first embodiment of the present invention shown in FIG. 3; FIG.
5 is a cross-sectional view taken along the line A-A 'in the display device according to the first embodiment of the present invention shown in FIG.
6 is a photograph showing damage of a gate wiring due to dry etching.
7 is a plan view schematically showing a display device according to a second embodiment of the present invention.
FIG. 8 is an enlarged plan view showing a part of a display device according to a second embodiment of the present invention shown in FIG. 7; FIG.
9 is a cross-sectional view taken along the line B-B 'in the display device according to the second embodiment of the present invention shown in FIG.
FIGS. 10A to 10E are sectional views sequentially showing the manufacturing process of the display device according to the second embodiment of the present invention shown in FIG. 9; FIG.

Hereinafter, preferred embodiments of a display device and a manufacturing method thereof according to the present invention will be described in detail with reference to the accompanying drawings.

3 is a plan view schematically showing a display device according to the first embodiment of the present invention.

4 is an enlarged plan view showing a part of the display device according to the first embodiment of the present invention shown in FIG. 3, and a part of the link portion E 'is enlarged.

FIG. 5 is a schematic cross-sectional view taken along the line A-A 'in the display device according to the first embodiment of the present invention shown in FIG.

Referring to the drawings, a display device 100 according to a first embodiment of the present invention includes a pixel portion 120 in which a plurality of subpixels (not shown) arranged in a matrix are arranged, .

The driving unit includes a timing driver (not shown) and a data driver 130. At this time, the data driver 130 may be formed on a panel of the display device 100, and the timing driver may be formed on a flexible circuit board (not shown) connected to the panel. However, the present invention is not limited thereto.

Reference numeral 118 denotes a common line.

At this time, the display device 100 includes a flat panel display device such as a liquid crystal display device or an organic light emitting display device.

Although not shown in detail in the drawings, the panel of the display device 100 includes a color filter substrate, which is a first substrate, and an array substrate 110, which is a second substrate, And a liquid crystal layer formed between the color filter substrate and the array substrate 110.

At this time, the color filter substrate may include a black matrix for separating the sub-color filter from the color filter composed of red, green, and blue sub-color filters and blocking light transmitted through the liquid crystal layer, And an overcoat layer formed on the top.

A gate line and a data line are vertically and horizontally arranged on the array substrate 110 to define a pixel region. A thin film transistor, which is a switching element, is formed in a crossing region of the gate line and the data line, that is, in a TFT region.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The thin film transistor may further include a gate insulating layer for insulating between the gate electrode and the source / drain electrode, and an active layer formed between the source electrode and the drain electrode by a gate voltage supplied to the gate electrode. Layer.

The display device 100 according to the first embodiment of the present invention configured as described above includes a number of link wirings 126a and 126b corresponding to the gate lines for applying a gate signal to each gate line of the plurality of subpixels, .

At this time, the display device 100 according to the first embodiment of the present invention applies a dual link structure in which not only gate wirings but also the link wirings 126a and 126b are formed using data wirings, The link wirings 126a and 126b of the display device 100 can be designed to have a smaller width than the conventional link wirings, and the bezel width W 'of the display device 100 can be reduced. That is, in the case of the first embodiment of the present invention, compared to the conventional case in which the link wiring is formed in the same layer, the first layer wiring line 126a and the second link layer As the wiring 126b is formed, the interval between the neighboring link wirings 126a and 126b can be reduced, and the same number of the link wirings 126a and 126b can be designed in a link portion having a width smaller than that of the existing link wirings 126a and 126b.

In the display device 100 according to the first embodiment of the present invention, the second link line 126b formed in the data line layer is connected to the gate line 116 (here, the gate line 116) are required to form the link portion contact holes 140b, 140c for connecting the gate line of the pixel portion to the link portion gate line extending to the driving portion. That is, the second link wiring 126b formed on the data wiring layer is electrically connected to the second connection electrode 145b on the upper side through the second link portion contact hole 140b, while the second connection wiring 145b Is electrically connected to the lower gate line 116 through the third link portion contact hole 140c so that the second link wiring 126b formed in the data wiring layer is connected to the corresponding gate line 116 do.

At this time, the first link wiring 126a formed in the gate wiring layer is electrically connected to the upper first connection electrode 145a through the first link portion contact hole 140a in the same manner, The electrode 145a is electrically connected to the lower gate line 116 through the third link portion contact hole 140c so that the first link wiring 126a formed in the gate wiring layer is electrically connected to the corresponding gate line 116 ).

The first and second link wirings 126a and 126b are alternately formed in the order of the gate line 116. In this case, for example, And the even-numbered gate line 116 may be connected to the second link wiring 126b. However, the present invention is not limited thereto.

The first and second connection electrodes 145a and 145b may be formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). The first link portion contact hole 140a and the second link portion contact hole 140b and the third link portion contact hole 140c are connected to the first and second link wirings 126a and 126b, The first link wiring 126a and the gate line 116 and the second link wiring 126b and the gate line 116 may be formed in such a manner as to pierce the gate line 116. In this case, Side contact with the first connection electrode 145a and the second connection electrode 145b.

In the case of the first embodiment of the present invention, in the dry etching process for forming the link portion contact holes 140a, 140b and 140c, the first link wiring 126a and the gate line 116 may be damaged and the contact resistance with the first and second connection electrodes 145a, 145b may increase. That is, the gate insulating layer 115a and the passivation layer 115b are etched to form the link portion contact holes 140a, 140b, and 140c in the jumping region. At this time, according to the etching process under the same conditions, In the case of the first link interconnection 126a and the gate line 116 to be etched to the gate insulating layer 115a in addition to the first interconnection 126a and the gate line 116 of the contact portion, So that some of the remaining first link wiring 126a and the side surface morphology of the gate line 116 are roughened (see FIG. 6). As a result, ITO disconnection occurs during ITO deposition for the first and second connection electrodes 145a and 145b, or contact resistance increases to cause defects.

Thus, in the display device according to the second embodiment of the present invention, the gate wiring, that is, the first link wiring and the gate line are formed as a double layer including a conductive film which does not react with the dry etching, Thereby preventing damage to the wiring, which will be described in detail with reference to the drawings.

7 is a plan view schematically showing a display device according to a second embodiment of the present invention.

8 is an enlarged plan view showing a part of the display device according to the second embodiment of the present invention shown in Fig. 7, and a part of the link portion E "is enlarged.

FIG. 9 is a schematic cross-sectional view taken along the line B-B 'in the display device according to the second embodiment of the present invention shown in FIG.

Referring to the drawings, a display device 200 according to a second embodiment of the present invention includes a pixel portion 220 in which a plurality of subpixels (not shown) arranged in a matrix are arranged, .

The driving unit includes a timing driver (not shown), a data driver 230, and a level shifter (not shown). At this time, the data driver 230 is formed on a panel of the display device 200, and the timing driver is formed on a flexible circuit board (not shown) connected to the panel or an external system board connected to the flexible circuit board . However, the present invention is not limited thereto, and the timing driver may be formed in the data driver 230 together.

The driving unit is mounted on a panel in the form of an integrated circuit (IC), and a flexible circuit board is attached to the panel. At this time, the panel and the flexible circuit board may be attached by an anisotropic conductive film (ACF).

Reference numeral 218 denotes a common line.

At this time, the display device 200 includes a flat panel display device such as a liquid crystal display device or an organic light emitting display device.

Although not shown in detail in the drawings, the panel of the display device 200 includes a color filter substrate, which is a first substrate, and an array substrate 210, which is a second substrate, And a liquid crystal layer formed between the color filter substrate and the array substrate 210.

At this time, the color filter substrate may include a black matrix for separating the sub-color filter from the color filter composed of red, green, and blue sub-color filters and blocking light transmitted through the liquid crystal layer, And an overcoat layer formed on the top.

A gate line and a data line are vertically and horizontally arranged on the array substrate 210 to define a pixel region. A thin film transistor, which is a switching element, is formed in a crossing region of the gate line and the data line, that is, a TFT region.

The thin film transistor includes a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode. The thin film transistor includes a gate insulating film for insulation between the gate electrode and the source / drain electrode, and an active layer for forming a conduction channel between the source electrode and the drain electrode by a gate voltage supplied to the gate electrode .

The display device 200 according to the second embodiment of the present invention has a number of link wirings 226a and 226a 'corresponding to the gate lines for applying gate signals to the gate lines of the plurality of subpixels, , 226b are required.

At this time, the display device 200 according to the second embodiment of the present invention is configured such that the link wirings 226a, 226a ', 226b are formed by using the data wirings as well as the gate wirings, as in the first embodiment of the present invention described above And a dual link structure formed thereon is applied. As described above, in the case of the second embodiment of the present invention, the first link wirings 226a and 226a 'and the second link wirings 226b are formed in the gate wiring layer and the data wiring layer, respectively, Can be reduced, and the same number of link wirings 226a, 226a ', 226b can be designed in a link portion having a smaller width than the existing link wirings 226a, 226a', 226b.

In particular, in the case of the second embodiment of the present invention, the first link wirings 226a and 226a 'and the gate lines 216 and 216' (here, the gate lines 216 and 216 ' (For example, ITO, aluminum-neodymium (AlNd), or the like) that does not react to dry etching, thereby forming a link portion contact hole Damage to the first link wirings 226a and 226a 'and the gate lines 216 and 216' due to dry etching can be prevented in forming the first and second wiring lines 240a and 240b. The first link wirings 226a and 226a 'and the gate lines 216 and 216' are upper layers, respectively. The first link wirings 226a 'and 227b' are made of a conductive material that does not react with dry etching of ITO, AlNd, A lower gate line 216 'and a lower layer made of a low resistance opaque conductive material such as aluminum (Al), copper (Cu), chromium (Cr), molybdenum (Mo) 1 link wiring 226a and a lower gate line 216. [ However, the present invention is not limited thereto, and the first link wirings 226a and 226a 'and the gate lines 216 and 216' may have a structure of a bilayer or more in which a conductive film which does not react with a dry etching is formed in the uppermost layer .

In the case where the first link wirings 226a and 226a 'and the gate lines 216 and 216' are constituted by two or more layers including ITO in this way, in the dry etching process of the gate insulating layer 215a and the protective layer 215b The ITO of the upper layer acts as an etch stopper so that damage to the gate wiring by the dry etching, that is, the first link wirings 226a and 226a 'and the gate lines 216 and 216' do.

For reference, it was found that ITO deterioration in the jumping region did not occur when the test was conducted for 1000 hours at a temperature of 60 ° C and a humidity of 90%.

The display device 200 according to the second embodiment of the present invention, as in the first embodiment of the present invention described above, applies the second link wiring 226b formed in the data wiring layer to the gate line 216, and 216 ', respectively, are required. That is, the second link wiring 226b formed on the data wiring layer is electrically connected to the upper second connection electrode 245b through the second link portion contact hole 240b, while the second connection electrode 245b Are electrically connected to the lower gate lines 216 and 216 'through the third link portion contact hole 240c, the second link wirings 226b formed on the data wiring layer are electrically connected to the corresponding gate lines 216 and 216' 216 '.

At this time, the first link wirings 226a and 226a 'formed in the gate wiring layer are electrically connected to the first connection electrode 245a at the upper portion through the first link portion contact hole 240a in the same manner, The first connection electrode 245a is electrically connected to the lower gate lines 216 and 216 'through the third link portion contact hole 240c so that the first link wiring 226a formed in the gate wiring layer Are connected to the corresponding gate lines 216 and 216 '.

The first link wirings 226a and 226a 'and the second link wirings 226b are alternately formed in the order of the gate lines 216 and 216'. In this case, for example, the odd gate lines 216, 216 'may be connected to the first link wirings 226a and 226a', and the even gate lines 216 and 216 'may be connected to the second link wirings 226b. However, the present invention is not limited thereto.

The first and second connection electrodes 245a and 245b may be formed of a transparent conductive material such as ITO or IZO. The second link portion contact hole 240b may be formed in a manner to penetrate the second link portion 226b. In this case, the second link portion 226b may be formed on the second connection portion 245b, And side contact. The first link portion contact hole 240a and the third link portion contact hole 240c are formed to expose the upper first link wiring 226a 'and the upper gate line 216', respectively. In this case, The upper first link wiring 226a 'and the upper gate line 216' make surface contact with the first connection electrode 245a on the upper side.

That is, in the case of the present invention, the first link wiring 245a, 245b of the contact portion between the first and second connection electrodes 245a, 245b and the first link wirings 226a, 226a 'and the gate lines 216, 216' The first and second connection electrodes 245a and 245b and the first link wirings 226a and 226a 'and the gate lines 216 and 216' through surface modification of the gate lines 216a and 216a 'and the gate lines 216 and 216' '), Thereby reducing the resistance of the contact portion. Therefore, deterioration of the first and second connection electrodes 245a and 245b due to an increase in contact resistance can be prevented, thereby preventing a failure phenomenon.

In this case, when the upper first link wiring 226a 'and the upper gate line 216' are formed of the same ITO as the first and second connection electrodes 245a and 245b, The contact resistance between the ITO and the third link portion contact holes 240a and 240c can be reduced.

Hereinafter, a manufacturing method of the display device constructed as above will be described in detail with reference to the drawings.

10A to 10E are sectional views sequentially showing a manufacturing process of the display device according to the second embodiment of the present invention shown in FIG. 9, wherein the manufacturing process of the link portion in the driving portion and the manufacturing of the array substrate for a liquid crystal display in the TFT region of the pixel portion The process is shown as an example.

Gate electrodes 221 and 221 'and a pixel portion gate line (not shown) are formed in the pixel portion of the array substrate 210 made of a transparent insulating material such as glass, as shown in FIG. 10A, First link wirings (not shown) and link portion gate lines 216 and 216 'are formed in a driving portion of the first and second TFTs 210 and 210'.

At this time, the pixel portion gate line extends toward the driving portion to form the link portion gate lines 216 and 216 ', and is represented by the same gate lines 216 and 216' for convenience of explanation.

The gate electrodes 221 and 221 'and the gate lines 216 and 216' and the first link wiring are formed by sequentially depositing a first conductive film and a second conductive film on the entire surface of the array substrate 210, And then selectively patterned through a process (first mask process).

The gate electrodes 221 and 221 'are composed of the lower gate electrode 221 formed of the first conductive film and the upper gate electrode 221' formed of the second conductive film. The gate lines 216 and 216 ' May include a lower gate line 216 formed of the first conductive film and an upper gate line 216 'formed of the second conductive film. Although not shown in the drawing, the first link wiring may be composed of a lower first link wiring made of the first conductive film and an upper first link wiring made of the second conductive film.

A low resistance opaque conductive material such as aluminum, copper, chromium, or molybdenum may be used as the first conductive film, and a conductive material that does not react with a dry etching process such as ITO or AlNd may be used as the second conductive film . The first conductive layer may have a multi-layer structure in which two or more low-resistance conductive materials are stacked.

10B, a gate insulating layer 215a and an amorphous silicon layer are formed on the entire surface of the array substrate 210 on which the gate electrodes 221 and 221 ', the gate lines 216 and 216' and the first link interconnection are formed, A silicon thin film and an n + amorphous silicon thin film are formed.

Thereafter, the amorphous silicon thin film and the n + amorphous silicon thin film are selectively removed through a photolithography process (second mask process) to form an active layer 224 made of the amorphous silicon thin film in the TFT region of the array substrate 210 do.

At this time, an n + amorphous silicon thin film pattern 225 patterned in substantially the same shape as the active layer 224 is formed on the active layer 224.

Next, as shown in FIG. 10C, a third conductive layer is formed on the entire surface of the array substrate 210 on which the active layer 224 and the n + amorphous silicon thin film pattern 225 are formed. Here, the third conductive layer may be formed of a low-resistance opaque conductive material such as aluminum, aluminum alloy, tungsten, copper, chromium, molybdenum, and molybdenum alloy to form the source / drain electrodes, the data lines, and the second link wiring. In addition, the third conductive film may be formed in a multi-layered structure in which two or more low resistance conductive materials are stacked.

Thereafter, the n + amorphous silicon thin film and the third conductive film are selectively removed through a photolithography process (a third mask process) to form a source electrode 222 and a drain electrode 222, which are the third conductive film, on the active layer 224, (223).

At this time, a data line (not shown) made of the third conductive film is formed in the data line area of the array substrate 210 through the third mask process, and the data line Thereby forming a second link wiring 226b made of a film.

The first and second link wirings 226a and 226b are alternately formed in the order of the gate lines 216 and 216 '. In this case, for example, the odd gate lines 216 and 216' 1 link wiring, and the even gate lines 216 and 216 'may be connected to the second link wiring 226b.

At this time, an n + amorphous silicon thin film is formed on the active layer 224, and an ohmic contact layer is formed between the source / drain region of the active layer 224 and the source / drain electrodes 222 and 223, (225n) is formed.

10D, a protective film 215b is formed on the entire surface of the array substrate 210 on which the source / drain electrodes 222 and 223, the data lines, and the second link wirings 226b are formed.

Then, the protective film 215b and the gate insulating film 215a are selectively removed through a photolithography process (a fourth mask process) so that the upper first gate line 216 and the upper first gate line 216 are electrically connected to the driving unit of the array substrate 210 A second contact hole 240b exposing a part of the side surface of the second link wiring 226b and a second contact hole 240b exposing a part of the side surface of the second link wiring 226b, .

A fourth contact hole 240d exposing a part of the drain electrode 223 is formed in the pixel portion of the array substrate 210 through the fourth mask process.

At this time, the protective film 215b and the gate insulating film 215a are removed by dry etching using plasma. The second link wiring 226b of the driving part is etched by the dry etching, The upper first gate line and the upper gate line 216 'of the driver are formed of a conductive material which does not react with dry etching such as ITO or AlNd, The first contact hole 240a and the third contact hole 240c are formed to expose the surfaces of the upper first link wiring line and the upper gate line 216 '.

Thus, the upper first link interconnection and the upper gate line 216 'act as an etch stop layer to prevent damage to the gate interconnection, that is, the first link interconnection and the gate lines 216 and 216' .

Next, as shown in FIG. 10E, a fourth conductive film made of a transparent conductive material is formed on the entire surface of the array substrate 210 on which the protective film 215b is formed, and then a photolithography process (fifth mask process) A pixel electrode 228 electrically connected to the drain electrode 223 is formed in the pixel portion of the array substrate 210 through the fourth contact hole 240d.

At this time, the fourth conductive film is selectively patterned using the fifth mask process to connect the first link wiring and the gate line (not shown) to the link portion through the first contact hole 240a and the third contact hole 240c, (Not shown) electrically connected to the first and second contact wirings 216 and 216 'and the second connection wirings 226a and 226b through the second contact holes 240a and the third contact holes 240c, And a second connection electrode 245b electrically connected to the gate lines 216 and 216 '.

The array substrate of the first and second embodiments of the present invention having the above-described structure of the present invention is adhered to and opposed to the color filter substrate by a sealant formed on the periphery of the image display area. At this time, A black matrix for preventing light from leaking into the data lines, and a color filter for realizing red, green and blue colors are formed.

At this time, the color filter substrate and the array substrate are bonded together through a covalent key formed on the color filter substrate or the array substrate.

The present invention can be applied not only to liquid crystal display devices but also to other display devices manufactured using thin film transistors, for example, organic electroluminescent display devices in which organic light emitting diodes (OLEDs) are connected to driving transistors.

While a great many are described in the foregoing description, it should be construed as an example of preferred embodiments rather than limiting the scope of the invention. Therefore, the invention should not be construed as limited to the embodiments described, but should be determined by equivalents to the appended claims and the claims.

100, 200: display device 110, 210: array substrate
116, 216, 216 ': gate lines 120, 220:
126a, 226a, 226a ': first link wiring 126b, 226b: second link wiring
140a, 240a: first contact holes 140b, 240b: second contact holes
140c and 240c: third contact holes 145a and 245a: first connection electrodes
145b, 245b: a second connecting electrode

Claims (16)

Forming a thin film transistor on a pixel portion of the first substrate;
Forming a first wiring line and a gate line extending from the pixel portion in a driver of the first substrate;
Forming a gate insulating film on the gate line and the first link wiring;
Forming a second link wiring on the gate insulating film;
Forming a protective film on the second link wiring; And
And forming a link portion contact hole exposing a part of the first link wiring and the gate line and the second link wiring by removing a part of the gate insulating film and the protective film,
Wherein the first link wiring is formed of an upper first link wiring and a lower first link wiring of different conductive materials,
Wherein the upper first link wiring is formed of a conductive material which does not react with dry etching when forming the link portion contact hole. The semiconductor device according to claim 1, wherein the protective film and the gate insulating film are subjected to a dry etching to form first contact holes and third contact holes exposing surfaces of the first link wiring and the gate lines, respectively, And a second contact hole exposing a side surface of the wiring. 3. The semiconductor memory device according to claim 2, further comprising a first connection electrode electrically connected to the first link wiring and the gate line through the first contact hole and the third contact hole, And forming a second connection electrode electrically connected to the second link wiring and the gate line through the third contact hole, respectively. 2. The semiconductor device according to claim 1, wherein the first link wiring and the second link wiring are alternately formed in the order of the gate line, the first link wiring is formed in the gate wiring layer, Wherein the distance between adjacent first and second link wirings is reduced. The method of manufacturing a display device according to claim 1, wherein the conductive material that does not react with the dry etching includes ITO and aluminum-neodymium. A first substrate divided into a pixel portion and a driving portion;
A thin film transistor provided in a pixel portion of the first substrate;
A gate line extending from the pixel portion;
A gate insulating film provided on the gate line and the first link wiring;
A second link wiring provided on the gate insulating film;
A protective film provided on the second link wiring; And
And a link portion contact hole for removing a part of the gate insulating film and the protective film to expose a part of the first link wiring and the gate line and the second link wiring,
Wherein the first link wiring is composed of an upper first link wiring and a lower first link wiring of different conductive materials,
Wherein the upper first link wiring is made of a conductive material which does not react to dry etching when forming the link portion contact hole. 7. The semiconductor memory device according to claim 6, wherein the link section contact holes each have a first contact hole and a third contact hole exposing a surface of the first link wiring and the gate line, and a second contact hole exposing a side surface of the second link wiring, And further comprising a contact hole. The semiconductor memory device of claim 7, further comprising: a first connection electrode electrically connected to the first link wiring and the gate line through the first contact hole and the third contact hole, And a second connection electrode electrically connected to the second link wiring and the gate line through the first connection wiring and the second connection wiring, respectively. 7. The semiconductor memory device according to claim 6, wherein the first link wiring and the second link wiring are alternately arranged in the order of the gate lines, the first link wiring is provided in the gate wiring layer, Wherein the distance between adjacent first and second link wirings is reduced. 10. The display device according to claim 9, wherein an odd gate line is connected to the first link wiring and an even gate line is connected to the second link wiring. 7. The display device according to claim 6, wherein the conductive material which does not react with the dry etching comprises ITO, aluminum-neodymium. 9. The display device according to claim 8, wherein the second link wiring has a side contact with the second connection electrode, and the first link wiring and the gate line make a surface contact with the first connection electrode. 7. The display device according to claim 6, wherein the gate line comprises an upper gate line made of a conductive material which does not react with the dry etching and a lower gate line made of a low resistance conductive material. delete 14. The display device according to claim 13, wherein the upper first link wiring and the upper gate line serve as an etching stopper film to prevent damage to the first link wiring and the gate line by the dry etching. A first substrate divided into a pixel portion and a driving portion;
A thin film transistor provided in a pixel portion of the first substrate;
A gate line extending from the pixel portion;
A gate insulating film provided on the gate line and the first link wiring;
A second link wiring provided on the gate insulating film;
A protective film provided on the second link wiring;
A link portion contact hole for removing a part of the gate insulating film and the protective film to expose a part of the first link wiring, the gate line and the second link wiring; And
A first connection electrode connecting the first link wiring and the gate line through the link section contact hole and a second connection electrode connecting the second link wiring and the gate line through the link section contact hole, ,
Wherein the first link wiring is composed of an upper first link wiring and a lower first link wiring of different conductive materials,
Wherein the upper first link wiring is made of a conductive material which does not react to dry etching when forming the link portion contact hole.

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