KR101880226B1 - Display panel and display apparatus having the same - Google Patents

Abstract

The display panel includes a first display substrate, a second display substrate, and a liquid crystal layer. The first display substrate includes a first base substrate having a plurality of cell regions, a plurality of data lines separated from each other, a plurality of gate lines, and a plurality of pixel electrodes. The second display substrate includes a second base substrate, a light-shielding pattern corresponding to the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common line overlapping the light-blocking pattern. The liquid crystal layer is disposed between the first and second display substrates. Accordingly, the display cells are formed as one of the first display substrates, and common wirings electrically connected to the common electrodes are formed on the second display substrate, whereby the display of the frame edges due to the bezel width and the difference The quality deterioration can be improved.

Description

DISPLAY PANEL AND DISPLAY APPARATUS HAVING THE SAME [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention [0002] The present invention relates to a display panel and a display device having the same, and more particularly, to a display panel having a plurality of display cells and a display device having the same.

In general, a tiled display device has a structure in which a plurality of flat display panels are connected to each other to efficiently utilize a narrow space and to realize a large screen.

In the flat panel display panel, a driving circuit for displaying an image in the display area is disposed in a display area for displaying an image and a peripheral area surrounding the display area. Accordingly, the peripheral region of the flat panel display panel has a bezel width for outer lead bonding (OLB) bonding. According to the structure in which a plurality of the flat panel display panels are connected, the bezel width is about 7 mm or more in the boundary region.

In the tiled display device, a frame frame such as black or gray is formed in the boundary region between the display panels in which the entire screen is separated by the bezel width. Since the frame border of the border area can not control the color and the brightness, it is easily visually recognized by the observer's eyes, thereby deteriorating the display quality of the entire screen.

Accordingly, it is an object of the present invention to provide a display panel having a plurality of display cells for improving display quality.

Another object of the present invention is to a display device having the display panel.

According to an embodiment of the present invention, a display panel includes a first display substrate, a second display substrate, and a liquid crystal layer. The first display substrate includes a first base substrate having a plurality of cell regions, a plurality of data lines separated from each other, a plurality of gate lines, and a plurality of pixel electrodes. The second display substrate includes a second base substrate, a light-shielding pattern corresponding to the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common line overlapping the light-blocking pattern. The liquid crystal layer is disposed between the first and second display substrates.

In the present embodiment, the common wiring may include at least one first wiring extending in a direction in which the data lines extend, and at least one second wiring connected to the first wiring and extending in a direction in which the gate wirings extend .

In this embodiment, the common wiring is located on the second display substrate corresponding to the boundary region of the cell regions.

In this embodiment, the common wiring is disposed between the light-shielding pattern and the common electrode, and is in direct contact with the common electrode.

In this embodiment, the common wiring is disposed between the first base substrate and the shielding pattern, and is in direct contact with the common electrode through the contact hole formed in the shielding pattern.

According to another aspect of the present invention, there is provided a display apparatus including a display panel and a plurality of driving units. Wherein the display panel includes a first base substrate including a display region made up of a plurality of cell regions and a peripheral region surrounding the display region, a plurality of data wirings separated from each other, a plurality of gate wirings, Shielding pattern corresponding to the second base substrate, the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common line overlapping the light-shielding pattern are formed on the first display substrate, And the second display substrate. The driving units are mounted in the peripheral region of the display panel to drive the pixel electrodes in each cell region.

In the present embodiment, the plurality of driving units include a first driving unit, a second driving unit, a third driving unit, and a fourth driving unit. The first driving unit may include a plurality of first data lines and a plurality of first gate lines included in the first cell region and a plurality of second gate lines disposed in the peripheral region adjacent to the first cell region located on the upper left of the display region, And is electrically connected. The second driving unit is mounted on the peripheral region adjacent to the second cell region located on the upper right side of the display region and the plurality of second data lines included in the second cell region and the plurality of second gate lines Respectively. The third driver may be mounted on the peripheral region adjacent to a third cell region located on the lower left side of the display region, and may include a plurality of third data lines included in the third cell region, Respectively. The fourth driver is mounted on the peripheral region adjacent to the fourth cell region located on the lower right side of the display region, and the plurality of fourth data lines included in the fourth cell region and the plurality of fourth gate lines Respectively.

According to the embodiments of the present invention, since the display cells are formed as one first display substrate and the common wiring electrically connected to the common electrode is formed on the second display substrate, the frame edge visibility due to the bezel width and the delay It is possible to improve display quality deterioration caused by the difference.

1 is a plan view of a display device according to an embodiment of the present invention.
2 is a plan view of the first display substrate of the display panel shown in Fig.
3 is a plan view of the second display substrate of the display panel shown in Fig.
4 is a plan view of a display panel in which the portion A in Figs. 2 and 3 is enlarged.
5 is a cross-sectional view of the display panel taken along the line I-I 'in FIG.
6A to 6D are timing diagrams of driving signals for explaining the driving method of the display panel shown in FIG.
7 is a plan view of a display panel according to another embodiment of the present invention.
8 is a cross-sectional view of the display panel taken along line II-II 'in FIG.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the drawings.

1 is a plan view of a display device according to an embodiment of the present invention.

Referring to FIG. 1, the display device includes a display panel 100 and a plurality of drivers 610, 620, 630, and 640 that drive the display panel 100.

The display panel 100 includes a first display substrate 200 and a second display substrate 300 facing the first display substrate 100. The plurality of display cells 100a, 100b, 100c, As shown in Fig. Each of the display cells 100a, 100b, 100c, and 100d may have a size of 46 inches or more, and the display panel 100 may have a high resolution using the display cells 100a, 100b, 100c, Images can be displayed.

Each of the driving units 610, 620, 630, and 640 drives the display cells 100a, 100b, 100c, and 100d. For example, the first driver 610 may include a first data driver 611 for supplying a data signal to the first display cell 100a, a first gate driver 600 for providing a gate signal to the first display cell 100a, And a first control unit 613 for controlling the first data driver 611 and the first gate driver 612. The second driver 620 includes a second data driver 621 for supplying a data signal to the second display cell 100b, a second gate driver 622 for providing a gate signal to the second display cell 100b, And a second controller 623 for controlling the second data driver 621 and the second gate driver 622. The third driver 630 includes a third data driver 631 for supplying a data signal to the third display cell 100c, a third gate driver 632 for providing a gate signal to the third display cell 100c, And a third controller 633 for controlling the third data driver 631 and the third gate driver 632. The fourth driving unit 640 includes a fourth data driver 641 for supplying a data signal to the fourth display cell 100d, a fourth gate driver 642 for providing a gate signal to the fourth display cell 100d, And a fourth control unit 643 for controlling the fourth data driver 641 and the fourth gate driver 642. The display panel 100 can be driven at a high frequency of 60 Hz or more by spatially dividing and driving the display panel 100 using the driving units 610, 620, 630, and 640.

The first driving unit 610 is disposed at the upper left corner of the display panel 100 and the second driving unit 620 is disposed at the upper right corner of the display panel 100. The third driving unit 630 May be disposed at a lower left corner of the display panel 100 and the fourth driver 640 may be disposed at a lower right corner of the display panel 100. [

2 is a plan view of the first display substrate of the display panel shown in Fig.

Referring to FIGS. 1 and 2, the first display substrate 200 includes first, second, third and fourth peripheral areas PA1 and PA2 surrounding the display area DA and the display area DA, PA2, PA3, PA4).

A plurality of data lines, a plurality of gate lines, and a plurality of pixel electrodes are formed in the display area DA corresponding to the display cells 100a, 100b, 100c, and 100d, respectively.

A plurality of first data lines DL11 to DL1m are formed in a first cell area SA1 of the display area DA corresponding to the first display cell 100a, (GL11, ..., GL1n) and a plurality of first pixel electrodes (not shown) are formed. A plurality of second data lines DL21 to DL2m are formed in a second cell area SA2 of the display area DA corresponding to the second display cell 100b, (GL21, ..., GL2n) and a plurality of second pixel electrodes (not shown) are formed. A plurality of third data lines DL31 to DL3m are formed in a third cell area SA3 of the display area DA corresponding to the third display cell 100c, GL31, ..., GL3n and a plurality of third pixel electrodes are formed. A plurality of fourth data lines DL41 to DL4m are formed in a fourth cell region SA4 of the display region DA corresponding to the fourth display cell 100d, GL4, ..., GL4n and a plurality of fourth pixel electrodes are formed.

The first data lines DL11 through DL1m of the first cell area SA1 and the third data lines DL31 through DL3m of the third cell area SA3 And are electrically separated from each other. The first gate lines GL11 to GL1n and the second gate lines GL21 to GL2n of the second cell region SA2 are separated from each other and electrically separated. The second data lines DL21 to DL2m of the second cell area SA2 and the fourth data lines DL41 to DL4m of the fourth cell area SA4 are spaced apart from each other Electrically disconnected. The third gate lines GL31 through GL3n of the third cell region SA3 and the fourth gate lines GL41 through GL4n of the fourth cell region SA4 are spaced apart from each other Electrically disconnected.

The first peripheral area PA1 includes a first data pad part 261 on which the first data driver 611 is mounted, a second data pad part 262 on which the second data driver 621 is mounted, The first short points 281 and 282 are formed.

A third data pad unit 263 on which the third data driver unit 631 is mounted and a fourth data pad unit 264 on which the fourth data driver unit 641 is mounted are formed in the second peripheral area PA2, The second short points 283 and 284 are formed.

The third peripheral region PA3 includes a first gate pad portion 271 on which the first gate driver 612 is mounted, a third gate pad portion 273 on which the third gate driver 632 is mounted, The third short points 285 of the second short point 285 are formed.

The fourth peripheral pad PA4 includes a second gate pad portion 272 on which the second gate driver 622 is mounted, a fourth gate pad portion 274 on which the fourth gate driver 634 is mounted, Fourth shot points 286 are formed.

That is, the first driving unit 610 is mounted on the peripheral area adjacent to the upper left of the display area DA, and the second driving unit 620 is mounted on the peripheral area adjacent to the upper right of the display area DA. The third driving part 630 is mounted on the peripheral area adjacent to the lower left side of the display area DA and the fourth driving part 630 is mounted on the peripheral area adjacent to the lower right side of the display area DA 640 are mounted.

A common voltage is applied to the first to fourth short points 281, ..., and 286 from the first to fourth control units 613, 623, 633, and 643. The first through fourth short points 281, ..., and 286 are electrically connected to the common electrode of the second display substrate 300 and the common wiring electrically connected to the common electrode by a conductive member, A common voltage is applied to the second display substrate 300. A detailed description of the second display substrate 300 will be described later.

3 is a plan view of the second display substrate of the display panel shown in Fig.

Referring to FIGS. 1, 2 and 3, the second display substrate 300 includes a common line 330 and a common electrode 340.

The common wiring 330 includes at least one first wiring 331 that divides the entire area of the second display substrate 300 in the first direction and a second wiring 332 that covers the entire area of the second display substrate 300 And at least one second wiring (332) that divides a plurality of wires in the second direction. The first wiring 331 extends in the second direction D2 and the second wiring 332 extends in the first direction D1 and the first and second wirings 331 and 332 Are electrically connected to each other by a metal wiring. For example, the common line 330 may be formed at a position corresponding to a boundary region of the cell regions SA1, SA2, SA3, and SA4 of the first display substrate 200. [

The end of the common line 330 may be electrically connected to at least one of the short points 281, ..., and 286 of the first display substrate 200. The first end 331a of the first wiring 331 is electrically connected to the first short point 282 and the second end 331b is electrically connected to the second short point 283. [ . The first end portion 332a of the second wiring 332 is electrically connected to the third short point 285 and the second end portion 332b is electrically connected to the fourth short point 286. [ Therefore, the common wiring 330 can transmit the common voltage by minimizing the signal delay due to the wiring resistance in the metal wiring.

The common electrode 340 is formed on the entire area of the second display substrate 300 and is electrically connected to the common wiring 330. The edge of the common electrode 340 is electrically connected to the short points 281, ..., and 286 of the first display substrate 200. Accordingly, the common voltage can be uniformly applied to the common electrode 340 formed on the entire area of the second display substrate 300 without a delay difference.

4 is a plan view of a display panel in which the portion A in Figs. 2 and 3 is enlarged. 5 is a cross-sectional view of the display panel taken along the line I-I 'in FIG.

4 and 5, the display panel 100 includes the first display substrate 200, the second display substrate 300, and the liquid crystal layer 400.

The first display substrate 200 includes a first base substrate 201, and a plurality of data lines, a plurality of gate lines, and a plurality of pixel electrodes are formed on the first base substrate 201. The first display substrate 200 further includes a gate insulating layer 202 formed on the first metal pattern including the gate lines and a protective insulating layer 204 formed on the second metal pattern including the data lines .

For example, the mth data line DL1m, the nth gate wiring GL1n, the switching element TR1, and the pixel electrode PE1 are formed in the first cell area SA1 of the first base substrate 201 do. The switching element TR1 is connected to the gate electrode GE1 connected to the nth gate wiring GL1n through the first contact hole CT1 and the source electrode SE1 connected to the mth data wiring DL1m, And a drain electrode DE1 connected to the electrode PE1. The switching element TR1 further includes a semiconductor pattern AP1 formed on the gate electrode GE1. The data lines DL1m formed in the first cell region SA1 are spaced apart from the mth data line DL3m formed in the third cell region SA3, The gate wirings formed on the first cell region SA1, that is, the n-th gate wiring GL1n, are spaced apart from the n-th gate wiring GL2n formed in the second cell region SA2.

The first data line DL21, the nth gate line GL2n, the switching element TR2 and the pixel electrode PE2 are formed in the second cell region SA2 of the first base substrate 201. [ The switching element TR2 is connected to the gate electrode GE2 through the gate electrode GE2 connected to the nth gate wiring GL2n, the source electrode SE2 connected to the first data wiring DL21, and the second contact hole CT2. And a drain electrode DE2 connected to the electrode PE2. The switching element TR2 further includes a semiconductor pattern AP2 formed on the gate electrode GE2. The data lines DL21 formed in the second cell area SA2 are spaced apart from the first data line DL41 formed in the fourth cell area SA4.

The mth data line DL3m, the first gate line GL31, the switching element TR3 and the pixel electrode PE3 are formed in the third cell region SA3 of the first base substrate 201. [ The switching device TR3 is connected to the pixel electrode PE3 through a gate electrode connected to the first gate line GL31, a source electrode connected to the mth data line DL3m, and a third contact hole CT3. Drain electrode. The switching element TR3 further includes a semiconductor pattern formed on the gate electrode. The data lines formed in the third cell region SA3, that is, the mth data line DL3m are spaced apart from the mth data line DL1m formed in the first cell region SA1, The first gate wiring GL31 formed on the first cell region SA2 is separated from the first gate wiring GL41 formed on the fourth cell region SA4.

A first data line DL41, a first gate line GL41, a switching element TR4 and a pixel electrode PE4 are formed in the fourth cell region SA4 of the first base substrate 201. [ The switching element TR4 is connected to the pixel electrode PE4 through a gate electrode connected to the first gate line GL41, a source electrode connected to the first data line DL41 and a fourth contact hole CT4. Drain electrode. The switching device TR4 further includes a semiconductor pattern formed on the gate electrode. The data lines DL41 formed in the fourth cell region SA4 are spaced apart from the first data line DL21 formed in the second cell region SA2.

The second display substrate 300 includes a second base substrate 301 and a light shielding pattern 310, a color filter 320, a common wiring 330, and a common electrode 340 are formed.

The light blocking pattern 310 is formed on the second base substrate 301 corresponding to an area where the data lines, the gate lines, and the switching elements of the first display substrate 200 are formed.

The color filter 320 is formed on the second base substrate 301 corresponding to an area where the pixel electrodes of the first display substrate 200 are formed. The color filter 320 may be formed on the first display substrate 200. That is, when the color filter 320 is included in the first display substrate 200, the color filter 320 is formed on the protective insulating layer 204 of the first display substrate 200, As shown in FIG.

The common line 330 is formed to overlap the light blocking pattern 310 in the region where the light blocking pattern 310 is formed. The common wiring 330 is a metal wiring patterned with a metal layer. The common wiring 330 includes a first wiring 331 extending in a first direction D1 extending in the data lines and a second wiring 331 extending in a second direction D2 extending in the gate lines 332, and the first and second wirings 331, 332 are connected to each other.

As shown in the figure, the common wiring 330 may be formed in a cross shape having one first wiring 331 and one second wiring 332 intersecting with each other or a plurality of first wirings 331 and a plurality of second wirings 332 intersecting the first wirings 331. The second wirings 332 may be formed in a matrix shape. In addition, the common line 330 may be formed corresponding to the boundary region of the cell regions. The common wiring 330 is formed in the region where the light-shielding pattern 310 is formed, so that the aperture ratio and the transmittance of the display panel 100 are not affected.

The common electrode 340 is formed in the entire area of the second base substrate 301 on which the common wiring 330 is formed. The common electrode 340 is formed of a transparent conductive layer. The common electrode 340 may be in contact with the common wiring 330 to be electrically connected thereto, so that a common voltage applied to the common wiring 330 may be applied. That is, the common wiring 330 can improve the signal delay of the common electrode 340 formed of the transparent conductive layer having a relatively larger resistance than the metal layer. Accordingly, the common voltage can be uniformly transmitted to the entire area of the second display substrate 300 without signal delay, thereby improving display quality.

6A to 6D are timing diagrams of driving signals for explaining the driving method of the display panel shown in FIG.

Referring to FIGS. 1, 6A, 6B, 6C, and 6D, the first to fourth driving units 610, 620, 630, and 640 are synchronized with each other, 4 display cells 100a, 100b, 100c, and 100d, respectively.

For example, referring to FIGS. 1 and 6A, the first controller 613 controls the first driver 610 using a received original control signal, for example, a data enable signal DE. 1 data control signal and a first gate control signal. The first data driver 611 applies first data (1st DATA) corresponding to the first display cell 100a to the first display cell 100a in one horizontal period (1H) based on the first data control signal. To the data lines of the memory cell array 100a. The first gate driver 612 generates the gate signals G11, G12, ..., G1n based on the first gate control signal, And sequentially outputs the data to the gate wirings of the first display cell 100a.

Referring to FIGS. 1 and 6B, the second controller 623 generates a second data control signal and a second gate control signal for controlling the second driver 620 using the data enable signal DE . Accordingly, the first driving unit 610 and the second driving unit 620 are synchronized with each other. The second data driver 621 may apply the second video data (2nd DATA) corresponding to the second display cell 100b to the second display cell 100b in one horizontal period (1H) based on the second data control signal. To the data lines of the data driver 100b. The second gate driver 622 generates the gate signals G21, G22, ..., G2n based on the second gate signal, and synchronizes with the output timing of the second video data (2nd DATA) Sequentially to the gate wirings of the second display cell 100b.

Referring to FIGS. 1 and 6C, the third controller 633 uses the data enable signal DE to generate a third data control signal and a third gate control signal for controlling the third driver 630 . Therefore, the first, second, and third drivers 610, 620, and 630 are synchronized with each other. The third data driver 631 applies the third video data (3rd DATA) corresponding to the third display cell 100c to the third display cell 100c in one horizontal period (1H) based on the third data control signal. Lt; / RTI > to the data lines of the memory cell array 100c. The third gate driver 632 generates the gate signals G31, G32, ..., G3n based on the third gate signal, and synchronizes with the output timing of the third video data (3rd DATA) To the gate wirings of the third display cell 100c.

Referring to FIGS. 1 and 6D, the fourth control unit 643 uses the data enable signal DE to generate a fourth data control signal and a fourth gate control signal for controlling the fourth driver 640 . Accordingly, the first, second, third and fourth driving units 610, 620, 630 and 640 are synchronized with each other. The fourth data driver 641 sequentially applies the fourth video data (4th DATA) corresponding to the fourth display cell (100d) to the fourth display cell (100b) in one horizontal period (1H) based on the fourth data control signal. Lt; / RTI > to the data lines of the data line 100d. The fourth gate driver 642 generates the gate signals G41, G42, ..., G4n based on the fourth gate signal, and synchronizes with the output timing of the fourth image data (4th DATA) Sequentially to the gate wirings of the fourth display cell 100d.

As a result, when the image is displayed on the first horizontal line of each of the second, third, and fourth display cells 100b, 100c, and 100d at the timing when the image is displayed on the first horizontal line of the first display cell 100a And the image is displayed on the n-th horizontal line of each of the second, third and fourth display cells 100b, 100c, and 100d at the timing when the image is displayed on the n-th horizontal line of the first display cell 100a Is displayed.

Accordingly, the first to fourth display cells 100a, 100b, 100c, and 100d of the display panel 100 can be independently driven, and a large-sized image can be displayed at a high frame frequency.

7 is a plan view of a display panel according to another embodiment of the present invention. 8 is a cross-sectional view of the display panel taken along line II-II 'in FIG.

Referring to FIGS. 7 and 8, the display panel according to the present embodiment is substantially the same as the other components except for the second display substrate, as compared with the display panel according to the previously described embodiment. Hereinafter, the same constituent elements as those of the previously described embodiment will be denoted by the same reference numerals and the repeated description will be omitted or simplified.

The display panel 700 according to this embodiment includes a first display substrate 200, a second display substrate 800, and a liquid crystal layer 400.

The second display substrate 800 includes a second base substrate 801 and a common wiring 810, a light shielding pattern 820, a color filter 830, and a common electrode (not shown) 840 are formed.

The common wiring 810 is formed on the second base substrate 801 corresponding to a part of the area where the data lines and the gate lines of the first display substrate 200 are formed and is formed of a metal layer. The common wiring 810 includes a first wiring 811 extending in a first direction D1 extending in the data lines and a second wiring 811 extending in a second direction D2 extending in the gate wiring 812), and the first and second wirings 811, 812 are connected to each other.

 As shown in the figure, the common wiring 810 may be formed in a cross shape having one first wiring 811 and one second wiring 812 intersecting each other or a plurality of first wirings 811 And a plurality of second wirings 812 intersecting the first wirings 811. The second wirings 812 may be formed in a matrix shape.

The light shielding pattern 820 is formed on the second base substrate 801 corresponding to an area where the data lines, gate lines and switching elements of the first display substrate 200 are formed, And is formed so as to cover the wiring 810. A plurality of fifth contact holes CT5 are formed in the light-shielding pattern 820 to partially expose the common wiring 810.

The color filter 830 is formed on the second base substrate 801 corresponding to an area where the pixel electrodes of the first display substrate 200 are formed. The color filter 830 may be formed on the first display substrate 200. That is, when the color filter 830 is included in the first display substrate 200, the color filter 830 is electrically connected to the protective insulation layer 204 of the first display substrate 200, As shown in FIG.

The common electrode 840 is formed on the second base substrate 801 so as to cover the light-shielding pattern 820 in which the fifth contact holes CT5 are formed and the color filter 830. The common electrode 840 may be formed as a transparent conductive layer.

The common electrode 840 is electrically connected to the common wiring 810 through the fifth contact holes CT5. The signal delay difference of the common electrode 840 formed of the transparent conductive layer can be improved by the common wiring 810 which is the metal wiring. Accordingly, the common voltage can be uniformly transmitted to the entire area of the second display substrate 800 without signal delay, thereby improving display quality. In addition, the common line 810 is formed in the region where the light-shielding pattern 820 is formed, so that the aperture ratio and the transmittance of the display panel 100 are not affected.

According to embodiments of the present invention, since the display cells are formed of one first display substrate and the common wiring electrically connected to the common electrode is formed on the second display substrate, the frame edge visibility and the common voltage It is possible to improve the display quality deterioration due to the delay difference in the display quality. In addition, by driving for each display cell, high resolution and high-speed driving can be achieved.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined in the appended claims. It will be possible.

100: display panel 200: first display substrate
300: second display substrate
610, 620, 630, and 640: first, second, third,
611, 621, 631, 641: first, second, third and fourth data drivers
612, 622, 632, and 642: first, second, third,
613, 623, 633, 643: the first, second, third,

Claims (19)

A first display substrate including a first base substrate made of a plurality of cell regions, a plurality of data lines separated by each cell region, a plurality of gate lines, and a plurality of pixel electrodes;
A second display substrate including a second base substrate, a shielding pattern corresponding to the data lines and the gate lines, a common electrode facing the pixel electrodes, and a common wiring overlapping the shielding pattern; And
And a liquid crystal layer disposed between the first and second display substrates. The semiconductor device according to claim 1, wherein the common wiring includes at least one first wiring extending in a direction in which the data lines extend; And
And at least one second wiring connected to the first wiring and extending in a direction in which the gate wiring extends. The display panel according to claim 2, wherein the common wiring is located on the second display substrate corresponding to the boundary region of the cell regions. The display panel according to claim 2, wherein the common wiring is disposed between the light shielding pattern and the common electrode, and is in direct contact with the common electrode. The display panel according to claim 2, wherein the common wiring is disposed between the first base substrate and the shielding pattern, and is in direct contact with the common electrode through a contact hole formed in the shielding pattern. The display device according to claim 1, wherein the first display substrate includes a display region in which the pixel electrodes are formed and a peripheral region surrounding the display region,
And a pad unit located in the peripheral region and receiving a driving signal for driving each of the display cells. The display panel of claim 6, wherein the first display substrate further includes a plurality of short points located in the peripheral region and connected to the common electrode. 8. The display panel of claim 7, wherein an end of the common line is connected to at least one of the short points. The display device according to claim 1, wherein the first display substrate
A plurality of first data lines and a plurality of first gate lines disposed in a first cell region of the first base substrate,
A plurality of second data lines located in the first cell region and a second cell region neighboring the first gate line, a plurality of second gate lines separated from the first gate lines,
A plurality of third data lines and third gate lines located in a third cell region adjacent to the first cell region and the second side and separated from the second data lines,
A plurality of fourth data lines located in the third cell region and a fourth cell region neighboring the first side, and a plurality of fourth gate lines separated from the third gate lines. . The display panel according to claim 9, wherein the common wiring is located on the second display substrate corresponding to a border region of the first, second, third and fourth cell regions. A first base substrate including a display region including a plurality of cell regions and a peripheral region surrounding the display region, and a plurality of data lines, a plurality of gate lines, and a plurality of pixel electrodes separated for each cell region And a common wiring which overlaps with the data wiring and the gate wiring, a common electrode facing the pixel electrode, and a common wiring overlapping the light shielding pattern. A display panel including a display substrate; And
And a plurality of drivers mounted in the peripheral region of the display panel to drive the pixel electrodes in each cell region. 12. The apparatus of claim 11, wherein the plurality of drivers
A plurality of first data lines and a plurality of first data lines electrically connected to the plurality of first gate lines, which are mounted in the peripheral region adjacent to the first cell region located on the upper left side of the display region, A driving unit;
A plurality of second data lines included in the second cell region and a plurality of second data lines electrically connected to the plurality of second gate lines, 2 driver;
A plurality of third data lines included in the third cell region and a plurality of third data lines electrically connected to the plurality of third gate lines, 3 driver; And
A plurality of fourth data lines included in the fourth cell region and a plurality of fourth data lines electrically connected to the plurality of fourth gate lines, 4 driver. 13. The display device according to claim 12, wherein the common wiring is located on the second display substrate corresponding to a border region of the first, second, third and fourth cell regions. 12. The semiconductor device according to claim 11, wherein the common wiring includes at least one first wiring extending in a direction in which the data lines extend; And
And at least one second wiring connected to the first wiring and extending in a direction in which the gate wiring extends. 15. The display device according to claim 14, wherein the common wiring is disposed between the shielding pattern and the common electrode, and is in direct contact with the common electrode. 15. The display device according to claim 14, wherein the common wiring is disposed between the first base substrate and the shielding pattern, and is in direct contact with the common electrode through a contact hole formed in the shielding pattern. The display device of claim 11, further comprising a plurality of short points located in the peripheral region of the display panel and receiving a common voltage from the drivers. 18. The display device of claim 17, wherein an end of the common line is connected to at least one of the short points. 12. The display device according to claim 11, wherein the common wiring is located on the second display substrate corresponding to a boundary region of the cell regions.

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