KR101875835B1 - Crossbar RRAM with Sneak Current Cancellation Based on a Two-Port Current-Mode Sensing and Readout Method thereof - Google Patents

Abstract

The present invention relates to a crossbar resistance memory and a method of reading the crossbar resistance memory and a method of reading the stored crossbar resistance memory _, And determining the data stored in the selected cell, wherein the offset is determined based on a current sensed in a word line different from a word line of the selected cell among the array of word lines crossing the bit line of the selected cell Detection current 'I _COMP ).

Description

{Crossbar RRAM with Sneak Current Cancellation Based on Two-Port Current-Mode Sensing and Readout Method}

The present invention relates to a crossbar resistance memory (RRAM) and relates to a method of reading a crossbar resistance memory.

DRAM is a volatile memory that has fast processing speed but can not store data permanently. NAND flash memory has nonvolatility but has a disadvantage of slow processing speed. Resistor memory (also known as 'resistance change memory') is a new structure memory that is expected to have high capacity beyond both DRAM and NAND flash while having both DRAM's fast processing speed and NAND flash non-volatility to be.

The operating principle of the RRAM is to store data through a resistance value by allowing the device to have a state of a high-resistance state or a low-resistance state.

The RRAM has a 1-selector and a 1-resistor (1S1R) structure unit memory cell in comparison with an RRAM having a 1-transistor and 1-resistance (1T1R) Crossbar RRAM (crossbar RRAM) is expected to dramatically increase its capacity.

However, in the case of crossbar RRAM, the current flowing through the unselected cells can not be completely controlled due to incomplete switching characteristics, thereby causing a problem of a sneak current flowing through unselected cells. Especially, this snick current causes a serious problem when performing read operation stored in the memory.

In order to read data stored in the RRAM, a predetermined voltage is applied to a selected cell, and a current flowing through the selected cell is sensed to determine a resistance value of the selected cell. In addition to the current flowing in the selected cell, Current (snick current) is summed and detected, so accurate data can not be read.

The size of the snick current is proportional to the capacity of the crossbar RRAM. In order to prevent data read errors, the snick current must be reduced by reducing the capacity, so that the snick current makes it difficult to create a large capacity RRAM.

A typical reading method for the crossbar RRAM is to apply voltages (referred to as 'sense voltage' (V _SS ) and 'read voltage' (V _R ) respectively) to only one bit line and one word line A floating read scheme is used to select only one cell.

However, in order to reduce the data read error due to the snitch current, a new read scheme specific to RRAM has been proposed. Unlike the floating read scheme described above, the V / V conversion circuit applies half the voltage (V _R -V _SS ) / 2 to all unselected bit lines and word lines. There are two ways to read. In the V / 2 reading method, only the current flowing in the cells connected to the bit line to which 0 (zero) V is applied is different from that in the floating reading method, unlike the case in which the snick current flowing in all cells not selected in the floating reading method is detected by adding to the current of the selected cell And is combined with the current of the selected cell to be detected. Therefore, it has the advantage of reducing the amount of the snake current which is undesirably detected, but has a disadvantage that the consumed power is increased from several tens to several thousands times as compared with the floating reading method.

1 (a) is a schematic diagram for explaining the V / 2 reading method (left) and the floating reading method (right) as the most typical crossbar RRAM reading method.

In both methods, a sense voltage (V _SS ) and a read voltage (V _R ) are applied to the selected bit line and word line, respectively, and the current flowing to the point (read point) The stored data is read.

For the V / 2 read method, V _R / 2 is applied to all unselected bit lines and word lines to reduce the snick current flowing to the sense point, thereby reading only the snick current flowing through the cells connected to the selected bit line only Let it flow into the branch. Although the remaining cells connected to the selected word line do not affect the read operation, a forward bias is applied, so that a large amount of current flows. As a result, the V / 2 reading method consumes a large amount of power.

On the other hand, in the floating read method, all the unselected bit lines and word lines are kept in a floating state without applying a voltage so that only a small amount of reverse current flows to all unselected cells in comparison with the forward current, thereby greatly reducing power consumption . However, all the reverse currents flowing in all unselected cells are detected at the reading point, which increases the likelihood of causing a data read error.

1 (b) shows a simplified current-voltage characteristic curve of 1S1R RRAM. R _L is the low resistance state resistance value, R _H is the high resistance state resistance value, and R _R is the resistance value when the reverse bias is applied. The 1S1R RRAM has a feature of selecting a cell and increasing a reverse resistance value to reduce a snick current.

1 (c) is a schematic view of another form for explaining a floating reading method.

The current (I _{MAIN, 1P} ) sensed at the sensing point appears as the sum of the current (I _CELL ) flowing in the selected cell and the sum of the total snick current (I _SNEAK ).

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments.

U.S. Patent No. 8,982,647 (Mar. 17, 201), "RESISTIVE RANDOM ACCESS MEMORY EQUALIZATION AND SENSING"

The present invention provides a crossbar resistance memory read method capable of reducing the influence of a snick current and a crossbar resistor memory using the same.

In addition, the present invention provides a crossbar resistance memory read method and a crossbar resistor memory that can solve the problem of a snick current while reducing power consumption compared to the V / 2 read method.

In a crossbar resistor memory according to one aspect of the present invention, a crossbar resistance memory is provided in which a current flowing by applying a first sense voltage to a bit line of a selected cell (hereinafter referred to as a 'main sense current'), (Hereinafter referred to as 'compensation sense current') by applying a second sense voltage to a word line different from the word line of the selected cell among the arrays of the word lines and receiving the main sense current and the compensation sense current And a read block for determining data stored in the selected cell by using the read block.

In the above-described crossbar resistor memory, the first sensing voltage and the second sensing voltage may be the same.

In the crossbar resistor memory described above, in the crossbar array to which the selected cell belongs, the remaining word lines except the word line of the selected cell and the word line to which the second sense voltage is applied are floated, and the crossbar array The remaining bit lines excluding the bit line of the selected cell are floating.

In the crossbar resistor memory according to one aspect of the present invention, after the influence of the sneak current contained in the current sensed in the bit line of the selected cell (hereinafter, referred to as 'main sensing current') is canceled, Wherein the offset is a current sensed in a word line different from a word line of the selected cell among the array of word lines intersecting the bit line of the selected cell (Hereinafter referred to as " a ").

In a crossbar resistance memory according to an aspect of the present invention, among a current sensed in a bit line of a selected cell (hereinafter referred to as a 'main sensing current') and an array of word lines crossing the bit line of the selected cell, And a read block for determining data stored in the selected cell by using a current sensed by a word line different from a word line of the selected cell (hereinafter, referred to as 'compensation sensing current').

In the above crossbar resistor memory, the read block may include a current amplification unit for outputting an amplification current obtained by amplifying the compensation sense current by a constant magnification.

In the above-described crossbar resistance memory, the current amplification section may include: a first MOS transistor connected to the compensation sense current to flow through a drain-source path; A second MOS transistor whose gate is connected to the gate of the first MOS transistor and the amplified current flows through a drain-source path; And an amplifier having an output terminal connected to the gates of the first MOS transistor and the second MOS transistor, a + input terminal connected to a drain of the first MOS transistor, and an input terminal to which a constant voltage is applied .

In the crossbar resistor memory described above, the constant voltage may be larger than a threshold voltage of the first MOS transistor and the second MOS transistor.

In the crossbar resistor memory described above, the constant may be set by the number (M) of word lines in the crossbar array to which the selected cell belongs, or the number of word lines (M) in the crossbar array to which the selected cells belong, (N).

In the above crossbar resistor memory, the read block may include: a reference current generator for generating a reference current; And a current mirror unit for outputting a mirror current to which the main sensing current is copied.

In the above crossbar resistor memory, the current mirror section may include: a first MOS transistor connected to the main sense current to flow through a drain-source path; A second MOS transistor whose gate is connected to the gate of the first MOS transistor and the mirror current flows through a drain-source path; And an amplifier to which a gate of the first MOS transistor and a gate of the second MOS transistor are connected to an output terminal, a drain of the first MOS transistor is connected to a + input terminal, and a constant voltage is applied to the input terminal.

The crossbar resistance memory may further include a sense amplifier for outputting a result of comparing the sum current obtained by adding the amplified current and the reference current to the mirror current.

In the above-described crossbar resistor memory, the sense amplifier includes: a pre-charge MOS transistor for precharging a charge to a complementary output node; A gating MOS transistor for opening / closing a path for discharging charge accumulated in the complementary output node by the mirror current and the sum current, respectively; And a MOS switching transistor for imparting a positive feedback to the potential difference between the complementary output nodes.

In the above crossbar resistance memory, the sense amplifier may include: a first NMOS transistor and a second NMOS transistor, the mirror current and the sum current flowing through a drain-source path and receiving a read enable signal at a gate; And a third NMOS transistor and a fourth NMOS transistor having their sources connected to the drains of the first NMOS transistor and the second NMOS transistor, respectively. The gate of the third NMOS transistor may be coupled to the drain of the fourth NMOS transistor and the gate of the fourth NMOS transistor may be coupled to the drain of the third NMOS transistor.

In the above-described crossbar resistor memory, each cell of the crossbar resistor memory has a structure of a 1-selector and a 1-resistor.

In the above-described crossbar resistor memory, a read voltage is applied to a word line of the selected cell, a first sense voltage is applied to a bit line of the selected cell, and a word line different from the word line of the selected cell The sensing voltage is applied, and the remaining bit lines and the remaining word lines in the crossbar array to which the selected cell belongs are floated.

In the above-described crossbar resistor memory, the first sense voltage and the second sense voltage are the same, and the read voltage is different from the first sense voltage and the second sense voltage, and thus has a potential difference.

In a method of reading a crossbar resistance memory according to an aspect of the present invention, the influence of a snick current included in a current sensed in a bit line of a selected cell (hereinafter, referred to as a 'main sensing current' And determining the data stored in the selected cell, wherein the cancellation is performed using a current sensed in a word line different from a word line of the selected cell among the array of word lines crossing the bit line of the selected cell Hereinafter, this is referred to as 'compensation current').

In the crossbar resistor memory read method, the snitch current is regarded as a constant multiple of the compensation sense current, thereby canceling the influence of the snick current.

In the crossbar resistor memory read method, the snitch current is regarded as being directly proportional to the compensation sense current, thereby canceling the influence of the snick current.

In another aspect of the present invention, there is provided a method of reading a crossbar resistance memory, comprising: sensing a current (hereinafter, referred to as a 'main sensing current') sensed in a bit line of a selected cell to read stored data; Determining data stored in the selected cell by using a current sensed in a word line different from a word line of the selected cell among the arrays of intersecting word lines (hereinafter referred to as 'compensation sensing current') .

In the above crossbar resistance memory read method, the determination is made by comparing the main sensing current with a reference current, offsetting the compensation sensing current by an amplification current amplified by a predetermined constant multiplication factor in the main sensing current And the comparison is performed.

In the crossbar resistor memory read method, the offset may be added to the reference current, or subtract the amplified current to the main sensing current.

The method of reading the crossbar resistor memory may further include amplifying the compensation sensing current by a predetermined constant multiplication factor using the compensation sensing current.

(M) in the crossbar array to which the selected cell belongs, or the number of word lines (M) in the crossbar array to which the selected cell belongs, And the number of bit lines (N).

In the method of reading the crossbar resistance memory, a read voltage is applied to a word line of the selected cell, a first sense voltage is applied to a bit line of the selected cell, and a word line The second sensing voltage is applied and the remaining bit lines and the remaining word lines in the crossbar array to which the selected cell belongs are floated.

In the above method of reading a crossbar resistor memory, the first sensing voltage and the second sensing voltage may be the same.

According to an aspect of the present invention, a crossbar resistance memory read method and a crossbar resistor memory using the crossbar resistor memory have an effect of reducing reading (canceling) the influence of a snick current.

In addition, the crossbar resistance memory read method and the crossbar resistor memory using the crossbar resistor memory according to an embodiment of the present invention have the effect of solving the problem of the snick current while reducing power consumption compared to the conventional V / 2 read method.

The method of reading a crossbar resistor memory according to an aspect of the present invention and the crossbar resistor memory using the method can substantially increase the capacity of a crossbar resistor memory (crossbar array) while maintaining power consumption substantially equal to that of a conventional floating read method. .

FIG. 1 (a) is a schematic diagram for explaining a V / 2 reading method (left side) and a floating reading method (right side) as a typical crossbar RRAM reading method. FIG. 1 (b) is a simplified schematic diagram of a 1S1R RRAM, 1 (c) is a schematic diagram of another form for explaining the floating reading method.
2 is a conceptual diagram for explaining a method of reading a crossbar resistance memory according to an embodiment of the present invention.
3 (a) illustrates an example of a path of a snick current flowing from a crossbar resistance memory to a main sensing point according to an embodiment of the present invention. FIG. 3 (b) And an example of the path of the snick current flowing from the resistance memory to the compensation detection point.
FIG. 4 (a) is a comparison of the sense current obtained through the method of FIG. 8 (two-point sensing) and the sensing current obtained through the conventional floating reading method (single-point reading) through simulation. 4 (b) compares the sense current obtained through the method of equation (8) (two-point sensing) with the sensing current obtained through the conventional floating reading method (single-point reading).
5 shows the result obtained by using a method for solving a reading error caused by an overestimated snitch current.
6 is a diagram showing a change in sensing current according to a memory capacity.
FIG. 7 is a circuit diagram of a read block to which a read method according to an embodiment of the present invention is applied. FIG. 7B shows a specific example of the sense amplifier 140 in FIG. c) illustrates steps and waveforms of a read block in accordance with an embodiment of the present invention.
FIG. 8A is a circuit diagram again showing the current amplification section 110 and the current mirror section 120 in FIG. 7A. FIG. 8B is a circuit diagram showing the current amplification section 210 and And a current mirror unit 220. FIG.
Fig. 9 shows two embodiments of a three-dimensional (3D) crossbar RRAM. Fig. 9 (a) shows a stacked structure and Fig. 9 (b) shows a vertical structure.
10 (a) and 10 (b) illustrate the paths of the snick current in the stacked 3D RRAM. FIG. 10 (c) shows the paths of the snick current flowing from the reading method according to the embodiment of the present invention to the compensation sensing point FIG.
FIG. 11 illustrates a sensing read method according to an embodiment of the present invention applied to a 3D RRAM of a vertical structure.

BRIEF DESCRIPTION OF THE DRAWINGS The above and other features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings in which: FIG. The present invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. In order to clearly illustrate the present invention in the drawings, parts not related to the description are omitted, and similar names and reference numerals are used for similar parts throughout the specification.

2 is a conceptual diagram for explaining a method of reading a crossbar resistance memory according to an embodiment of the present invention.

Instead of floating all the unselected bit lines and word lines as in the conventional floating reading method, in the present invention, a sensing voltage is applied to an additional word line to additionally take one compensation sensing point.

(Hereinafter, referred to as 'main sensing current') I _{MAIN, 2P} in the bit line of the selected cell as in the conventional floating reading method in order to read the data stored in the selected cell. However, unlike the conventional floating reading method, in a word line different from a word line of a selected one of the arrays of word lines crossing a bit line of a selected cell (hereinafter, also referred to as 'compensation sensing word line' (Hereinafter, referred to as 'compensation current') I _COMP , and determines the data stored in the selected cell using the main sensing current and the compensation sensing current. The word line for compensation sensing is on the same layer as the word line of the selected cell.

A read voltage V _R is applied to a word line of a selected cell, a first sense voltage V _SS is applied to a bit line of the selected cell, and a second sense voltage V _SS is applied to a word line different from the word line of the selected cell V _SS ) are applied and the remaining bit lines and the remaining word lines in the crossbar array to which the selected cell belongs are floated (indicated by 'F'). The first sensing voltage V _SS and the second sensing voltage V _SS are the same voltage.

The current I _COMP sensed at the compensation sensing point is used to predict the total sneak current flowing into the main sensing point and can cancel the snick current to predict the current I _CELL flowing in the selected cell .

According to the embodiment of the present invention, since the main sensing point and the compensation sensing point are detected at two points, it can be referred to as a 'two-point sensing method'. However, in addition to defining a single sensing point in defining the compensation sensing point, it is also possible to define a plurality of compensation sensing points using a plurality of word lines. Therefore, the sum of the main detection point and the compensation detection point may be physically three or more, and in this case, the concept can be referred to as a "two-point detection method".

3 (a) shows an example of a path of a snick current flowing from a crossbar resistance memory to a main sensing point according to an embodiment of the present invention.

Each cell (element) of the crossbar resistance memory has a structure of a 1-selector and a 1-resistor (1S1R).

The path consists of two devices with forward bias and one device with reverse bias. At this time, since the resistance R _R of the device to which the reverse bias is applied in the 1S1R device is much larger, most of the applied voltage is caught by the device to which the reverse bias is applied, and the magnitude of the snick current flowing in the corresponding path is expressed as .

In the case of the conventional floating reading method as shown in FIG. 1 (c), since the snick current flowing in all the remaining elements excluding the elements connected to the selected one bit line and one word line flows into one main sensing point, The sum of the total snick currents (I _SNEAK ) can be expressed as (number of word lines in the crossbar array: M, number of bit lines in the crossbar array: N).

3 (b) shows an example of a path of a snick current flowing from the crossbar resistor memory to the compensation detection point according to an embodiment of the present invention.

The path consists of one device with forward bias and one device with reverse bias. Also in this case, since the resistance (R _R ) of the element to which the reverse bias is applied is much larger, the magnitude of the snick current flowing in the path is as follows.

At this time, the sum of the snick current flowing in the elements connected to the word line to which the sensing voltage is further applied is sensed as the compensation sensing current at the compensation sensing point. This can be expressed as follows.

At this time, since the snick current corresponding to the compensation sensing current I _COMP among all the snick currents expressed by Equation (2) passes to the compensation detection point, the magnitude of the current (main sensing current) sensed at the main sensing point is Respectively.

Substituting Equation (4) into Equation (5) yields the following results.

If we replace (M-2) I _COMP in Equation 6,

(Main sensing current: I _{MAIN, 2P} ) of the main sensing point is multiplied by a constant (more specifically, integer multiple) M-2 of the current (compensation sensing current; I _COMP ) It is possible to obtain the current (I _CELL ) flowing in the selected cell. Therefore, if the final sense current (I _MEAS ) is set as follows, the snick current can be completely eliminated.

FIG. 4 (a) shows a comparison between the sensing current obtained through the method of FIG. 8 (two-point sensing) and the sensing current obtained through the conventional floating reading method (single-point sensing) through simulation.

At this time, R _L was fixed to 50 kOhm, R _H / R _L = 10, N = 100 and M = 100 (where R _L is the low resistance state resistance value, R _H is the high resistance state resistance value, And the applied voltage (V _R -V _SS ) was fixed at 1V. I _{CELL, HR} and I _{CELL, LR} are the currents flowing in the selected cell when the selected cell is in the high resistance state and the low resistance state, respectively, and I _{MEAS, HR} and I _MEAS, State of the sensing current.

As the ratio of the resistance R _{R at the} time of applying the reverse bias to the resistance R _{H at the} high resistance state becomes smaller, in the conventional method _, I _{MEAS and HR} exceed the reference current due to the snick current, Lt; / RTI >

On the other hand, the method provided by the present invention keeps the current I _{MEAS, HR} equal to the current flowing in the almost selected cell. However, if R _R / R _H becomes smaller to a certain level, the assumption that the current flowing in the path shown in FIG. 3A and the current flowing in the path shown in FIG. 3B are broken, And I _{MEAS and HR} are decreased. As long as R _R / R _H becomes smaller within a certain level, it proceeds in a direction having a smaller value than the reference current (I _REF ), so that it does not cause a data read error.

On the other hand, if R _R / R _H becomes smaller, I _{MEAS, LR} also starts decreasing, and if I _{MEAS, LR} becomes smaller than the reference current, it may cause a data read error. A method for solving this is shown in FIG. 5 and FIG. 9 which will be described later.

4 (b) compares the sense current obtained through the method of equation (8) (two-point sensing) with the sensing current obtained through the conventional floating reading method (single-point reading).

At this time, R _H / R _L = 100 was fixed. The other parameters were fixed to the same conditions as in Fig. 4 (a). In this case, the reduction due to the overestimated snick current is negligible since I _{MEAS, LR} has a value sufficiently larger than the snick current.

5 shows the result obtained by using a method for solving a reading error caused by an overestimated snitch current.

In order to prevent an overestimation of the snick current, the coefficient of I _COMP in equation (8) can be taken smaller than (M-2). The results in FIG. 5 are the results obtained according to the following equation.

All other conditions are fixed as shown in FIG. 4 (a), and the results obtained by solving the overestimated decrease due to the snick current generated in FIG. 4 (a) are shown.

From the simulation results of FIGS. 4 (a), 4 (b) and 5, it can be seen that adjusting the coefficients of I _COMP can yield optimized results for different situations. When R _H / R _L is large, a value close to the equation (8) can be used. In the case where R _H / R _L is small, optimization can be performed by reducing the coefficient.

The reading method according to an aspect of the present invention includes a process of determining data stored in a selected cell after canceling an effect of a snick current included in a main sense current I _{MAIN, 2P} sensed in a bit line of a selected cell do. The offset is obtained by using the compensation sense current I _COMP sensed in a word line (compensation sense word line) different from the word line of a selected one of the arrays of the word lines crossing the bit line of the selected cell .

In this process, the sneak current is regarded as a constant multiple of the compensation sense current I _COMP (a value obtained by multiplying by a constant, for example, M-2, M-10, etc.) Lt; / RTI > The snitch current is regarded as being directly proportional to the compensation sense current (I _COMP ), thereby canceling the effect of the snick current.

6 is a diagram showing a change in sensing current according to a memory capacity.

R _H / R _L = 100, and R _R / R _H = 100. In the case of a single point reading, a data reading error occurs due to the sneak current as the memory capacity increases, whereas the method according to one aspect of the present invention (two-point sensing method) shows a constant result regardless of the increase in the memory capacity . That is, a scheme according to an aspect of the present invention enables an increase in memory capacity.

FIG. 7 is a circuit diagram of a read block to which a read method according to an embodiment of the present invention is applied, and FIG. 7 (b) specifically shows a sense amplifier 140 in FIG. 7 (a).

The read-out block according to an embodiment of the present invention may further include a portion not shown, for example, a portion for applying a read voltage V _R to a selected cell .

The read block 100 illustrates a circuit for calculating the current corresponding to equation (8). The read block 100 receives the main sense current I _{MAIN, 2P} flowing by applying the sense voltage to the selected bit line and the compensation sense current I _COMP flowing by applying the sense voltage to the word line for compensation sensing , The main sensing current and the compensation sensing current to determine the data stored in the selected cell. The read block 100 determines the data stored in the selected cell after offsetting the effect of the snick current included in the main sense current, and the offset is determined by the compensation sense current I _COMP sensed in the compensation sense word line, .

The current amplification unit 110 amplifies the compensation sense current sensed at the compensation detection point, and the amplified current and the reference current I _REF are added to flow to the left path of the sense amplifier 140. The current amplification unit 110 outputs an amplified current obtained by amplifying the compensation sense current by a factor of a constant vlaue. The constants may be set by the number of word lines M in the crossbar array to which the selected cell belongs (for example, M-2 in Equation 8 or M-10 in Equation 9) May be set by both the number M of word lines and the number N of bit lines in the crossbar array to which the selected cell belongs.

The current mirror unit 120 copies the main sensing current sensed at the main sensing point and flows the sensing current to the right path of the sense amplifier 140. The current mirror unit 120 outputs the mirror current to which the main sensing current is copied. The reference current generating unit 130 generates and supplies a reference current in a manner such that it is added to an amplified current output from the current amplifying unit 110 or subtracted from a mirror current that is an output of the current mirror unit 120 Can be applied.

The determination of the data stored in the selected cell can be performed by comparing the main sensing current with the reference current, offsetting the compensating sensing current at the main sensing current by the amplified current amplified by a factor of the predetermined constant and then comparing. And this offset can be done by adding the amplified current to the reference current, or subtracting the amplified current from the main sense current.

The sense amplifier 140 compares the magnitudes of the currents of both paths and outputs a digital signal according to the result of comparing the magnitudes of the currents. The sense amplifier 140 outputs a result of comparing the sum current obtained by adding the amplified current output from the current amplifier 110 to the reference current and the mirror current output by the current mirror unit 120.

The sense amplifier 140 includes a plurality of precharge PMOS transistors P1 and P4 for precharging a charge to a complementary output node; Gating NMOS transistors N3 and N4 for opening and closing a path for discharging charge accumulated in the complementary output node by the mirror current and the sum current, respectively; (N1, N2, P2, P3) for providing positive feedback to the potential difference between complementary output nodes.

The NMOS transistor N3 and the NMOS transistor N4 receive the mirror enable signal and the read enable signal Read_en through the drain and source paths of the mirror current and the sum current, The NMOS transistor N1 and the NMOS transistor N2 are connected to the drains of the NMOS transistor N3 and the NMOS transistor N4, respectively.

The NMOS transistor N1 and the PMOS transistor P2 form an inverter and the NMOS transistor N2 and the PMOS transistor P3 constitute an inverter. It is connected. The gate of the NMOS transistor N1 is connected to the drain of the NMOS transistor N2 and the gate of the NMOS transistor N2 is connected to the drain of the NMOS transistor N1.

FIG. 7 (c) illustrates operation and waveforms of a read block according to an embodiment of the present invention.

The operation of the read block can be divided into three steps in total. In the first precharge phase, the voltage of the output node is raised to V _DD such that the Read_en signal has a value of zero. In the second discharge stage, the Read-en signal is changed to 1, and the output voltage of both complementary output nodes decreases according to the current flowing in both paths. When the output voltage of the PMOS transistor P2 or P3 is reduced to a certain level or less, the PMOS transistor P2 or P3 is turned on to generate a positive feedback, Amplified to the output level.

The bridge transistor P5 connecting between the two output nodes in Figs. 7 (b) and 7 (c) has both output nodes at the same voltage even if both output nodes are not sufficiently raised to V _DD during the pre- If you have enough time to get up to V _DD , you can remove it to reduce the number and area of devices.

FIG. 8A is a circuit diagram again showing the current amplification section 110 and the current mirror section 120 in FIG. 7A. FIG. 8B is a circuit diagram showing the current amplification section 210 and And a current mirror unit 220. FIG.

Referring to FIG. 8A, since a current is sensed using a diode-connected NMOS (NMOS) device, the sense voltage V _SS is a gate-overdrive added to the threshold voltage V _TH , The voltage is determined by adding. Accordingly, since the value of the sense voltage V _SS increases, the voltage (V _R -V _SS ) applied to the RRAM itself (that is, the selected cell of the RRAM) becomes small, and the size of the sense current becomes small. In addition, since the compensation sense current and the main sense current are different in size, different gate-overdrive voltages are provided, so that the compensation sense voltages V _{SS, C} and the main sense voltages V _SS, May also occur.

The circuit of Fig. 8 (b) is intended to solve the problem of the circuit of Fig. 8 (a). By using the amplifiers 213 and 223, a constant voltage can always be used as the compensation sense voltage and the main sense voltage, and this value is set to be smaller than the threshold voltage plus an additional gate-overdrive voltage (V _GS ) The voltage drop that occurs can be reduced.

V _DS = V _GS , and it is possible to obtain a lower sensing voltage since V _CS ? V _DS can be arbitrarily applied so that? V _GS <V _DS <V _GS . Also, the compensation sense voltage V _{SS, C} and the main sense voltage V _{SS, M} can be made equal.

The current amplification unit 210 includes a first NMOS transistor 211, a second MOS transistor 213, and an amplifier 213.

The first NMOS transistor 211 is coupled such that the compensation sense current flows through the drain-source path, and the second MOS transistor 213 is connected to the gate of the first NMOS transistor 211 and the drain- Thereby allowing the amplified current to flow. The gates of the first and second MOS transistors 211 and 212 are connected to the output terminal of the amplifier 213 and the drain of the first MOS transistor 211 is connected to the + A constant voltage is applied.

The current mirror unit 120 includes a first MOS transistor 221, a second MOS transistor 222, and an amplifier 223.

The first MOS transistor 211 is connected such that the main sense current flows through the drain-source path, and the second MOS transistor 222 is connected to the gate of the first MOS transistor 221 at its gate and the drain- So that the mirror current flows. The amplifier 223 has the output terminal connected to the gates of the first MOS transistor 221 and the second MOS transistor 222 and the + input terminal connected to the drain of the first MOS transistor 221, .

Fig. 9 shows two embodiments of a three-dimensional (3D) crossbar RRAM. Fig. 9 (a) shows a stacked structure and Fig. 9 (b) shows a vertical structure.

The concept of the present invention can be similarly applied to a crossbar RRAM having such a three-dimensional structure. Hereinafter, the same concept as that of FIGS. 2 to 8 may be omitted. The word line of the selected cell in the three-dimensional crossbar RRAM and the word line different from the word line of the selected cell (i.e., the compensation sense word line) are on the same layer.

10 (a) and 10 (b) illustrate the paths of a snick current in a stacked 3D RRAM.

In stacked 3D RRAMs, this path is negligible because the amount of current flowing through the path that contains the device with two or more reverse voltages is small. As shown in Figs. 10 (a) and 10 (b), the selected bit line and the word line have a height difference corresponding to one floor, and a combination of the sneak current paths capable of connecting the two There are three kinds of things.

Case 1. Bottom-Up-Top: Cells with reverse voltage are on the first floor

Case 2. Up-down-top: Cells with reverse voltage on the second floor

Case 3. Up-up-down: cell with reverse voltage is on the third floor

In other cases (for example, below-below-above-above-above), two or more reverse voltage devices are included in the path and can be ignored. In each case, the total number of sneak current paths is:

Case 1. Down-Up-Up: N x (M-1)

Case 2. Top-bottom-top: (N-1) x (M-1)

Case 3. Top-Up-Down: (N-1) x M

Since the current flowing in each path is as shown in Equation (3), the total amount of the snick current is as follows.

10 (c) shows the path of the snick current flowing from the reading method to the compensation sensing point according to an embodiment of the present invention.

The word line for compensation sensing is selected as the word line in the same layer as the word line of the selected cell. Since the word line of the cell to read data and the word line of the compensation detection point have the same height, the total number of the sneak current paths that can connect the two is as follows.

Case 1. Down-Up: N-1 cells with reverse voltage on the first floor

Case 2. Up-down: If there is a cell with reverse voltage on the second floor, N

Then, the magnitude of the snick current sensed at the compensation detection point is expressed by Equation (11).

The current sensed at the main sensing point by the reading method according to an embodiment of the present invention is as follows.

Then, if the final sensing current (I _SENSE ) is set by estimating the current (I _CELL ) flowing in the selected cell as described below, the influence of the snick current on the final sensing current can be completely eliminated.

The snitch current is affected by both the number of word lines (M) and the number of bit lines (N) in the crossbar array. In amplifying the sense current sensed at the compensation sensing point, the constant current ) Can be set by both the number (M) of word lines and the number (N) of bit lines in the crossbar array.

FIG. 11 illustrates a sensing read method according to an embodiment of the present invention applied to a 3D RRAM of a vertical structure.

In the case of a vertical structure, the sneak current is not limited to three layers because the word line is shared across all the layers, unlike the stacked structure. That is, all the cells except the cells connected to the selected word line and the bit line may be cells to which the reverse bias of the snick current path is applied. Thus, the total snitch current is (M is the number of word lines, N is the number of longitudinal floors, and L is the number of bit lines included in one longitudinal floor).

At this time, the number of the sneak current paths passing from the selected word line W1 to the compensation sense word line W2 can be obtained as follows.

Case 1. Longitudinal floor containing the selected bit line: Except for one directly connected to the selected bit line in the selected word line: L-1

Case 2. Other longitudinal floorings: (N-1) x L

Then, since the total number of paths is NL-1, the magnitude of the snick current detected at the compensation detection point is as follows.

The current sensed at the main sensing point of the reading method according to an embodiment of the present invention is as follows.

Therefore, if the final sense current (I _SENSE ) is set as follows, the snick current can be completely eliminated.

This is consistent with equation (8) for one-dimensional RRAM. Actually, the vertical structure is the same as the two-dimensional crossbar RRAM having M word lines and (N x L) bit lines when expanded.

100: read block 110, 210:
120, 220: current mirror part 130: reference current generating part
140: Sense Amplifier

Claims (28)

In a crossbar resistance memory,
(Hereinafter, referred to as a 'main sensing current') which applies a first sensing voltage to a bit line of a selected cell and flows to a point where the first sensing voltage is applied and a word line crossing a bit line of the selected cell A second sense voltage is applied to a word line different from a word line of the selected cell in the array to receive a current (hereinafter, referred to as 'compensation sense current') flowing to a point where the second sense voltage is applied, And a read block for determining data stored in the selected cell using the sense current and the compensation sense current.
Lt; / RTI &gt; memory. The method according to claim 1,
Wherein the first sensing voltage and the second sensing voltage are the same,
Lt; / RTI &gt; memory. The method according to claim 1,
Wherein a word line of the selected cell and a word line different from the word line of the selected cell are on the same layer,
Lt; / RTI &gt; memory. The method according to claim 1,
In the crossbar array to which the selected cell belongs, the remaining word lines except for the word line of the selected cell and the word line to which the second sense voltage is applied are floated,
In a crossbar array to which the selected cell belongs, the remaining bit lines except the bit line of the selected cell are floated,
Lt; / RTI &gt; memory. In a crossbar resistance memory,
And a read block for canceling an influence of a snick current included in a current sensed by a bit line of a selected cell (hereinafter, referred to as a 'main sensing current') and determining data stored in the selected cell,
The offset is performed using a current sensed in a word line different from the word line of the selected cell (hereinafter, referred to as 'compensation sense current') among the array of word lines crossing the bit line of the selected cell Features a crossbar resistor memory. In a crossbar resistance memory,
(Hereinafter, referred to as a 'main sense current') sensed in a bit line of a selected cell and an array of word lines crossing the bit line of the selected cell are detected in a word line different from the word line of the selected cell And a read block for determining data stored in the selected cell using a current (hereinafter, referred to as 'compensation current').
Lt; / RTI &gt; memory. The method according to any one of claims 1, 5 and 6,
The read block includes:
And a current amplification unit for outputting an amplification current obtained by amplifying the compensation sense current by a factor of a constant,
Lt; / RTI &gt; memory. The method of claim 7,
Wherein the current amplifying part comprises:
A first MOS transistor connected such that the compensation sense current flows through a drain-source path;
A second MOS transistor whose gate is connected to the gate of the first MOS transistor and the amplified current flows through a drain-source path;
An output terminal connected to the gates of the first MOS transistor and the second MOS transistor, a + input terminal connected to a drain of the first MOS transistor, and an input terminal to which a constant voltage is applied;
Lt; / RTI &gt; memory. The method of claim 8,
The constant-
And a gate-overdrive voltage of the first MOS transistor and the second MOS transistor,
Lt; / RTI &gt; memory. The method of claim 7,
The constant,
(M) of the word lines in the crossbar array to which the selected cell belongs,
(M) of the word lines and the number (N) of bit lines in the crossbar array to which the selected cell belongs.
Lt; / RTI &gt; memory. The method of claim 7,
The read block includes:
A reference current generator for generating a reference current; And
And a current mirror unit for outputting a mirror current to which the main sensing current is copied
Lt; / RTI &gt; memory. The method of claim 11,
The current mirror unit includes:
A first MOS transistor connected such that the main sense current flows through a drain-source path;
A second MOS transistor whose gate is connected to the gate of the first MOS transistor and the mirror current flows through a drain-source path;
An output terminal connected to the gates of the first MOS transistor and the second MOS transistor, a + input terminal connected to a drain of the first MOS transistor, and an input terminal to which a constant voltage is applied;
Lt; / RTI &gt; memory. The method of claim 11,
And a sense amplifier for outputting a result of comparing the sum current obtained by adding the amplified current and the reference current to the mirror current
Lt; / RTI &gt; memory. 14. The method of claim 13,
The sense amplifier includes:
A precharging MOS transistor for precharging a charge to the complementary output node;
A gating MOS transistor for opening / closing a path for discharging charge accumulated in the complementary output node by the mirror current and the sum current, respectively;
And an inverting MOS transistor for giving a positive feedback to the potential difference between the complementary output nodes.
Lt; / RTI &gt; memory. 14. The method of claim 13,
The sense amplifier includes:
A first NMOS transistor and a second NMOS transistor having the mirror current and the sum current respectively flowing through a drain-source path and receiving a read enable signal at a gate thereof; And
And a third NMOS transistor and a fourth NMOS transistor, the sources of which are respectively connected to the drains of the first NMOS transistor and the second NMOS transistor,
Wherein a gate of the third NMOS transistor is coupled to a drain of the fourth NMOS transistor and a gate of the fourth NMOS transistor is coupled to a drain of the third NMOS transistor.
Lt; / RTI &gt; memory. The method according to any one of claims 1, 5 and 6,
Each cell of the crossbar resistance memory has a 1-selector and a 1-
Lt; / RTI &gt; memory. The method according to claim 5 or 6,
A read voltage is applied to the word line of the selected cell,
A first sense voltage is applied to a bit line of the selected cell and a second sense voltage is applied to a word line different from the word line of the selected cell,
The remaining bit lines and the remaining word lines in the crossbar array to which the selected cell belongs are floated,
Lt; / RTI &gt; memory. 18. The method of claim 17,
Wherein the first sense voltage and the second sense voltage are the same and the read voltage is different from the first sense voltage and the second sense voltage,
Lt; / RTI &gt; memory. In a crossbar resistor memory read method,
Determining the data stored in the selected cell after canceling the influence of the snick current included in the current sensed by the bit line of the selected cell (hereinafter, referred to as 'main sensing current') to read the stored data,
The offset is performed using a current sensed in a word line different from the word line of the selected cell (hereinafter, referred to as 'compensation sense current') among the array of word lines crossing the bit line of the selected cell A feature of the crossbar resistor reading method of memory. The method of claim 19,
Wherein the snitch current is regarded as a constant multiple of the compensation sense current to cancel the influence of the snick current,
Wherein the crossbar resistance memory is read from the memory. The method of claim 19,
Wherein the snitch current is regarded as being directly proportional to the compensation sense current,
Wherein the crossbar resistance memory is read from the memory. In a crossbar resistor memory read method,
(Hereinafter, referred to as a 'main sense current') sensed in a bit line of a selected cell to read stored data and a word line of the selected cell among the array of word lines crossing the bit line of the selected cell Determining data stored in the selected cell using a current sensed in a word line (hereinafter, referred to as 'compensation sensing current').
Wherein the crossbar resistance memory is read from the memory. 23. The method of claim 22,
The determination,
Comparing the main sensing current with a reference current,
And compensating the compensated sensing current by the amplified current amplified by the magnification of the predetermined constant,
Wherein the crossbar resistance memory is read from the memory. 24. The method of claim 23,
The offset,
Adding the amplified current to the reference current,
And subtracting the amplified current from the main sensing current.
Wherein the crossbar resistance memory is read from the memory. The method of claim 19 or claim 22,
In using the compensation sense current,
And amplifying the compensation sense current by a predetermined constant multiplication factor.
Wherein the crossbar resistance memory is read from the memory. 26. The method of claim 25,
The constant,
(M) of the word lines in the crossbar array to which the selected cell belongs,
(M) of the word lines and the number (N) of bit lines in the crossbar array to which the selected cell belongs.
Wherein the crossbar resistance memory is read from the memory. The method of claim 19 or claim 22,
A read voltage is applied to the word line of the selected cell,
A first sense voltage is applied to a bit line of the selected cell and a second sense voltage is applied to a word line different from the word line of the selected cell,
The remaining bit lines and the remaining word lines in the crossbar array to which the selected cell belongs are floated,
Wherein the crossbar resistance memory is read from the memory. 28. The method of claim 27,
Wherein the first sensing voltage and the second sensing voltage are the same,
Wherein the crossbar resistance memory is read from the memory.

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