KR101870999B1

KR101870999B1 - Antifuse of semiconductor device and manufacturing method of the same

Info

Publication number: KR101870999B1
Application number: KR1020120070677A
Authority: KR
Inventors: 최우영; 윤규한
Original assignee: 에스케이하이닉스 주식회사; 서강대학교산학협력단
Priority date: 2012-06-29
Filing date: 2012-06-29
Publication date: 2018-06-25
Also published as: KR20140003089A

Abstract

Disclosed is an anti-fuse of a semiconductor device capable of controlling a breakdown position of an insulating film by using a difference in permittivity and improving resistance scattering after an insulating film break, and a method for manufacturing the same.
An anti-fuse of a semiconductor device according to the present invention includes a source and a drain which are formed on a substrate and are spaced apart from each other; A gate insulating film formed on the substrate so as to include a material having a first permittivity so that an undercut is formed on at least one of the opposite ends of the substrate and one end of the gate is in contact with the source and the other end of the gate is in contact with the drain; An undercut filling part filling the undercut with a material having a second permittivity lower than the first permittivity; And a gate electrode formed on the gate insulating film and the undercut filling portion.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an anti-fuse of a semiconductor device,

The present invention relates to a semiconductor device, and more particularly, to an anti-fuse of a semiconductor device and a method of manufacturing the same.

A semiconductor device, particularly a memory device, can not function as a memory when any one of a large number of memory cells is defective at the time of manufacturing, and therefore, it is treated as a defective product. However, it is inefficient in terms of productivity to discard the entire memory device as a defective product even though only some memory cells in the memory are defective. Therefore, at present, replacement of a defective memory cell by using a redundancy cell manufactured in advance in a memory device improves the yield and reduces the cost by reviving all the devices.

The repair process using the spare cells is a process of connecting a cell determined to be defective through an inspection process to a spare cell built in the chip by using a fuse. That is, by cutting only specific fuses, position information of cells to be repaired is generated.

However, a method of repairing a semiconductor device using a fuse is to repair the semiconductor device in a wafer state. Since the laser repair device can not be used after packaging, it is not applicable when the defective cell is found to be present in the completed package There is a limit. An antifuse type has been developed to overcome the limitation of the fuse type.

The anti-fuse can be programmed for defect remedies simply at the package level. The anti-fuse is electrically opened in a steady state in relation to the pre-package fuse, and when the insulator between the conductors is broken by application of a high voltage as required, the antifuse is electrically short-circuited Fuse refers to. Such an anti-fuse is formed in a peripheral circuit area, and spare cells for anti-fuse are formed in a peripheral circuit area, but are formed as a static random access memory (SRAM) cell, which does not require refreshing.

Conventional anti-fuse has a structure including two conductive layers and a dielectric layer therebetween. These anti-fuses are programmed by applying a voltage between two conductive layers to breakdown the dielectric layer. Depending on the programming, the magnitude of the current between the two conductive layers is different. However, it is not easy to control the rupture position with the conventional anti-fuse.

Korean Patent Laid-Open Publication No. 2011-0014581 (published on Feb. 11, 2011) discloses a memory device including an antifuse memory cell having a double-thickness gate oxide.

One object of the present invention is to provide an anti-fuse of a semiconductor device which can control the rupture position of an insulating film by using a difference in permittivity and can improve resistance scattering after an insulating film breakdown.

Another object of the present invention is to provide a method of manufacturing an anti-fuse of a semiconductor device which can be easily manufactured using an existing process.

According to an aspect of the present invention, there is provided an anti-fuse of a semiconductor device, including: a source and a drain spaced apart from each other; A gate insulating film formed on the substrate so as to include a material having a first permittivity so that an undercut is formed on at least one of the opposite ends of the substrate and one end of the gate is in contact with the source and the other end of the gate is in contact with the drain; An undercut filling part filling the undercut with a material having a second permittivity lower than the first permittivity; And a gate electrode formed on the gate insulating film and the undercut filling portion.

According to another aspect of the present invention, there is provided an anti-fuse of a semiconductor device, including: a source and a drain spaced apart from each other; A gate insulating film formed on the substrate and including a material having a first permittivity so that an undercut is formed at both ends of the substrate, the one end of the gate insulating film contacting the source and the other end contacting the drain; A first undercut filling part filling the undercut at one end of the gate insulating film with a material having a second permittivity lower than the first permittivity; An interlayer dielectric material having a third dielectric constant higher than the second dielectric constant, the second undercut filling part filling an undercut of the other end of the gate insulating film; And a gate electrode formed on the gate insulating film, the first and second undercut filling portions.

According to another aspect of the present invention, there is provided a method of fabricating an anti-fuse of a semiconductor device, comprising: forming a source and a drain on a substrate; Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain; Forming a gate electrode on the gate insulating film; Etching the gate insulating film using the gate electrode as an etching mask to form an undercut at both ends of the gate insulating film; And forming an undercut filler filling the undercut with a material having a second permittivity lower than the first permittivity.

According to another aspect of the present invention, there is provided a method of fabricating an anti-fuse of a semiconductor device, comprising: forming a source and a drain on a substrate; Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain; Forming a gate electrode on the gate insulating film; Forming a photoresist pattern on at least one of the source and the drain and at least a portion of the gate electrode adjacent to the selected source or drain so as to cover the other end of the gate insulator; Etching the exposed end of the gate insulating film using the photoresist pattern as an etching mask to form an undercut; And forming an undercut filler filling the undercut with a material having a second permittivity lower than the first permittivity.

According to another aspect of the present invention, there is provided a method of fabricating an anti-fuse of a semiconductor device, comprising: forming a source and a drain on a substrate; Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain; Forming a gate electrode on the gate insulating film; Etching the gate insulating film using the gate electrode as an etching mask to form an undercut at both ends of the gate insulating film; Forming a photoresist pattern on at least one of the source and the drain and at least a portion of the gate electrode adjacent to the selected source or drain so as to cover the other end of the gate insulator; Forming a first undercut filling part filling the undercut at one end of the gate insulating film with a material having a second permittivity lower than the first permittivity; Removing the photoresist pattern so that an undercut of the other end of the gate insulator film located on the opposite side of the first undercut filler is exposed; And forming a second undercut filler filling the undercut of the other end of the gate insulating film with an interlayer dielectric material having a third permittivity higher than the second permittivity.

The anti-fuse according to the present invention is formed by filling an undercut formed on at least one of both ends of a gate insulating film with an undercut filling part made of a material having a dielectric constant lower than that of a gate insulating film and an ILD (inter-layer dielectric) film, At least one of both ends of the undercut filling portion can be selectively broken by the voltage. This makes it possible to control the breakdown position of the insulating film for anti-fuse and improve the resistance spread after the breakdown of the insulating film for anti-fuse.

Further, even at a low breakdown voltage, at least one of both ends of the undercut filling portion can be easily short-circuited to facilitate conduction between the gate electrode and the junction region.

Further, since the anti-fuse according to the present invention can be manufactured by utilizing the manufacturing process of a conventional semiconductor device, the anti-fuse according to the present invention can be easily manufactured along with the process of forming a device in a cell region such as a memory array .

1 is a cross-sectional view illustrating an anti-fuse of a semiconductor device according to an embodiment of the present invention.
2 is a cross-sectional view illustrating an anti-fuse of a semiconductor device according to another embodiment of the present invention.
FIGS. 3 to 5 are process cross-sectional views illustrating a method of manufacturing an anti-fuse of a semiconductor device according to an embodiment of the present invention.
6 to 10 are process sectional views illustrating a method of manufacturing an anti-fuse of a semiconductor device according to another embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and how to accomplish them, will become apparent by reference to the embodiments described in detail below with reference to the accompanying drawings. It should be understood, however, that the invention is not limited to the disclosed embodiments, but may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Is provided to fully convey the scope of the invention to those skilled in the art, and the invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

Hereinafter, an antifuse according to an embodiment of the present invention and a method of manufacturing the same will be described with reference to the accompanying drawings.

FIG. 1 is a cross-sectional view showing an anti-fuse of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view showing an anti-fuse of a semiconductor device according to another embodiment of the present invention, .

1, an anti-fuse of a semiconductor device according to an embodiment of the present invention includes a junction region 120 including a source 120a and a drain 120b spaced apart from each other on a substrate 110, A gate insulating film formed on the substrate 110 and including a material having a first permittivity so that an undercut R is formed and one end thereof is in contact with the source 120a and the other end is in contact with the drain 120b. An undercut filling part 150 filling the undercut R with a material having a second permittivity lower than the first permittivity and a gate electrode 130 formed on the gate insulating film 130 and the undercut filling part 150 140).

The substrate 110 may be a conventional semiconductor substrate. In one example, the substrate 110 may be a p-substrate doped with a p-type impurity at a low concentration, or the n-type impurity may be a doping pin n- substrate at a low concentration. Alternatively, the substrate 110 may be a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, and other substrates.

The gate insulating film 130, the gate electrode 140, and the undercut filler 150 form a gate stack in the form of a line extending in one direction.

The gate insulating layer 130 may be formed of a conventional insulating material, and may include a material having a dielectric constant epsilon of more than 3.0. For example, the gate insulating film 130 may be formed of silicon oxide (SiO ₂ ), silicon nitride (SiON), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ) These may be used singly or in combination of two or more.

The gate insulating film 130 is formed by etching one end of the gate insulating film 130 in contact with the source 120a and the other end of the gate insulating film 130 in contact with the drain 120b at a thickness of about 1 nm to about half the gate length cut R are formed. This undercut R is formed through deliberate damage by the etching of the gate insulating film 130. [

The undercuts R at both ends of the gate insulating film 130 are gap-filled by the undercut filler 150. [ The undercut filler 150 may be an example of the anti-fuse means which is irreversibly changed from the high resistance state to the low resistance state.

For this, the undercut filling portion 150 may be formed of a material having a dielectric constant lower than the dielectric constant epsilon of the gate insulating film 130. Preferably, the undercut filler 150 has a dielectric constant of 3.0 or less and may be formed of a material having an irreversible resistance change characteristic, that is, an insulation breakdown characteristic.

The undercut filler 150 may be formed of an organic material, an inorganic material, or an organic-inorganic composite having a dielectric constant of 3.0 or less, and they may be used alone or in combination of two or more.

For example, the organic material may be fluorinated glass (SiO 2) (ε = 2.8) or hydrogen silsesquioxane (HSQ) (ε = 2.9), and the inorganic material may be poly (arylene ether); PAE (ε = 2.6), polyimides (ε = 2.9), fluorinated system (ε = 2.3), parylene-N (ε = 2.7), parylene- 2.4), B-stage polymer (? = 2.6), diamond-like carbon (DLC) (? = 2.7), amorphous carbon (? = 3.0) Polytetrafluoroethylene (PTFE, Teflon ) (? = 1.9), and the organic / inorganic composite may be a SiOC polymer such as methylsilsesquioxane (MSQ).

Alternatively, the undercut filler 150 may be formed of a porous material having a dielectric constant of 3.0 or less. For example, the porous material may be porous MSQ (ε = 1.8), porous PAE (ε = 1.8), porous silk (ε = 1.5) and porous SiO ₂ (ε = 1.1) Two or more species may be used in combination.

In the above case, when the undercut filler 150 is formed of a material having a dielectric constant exceeding 3.0, breakdown at both ends of the undercut filler 150 may not be easy at a low breakdown voltage during the repair process.

On the other hand, when the gate insulating film 130 is formed to include a high-k material having a higher dielectric constant than that of the silicon oxide film (SiO ₂ ), the undercut filler 150 may be a low- k) as well as a material having a dielectric constant of 3.0 or more such as a silicon oxide film (SiO ₂ ).

The undercut filler 150 may induce the destruction of the insulating film due to the voltage applied during the repair process. This is because the voltage applied to both ends of the undercut filler 150, which is made of a material having a dielectric constant lower than that of the gate insulating film 130, is higher than the voltage applied across the gate insulating film 130 even if the same gate voltage is applied. Here, the principle is generally applied that the smaller the dielectric constant is, the higher the voltage applied to the film is.

According to an embodiment of the present invention, since both ends of the undercut filler 150 can be selectively destroyed by using the difference in dielectric constant of the film at a voltage applied during the repair process, the insulating film for anti- It is possible to control the failure position.

Also, since the breakdown voltage of the low dielectric material (low-k) is generally lower than the breakdown voltage of the high-k material (high-k), the undercut filler 150 formed of a material having a low dielectric constant of 3.0 or less Both ends of the undercut filler 150 can easily be short-circuited even at a low breakdown voltage, so that conduction between the gate electrode 140 and the junction region 120 can be facilitated.

The gate electrode 140 is formed on the gate insulating film 130 and the undercut filling portion 150. The gate electrode 140 is a second electrode for the anti-fuse, and may be formed to include a conductive material. For example, the gate electrode 140 may be formed as a single layer or a multi-layer structure including at least one of a metal material such as polysilicon or metal or silicide.

The junction region 120 includes a source 120a and a drain 120b and may be formed in the substrate 110 on both sides of the gate electrode 140. [ At this time, the source 120a may be formed along the edge of one end of the gate electrode 140, and the drain 120b may be formed along the edge of the other end of the gate electrode 140.

The source 120a and the drain 120b are used as the first electrode for the anti-fuse. The source 120a and the drain 120b may be an n + region doped with an n-type impurity at a high concentration or a p + region doped with a p-type impurity at a high concentration.

A part of each of the source 120a and the drain 120b may overlap with one end and the other end of the bottom surface of the gate insulating layer 130 and the source 120a and the drain 120b may overlap each other. May include a lightly doped drain (LDD) structure. The substrate 110 between the source 120a and the drain 120b is a channel (not shown).

The source 120a, the drain 120b, the gate insulating layer 130, the gate electrode 140, and the undercut filler 150 may form a transistor, which may be an n-channel metal-oxide-semiconductor (NMOS) ) Transistor or a p-channel metal-oxide-semiconductor (PMOS) transistor. The source 120a, the drain 120b, the gate insulating film 130, the gate electrode 140, and the undercut filler 150 constitute an anti-fuse according to an embodiment of the present invention.

The anti-fuse according to one embodiment of the present invention having such a structure uses a breakdown phenomenon at both ends of the undercut filler 150.

When a programming voltage is applied between the gate electrode 140 and the substrate 110, a voltage equal to or higher than a threshold voltage is applied between the gate electrode 140 and the channel region. At this time, the voltage applied across the gate insulating film 130 Insulation breakdown occurs at both ends of the undercut filler 150 where a high voltage is applied due to a lower dielectric constant. As a result, the gate electrode 140 and the junction region 120 are electrically connected. However, the gate insulating film 130 having a relatively higher dielectric constant than the undercut filling portion 150 can be prevented from dielectric breakdown. The operation of insulating and destroying both ends of the undercut filling part 150 is referred to as a programming operation. The program operation of the anti-fuse is programmed in such a manner that a high voltage is applied through the anti-fuse terminals for a sufficient time to destroy both ends of the undercut filler 150 between the junction region 120 and the gate electrode 140.

The magnitude of the programming voltage for insulating the both ends of the undercut filler 150 may vary depending on the material and the thickness of the undercut filler 150.

As described above, since the anti-fuse according to the embodiment of the present invention can selectively break both ends of the undercut filler 150 at an applied voltage, it is possible to control the breakdown position of the insulating film for anti-fuse.

When the undercut filling part 150 is formed of a low dielectric material (low-k), both ends of the undercut filling part 150 can be easily short-circuited even at a low breakdown voltage and the gate electrode 140 and the junction area 120 ).

When the anti-fuse is programmed, both ends of the gate electrode 140 and the source 120a and the drain 120b are short-circuited to have a small resistance. If the anti-fuse is used, the resistance of the undercut filler 150 after the insulation breakdown Scattering can be improved.

1, when an undercut is formed at both ends of the gate insulating film, a first undercut filling part having a lower dielectric constant than that of the gate insulating film is formed on the undercut at one end of the gate insulating film, A second undercut filling portion having a higher dielectric constant than the dielectric constant of the first undercut filling portion may be formed. In this case, the second undercut filling part may be an inter-layer dielectric (ILD) material used in a conventional contact process, for example, boron phosphorus silicate glass (BPSG) having a dielectric constant of about 3.5, phosphorus silicate glass ), Fluorinated silicate glass (FSG), or the like. The rest of the configuration may be the same as that of the embodiment of the present invention shown in FIG. 1, and thus a duplicated description thereof will be omitted. At this time, the breakdown position of the insulating film for the anti-fuse can be controlled by inducing the insulation breakdown only on one side where the first undercut filling part including the substance having the lowest dielectric constant is substantially formed at both ends by the voltage applied during the repair process .

2, the anti-fuse of the semiconductor device according to still another embodiment of the present invention includes an undercut R formed on only one of both ends of the gate insulating layer 130, A filling underfill portion 150 may be formed. At this time, the breakdown position of the insulating film for anti-fuse can be controlled by inducing dielectric breakdown only on one side where the undercut filler 150 at both ends is formed by the voltage applied during the repair process. The anti-fuse of the semiconductor device shown in FIG. 2 is the same as the anti-fuse of the semiconductor device of FIG. 1 except that the undercut filling portion 150 is formed so as to fill the undercut R at either end The anti-fuse of the semiconductor device according to the second embodiment of the present invention will not be described. It goes without saying that the same effect as in FIG. 1 can be obtained in the case of FIG.

The anti-fuses according to embodiments of the present invention may be arranged in a plurality of units to have a two-dimensional array structure, and may be a semiconductor memory device, a logic device, a microprocessor, a field programmable gate array (FPGA) (very large scale integration) circuits.

Hereinafter, methods of manufacturing an anti-fuse of a semiconductor device according to an embodiment of the present invention will be described.

FIGS. 3 to 5 are process cross-sectional views illustrating a method of manufacturing an anti-fuse of a semiconductor device according to an embodiment of the present invention.

3, a substrate 110 including a source 120a and a drain 120b is formed on the gate stack of the gate insulating film 130 and the gate electrode 140, and on one side and the other side of the gate insulating film 130, .

The gate insulating layer 130 may be formed on the substrate 110 by using an oxidation process or a chemical vapor deposition (CVD) process to deposit a material having a dielectric constant of more than 3.0, such as silicon oxide (SiO ₂ ) An insulating film (not shown) is formed by oxidizing or vapor depositing silicon nitride (SiON), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), hafnium oxide (HfO ₂ ) or may be patterned by a photolithography process to form a line type extending in one direction.

The junction region 120 including the source 120a and the drain 120b can be formed by doping a high concentration n-type or p-type impurity into the substrate 110 through an impurity ion implantation process using a mask have. The source 120a is in contact with one end of the gate insulating film 130 and the drain 120b is in contact with the other end of the gate insulating film 130. [ The substrate 110 between the source 120a and the drain 120b is a channel (not shown).

A part of each of the source 120a and the drain 120b may overlap with one end and the other end of the bottom surface of the gate insulating layer 130. The source 120a and the drain 120b may be formed to overlap with the LDD Structure can be formed.

It may be considered that the gate insulating film 130 is formed after the junction region 120 is formed or the junction region 120 is formed after the gate insulating film 130 is formed.

The gate electrode 140 may be formed in a line type extending in one direction on the gate insulating film 130. The gate electrode 140 may be formed of a polysilicon material, a metal material, or a silicide material by physical vapor deposition (PVD), CVD or metal organic chemical vapor deposition depositing a conductive film (not shown) using a MOCVD method or the like, and patterning the conductive film by a photolithography process.

On the other hand, a laminated film of an insulating film and a conductive film is sequentially formed on the entire surface of the substrate 110, and then the laminated film is patterned by a photolithography process to form a laminated structure of the gate insulating film 130 and the gate electrode 140 patterned in a line pattern Of course it is possible. At this time, the junction region 120, the gate insulating film 130, and the gate electrode 140 are formed in the peripheral circuit region and are formed in the process of forming the junction region of the cell region, the gate insulating film, and the gate electrode.

Referring to FIG. 4, both ends of the gate insulating layer 130 are selectively etched using the gate electrode 140 as an etch mask.

The etching process uses an etchant or etching gas having a high etch selectivity (or etching rate) for the gate insulating film 130 as compared with the gate electrode 140 so that both ends of the gate insulating film 130 can be selectively etched.

For example, the etching process can be carried out using a hydrofluoric acid (HF) solution or a gaseous hydrofluoric acid (HF vapor).

An etching process using a hydrofluoric acid (HF) solution may use a hydrofluoric acid (HF) solution at a temperature of 20 ° C to 30 ° C. If the temperature of the hydrofluoric acid solution is less than 20 캜, the process time may be prolonged. If the temperature exceeds 30 캜, the center of the gate insulating film 130 may overcorrect to control the breakdown position of the insulating film.

The etching process using gaseous hydrofluoric acid (HF vapor) can be performed in a temperature atmosphere of 35 ° C to 45 ° C. In this case, when the temperature is 35 ° C or lower, the process time may be prolonged. On the other hand, when the temperature exceeds 45 ° C, the center of the gate insulating film 130 may be overcorrected and the breakdown position of the insulating film may be difficult to control.

As a result, an undercut R is formed at both ends of the gate insulating film 130 by etching. In order to control the rupture position of the insulating film, the undercut R may be formed to be etched from about 1 nm to about half the gate length from the end of the gate insulating film 130.

As described above, the undercut R is formed through intentional damage by the etching of the gate insulating film 130.

Referring to FIG. 5, an undercut filling part 150 filling the undercut R at both ends of the gate insulating film 130 is formed.

Filling the undercut section 150, such as organic materials having a lower dielectric constant than the dielectric constant of the gate insulating film 130, for example, SiOF or HSQ, silicon oxide (SiO _2), PAE, polyimide, Florin-based, paril alkylene -N, paril alkylene -F, B- stage polymer, DLC, an amorphous carbon, PTFE (Teflon), such as inorganic minerals, such as MSQ, or SiOC polymer composites, porous MSQ, porous PAE, porous silk or porous SiO ₂ Or the like, and they may be used alone or in combination of two or more.

For example, the undercut filler 150 may be formed by depositing a material having a dielectric constant lower than that of the gate insulating layer 130 to gap-fill the undercut (R) using a CVD method. With such a CVD method, it is advantageous that the undercut R can be sufficiently applied even if the thickness of the gate insulating film 130 is small.

Alternatively, the undercut filling part 150 may be formed by filling a material having a dielectric constant lower than the dielectric constant of the gate insulating layer 130 by a gap-fill process using a spin-on-deposition (SOD) ). &Lt; / RTI >

The undercut filling part 150 may be formed by depositing or coating a substance having a lower dielectric constant than the dielectric constant of the gate insulating film 130 on the substrate 110 including the undercut R by a CVD method or an SOD method so as to cover the undercut R, (Not shown), the dielectric layer may be etched, for example, by blanket etching so that the dielectric layer may remain only in the undercut (R). When the dielectric film is etched by blanket etching, the dielectric film is not removed in other regions except for the undercut filling portion 150.

Thereby, the anti-fuse including the source 120a, the drain 120b, the gate insulating film 130, the gate electrode 140, and the undercut filler 150 is completed.

6 to 10 are process sectional views illustrating a method of manufacturing an anti-fuse of a semiconductor device according to another embodiment of the present invention.

6, a substrate 110 including a source 120a and a drain 120b is formed on the gate stack of the gate insulating film 130 and the gate electrode 140, and on one side and the other side of the gate insulating film 130, .

The forming material and the forming method of the junction region 120 including the substrate 110, the source 120a and the drain 120b, the gate insulating film 130 and the gate electrode 140 are the same as those of the manufacturing method of the present invention And therefore, a duplicate description thereof will be omitted.

7, a photoresist pattern 145 is formed on at least a part of the source electrode 120a and the gate electrode 140 adjacent to the source electrode 120a so as to cover the other end of the gate insulating film 130. [

The photoresist pattern 145 may be formed by applying a photosensitive material on the substrate 110 including the gate electrode 140 to form a photoresist (not shown), and then patterning the source and drain electrodes 120a and 120a The photoresist film may be patterned by a photolithography process so that the photoresist film corresponding to at least a partial region of the gate electrode 140 on the adjacent side is left. One end of the gate insulating film 130 is exposed by the photoresist pattern 145.

If the gate length is reduced, it may be difficult to precisely pattern the photoresist layer on the gate electrode 140. Therefore, the photoresist pattern 145 may be formed on the gate electrode 140 in consideration of alignment errors, It is preferable to form the gate electrode 140 so as to cover about one half of the gate electrode 140 in terms of the process margin. However, it is not particularly limited as long as it covers one end of the gate insulating film 130, Of course it is.

7, the photoresist pattern 145 is formed on the source region 120a and a portion of the gate electrode 140 adjacent to the source region 120a. However, the present invention is not limited thereto. The photosensitive film pattern 145 may be formed on at least a portion of the gate electrode 140 adjacent to the drain 120b and the drain 120b so as to cover one end of the gate insulating film 130. [

Referring to FIG. 8, the exposed end of the gate insulating layer 130 is selectively etched using the photoresist pattern 145 as an etching mask. The etch process is performed on the gate insulating layer 130 with respect to the photoresist pattern 145, the gate electrode 140, the drain 120b and the substrate 110 so that the exposed end of the gate insulating layer 130 can be selectively etched. Use an etchant or etching gas with a high etch selectivity (or etch rate).

For example, the etching process can be performed using a hydrofluoric acid (HF) solution or a gaseous hydrofluoric acid (HF vapor), which is the same as one embodiment of the manufacturing method of the present invention described above, The description will be omitted.

As a result, an undercut R is formed at one end exposed at both ends of the gate insulating film 130 by etching. In order to control the rupture position of the insulating film, the undercut R may be formed to be etched from about 1 nm to about half the gate length from the end of the gate insulating film 130.

Referring to FIG. 9, the photoresist pattern 145 is removed. For example, the photoresist pattern 145 may be removed using a sulfuric acid (H ₂ SO ₄ ) solution at about 120 to 150 ° C.

Referring to FIG. 10, an undercut filling part 150 filling an undercut R formed at one end of the gate insulating film 130 is formed.

The undercut filling part 150 may be formed by depositing or coating a material having a dielectric constant lower than the dielectric constant of the gate insulating film 130 by a CVD method or a SOD method so as to gap-fill the undercut (R) It is possible to form the dielectric film by etching, for example, blanket etching so as to remain only in the undercut R, which is the same as one embodiment of the manufacturing method of the present invention described above, do.

Thus, the anti-fuse including the source 120a, the drain 120b, the gate insulating film 130, the gate electrode 140, and the undercut filler 150 formed on one side of the gate insulating film 130 is completed.

Although not shown in the drawings, according to yet another embodiment of the present invention, in the completed state of FIG. 4, any one of the source and the drain, and the gate electrode adjacent to the selected source or drain to cover the other end of the gate insulating film A material having a second dielectric constant lower than the first dielectric constant of the gate insulating film is deposited by the SOD method to form a low dielectric film, and then the low dielectric film is anisotropically etched to form an undercut The low dielectric film is left only to form the first undercut filling portion. Then, the photoresist pattern is removed to expose the undercut of the other end of the gate insulating film located on the opposite side of the first undercut filling portion, and BPSG, PSG, FSG or the like having a dielectric constant of about 3.5, Or an SOD method to form a second undercut filling portion formed of an ILD film in the undercut of the other end of the gate insulating film. Since the conventional ILD materials such as BPSG, PSG, and FSG have a dielectric constant of about 3.5, the first undercut filling portion substantially has the lowest permittivity as compared with the second undercut filling portion and the gate insulating film.

In this case, an anti-fuse including a source, a drain, a gate insulating film, a gate electrode, and a first undercut filling part formed on one side of the gate insulating film and a second undercut filling part formed on the other side of the gate insulating film is completed.

As described above, the anti-fuse according to one embodiment, another embodiment, and another embodiment of the present invention can be manufactured by utilizing a manufacturing process of a conventional semiconductor device, and therefore, a device in a cell region such as a memory array It can be easily manufactured together with the above-mentioned process.

Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims. These changes and modifications may be made without departing from the scope of the present invention. Accordingly, the scope of the present invention should be determined by the following claims.

110: substrate 120: junction region
120a: source 120b: drain
130: gate insulating film 140: gate electrode
145: photosensitive film pattern 150: undercut filling part
R: Undercut

Claims

A source and a drain spaced apart from each other on the substrate;
A gate insulating film formed on the substrate so as to include a material having a first permittivity so that an undercut is formed on at least one of the opposite ends of the substrate and one end of the gate is in contact with the source and the other end of the gate is in contact with the drain;
An undercut filling part filling the undercut with a material having a second permittivity lower than the first permittivity; And
And a gate electrode formed on the gate insulating film and the undercut filling portion,
Wherein the undercut filling portion is filled in the undercut for controlling the breakdown position of the gate insulating film and is in contact with the upper surface of the substrate, the lower surface of the gate electrode, and the side surface of the gate insulating film.

The method according to claim 1,
The undercut filling part
Characterized in that the anti-fuse of the semiconductor device is formed of a material having a dielectric constant of 3.0 or less or a silicon oxide film (SiO ₂ ).

3. The method of claim 2,
The undercut filling part
(DLC), amorphous carbon (DLC), polyimide, fluorine, parylene-N, parylene-F, B-stage polymer, , Porous polytetrafluoroethylene (PTFE ), SiOC polymer, porous MSQ, porous PAE, porous silk, porous SiO ₂ and silicon oxide (SiO ₂ ).

The method according to claim 1,
The undercut filling part
Wherein an insulating property is destroyed by a voltage applied between the gate electrode and the substrate.

A source and a drain spaced apart from each other on the substrate;
A gate insulating film formed on the substrate and including a material having a first permittivity so that an undercut is formed at both ends of the substrate, the one end of the gate insulating film contacting the source and the other end contacting the drain;
A first undercut filling part filling the undercut at one end of the gate insulating film with a material having a second permittivity lower than the first permittivity;
An interlayer dielectric material having a third dielectric constant higher than the second dielectric constant, the second undercut filling part filling an undercut of the other end of the gate insulating film; And
And a gate electrode formed on the gate insulating film, the first and second undercut filling portions,
Wherein the first and second undercut filling portions are respectively filled in the undercut for controlling the breakdown position of the gate insulating film and are in contact with the upper surface of the substrate, the lower surface of the gate electrode and the side surface of the gate insulating film. Anti-fuse of.

6. The method of claim 5,
The first undercut filler
Characterized in that the anti-fuse of the semiconductor device is formed of a material having a dielectric constant of 3.0 or less or a silicon oxide film (SiO ₂ ).

The method according to claim 6,
The first undercut filler
(DLC), amorphous carbon (DLC), polyimide, fluorine, parylene-N, parylene-F, B-stage polymer, , Polytetrafluoroethylene (PTFE), polytetrafluoroethylene Characterized in that the anti-fuse of the semiconductor device is formed to include at least one of SiOC polymer, porous MSQ, porous PAE, porous silk, porous SiO ₂ and silicon oxide (SiO ₂ ).

Forming a source and a drain spaced apart from each other on the substrate;
Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain;
Forming a gate electrode on the gate insulating film;
Etching the gate insulating film using the gate electrode as an etching mask to form an undercut at both ends of the gate insulating film; And
Forming an undercut filler filling the undercut with a material having a second permittivity lower than the first permittivity,
Wherein the undercut filling part is filled in the undercut for controlling the breakdown position of the gate insulating film and is in contact with the upper surface of the substrate, the lower surface of the gate electrode, and the side surface of the gate insulating film.

Forming a source and a drain spaced apart from each other on the substrate;
Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain;
Forming a gate electrode on the gate insulating film;
Forming a photoresist pattern on at least one of the source and the drain and at least a portion of the gate electrode adjacent to the selected source or drain so as to cover the other end of the gate insulator;
Etching the exposed end of the gate insulating film using the photoresist pattern as an etching mask to form an undercut; And
Forming an undercut filler filling the undercut with a material having a second permittivity lower than the first permittivity,
Wherein the first and second undercut filling portions are respectively filled in the undercut for controlling the breakdown position of the gate insulating film and are in contact with the upper surface of the substrate, the lower surface of the gate electrode, and the side surface of the gate insulating film. / RTI >

Forming a source and a drain spaced apart from each other on the substrate;
Forming a gate insulating film on the substrate, the gate insulating film including a material having a first permittivity so that one end thereof is in contact with the source and the other end is in contact with the drain;
Forming a gate electrode on the gate insulating film;
Etching the gate insulating film using the gate electrode as an etching mask to form an undercut at both ends of the gate insulating film;
Forming a photoresist pattern on at least one of the source and the drain and at least a portion of the gate electrode adjacent to the selected source or drain so as to cover the other end of the gate insulator;
Forming a first undercut filling part filling the undercut at one end of the gate insulating film with a material having a second permittivity lower than the first permittivity;
Removing the photoresist pattern so that an undercut of the other end of the gate insulator film located on the opposite side of the first undercut filler is exposed; And
And forming a second undercut filler filling an undercut of the other end of the gate insulating film with an interlayer dielectric material having a third dielectric constant higher than the second dielectric constant.

The method according to any one of claims 8, 9 and 10,
The step of forming the undercut
Characterized in that at least one exposed portion of both ends of the gate insulating film is etched with a hydrofluoric acid (HF) solution at a temperature of 20 占 폚 to 30 占 폚.

The method according to any one of claims 8, 9 and 10,
The step of forming the undercut
Characterized in that at least one exposed portion of both ends of the gate insulating film is etched by gaseous hydrofluoric acid (HF vapor) at a temperature of 35 占 폚 to 40 占 폚.

10. The method according to claim 8 or 9,
The undercut filling part
(SiO ₂ ) having a dielectric constant of 3.0 or less. _{2. A} method for manufacturing an anti-fuse of a semiconductor device, comprising the steps of:

14. The method of claim 13,
The undercut filling part
(DLC), amorphous carbon (DLC), polyimide, fluorine, parylene-N, parylene-F, B-stage polymer, , Polytetrafluoroethylene (PTFE), polytetrafluoroethylene Wherein at least one of the SiOC polymer, the porous MSQ, the porous PAE, the porous silicate, the porous SiO _2, and the silicon oxide film (SiO ₂ ) is formed.

11. The method of claim 10,
The first undercut filler
(SiO ₂ ) having a dielectric constant of 3.0 or less. _{2. A} method for manufacturing an anti-fuse of a semiconductor device, comprising the steps of:

16. The method of claim 15,
The first undercut filler
(DLC), amorphous carbon (DLC), polyimide, fluorine, parylene-N, parylene-F, B-stage polymer, , Polytetrafluoroethylene (PTFE) , SiOC polymer, porous MSQ, porous PAE, porous silk, porous SiO ₂ and silicon oxide (SiO ₂ ). Way.

10. The method according to claim 8 or 9,
The step of forming the undercut filler
(a) depositing or coating a material having the second permittivity on a substrate including the undercut to form an undercut, thereby forming a dielectric film;
(b) etching the dielectric film to leave the dielectric film only inside the undercut. < Desc / Clms Page number 19 >

18. The method of claim 17,
The step (a)
Wherein the dielectric film is formed by a chemical vapor deposition (CVD) method or a spin on deposition (SOD) method.

18. The method of claim 17,
The step (b)
Wherein the dielectric film is blanket etched. &Lt; RTI ID = 0.0 > 15. < / RTI >

11. The method of claim 10,
The step of forming the first undercut filler
(a) coating a material having the second dielectric constant by a spin-on deposition (SOD) method on a substrate including the undercut to form an undercut at one end of the gate insulating film to form a low dielectric film;
(b) anisotropically etching the low dielectric film to leave the low dielectric film only inside the undercut of the gate insulating film.

The method according to any one of claims 8, 9 and 10,
The gate electrode, the gate insulating film, the source and the drain
Wherein the step of forming the cell region of the semiconductor device is performed in the process of forming the cell region of the semiconductor device.

10. The method of claim 9,
Between forming the undercut and forming the undercut fill,
Further comprising the step of removing the photoresist pattern. &Lt; RTI ID = 0.0 > 11. < / RTI >