KR101866186B1 - Liquid crystal display device - Google Patents

Abstract

The present invention relates to a liquid crystal display, and more particularly, to a uniformly standing helix (USH) mode liquid crystal display which can be driven by a low voltage.
A feature of the present invention is that the first pixel electrode and the second common electrode are formed on the first substrate and the second pixel electrode and the second common electrode are formed on the second substrate, the horizontal component of the electric field can be maximized, The driving voltage of the liquid crystal can be lowered.
In the USH mode liquid crystal display of the present invention, a signal voltage can be applied to the second substrate through the conductive patterned spacer even if the pad portion is formed only on the first substrate, and a separate pad portion is provided on the second substrate It is possible to improve the process cost and the efficiency of the process.

Description

[0001] Liquid crystal display device [0002]

The present invention relates to a liquid crystal display, and more particularly, to a uniformly standing helix (USH) mode liquid crystal display which can be driven by a low voltage.

2. Description of the Related Art In recent years, the display field has rapidly developed in line with the information age. In response to this trend, a flat panel display device (FPD) having a thinness, light weight, A plasma display panel (PDP), an electroluminescence display device (ELD), and a field emission display device (FED) : CRT).

Among these, liquid crystal display devices are excellent in moving picture display and are most actively used in the fields of notebook computers, monitors, TVs and the like due to their high contrast ratios.

The liquid crystal used in such a liquid crystal display device includes nematic liquid crystal, smectic liquid crystal, and cholesteric liquid crystal, and a nematic liquid crystal is mainly used.

On the other hand, the response speed of such a liquid crystal display device is low, resulting in deterioration of image quality due to afterimage.

Recently, a liquid crystal display device including a USH (uniformly standing helix) mode liquid crystal has been proposed, and a USH mode liquid crystal has been proposed as a bismuth bimesogen) liquid crystals are arranged in a structure having polarity, so that the response speed is very fast.

Therefore, the response speed of the liquid crystal display device can be improved.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is an object of the present invention to provide a liquid crystal display device having all the merits of a conventional liquid crystal display device and compensating for the drawbacks.

That is, it is an object of the present invention to provide a liquid crystal display device having excellent characteristics in terms of response speed and viewing angle, and having excellent contrast ratio. Also, it is an object of the present invention to provide a liquid crystal display device which can be driven by a low voltage, and to provide a liquid crystal display device with improved process cost and process efficiency.

In order to achieve the above object, the present invention provides a liquid crystal display comprising: a first substrate; A first switching element located on the first substrate; A first pixel electrode located on the first substrate and connected to the first switching device; A first common electrode disposed on the first substrate and alternately arranged with the first pixel electrode; A second substrate facing the first substrate; A second switching element positioned on the second substrate; A second pixel electrode located on the second substrate and connected to the second switching element; A second common electrode disposed on the second substrate and alternately arranged with the second pixel electrode; A liquid crystal layer disposed between the first and second substrates; And a conductive patterned spacer located in a non-display area covering the edges of the first and second substrates and electrically connecting the first switching device and the second switching device.

In this case, the second pixel electrode is located corresponding to the first pixel electrode, the second common electrode is located in correspondence with the first common electrode, and a signal voltage applied from the outside to the first switching element is the conductive And is applied to the second switching element through a patterned spacer.

The same first voltage is applied to the first pixel electrode and the second pixel electrode, the same second voltage is applied to the first common electrode and the second common electrode, A first gate wiring; A first data line disposed on the first substrate and intersecting the first gate line; A second gate wiring disposed on the second substrate; And a second data line disposed on the second substrate and intersecting the second gate line, wherein the first switching device is connected to the first gate line and the first data line, Is connected to the second gate wiring and the second data wiring.

A first passivation layer covering the first data line and the first switching device, and a second passivation layer covering the second data line and the second switching device, the first passivation layer covering the first data line and the first switching device, 1 common electrode is located on the first passivation layer, the second pixel electrode and the second common electrode are located on the second passivation layer, and the conductive patterned spacer is formed on the first and second data lines The first and second data lines and the first and second gate lines are electrically connected to each other.

The second common electrode may be electrically connected to the first common electrode, and the conductive patterned spacer may include a conductive ball or may be coated with a conductive metal film.

The conductive patterned spacers may include a plurality of holes passing through the conductive patterned spacers. The plurality of holes may be filled with a conductive material, and correspond to the first and second switching elements, A black matrix disposed on one of the two substrates; And a color filter layer disposed on the black matrix.

The second pixel electrode may have a width equal to or greater than the width of the first pixel electrode, the second common electrode may have a width equal to or greater than the width of the first common electrode, and the liquid crystal layer may be a USH mode liquid crystal Blue phase mode liquid crystal.

As described above, according to the present invention, the first pixel electrode and the second common electrode are formed on the first substrate and the second pixel electrode and the second common electrode are formed on the second substrate, thereby maximizing the horizontal component of the electric field And the driving voltage of the USH mode liquid crystal can be lowered.

In the USH mode liquid crystal display of the present invention, a signal voltage can be applied to the second substrate through the conductive patterned spacer even if the pad portion is formed only on the first substrate, and a separate pad portion is provided on the second substrate It is possible to improve the process cost and the efficiency of the process.

Further, by using the USH mode liquid crystal, there is an effect of providing a liquid crystal display device excellent in response speed, viewing angle, and contrast ratio.

1 is a view schematically showing a driving principle of a USH mode liquid crystal in a USH mode liquid crystal display according to the present invention;
FIG. 2A is a front view of a liquid crystal array structure, and FIG. 2B is a sectional view showing an equivalent structure of a liquid crystal. FIG.
3 is a schematic cross-sectional view for explaining the principle of driving a USH mode liquid crystal in a general IPS type liquid crystal display device.
4 is a cross-sectional view schematically illustrating a plurality of pixel regions of a liquid crystal display device including a USH mode liquid crystal layer according to an embodiment of the present invention.
Figures 5A-5D schematically illustrate various aspects of a patterned spacer according to an embodiment of the present invention.
6 is a plan view schematically showing a patterned spacer formed on a substrate;
FIG. 7 is a graph for explaining a driving voltage and a transmittance relationship of a USH mode liquid crystal display device according to an embodiment of the present invention. FIG.
8A to 8C are graphs for explaining the response speed of the USH mode liquid crystal display device according to the embodiment of the present invention.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the drawings.

The liquid crystal display of the present invention is characterized by being a USH (uniformly standing helix) mode using a flexoelectric effect. The driving principle of the USH mode liquid crystal display device will be schematically described with reference to the drawings.

FIG. 1 is a view schematically showing a driving principle of a USH mode liquid crystal in a USH mode liquid crystal display according to the present invention.

As shown, in the OFF state, the USH mode liquid crystal has a helical structure in which short pitch chiral nematic liquid crystal molecules are twisted twenty times, and the axis of the helical structure, that is, the helical axis, parallel to the optical axis.

On the other hand, when the voltage is applied (ON), the optical axis of the USH mode liquid crystal is turned off and birefringence is expressed.

FIG. 2A is a front view of the liquid crystal array structure, FIG. 2B is a cross-sectional view illustrating an equivalent structure of a liquid crystal, and FIG. 3 is a schematic cross-sectional view for explaining the principle of driving a USH mode liquid crystal in a general IPS type liquid crystal display.

As shown in the figure, the USH mode liquid crystal display includes opposing first and second substrates 112 and 114, a USH mode liquid crystal 130 located between the first and second substrates 112 and 114, And first and second polarizing plates (not shown) positioned outside the first and second substrates 112 and 114, respectively.

The USH mode liquid crystal 130 has a very fast response speed because the bimesogen liquid crystal is arranged in a structure having polarity.

As described above, the USH mode liquid crystal 130 has a helical structure in which short pitch chiral nematic liquid crystal molecules are twisted twenty times, and the axis of the helical structure, that is, the helical axis, z direction).

Further, the liquid crystal 130 has a refractive index in the z direction smaller than that in the x and y directions perpendicular to the z direction, and refractive indices in the x and y directions are equal to each other (nz <nx = ny)

That is, it has an optical isotropic property at a front viewing angle, has an advantage that excellent birefringence is not exhibited at a front viewing angle and excellent black characteristic can be obtained when a voltage is not applied.

Therefore, it has an advantage of high contrast ratio.

In order to control the transmittance of the USH mode liquid crystal 130 from this property by generating birefringence in a voltage application direction by applying a voltage, the USH mode liquid crystal 130 is optically isotropic in voltage, It is necessary to arrange the polarizing plates (not shown) perpendicularly to each other and apply an electric field in the in-plane direction (horizontal direction) of the substrates 112 and 114.

Therefore, the USH mode liquid crystal display device basically has an electrode structure of an in-plane switching mode.

3, which is a schematic cross-sectional view for explaining the principle of driving the USH mode liquid crystal 130 of the USH mode liquid crystal display device, the first and second substrates 112 and 114 facing each other, A USH mode liquid crystal layer 130 is interposed between the second substrates 112 and 114 and pixel electrodes 121 and common electrodes 124 arranged alternately on the first substrate 112 are arranged.

In such a USH mode liquid crystal display device, the structure of the electrodes 121 and 124 is a transverse electric field system, and a wide viewing angle can be obtained.

Meanwhile, in the USH mode liquid crystal display device of the present invention, it is necessary to apply a strong electric field of several tens of volts / μm or more to the USH mode liquid crystal layer 130.

That is, the USH mode liquid crystal layer 130 is driven by an electric field generated between the pixel electrode 121 and the common electrode 124. This electric field is applied not only to the horizontal components on the substrates 112 and 114, .

Therefore, in order to obtain the horizontal electric field necessary for driving the USH mode liquid crystal layer 130, a larger electric field must be formed between the pixel electrode 121 and the common electrode 124. [

That is, there is a problem that a high driving voltage is required.

Accordingly, the present invention provides a liquid crystal display device in which a horizontal electric field is maximized in order to solve a rise in a high driving voltage, which will be described in detail with reference to FIG. 4 below.

4 is a cross-sectional view schematically showing a plurality of pixel regions of a liquid crystal display device including a USH mode liquid crystal layer according to an embodiment of the present invention.

As shown in the drawings, the USH mode liquid crystal display 100 of the present invention includes a first substrate 112 as a lower substrate and a second substrate 114 as an upper substrate, (112, 114) are formed by facing each other with the USH mode liquid crystal layer (130) interposed therebetween.

In order to prevent the high driving voltage from rising, the USH mode liquid crystal display 100 according to the present invention includes a first thin film transistor Tr1 formed on a first substrate 112 as a lower substrate, And a second thin film transistor (Tr2) is formed on the second substrate (112).

That is, on the first substrate 112, a plurality of first gate wirings 116, which are arranged parallel and spaced apart from each other by a predetermined distance, and a first common wiring (not shown) arranged parallel to the first gate wirings 116, (Not shown) that intersects the first gate wiring 116 and the first common wiring (not shown), particularly intersects the first gate wiring 116, (Not shown).

At this time, the first thin film transistor Tr1 is formed in the switching region TrA, which is the intersection of the first gate wiring 116 and the first data wiring (not shown) in each pixel region P, The first pixel electrode 121 and the first common electrode 124 are formed in the display area AA.

A plurality of second gate wirings 216 and a plurality of second gate wirings 216 are formed on the inner surface of the second substrate 114 facing the first substrate 112 and spaced apart from each other by a predetermined distance. (Not shown) configured to be parallel with the gate wiring 216 and a second common wiring (not shown) that intersects the second gate wiring 216 and the second common wiring And a second data line (not shown) for defining the pixel region P are formed.

The second thin film transistor Tr2 is formed in the switching region TrA which is the intersection of the second gate wiring 216 and the second data wiring (not shown) of each pixel region P, A second pixel electrode 221 and a second common electrode 224 are formed in the display area AA.

At this time, the second thin film transistor Tr2 is located corresponding to the first thin film transistor Tr1.

The first and second thin film transistors Tr1 and Tr2 are connected to the first and second gate electrodes 111 and 211 and the first and second gate insulating films 113 and 213 and the first and second semiconductor layers The first and second common electrodes 124 and 224 are formed of first and second common wirings (not shown), first and second common wirings 115 and 215, first and second source and drain electrodes 117 and 217, 118 and 218, ).

At this time, the first and second semiconductor layers 115 and 215 are formed of the first and second active layers 115a and 215a of pure amorphous silicon and the first and second ohmic contact layers 115b and 115b of amorphous silicon containing impurities, , And 215b.

The first and second protective layers 119 and 219 are formed on the front surfaces of the first and second substrates 112 and 114 including the first and second thin film transistors Tr1 and Tr2, 1 and the second pixel electrodes 121 and 221 are electrically connected to the first and second drain electrodes 118 and 218 of the first and second thin film transistors Tr1 and Tr2, respectively.

The first and second common electrodes 124 and 224 are formed on one side of the first and second pixel electrodes 121 and 221 of the display area AA at predetermined intervals to form a transverse electric field.

Although the first and second pixel electrodes 121 and 221 and the first and second common electrodes 124 and 224 are not shown in the drawing, a plurality of the first and second pixel electrodes 121 and 221 and the common electrodes 124 and 224 are alternately arranged in a staggered arrangement .

According to such a configuration, the first and second common electrodes 124 and 224 at the positions where the first and second pixel electrodes 121 and 221 at the positions corresponding to each other are at the same potential, An electric field is generated between the equipotential lines connecting the first and second pixel electrodes 121 and 221 and the equipotential lines connecting the first and second common electrodes 124 and 224.

This electric field maximizes the horizontal component parallel to the first and second substrates 112 and 114 and minimizes the vertical component perpendicular to the first and second substrates 112 and 114. That is, the pixel electrodes 121 and 221 alternately arranged on the same plane by the first and second common electrodes 124 and 224 facing the first and second pixel electrodes 121 and 221 facing each other, And the common electrodes 124 and 224 can be repeatedly stacked, so that the horizontal electric field component is maximized.

As a result, a strong horizontal electric field is applied to the USH mode liquid crystal layer 130 interposed between the first and second substrates 112 and 114.

Therefore, by driving the USH mode liquid crystal layer 130 requiring a high driving voltage by a strong horizontal electric field, a contrast ratio, a viewing angle, and a fast response speed can be obtained.

By locating the first and second pixel electrodes 121 and 221 and the first and second common electrodes 124 and 224 so as to correspond to the first and second substrates 112 and 114 facing each other, The driving voltage can be lowered.

At this time, the second pixel electrode 221 formed on the second substrate 114 is positioned to correspond to the first pixel electrode 121 formed on the first substrate 112 and has the same width. The second pixel electrode 221 may have a larger width than the first pixel electrode 121 in consideration of the cohesion margin of the first and second substrates 112 and 114.

The second common electrode 224 may be positioned corresponding to the first common electrode 124 and may have the same width. In addition, the second common electrode 224 may have the same width as that of the second common electrode 224, The width of the common electrode 224 may be formed to have a larger width than the width of the first common electrode 124.

A planarization layer 141 is formed on the second pixel electrode 221 and the second common electrode 224 of the second substrate 114. The second thin film transistor Tr2 and the second thin film transistor Tr2 are formed on the planarization layer 141. [ And a black matrix 143 for blocking light corresponding to the second gate wiring 216 and the second data wiring (not shown).

The second thin film transistor Tr2 and the second gate wiring 216 and the second data wiring (not shown) are connected to the first thin film transistor Tr1 and the first gate wiring 116 The black matrix 143 formed on the second substrate 114 is electrically connected to the first thin film transistor Tr1 and the first gate wiring 116 and the second thin film transistor Tr1, 1 data lines (not shown).

A red, green and blue color filter 145 is formed on the planarization layer 141 in correspondence with each pixel region P and an overcoat 145 is formed on the black matrix 143 and the color filter 145 A layer (not shown) is formed.

In this case, the black matrix 143 and the color filter 145 are formed on the second substrate 114 and the black matrix 143 and the color filter 145 are formed on the second thin film transistor Tr2, And the second thin film transistor Tr2 or the like may be formed on the black matrix 143 and the color filter 145. [

The black matrix 143 and the color filter 145 may be formed on the first substrate 112. The black matrix 143 and the color filter 145 may be formed on the first thin film transistor Tr1 .

The first substrate 112 has a larger area than the second substrate 114. The first substrate 112 has a larger area than the second substrate 114, The edge of the substrate 112 is exposed to the outside, and a pad portion PA for applying a signal voltage to the first and second thin film transistors Tr1 and Tr2 is provided.

The pad portion PA is provided with a gate and a data pad electrode 220 (not shown) connected to the first and second gates and data lines 116 and 216 (not shown).

A seal pattern 230 is formed along the edges of both substrates 112 and 114 to prevent leakage of the USH mode liquid crystal layer 130 in the non-display area NA covering the edge of the display area AA. .

A patterned spacer 250 is formed between the first and second substrates 112 and 114 to maintain a constant cell gap between the two substrates 112 and 114. The patterned spacer 250 of the present invention has conductivity And is electrically connected to the pad portion PA formed on the first substrate 112 in order to apply a signal voltage to the second thin film transistor Tr2 formed on the second substrate 114. [

That is, the USH mode liquid crystal display 100 according to the present invention has the first and second thin film transistors Tr1 and Tr2 connected to the first substrate 112 and the second substrate 114, respectively, A pad portion PA for applying a signal voltage to each of the first and second thin film transistors Tr1 and Tr2 is formed only on the first substrate 112 and the second substrate 114 is formed only on the first substrate 112. [ And the second thin film transistor Tr2 formed on the second conductive layer 250 receives the signal voltage through the conductive patterned spacer 250. [

The conductive patterned spacers 250 are preferably formed in the non-display area NA so as to cover all the four edges of the display area AA. The conductive patterned spacers 250 are formed on the gate and data wirings 116, 216, not shown).

The first and second gate wirings 116 and 216 and the first and second data wirings (not shown) formed on the first substrate 112 and the second substrate 114 are electrically connected to the conductive patterned spacers 250, Respectively.

Accordingly, a signal voltage flowing through the first gate and the data line 116 (not shown) on the first substrate 112 is transmitted to the second gate and the data line 216 (not shown) on the second substrate 114.

The USH mode liquid crystal display 100 according to the present invention can be described in more detail with reference to FIG. 1, in which a signal voltage applied from a pad portion PA provided on a first substrate 112 is applied to a first thin film transistor (Tr1) on the second substrate 114 and the second thin film transistor Tr2 on the second substrate 114 simultaneously.

That is, the on / off states of the first and second thin film transistors Tr1 and Tr2 from the external power source (not shown) to the first gate wiring 116 on the first substrate 112 through the pad portion PA, a signal applied to the first gate wiring 116 is applied to the second gate wiring 216 on the second substrate 114 through the conductive patterned spacers 250. In this case,

When image signals are transmitted to the first and second pixel electrodes 121 and 221 of the selected pixel region P and the first and second data lines (not shown), the first and second pixel electrodes 121 and 122, 221 are equipotential and the first and second common electrodes 124 and 224 are equipotential so that an equal potential line connecting the first and second pixel electrodes 121 and 221 and the first and second common electrodes 124 and 224, An electric field is generated between the equipotential lines connecting the electrodes 224 and 224.

Therefore, the optical axis of the USH mode liquid crystal layer 130 is interrupted by the electric field therebetween, and birefringence is manifested, and various images are displayed due to the change of the light transmittance.

At this time, the electric field is maximized in the horizontal component parallel to the first and second substrates 112 and 114 and the vertical component perpendicular to the first and second substrates 112 and 114 is minimized, A strong horizontal electric field is applied to the USH mode liquid crystal layer 130 interposed between the liquid crystal layer 130 and the USH mode liquid crystal layer 130 interposed therebetween.

Therefore, although the USH mode liquid crystal display 100 of the present invention has the first and second thin film transistors Tr1 and Tr2 formed on the first substrate 112 and the second substrate 114 respectively, The pad portion PA for applying a signal voltage to the second thin film transistors Tr1 and Tr2 is formed only on the first substrate 112 and the second thin film transistor Tr2 formed on the second substrate 114 is formed And receives the signal voltage through the conductive patterned spacers 250.

5a to 5d are schematic views showing various aspects of the conductive patterned spacer according to the embodiment of the present invention.

The conductive patterned spacers 250 electrically connecting the first and second gate wirings 116a and 216a or the first and second data wirings 116b and 216b are formed of a conductive material Or may be formed to include a conductive material such as conductive balls 251 as shown in FIG. 5B.

It is also possible to form the hole 253 penetrating through the conductive patterned spacer 250 and to fill the hole 253 with the conductive material 255 as shown in FIG. , And the conductive patterned spacers 250 may be made of benzocyclobutene (BCB), photo acryl, and photoresist.

Although the conductive patterned spacers 250 are illustrated as being in contact with the first and second substrates 112 and 114, the conductive patterned spacers 250 may be formed on the first and second substrates 112 and 114, It is also possible to form them on any one of the substrates 112 and 114.

Further, as shown in FIG. 5D, the conductive metal film 259 may be coated.

6 is a plan view schematically showing a conductive patterned spacer formed on a substrate.

As shown, a conductive patterned spacer 250 is formed on the gate wiring 116a and / or the data wiring 116b in the non-display area (NA in FIG. 4) of the substrate (112 and 114 in FIG. 5D) Here, the conductive patterned spacer 250 has a plurality of holes 253 formed therein, and the conductive material 255 is filled in the holes 253.

At this time, it is preferable that the conductive patterned spacers 250 formed on the neighboring gate wirings 116a and / or the data wirings 116b are arranged in two rows of staggered shapes because the spacing is very narrow.

Thus, the conductive patterned spacers 250 having a wider area can be formed.

As the area of the conductive patterned spacers 250 is wider, signals can be more stably transmitted to the second thin film transistors (Tr2 in FIG. 4) on the second substrate (114 in FIG. 5D).

FIG. 7 is a graph for explaining the relationship between the driving voltage and the transmittance of the USH mode liquid crystal display device according to the embodiment of the present invention.

As shown in the figure, the USH mode liquid crystal display device B of the present invention is different from the IPS mode liquid crystal display device A including a general USH mode liquid crystal in that the USH mode liquid crystal display device B includes first and second pixels It is confirmed that the driving voltage is lowered by forming the electric field by the electrode and the first and second common electrodes.

8A to 8C are graphs for explaining the response speed of the USH mode liquid crystal display device according to the embodiment of the present invention.

8A is a graph showing a response speed of a general IPS type liquid crystal display device, FIG. 8B is a graph showing a response speed of a general IPS type liquid crystal display device including a USH mode liquid crystal, and FIG. 7 is a graph showing the response speed of the USH mode liquid crystal display device.

Prior to the description, the response speed can be expressed through Ton (on display timer) and Toff (off display timer) values when the luminance falls from 90 to 10.

As shown in the figure, a typical IPS type liquid crystal display device has a response speed of 10.1 ms until the luminance of the display drops from 90 to 10, and the IPS type liquid crystal display device including the USH mode liquid crystal has a response speed of 0.9 ms, The USH mode liquid crystal display of the present invention has a response speed of 0.5 ms.

That is, the USH mode liquid crystal display device of the present invention confirms that the response speed is lowered by forming the electric field by the first and second pixel electrodes and the first and second common electrodes respectively formed on the first and second substrates .

As described above, in the USH mode liquid crystal display device of the present invention, the first pixel electrode and the second common electrode are formed on the first substrate and the second pixel electrode and the second common electrode are formed on the second substrate, The component can be maximized, and the driving voltage of the USH mode liquid crystal can be lowered.

In the USH mode liquid crystal display of the present invention, the signal voltage may be applied to the second substrate through the conductive patterned spacers even if the pad portion is formed only on the first substrate.

Accordingly, it is unnecessary to provide a separate pad portion on the second substrate, thereby improving the process cost and process efficiency.

On the other hand, the liquid crystal layer of the present invention is not limited to the USH mode liquid crystal. Blue phase mode liquid crystal, and in a general IPS mode liquid crystal display device, the driving voltage can be reduced by the structure of the above-described electrode.

Further, the present invention is also applicable to an IPS mode liquid crystal display device capable of forming a horizontal electric field without applying a common wiring and a common electrode to which a constant voltage is applied, that is, the common electrode is eliminated and an electric field is formed through neighboring pixel electrodes.

In such an IPS mode liquid crystal display device, a voltage twice as high as that of a liquid crystal display device including a common electrode can be applied to the liquid crystal layer, and when the structure of the electrode of the present invention is included, the driving voltage can be further reduced.

The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the present invention.

100: USH mode liquid crystal display, 111, 211: first and second gate electrodes
A first and a second semiconductor layers 115a and 215a (first and second active layers, 115b and 215b: first and second ohmic contact layers)
117, 217: first and second source electrodes, 118, 218: first and second drain electrodes
119, 219: first and second protective layers
121, 221: first and second pixel electrodes, 124, 224: first and second common electrodes
112, 114: first and second substrates, 130: USH mode liquid crystal layer
141: planarization layer, 143: black matrix, 145: color filter
220: Gate pad electrode, 230: Seal pattern, 250: Conductive patterned spacer

Claims (13)

A first substrate;
A first switching element located on the first substrate and connected to a first gate wiring and a first data wiring intersecting with each other;
A first pixel electrode located on the first substrate and connected to the first switching device;
A first common electrode disposed on the first substrate and alternately arranged with the first pixel electrode;
A second substrate facing the first substrate;
A second switching element located on the second substrate and connected to a second gate wiring and a second data wiring intersecting with each other;
A second pixel electrode located on the second substrate and connected to the second switching element;
A second common electrode disposed on the second substrate and alternately arranged with the second pixel electrode;
A liquid crystal layer disposed between the first and second substrates;
And first and second conductive pattern spacers located in a non-display area covering the edges of the first and second substrates and electrically connecting the first switching element and the second switching element,
Wherein the first and second conductive patterned spacers electrically connect the first gate wiring and the second gate wiring to the first data wiring and the second data wiring, respectively,
Wherein the first and second conductive patterned spacers are located inside the seal pattern covering the edges of the first substrate and the second substrate,
A third gate wiring is further located adjacent to the first gate wiring, a fourth gate wiring is further located adjacent to the second gate wiring,
A third data line is further located adjacent to the first data line, a fourth data line is further located adjacent to the second data line,
Wherein the first conductive patterned spacer connecting the first and second gate wirings is arranged in a staggered pattern with a third conductive patterned spacer connecting the third and fourth gate wirings,
And the second conductive pattern spacers connecting the first and second data wirings are arranged in a staggered pattern with fourth conductive pattern spacers connecting the third and fourth data wirings.
The method according to claim 1,
Wherein the second pixel electrode is located corresponding to the first pixel electrode, and the second common electrode is located corresponding to the first common electrode.
The method according to claim 1,
And a signal voltage applied from the outside to the first switching element is applied to the second switching element through the first to fourth conductive patterned spacers.
The method of claim 3,
Wherein the same first voltage is applied to the first pixel electrode and the second pixel electrode, and the same second voltage is applied to the first common electrode and the second common electrode.
delete The method according to claim 1,
A first protective layer covering the first data line and the first switching element and a second protective layer covering the second data line and the second switching element,
Wherein the first pixel electrode and the first common electrode are located on the first passivation layer and the second pixel electrode and the second common electrode are located on the second passivation layer.
delete The method according to claim 1,
And the second common electrode is electrically connected to the first common electrode.
The method according to claim 1,
Wherein the first to fourth conductive patterned spacers include conductive balls or are coated with a conductive metal film.
The method according to claim 1,
Wherein the first to fourth conductive patterned spacers include a plurality of holes passing through the first to fourth conductive patterned spacers, and the plurality of holes are filled with a conductive material.
The method according to claim 1,
A black matrix corresponding to the first and second switching elements and positioned on one of the first and second substrates;
And a color filter layer disposed on the black matrix.
The method according to claim 1,
Wherein the second pixel electrode has a width equal to or greater than that of the first pixel electrode, and the second common electrode has a width equal to or greater than the width of the first common electrode.
The method according to claim 1,
Wherein the liquid crystal layer is a USH mode liquid crystal or a blue phase mode liquid crystal.

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