KR101864643B1 - Voltage controlled oscillator - Google Patents

Abstract

A voltage controlled oscillator according to an embodiment of the present invention includes a plurality of sequentially connected delay cells. Each delay cell has a source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage. Wherein the constant delay input stage inputs a first signal output from an output terminal of a previous (m) (where m is 1) cell and the negative delay input terminal is a previous (n), where n is 2 or 3 Th < th > cell. As described above, the voltage-controlled oscillator according to the embodiment of the present invention is configured such that each delay cell additionally includes transistors receiving a negative delay input, instead of using an additional circuit to reduce power noise. Accordingly, jitter caused by power supply noise can be reduced, and power consumption can be reduced.

Description

[0001] VOLTAGE CONTROLLED OSCILLATOR [0002]

The present invention relates to an integrated circuit system, and more particularly, to a voltage controlled oscillator for generating a precise clock.

In a high-speed integrated circuit system, a voltage controlled oscillator is used to generate a precise clock. Jitter is generated by the external noise in the signal output from the voltage controlled oscillator. The jitter is most affected by power supply noise. A variety of voltage controlled oscillators have been proposed to reduce the effects of power supply noise.

For example, the voltage controlled oscillator shown in FIG. 1 uses an additional regulator circuit that stabilizes the power supply voltage to reduce power supply noise. In addition, the voltage controlled oscillator uses a replica load to improve the frequency characteristics of the regulator. This structure is good because the voltage-controlled oscillator uses a stable independent voltage. However, the power consumption by the additional circuit increases, and the area is increased by the stabilization capacitor Cdecap. The voltage controlled oscillator shown in FIG. 1 is described in E. Alon, J. Kim, S. Pamarti, K. Chang, and M. Howowitz, "Replica compensated linear regulators for supply-regulated phase-locked loops, -State Circuits, vol. 41, Feb., 2006.

The voltage-controlled oscillator shown in Fig. 2 uses a power supply noise-canceling circuit. This circuit allows the circuit controlling the current of the current controlled oscillator to remove the additional current component Icomp generated by the power supply noise so that the current ICCO supplied to the current controlled oscillator is constant. This structure uses a feedback cascode to increase the output impedance of the current source. The feedback cascade is difficult to use when the power supply voltage is low, and the operating range is narrow because the parameter values (a, b) for determining the additional current component must be changed according to the control voltage. Also, the power consumption increases due to the additional current component. The voltage controlled oscillator shown in FIG. 1 is described in M. Mansuri, and C.-K. K. Yang, " A low-power adaptive bandwidth PLL and clock buffer with supply-noise compensation. &Quot; IEEE Journal of Solid-State Circuits, vol. 38, Nov., 2003.

The voltage-controlled oscillator shown in Fig. 3 has a delay cell having a source-coupled differential structure and a symmetrical load, and uses a replica-feedback bias generator. Since the output swing width is determined by the load resistance and the bias current irrespective of the power supply voltage, the source-shared differential structure is basically insensitive to the power supply noise. However, the active load using the PMOS is used to widen the operating range of the voltage controlled oscillator, and the influence of the power supply noise can not be completely eliminated due to incomplete characteristics of the pseudo feedback bias. The voltage-controlled oscillator shown in FIG. 3 is a self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL, JG Maneatis, J. Kim, I. McClatchie, J. Maxey, and M. Shankaradas, IEEE Journal of Solid-State Circuits, vol. 38, Nov., 2003. < / RTI >

The voltage-controlled oscillator shown in FIG. 4 is shown under US Pat. No. 7,573,339 B2, issued to the inventor CONG, Youngha on Aug. 11, 2009 under the title "RING OSCILLATOR WITH ULTRA-WIDE FREQUENCY TUNING RANGE". The voltage controlled oscillator includes a delay cell of an inverter structure. Delay cells of the inverter structure are vulnerable to power supply noise because the power supply voltage directly affects the delay time, and there is a restriction that a regulator such as a voltage buffer or a voltage-to-current converter must be used.

US 7573339 B2 (CONG, YOUNGHUA) Aug. 11, 2009.

Embodiments of the present invention propose a voltage-controlled oscillator in which a delay cell has a source-shared differential structure so that power noise characteristics are good as well as power consumption can be reduced.

According to an embodiment of the present invention, the voltage controlled oscillator includes a plurality of delay cells sequentially connected. Each delay cell has a source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage. Wherein the constant delay input stage inputs a first signal output from an output terminal of a previous (m) (where m is 1) cell and the negative delay input terminal is a previous (n), where n is 2 or 3 Th < th > cell.

For example, the source-shared differential structure may include a power supply voltage terminal, a ground terminal, a bias current source connected to the ground terminal, and a first load connected to the power supply voltage terminal and having a load variable according to an applied external control voltage And a load connected to the first load and the bias current source and between the second load and the bias current source, respectively, and in response to the input of the first signal and the second signal, And a pair of switching parts of the first switching part and the second switching part output the corresponding oscillation frequency.

As another example, the source-shared differential structure may include: a bias current source connected to a power supply voltage terminal, a ground terminal, and the power supply voltage terminal; and a first load connected to the ground terminal and having a load varying according to an applied external control voltage And a load pair of a first load and a second load, and a second load connected between the bias current source and the first load and between the bias current source and the second load, respectively, and in response to the input of the first signal and the second signal, And a pair of switching parts of the first switching part and the second switching part output the corresponding oscillation frequency.

As another example, the source-shared differential structure may include a power supply voltage stage, a ground stage, a first load and a second load of a passive element connected to the power supply voltage terminal, and a second load connected to the ground terminal, A bias current source which is switched in accordance with a bias current to provide a bias current and a bias current source which is connected between the first load and the bias current source and between the second load and the bias current source, And a switching unit of the first switching unit and the switching unit of the second switching unit for switching in response to outputting a corresponding oscillation frequency.

As another example, the source-shared differential structure may include a power supply voltage terminal, a ground terminal, a first load and a second load of the active element connected to the power supply voltage terminal, and a ground terminal connected to the ground terminal, A bias current source connected between the first load and the bias current source and between the second load and the bias current source and configured to receive a first signal and a second signal, And a switching unit of the first switching unit and the switching unit of the second switching unit to output a corresponding oscillation frequency.

The voltage controlled oscillator according to embodiments of the present invention is configured in such a manner that each delay cell additionally includes transistors to which a negative delay input is provided, instead of using an additional circuit to reduce power supply noise. Accordingly, jitter caused by power supply noise can be reduced, and power consumption can be reduced. The embodiments of the present invention can reduce the temporal uncertainty of the clock and enhance the stability of the system when applied to digital and analog systems requiring a high-speed clock.

FIGS. 1 to 4 are views showing the configuration of a voltage-controlled oscillator according to the related art.
5 is a diagram illustrating a configuration of a voltage-controlled oscillator according to a first embodiment of the present invention.
6 is a diagram illustrating a configuration of a voltage-controlled oscillator according to a second embodiment of the present invention.
FIG. 7 is a view showing a specific configuration according to the first embodiment of the delay cell shown in FIG.
8 is a view showing a current waveform in the delay cell shown in Fig.
FIGS. 9A and 9B are eye diagrams illustrating power supply noise characteristics of the voltage-controlled oscillator shown in FIG.
FIG. 10 is a view showing a specific configuration according to a second embodiment of the delay cell shown in FIG.
11 is a view showing a specific configuration according to the third embodiment of the delay cell shown in FIG.
12 is a view showing a specific configuration according to the fourth embodiment of the delay cell shown in FIG.

Hereinafter, preferred embodiments of the present invention will be described in order to facilitate the present invention by those skilled in the art.

5 is a diagram illustrating a configuration of a voltage-controlled oscillator according to a first embodiment of the present invention. The voltage controlled oscillator includes a plurality of sequentially connected delay cells 110, 120, ..., 190. Each delay cell has a source-shared differential structure and includes a positive delay input stage (inp +, inp-), a negative delay input stage (inn +, inn-) and an output stage (outn, outp). The constant delay input terminal inp +, inp- receives the first signal output from the output terminal outn, outp of the previous cell m (where m is 1). The negative delay input terminals inn + and inn- input the second signals output from the output terminals outn and outp of the previous cell n (where n is 1). For example, the constant delay input terminal (inp +, inp-) of the delay cell 110 receives a signal output from the output terminal outn, outp of the previous first cell 190, and the negative delay input terminal inn + inn-) inputs a signal output from the output terminal outn, outp of the previous second cell, which is a signal input to the constant delay input terminal (inp +, inp-) of the previous first cell 190. The positive delay input terminals inp + and inp- of the delay cell 120 receive signals output from the output terminals outn and outp of the first cell 110 and the negative delay input terminals inn + and inn- (Outn, outp) of the previous second cell 190, which is a signal input to the constant delay input terminal (inp +, inp-) of the previous first cell 110.

Each of the delay cells 110, 120, ..., 190 of the voltage controlled oscillator receives the power supply voltage VDD, the ground voltage VSS, the external control voltage VCTRL, and the external voltage VB from the outside.

6 is a diagram illustrating a configuration of a voltage-controlled oscillator according to a second embodiment of the present invention. Unlike the first embodiment, each delay cell of the second embodiment inputs a signal output from the output terminals outn and outp of the third cell through the negative delay input terminals inn + and inn-. The voltage controlled oscillator includes a plurality of delay cells 210, 220, 230, ..., 290 sequentially connected. Each delay cell has a source-shared differential structure and includes a positive delay input stage (inp +, inp-), a negative delay input stage (inn +, inn-) and an output stage (outn, outp). The constant delay input terminal inp +, inp- receives the first signal output from the output terminal outn, outp of the previous cell m (where m is 1). The negative delay input terminals inn + and inn- input the second signals output from the output terminals outn and outp of the previous cell (n) (where n is the third one larger than 1). For example, the constant delay input terminal (inp +, inp-) of the delay cell 210 inputs a signal output from the output terminal outn, outp of the first first cell 290, and the negative delay input terminal inn + inn-) inputs a signal output from the output terminal outn, outp of the previous third cell (not shown), which is a signal input to the constant delay input terminal (inp +, inp-) of the previous second cell do. The positive delay input terminals inp + and inp- of the delay cell 220 receive signals output from the output terminals outn and outp of the first cell 210 and the negative delay input terminals inn + and inn- (Outn, outp) of the third cell (not shown) which is a signal inputted to the constant delay input terminal (inp +, inp-) of the previous second cell 290.

Each of the delay cells 210, 220, 230, ... 290 of the voltage-controlled oscillator receives the power supply voltage VDD, the ground voltage VSS, the external control voltage VCTRL, and the external voltage VB from the outside.

In the following, a specific embodiment of the present invention will be described with reference to the first embodiment, but it will be understood that the description can be applied to the second embodiment as well as those skilled in the art.

FIG. 7 is a view showing a specific configuration according to the first embodiment of the delay cell shown in FIG. 5, and FIG. 8 is a view showing a current waveform in the delay cell shown in FIG.

Referring to FIG. 7, the delay cell has a source-shared differential structure. The delay cell includes a power supply voltage stage, a ground stage, a bias current source 10, a load pair, and a switching unit pair. A power supply voltage VDD is applied to the power voltage terminal, and a ground voltage VSS is applied to the ground terminal. The bias current source 10 is connected to the ground terminal. The load pair includes a first load (load 1) 20 and a second load (load 2) 30 connected to the power voltage terminal and having a load variable according to an applied external control voltage VCTRL.

The switching pair includes a first switching unit and a second switching unit. The first switching unit is connected between the first load 20 and the bias current source 10 and is responsive to the input of the first signal and the second signal through the constant delay input terminal (inp +) and the negative delay input terminal inn + And outputs the corresponding oscillation frequency through the output terminal OUTn. The second switching unit is connected between the second load 30 and the bias current source 10, and the first signal and the second signal are inputted through the constant delay input terminal (inp-) and the negative delay input terminal inn-, respectively And outputs the corresponding oscillation frequency through the output port outp.

The first switching unit is connected between the first load 20 and the bias current source 10 and includes a first transistor Q11 for inputting a positive component of the first signal, And a second transistor Q12 for inputting a voltage. The second switching unit is connected between the second load 30 and the bias current source 10 and includes a third transistor Q21 for inputting negative (-) components of the first signal, a negative (-) component And a fourth transistor Q22 for inputting a voltage. The transistors Q11, Q12, Q13 and Q14 are implemented as NMOS transistors.

Each of the delay cells described above has a bias current source 10 controlled by an external voltage VB and includes a load pair 20, 30 for converting a bias current into a voltage. The load pair 20, 30 is a component for controlling the delay time of the delay cell, and receives the external control voltage VCTRL. The resistance value of the load 20, 30 is changed by the voltage of the external control voltage VCTRL.

Referring to FIG. 8, in the conventional delay cell shown in FIG. 3, the current corresponding to the bias current I_SRC_DC flows in accordance with the delay cell output voltage value of the previous stage. Since the delay cell according to the embodiment of the present invention further receives the output of the delay cell before the nth stage in addition to the output of the first stage, the bias current flows as shown in Fig. 5 is based on the assumption that the voltage-controlled delay cells shown in FIG. 5 are configured in four stages. When each delay cell receives the negative delay input two stages before, the current flowing in the input transistor and the bias current . Since the bias current determined by the external voltage VB corresponds to I_SRC_DC but the Vtail voltage is shaken by the input terminal, the current flowing in the actual bias current source has a waveform of I_SRC_AC. The current ratio of the currents I_inp + and I_inp- flowing in the quadrature input transistors Q11 and Q12 and the currents I_inn + and I_inn- flowing in the secondary delay input transistors Q21 and Q22 is determined by the W / L ratio of the two transistors, In the case of FIG. 8, W / L of the quiescent input transistors Q11 and Q12 is larger. Since the voltage control delay cell is composed of four stages and the output of the second stage pre-delay cell is received as the negative delay input, the phase difference between the quadrature input signal and the negative delay input signal becomes 45 degrees. The current also has a phase difference of 45 degrees. Since the two input signals are input with the phase difference, the Vtail voltage is more stable than the conventional delay cell and is insensitive to power supply noise.

An additional reason for the embodiment of the present invention to be insensitive to power supply noise compared to the conventional voltage controlled delay cell is due to the design margin of the delay cell as it receives the negative delay input. The voltage controlled delay cell shall have a wide frequency operating range within the voltage range of the limited control voltage VCTRL. For this, the load of the delay cell must have a wide range of resistance values by the control voltage VCTRL, and the input of the delay cell must have a sufficient gain. This requires a sufficient bias current and a large W / L value at the input stage. However, when the bias current is large, the output impedance of the bias current source becomes low, and the ability to remove the power noise, which is a common noise, becomes low. When the W / L of the input terminal is large, the parasitic capacitance change The jitter on the power supply noise is increased.

However, according to the embodiment of the present invention, since the delay cell receives the negative delay input, the output frequency of the voltage-controlled oscillator is higher under the same condition. This can reduce the bias current, thereby increasing the output impedance of the bias current source, reducing the W / L of the input stage, and reducing the jitter to the power supply noise. Since the bias current can be reduced, the embodiment of the present invention also reduces the power consumption as compared with the conventional structure.

In summary, the delay cell of the voltage controlled oscillator according to the embodiment of the present invention has a source shared differential structure. The source shared differential structure differs from the source shared differential structure shown in FIG. 3 in that two transistor pairs constitute a switching unit, and one transistor receives a negative delay input from the previous nth cell. This structure has the effect of reducing the delay time of the delay cell when the same bias current source is assumed. In other words, the above structure has an effect of reducing the bias current when the delay time of the delay cell is the same, which shows an effect of increasing the output impedance of the via current source, thereby improving the power supply noise characteristic, Power can be reduced.

FIGS. 9A and 9B are eye diagrams illustrating power supply noise characteristics of the voltage-controlled oscillator shown in FIG. In order to observe the characteristics of the voltage-controlled oscillator according to the embodiment of the present invention, the voltage-controlled oscillator is designed to oscillate at 1.6 GHz. Then, in a typical condition, the power- % Of a sinusoidal noise of 70 MHz. As shown in FIG. 9B, it can be seen that the voltage controlled oscillator according to the embodiment of the present invention has reduced jitter as compared with the conventional voltage controlled oscillator shown in FIG. 9A. The voltage controlled oscillator according to the embodiment of the present invention can reduce power noise in various environments (VCTRL, VDD / VSS, transistor process characteristics).

FIG. 10 is a view showing a specific configuration according to a second embodiment of the delay cell shown in FIG. This embodiment corresponds to an embodiment in which the switching unit of the delay cell is implemented by a PMOS transistor. The delay cell has a source shared differential structure. The delay cell includes a power supply voltage stage, a ground stage, a bias current source 10, a load pair, and a switching unit pair. A power supply voltage VDD is applied to the power voltage terminal, and a contact low voltage VSS is applied to the ground terminal. The bias current source 10 is connected to the power supply voltage terminal. The load pair includes a first load 20 and a second load 30 connected to the ground terminal and having a load variable according to an applied external control voltage VCTRL.

The switching pair includes a first switching unit and a second switching unit. The first switching unit is connected between the bias current source 10 and the first load 20 and is responsive to input of the first signal and the second signal through the constant delay input terminal (inp +) and the negative delay input terminal inn + And outputs the corresponding oscillation frequency through the output terminal OUTn. The second switching unit is connected between the bias current source 10 and the second load 30, and the first signal and the second signal are input through the constant delay input terminal (inp-) and the negative delay input terminal inn-, respectively And outputs the corresponding oscillation frequency through the output port outp.

The first switching unit includes a first transistor Q31 connected between the bias current source 10 and the first load 20 and receiving a positive component of the first signal, And a second transistor Q32. The second switching unit is connected between the bias current source 10 and the second load 30, and includes a third transistor Q41 for inputting negative (-) components of the first signal, And a fourth transistor Q42 for inputting a voltage.

11 is a view showing a specific configuration according to the third embodiment of the delay cell shown in FIG. This embodiment corresponds to an embodiment in which the load of the delay cell is implemented as a passive element and the delay time of the delay cell is adjusted using the current of the bias current source. The delay cell has a source shared differential structure. The delay cell includes a power supply voltage terminal, a ground terminal, a bias current source Q70, a load pair, and a switching unit pair. A power supply voltage VDD is applied to the power voltage terminal, and a ground voltage VSS is applied to the ground terminal. The load pair includes a first load 41 and a second load 42 of a passive element connected to the power supply voltage terminal. The passive element may be a resistor. The bias current source Q70 is connected to the ground terminal and is switched in accordance with the applied external control voltage VCTRL to provide a bias current. The bias current source Q70 may be an NMOS transistor.

The switching pair includes a first switching unit and a second switching unit. The first switching unit is connected between the first load 41 and the bias current source Q70, and in response to input of the first signal and the second signal through the constant delay input terminal (inp +) and the negative delay input terminal inn + And outputs the corresponding oscillation frequency through the output terminal OUTn. The second switching unit is connected between the second load 42 and the bias current source Q70, and the first signal and the second signal are inputted through the constant delay input terminal (inp-) and the negative delay input terminal inn-, respectively And outputs the corresponding oscillation frequency through the output port outp.

The first switching unit includes a first transistor Q51 connected between the first load 41 and the bias current source Q70 and configured to receive a positive component of the first signal, And a second transistor Q52 for inputting the second voltage. The second switching unit includes a third transistor Q61 connected between the second load 42 and the bias current source Q70 and receiving a negative component of the first signal, And a fourth transistor Q62 for inputting a voltage. The transistors Q51, Q52, Q61 and Q62 may be NMOS transistors.

12 is a view showing a specific configuration according to the fourth embodiment of the delay cell shown in FIG. This embodiment corresponds to an embodiment in which the load of the delay cell is implemented using an active device and the resistance value of the active device is adjusted to the external control voltage VCTRL to adjust the delay time of the delay cell. The delay cell has a source shared differential structure. The delay cell includes a power supply voltage terminal, a ground terminal, a bias current source Q70, a load pair, and a switching unit pair. A power supply voltage VDD is applied to the power voltage terminal, and a ground voltage VSS is applied to the ground terminal. The load pair includes a first load and a second load of the active element connected to the power supply voltage terminal. The first load includes transistors Q81 and Q82, and the second load includes transistors Q91 and Q92. The bias current source Q70 is connected to the ground terminal and is switched in accordance with an applied external voltage VB. The bias current source Q70 may be an NMOS transistor.

The switching pair includes a first switching unit and a second switching unit. The first switching unit is connected between the first load and the bias current source Q70 and is responsive to the input of the first signal and the second signal through the constant delay input terminal (inp +) and the negative delay input terminal inn + And outputs the oscillation frequency through the output terminal outn. The second switching unit is connected between the second load and the bias current source Q70 and receives a first signal and a second signal through a constant delay input terminal (inp-) and a negative delay input terminal inn-, respectively, And outputs the corresponding oscillation frequency through the output terminal outp.

The first switching unit includes a first transistor Q51 connected between the first load and the bias current source Q70 for inputting a positive component of the first signal, And a second transistor Q52 for input. The second switching unit is connected between the second load and the bias current source Q70 and includes a third transistor Q61 for inputting negative (-) components of the first signal, and a negative (-) component of the second signal And a fourth transistor Q62 for input. The transistors Q51, Q52, Q61 and Q62 may be NMOS transistors.

The first load includes a pair of a fifth transistor Q81 and a sixth transistor Q82 connected between the power supply voltage terminal and the first switching unit and switched according to an external control voltage VCTRL. The second load includes a pair of a seventh transistor Q91 and an eighth transistor Q92 which are connected between the power supply voltage terminal and the second switching unit and switched in accordance with the external control voltage VCTRL. The transistors Q81, Q82, Q91 and Q92 may be PMOS transistors.

As described above, the voltage-controlled oscillator according to the embodiments of the present invention is configured in such a manner that, instead of using additional circuitry to reduce power supply noise, each delay cell additionally includes transistors to which a negative delay input is provided . This input having different phases makes the Vtail node shown in FIG. 7 more stable, and the bias current required to obtain the same frequency with the help of the negative delay input decreases, and as the bias current decreases, As the output impedance of the current source increases, the power supply voltage characteristic is improved. Also, as the bias current required to obtain the same frequency decreases, the power consumption can also be reduced.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. Accordingly, it is to be understood that various modifications may be made by those skilled in the art without departing from the scope of the present invention.

It can be applied to digital and analog systems that require high-speed clocks.

110, 120, 190, 210, 220, 230,
10, Q70: Bias current source
20, 30, 41,
Q11, Q12, Q21, Q22, Q51, Q52, Q61, Q62: NMOS transistors
Q31, Q32, Q41, Q42, Q81, Q82, Q91, Q92: PMOS transistors

Claims (13)

A plurality of delay cells sequentially connected,
For each delay cell,
Source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage,
Wherein the constant delay input terminal receives a first signal output from an output terminal of a previous (m) (where m is 1)
The negative delay input terminal inputs a second signal output from an output terminal of the previous (n) (where n is a number greater than 1)
The source shared differential structure includes:
Power supply voltage stage,
The ground,
A bias current source connected to the ground terminal,
A load pair of a first load and a second load connected to the power supply voltage terminal and varying in accordance with an applied external control voltage,
And a bias current source which is connected between the first load and the bias current source and between the second load and the bias current source and which is switched in response to the input of the first signal and the second signal, 1 < / RTI > switching unit and the second switching unit. 2. The voltage controlled oscillator of claim 1, wherein n is two.
2. The voltage controlled oscillator of claim 1, wherein n is three.
delete [2] The apparatus of claim 1,
A first transistor connected between the first load and the bias current source and configured to receive a positive component of the first signal and a second transistor to receive a positive component of the second signal; and,
Wherein the second switching unit comprises:
A third transistor connected between the second load and the bias current source for inputting a negative component of the first signal and a fourth transistor for receiving a negative component of the second signal; And a voltage controlled oscillator.
A plurality of delay cells sequentially connected,
For each delay cell,
Source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage,
Wherein the constant delay input terminal receives a first signal output from an output terminal of a previous (m) (where m is 1)
The negative delay input terminal inputs a second signal output from an output terminal of the previous (n) (where n is a number greater than 1)
The source shared differential structure includes:
Power supply voltage stage,
The ground,
A bias current source connected to the power supply voltage terminal,
A load pair of a first load and a second load connected to the ground terminal and having a load variable according to an applied external control voltage,
A bias current source connected between the bias current source and the first load, and a bias current source connected between the bias current source and the second load, the first and second signals being switched in response to the input of the first signal and the second signal, 1 < / RTI > switching unit and a second switching unit.
The apparatus of claim 6, wherein the first switching unit comprises:
A first transistor connected between the first load and the bias current source and configured to receive a positive component of the first signal and a second transistor to receive a positive component of the second signal; and,
Wherein the second switching unit comprises:
A third transistor connected between the second load and the bias current source for inputting a negative component of the first signal and a fourth transistor for receiving a negative component of the second signal; And a voltage controlled oscillator. A plurality of delay cells sequentially connected,
For each delay cell,
Source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage,
Wherein the constant delay input terminal receives a first signal output from an output terminal of a previous (m) (where m is 1)
The negative delay input terminal inputs a second signal output from an output terminal of the previous (n) (where n is a number greater than 1)
The source shared differential structure includes:
Power supply voltage stage,
The ground,
A first load and a second load of the passive element connected to the power supply voltage terminal,
A bias current source connected to the ground terminal and switched according to an applied external control voltage to provide a bias current,
And a bias current source which is connected between the first load and the bias current source and between the second load and the bias current source and which is switched in response to the input of the first signal and the second signal, 1 < / RTI > switching unit and a second switching unit.
9. The apparatus of claim 8,
A first transistor connected between the first load and the bias current source and configured to receive a positive component of the first signal and a second transistor to receive a positive component of the second signal; and,
Wherein the second switching unit comprises:
A third transistor connected between the second load and the bias current source for inputting a negative component of the first signal and a fourth transistor for receiving a negative component of the second signal; And a voltage controlled oscillator.
9. The voltage controlled oscillator of claim 8, wherein the passive element is a resistor.
A plurality of delay cells sequentially connected,
For each delay cell,
Source shared differential structure and includes a positive delay input stage and a negative delay input stage and an output stage,
Wherein the constant delay input terminal receives a first signal output from an output terminal of a previous (m) (where m is 1)
The negative delay input terminal inputs a second signal output from an output terminal of the previous (n) (where n is a number greater than 1)
The source shared differential structure includes:
Power supply voltage stage,
The ground,
A first load and a second load of the active element connected to the power supply voltage terminal,
A bias current source connected to the ground terminal and switched according to a first control voltage to provide a bias current,
And a bias current source which is connected between the first load and the bias current source and between the second load and the bias current source and which is switched in response to the input of the first signal and the second signal, 1 < / RTI > switching unit and a second switching unit.
12. The apparatus of claim 11, wherein the first switching unit comprises:
A first transistor connected between the first load and the bias current source and configured to receive a positive component of the first signal and a second transistor to receive a positive component of the second signal; and,
Wherein the second switching unit comprises:
A third transistor connected between the second load and the bias current source for inputting a negative component of the first signal and a fourth transistor for receiving a negative component of the second signal; And a voltage controlled oscillator.
13. The apparatus of claim 12,
A pair of a fifth transistor and a sixth transistor connected between the power supply voltage terminal and the first switching unit and switched according to a second control voltage,
Wherein the second load comprises:
And a pair of seventh and eighth transistors connected between the power supply voltage terminal and the second switching unit and switched according to the second control voltage.

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