KR101857811B1 - Embedded display port interface device and display device including the same - Google Patents

Abstract

An eDP interface device according to the present invention comprises an eDP transmission circuit; eDP receive circuit; And a plurality of link lanes for transmitting data symbols and control symbols having a main stream signal and an additional data packet output from the eDP transmission circuit to the eDP reception circuit; The eDP receiving circuit includes: a main stream attribute processing unit for receiving an MSA (Main Stream Attribute) signal included in the additional data packet and deriving first control information from the MSA signal; A control symbol detection & timing control unit for detecting second control information included in the control symbols; Based on the first and second control information, first information indicating an active pixel period during which an active pixel symbol is received, second information indicating a stuffing period during which an active pixel symbol is not received, A control unit; And generating a main stream unpacked clock which is activated only in the active pixel period and inactive in the stuffing period based on the first and second information, and supplies the main stream unpacked clock to predetermined blocks related to the main stream signal processing And a clock generating unit.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an eDP interface device and a display device including the eDP interface device,

The present invention relates to an eDP (embedded Display Port) interface device and a display device including the same.

As the display device becomes larger in size and higher in resolution, an interface for transmitting a signal between a video source and a display device is required to have high performance, and a new interface is being replaced according to the requirement. TVs are being replaced by Vx1, and IT products such as notebooks are being replaced by DPs (Display Ports). The products to which these new interfaces are applied should be designed to be competitive and designed and implemented accordingly.

Mobile IT products such as notebooks should be designed with all components in mind considering low power consumption because battery life is a key consideration. Therefore, eDP (embedded Display Port), which is applied to high-speed interfaces of mobile IT products such as notebooks, should also be considered for low power design. The eDP interface is a proposed standard for improved high-speed data transmission compared to the existing Low Voltage Differential Signaling (LVDS) interface, and its link speed is 1.67 Gbps / 2.7 Gbps. The eDP interface is divided into an eDP transmission circuit and an eDP reception circuit. The eDP receiving circuit includes an AUX channel receiving unit and a main link receiving unit, and receives video stream data from the eDP transmitting circuit through the main link.

However, due to the structure of the clock supply device that operates the eDP receiving circuit, the conventional eDP interface can distinguish the active period defined as the time for processing the actual data and the stuffing period defined as the idle time without processing the data. There is no control device. In the conventional eDP receiving circuit, a link clock for main stream data processing is divided into a main stream unpacker, a main stream processor, and a first-in first-out (FIFO) unit in all sections without discriminating between an active section and a stuffing section Supply. As a result, unnecessary clock supply power is consumed in the process of the main stream unpacker, the main stream processor, and the FIFO among the blocks for processing the main stream data.

Accordingly, it is an object of the present invention to provide an eDP interface device and a display device including the eDP interface device, which can reduce power consumption by generating a clock for main stream data processing separately from an existing link clock in an eDP reception circuit .

In order to achieve the above object, an eDP interface apparatus according to an embodiment of the present invention includes an eDP transmission circuit; eDP receive circuit; And a plurality of link lanes for transmitting data symbols and control symbols having a main stream signal and an additional data packet output from the eDP transmission circuit to the eDP reception circuit; The eDP receiving circuit includes: a main stream attribute processing unit for receiving an MSA (Main Stream Attribute) signal included in the additional data packet and deriving first control information from the MSA signal; A control symbol detection & timing control unit for detecting second control information included in the control symbols; Based on the first and second control information, first information indicating an active pixel period during which an active pixel symbol is received, second information indicating a stuffing period during which an active pixel symbol is not received, A control unit; And generating a main stream unpacked clock which is activated only in the active pixel period and inactive in the stuffing period based on the first and second information, and supplies the main stream unpacked clock to predetermined blocks related to the main stream signal processing And a clock generating unit.

The first control information includes the number of main link lanes, the number of active pixel symbols per horizontal line, and the total number of symbols per horizontal line.

The second control information includes a horizontal blanking end symbol indicating the end of the horizontal blanking interval, a horizontal blanking start symbol indicating the start of the blanking interval, a filling starting symbol indicating the start of the stuffing period, Ending symbol that indicates the end of the ending symbol.

a plurality of transmission units are arranged between the nth horizontal blanking end symbol and the (n + 1) th horizontal blanking start symbol; Each transmitting unit consists of a stuffing symbol defined by the filling starting symbol and a filling end symbol and the active pixel symbol.

The predetermined blocks include a main stream unpacker for receiving the main stream signal and releasing packing of the main stream signal; A first - in first - out unit; And a main stream processing unit for storing the unpacked main stream signal in the first-in-first-out unit.

A display device according to an embodiment of the present invention includes an eDP transmitting circuit, an eDP receiving circuit, and a plurality of transmitting data symbols and control symbols having main stream signals and additional data packets output from the eDP transmitting circuit to the eDP receiving circuit An eDP interface device having link lanes of; Timing controller; And a system for supplying video data information to the timing controller through the eDP interface device; The eDP receiving circuit includes: a main stream attribute processing unit for receiving an MSA (Main Stream Attribute) signal included in the additional data packet and deriving first control information from the MSA signal; A control symbol detection & timing control unit for detecting second control information included in the control symbols; Based on the first and second control information, first information indicating an active pixel period during which an active pixel symbol is received, second information indicating a stuffing period during which an active pixel symbol is not received, A control unit; And generating a main stream unpacked clock which is activated only in the active pixel period and inactive in the stuffing period based on the first and second information, and supplies the main stream unpacked clock to predetermined blocks related to the main stream signal processing And a clock generating unit.

The eDP interface device and the display device including the eDP interface device according to the present invention generate a main stream unpacked clock separately from a conventional link clock and operate the mainstream unpacked clock only in a section in which an active pixel symbol is received, Processing unit and the FIFO, and does not operate the main stream unpacked clock in the non-active period in which the active pixel symbol is not received (the stuffing period for buffering the difference between the link speed of the main stream signal and the output speed of the pixel data). Accordingly, the present invention eliminates unnecessary power consumption in the stuffing period, which is a problem of the prior art, and can remarkably enhance the product competitiveness of the display device to which the eDP interface device is applied.

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of an eDP interface apparatus according to an embodiment of the present invention; Fig.
2 is a view showing a clock generating device for generating a main stream unpacked clock;
3 is a diagram showing one frame structure of transmission data;
4 is a diagram showing a main stream unpacked clock in comparison with a link clock;
FIG. 5 is a diagram showing an example of the eDP reception circuit of FIG. 1 including the clock generator of FIG. 2, in which the main link receiver of the eDP reception circuit is composed of two lanes.
6 shows waveforms of control signals associated with the operation of an eDP receive circuit;
7 is a view illustrating a display device including an eDP interface device according to an embodiment of the present invention.
Figs. 8 and 9 are diagrams showing examples of configurations of an eDP interface device between a system and a timing controller; Fig.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Like reference numerals throughout the specification denote substantially identical components. In the following description, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear.

FIG. 1 schematically shows an eDP interface apparatus according to an embodiment of the present invention.

1, an eDP interface apparatus according to an embodiment of the present invention includes an eDP transmission circuit TX 10, an eDP reception circuit RX 20, an eDP transmission circuit TX 10, and an eDP reception circuit RX, And a plurality of link lanes 30 connected between the plurality of link lanes 20. Each of the link lanes 30 transmits a plurality of symbols output from the eDP transmission circuit TX 10 to the eDP reception circuit RX 20. The symbols include data symbols and control symbols. The eDP receiving circuit RX 20 includes an AUX channel receiving unit and a main link receiving unit and receives a main stream signal belonging to data symbols from the eDP transmitting circuit TX 10. The data symbol includes a main stream signal and an additional data packet.

The eDP receiving circuit RX 20 generates a link clock and outputs a pixel clock PXLCLK and pixel data PXLDATA and an audio clock ADOCLK and audio data ADODATA from the symbols transmitted through the link lanes 30, ). The eDP receiving circuit (RX, 20) further generates a main stream unpacked clock in addition to the link clock. The main stream unpack clock is used for driving predetermined blocks for main link data (main stream signal) processing. The main clock unpacked clock is generated only in the active pixel period and not in the stuffing period, whereas the link clock is generated in both the active pixel period and the stuffing period. Here, the stuffing period indicates a non-active period for buffering the difference between the link speed of the main stream signal and the output speed of the pixel data.

2 shows a clock generating device for generating a main stream unpacked clock. 3 shows one frame structure of transmission data. 4 shows the main stream unpacked clock in comparison with the link clock.

Referring to FIG. 2, the clock generator includes a main stream additive processing unit 222, a control symbol detection and timing control unit 223, a mainstream unpacked clock control unit 224, and a clock generation unit 225.

The main stream adaptation processing unit 222 receives a main stream attribute (MSA) signal and extracts from the MSA signal the first control information, i.e., the number of main link lanes, the number of active pixel symbols per horizontal line, And derives the number.

The control symbol detection and timing controller 223 generates second control information pertaining to control symbols, that is, a horizontal blank end symbol (HBE), a horizontal blank start symbol (HBS) A Filling Start symbol (FS), and a Filling End symbol (FE) in the form of a tick signal.

As shown in FIG. 3, the main link data in each horizontal line is divided into a horizontal blank interval and an effective display interval. The horizontal blank interval HB is defined by a horizontal blanking end symbol HBE indicating the end of the horizontal blanking interval and a horizontal blanking start symbol HBBS indicating the beginning of the blanking interval. a plurality of transfer units (TUs) are arranged until an n + 1th horizontal blank start symbol (HBS) is received after the reception of the nth horizontal blanking end symbol HBE. Each transmission unit TU consists of an active pixel symbol and a stuffing symbol. The stuffing symbol is defined by a filling start symbol (FS) and a filling end symbol (FE), and filling the extra space of each transmission unit (TU) to compensate for the difference between the link speed of the main stream signal and the output speed of the pixel data It plays a role. The fill starting symbol (FS) indicates the beginning of the stuffing symbol, and the filling end symbol (FE) indicates the end of the stuffing symbol. A plurality of transmission units TU are continuously received for one horizontal period, and another space generated by the number of symbols accommodated by one horizontal line and the number of symbols of the active pixel is not divided by an integer, is zero-padded ). The horizontal blank section HB is filled with attribute data in units of horizontal lines and other dummy symbols or secondary data. The attribute data includes a vertical blank (VB) ID symbol, a pixel clock (PXLCLK), restoration information for restoring the audio clock (ADOCLK), and the like. The remaining space is filled with dummy symbols until after the completion of the horizontal blank (HB) period after the completion of the receipt of the data. It is possible to receive a secondary data packet in this dummy symbol period. The additional data packet includes an audio signal and an MSA (Main Stream Attribute) signal.

The main stream unpack clock control unit 224 controls the number of main link lanes, the number of active pixel symbols per horizontal line, and the total number of symbols per horizontal line, which are input from the main stream adding processing unit 222, Based on the horizontal blank end symbol (HBE), the horizontal blank start symbol (HBS), the filling start symbol (FS), and the filling end symbol (FE) input in the form of a tick signal The second information indicating the stuffing period, and the third information indicating the zero pad period.

The clock generator 225 receives the first information indicating the active pixel period, the second information indicating the stuffing period, and the third information indicating the zero pad period from the main stream unpack clock controller 224, And generates a main stream unpack clock (MSUCLK) based on the information. As shown in Fig. 4, the main stream unpack clock MSUCLK is generated only in the active pixel period T1 of each transfer unit TU and not in the stuffing period T2 of each transfer unit TU. To this end, the clock generator 225 generates a main-stream unpacked clock signal MSUCLK having a first logic in the active pixel period T1 and a second logic opposite to the first logic in the stuffing period T2, And generates the main stream unload clock signal MSUCLK by the main stream unload clock signal MSUCLK.

The clock generating unit 225 also generates the link clock LSCLK as shown in FIG. The link clock LSCLK is generated in both the transmission unit TU and the stuffing period T2 without distinguishing between the active pixel period T1 and the stuffing period T2. To this end, the clock generator 225 can always generate the link clock (LSCLK) enable signal in the first logic in the active pixel period (T1) and the stuffing period (T2).

The clock generating unit 225 supplies the main stream unpack clock (MSUCLK) to predetermined blocks for main link data processing, that is, a main stream unpacker, a main stream processor, and a FIFO. The main stream unpack clock MSUCLK is used as an operation clock of the main stream unpacker, the main stream processor, and the FIFO. The main stream unpacking part removes the control symbols from the main stream signal packed in the front and back by the control symbol and also removes the stuffing period T2 from each transmission unit TU. The main stream processing unit receives the main stream signal corresponding to the actual pixel data size from which the control symbol and the stuffing period T2 are removed from the main stream unpacking unit, and stores the main stream signal in the FIFO.

Conventionally, a link clock LS_CLK of a high frequency is supplied during a period during which the main stream unpacking section and the main stream processing section are not operated (time when the active pixel symbol is not received) in the process of storing the active pixel data in the FIFO, The current consumption at the time of power consumption is generated.

However, according to the present invention, a mainstream unpackaging clock MSUCLK is generated separately from the link clock LS_CLK, and the main stream unpackaging clock MSUCLK is activated only during a period in which the active pixel symbol is received (i.e., T1) A stream unpacker, a main stream processor, and a FIFO. Therefore, an unnecessary power loss period, which is a problem of the conventional art, is eliminated, and unnecessary power consumption other than the active pixel period T1 can be eliminated.

FIG. 5 shows an example of the eDP reception circuit of FIG. 1 including the clock generator of FIG. 2, in which the main link receiver of the eDP reception circuit is composed of two lanes. And Fig. 6 shows waveforms of control signals related to the operation of the eDP receiving circuit.

Referring to FIG. 5, the eDP receiving circuit 20 includes first and second serial-parallel converters 201 and 204, first and second decoders 202 and 205, first and second descramblers 203 and 206, The first and second demultiplexers 208 and 209, the first and second mainstream unpackers 210 and 211, the main stream processor 212, the first FOFO 213, The first and second additional data packet unpacking sections 216 and 217, the additional data packet processing section 218, the second FIFO 219, the audio clock restoring section 220 An audio data processor 221, a mainstream processor 222, a control symbol detection and timing controller 223, a mainstream unpack clock controller 224, and a clock generator 225.

The first and second serial-to-parallel converters 201 and 204 convert a 1-bit serial signal inputted through the first and second lanes 30A and 30B, respectively, into a 10-bit parallel signal. The input speed is 10 times faster than the output speed. Therefore, the serial signal is converted into a parallel signal at a rate of 1/10.

The first and second decoders 202 and 205 convert the parallel 10 bits input from the first and second serial-to-parallel converters 201 and 204 into 8 bits according to the ANSI 8B / 10B standard. At this time, the input speed and the output speed are the same.

The first and second descramblers 203 and 206 are respectively inputted from the first and second decoders 202 and 205 and have a function of restoring a scrambled signal by mixing '1' and '0' . At this time, the input is 8 bits, the output is 8 bits, and the input / output speeds are equal to each other.

The interleyner decoding unit 207 receives the descrambled signals from the first and second descramblers 203 and 206. In order to eliminate transmission interference, transmission signals between the first and second lanes 30A and 30B are transmitted with a time difference of two symbols. This time difference is still maintained in the descrambled signal. The interlaced decoding unit 207 eliminates the time difference between the descrambled signals input from the first and second descramblers 203 and 206 and returns the same to the original phase.

The first and second demultiplexers 208 and 209 separate data of different attributes in the data input from the interleyner decoding unit 207, that is, the main stream signal and the additional data packet.

The first main stream unpacker 210 receives the main stream signal from the first demux 208. This main stream signal is packed in front and back by a control symbol indicating that it is a main stream signal area. In order to release the packed state, the first main stream unpacker 210 performs a function of removing the control symbol. Since the processing speed of the main stream signal is different from the speed of outputting the pixel data (the processing speed of the main stream signal is faster than the display speed of the pixel data), the first main stream unpacker 210 outputs the actual pixel data And removes the inserted stuffing interval to match the main stream processing speed.

The second main stream unpacker 211 receives the main stream signal from the second demux 209 and removes the control symbol to release the packing of the main stream signal. The second main stream unpacker 211 performs a function of removing the inserted stuffing interval to match the main stream processing speed.

The main stream processing unit 212 integrates the signal input from the first main stream unpacker 210 and the signal input from the second main stream unpacker 211 and outputs the combined main stream And stores the signal in the first FIFO 213 for the main stream.

The pixel clock restoring unit 213 receives the restored information MVID and NVID from the main stream processor 222 and outputs the ratio MVID and NVID of the restored information MVID and NVID to the link clock (MVID / NVID) * LSCLK) to the pixel clock (PXLCLK). The link clock LSCLK is input from the clock generator 225.

The pixel data processing unit 215 reads the main stream signal corresponding to the pixel data from the first FIFO 213 at the restored pixel clock (PXLCLK) speed. Then, the read main stream signal is formatted in the manner of RGB, YCbCr, etc., and output as pixel data (PXLDATA).

The first additional data packet unpacking section 216 receives additional data packets from the first demux 208. This additional data packet is packed in front and back by a control symbol indicating that it is an additional data packet. In order to release the packed state, the first additional data packet unpacking section 216 performs a function of removing control symbols.

The second additional data packet unpacking section 217 receives the additional data packet from the second demultiplexer 209 and removes the control symbol to release the packing of the additional data packet.

The additional data packet processing unit 218 integrates the signal input from the first additional data packet unpacking unit 216 and the signal input from the second additional data packet unpacking unit 217. The integrated additional data packet includes an audio signal and an MSA (Main Stream Attribute) signal. The additional data packet processing unit 218 separates the audio signal and the MSA signal from the additional data packet. The additional data packet processing unit 218 stores the additional data packet separated into the audio signal in the second FIFO 219 for the audio signal. Then, the additional data packet separated by the MSA signal is supplied to the main stream adaptation processing unit 222.

The audio clock restoring unit 220 receives restoration information MAUD and NAUD from the mainstream processor 222 and outputs the restored information MAUD and NAUD to the link clock (MAUD / NAUD) * LSCLK) to the audio clock ADOCLK. The link clock LSCLK is input from the clock generator 225.

The audio data processing unit 221 reads the additional data packet corresponding to the audio data from the second FIFO 219 at the restored audio clock (ADOCLK) speed. Then, the read additional data packet is formatted according to the audio signal and output as audio data (ADODATA).

The main stream addit processing unit 222, the control symbol detection and timing control unit 223, the main stream unpack clock control unit 224 and the clock generating unit 225 are the same as those described with reference to FIG. 2 to FIG.

The main stream unpacked clock signal MSUCLK of the present invention is output from the clock generating unit 225. [ The clock generating unit 225 outputs the main stream unpacked clock signal MSUCLK together with the output of the existing link clock signal LSCLK. The added main stream unload clock signal MSUCLK is used as an operation clock for the first and second main stream unpacking sections 210 and 211 and the main stream processing section 212 and as a write clock for the first FIFO 213. As shown in FIG. 6, the main stream unpack clock MSUCLK is enabled only in a period in which the active pixel symbol is received, and is supplied to the corresponding hardware blocks 210, 211, 212, and 213. Therefore, a power loss period which is a problem of the related art is eliminated, and unnecessary power consumption in other than the active pixel period is prevented in advance.

FIG. 7 shows a display device including an eDP interface device according to an embodiment of the present invention.

 Referring to FIG. 7, the display apparatus of the present invention includes a display panel 100, a system 300, a timing controller 200, a data driving circuit 110, and a scan driving circuit 120.

In the display panel 100, the data lines and the scan lines (or gate lines) are crossed. The display panel 100 includes pixels formed in the form of a matrix defined by data lines and scan lines. A TFT (Thin Film Transistor) may be formed at the intersection of the data lines and the scan lines of the display panel 100. The display panel 100 includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP), and an organic electroluminescent A display panel of a flat panel display device such as an electroluminescence device (EL) including an organic light emitting diode (OLED), an electrophoresis display device (Electrophoresis, EPD), or the like. When the display panel 100 is implemented as a display panel of a liquid crystal display element, a backlight unit is required. The backlight unit may be implemented as a direct type backlight unit or an edge type backlight unit.

The system 300 transmits main stream data including video data information to the timing controller 200 through the above-described eDP interface device. The timing controller 200 transmits the restored pixel data through the eDP interface device to the data driving circuit 110 as digital video data. In addition, the timing controller 200 generates timing control signals for controlling the operation timing of the data driving circuit 110 and the scan driving circuit 120 based on the restored pixel clock through the eDP interface device. The interface for data transmission between the timing controller 200 and the data driving circuit 110 may be implemented by a mini LVDS interface, but is not limited thereto. For example, the interface between the timing controller 200 and the data driving circuit 110 is described in Korean Patent Application No. 10-2008-0127458 (2008.12.15) filed by the present applicant, Korean Patent Application No. 10-2008-0127456 (2008.12. 15, Korean Patent Application 10-2008-0127453 (2008.12.15), Korean Patent Application 10-2008-0132466 (2008.12.23), Korean Patent Application 10-2008-0132479 (December 23, 2008), Korean Patent Application 10- Korean Patent Application 10-2010-0046146 (2010.05.17), Korean Patent Application 10-2009-0047672 (2009.05.29), Korean Patent Application 10-2009-0120595 (2009.12.07), 2008-0132493 (2008.12.23) , Korean Patent Application 10-2010-0049739 (May 28, 2010), etc. may be applied.

The data driving circuit 110 latches the digital video data under the control of the timing controller 200. The data driving circuit 110 converts the digital video data into a data voltage and outputs the data voltage to the data lines. The scan driving circuit 120 sequentially supplies scan pulses synchronized with the data voltage to the scan lines under the control of the timing controller 200.

8 and 9 are diagrams showing examples of configurations of the eDP interface device between the system 300 and the timing controller 200. As shown in Fig.

8, the system 300 is mounted on the first PCB 350 in the form of a system-on-chip, and the timing controller 200 and the eDP receiving circuit 20 are mounted on the second PCB 250. A third PCB 450 on which the eDP transmission circuit 10 is mounted is disposed between the first PCB 350 and the second PCB 250. The first PCB 350 and the third PCB 450 are connected to the flexible cable 302 through a connector such as a flexible flat cable (FFC). Data generated from the system 300 of the first PCB 350 may be transmitted to the third PCB 450 via the LVDS interface. The second PCB 250 and the third PCB 450 are connected to the flexible cable 401 through a connector. The eDP transmitting circuit 10 transmits the data received from the system 300 to the second PCB 250 via the eDP interface and the eDP receiving circuit 20 restores the pixel clock and the pixel data to the timing controller 200, Lt; / RTI >

The second PCB 250 and the source PCBs 111 are connected via flexible cables 112. A TCP (Tape Carrier Package) on which the source drive ICs 110a of the data driving circuit are mounted is attached between the source PCBs 111 and the display panel 100. [

9, the eDP transmitting circuit 10 may be embedded in the system 300, and the eDP receiving circuit 20 may be embedded in the timing controller 200. Referring to FIG. The system 300 is mounted on the first PCB 350 and the timing controller 200 is mounted on the second PCB 250. The first PCB 350 and the second PCB 250 are connected to the flexible cable 401 through a connector. Data generated from the system 300 of the first PCB 350 is transmitted to the second PCB 250 via the eDP interface.

As described above, the eDP interface device and the display device including the eDP interface device according to the present invention generate a mainstream unpacked clock separately from the existing link clock, and operate the mainstream unpacked clock only during a period in which the active pixel symbol is received, (The stuffing interval for buffering the difference between the link speed of the main stream signal and the output speed of the pixel data) in which the active pixel symbol is not received (the main stream unpacking clock, the main stream processing unit, and the FIFO) Do not operate. Accordingly, the present invention eliminates unnecessary power consumption in the stuffing period, which is a problem of the prior art, and can remarkably enhance the product competitiveness of the display device to which the eDP interface device is applied.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

10: eDP transmission circuit 20: eDP reception circuit
30: Link Lane 222: Mainstream Submission Processor
223: Control symbol detection & timing control unit 224: Main stream unpack clock control unit
225: clock generator

Claims (10)

eDP transmission circuit;
eDP receive circuit; And
And a plurality of link lanes for transmitting data symbols and control symbols having main stream signals and additional data packets output from the eDP transmission circuit to the eDP reception circuit;
The eDP receiving circuit includes:
A main stream attribute processing unit for receiving an MSA (Main Stream Attribute) signal included in the additional data packet and deriving first control information from the MSA signal;
A control symbol detection & timing control unit for detecting second control information included in the control symbols;
Based on the first and second control information, first information indicating an active pixel period during which an active pixel symbol is received, second information indicating a stuffing period during which an active pixel symbol is not received, A control unit; And
Generating a main stream unpacked clock which is activated only in the active pixel period and inactive in the stuffing period based on the first and second information, and supplies the main stream unpacked clock to predetermined blocks related to the main stream signal processing And a generation unit configured to generate the eDP message. The method according to claim 1,
Wherein the first control information includes a number of main link lanes, a number of active pixel symbols per horizontal line, and a total number of symbols per horizontal line. The method according to claim 1,
Wherein the second control information comprises:
A horizontal blank end symbol indicating the end of the horizontal blank section,
A blank blank start symbol indicating the start of a blank section,
A filling start symbol indicating the start of the stuffing period,
And a filling end symbol indicating an end of the stuffing period. The method of claim 3,
a plurality of transmission units are arranged between the nth horizontal blanking end symbol and the (n + 1) th horizontal blanking start symbol;
Each transmitting unit comprising a stuffing symbol defined by the filling starting symbol and a filling end symbol and the active pixel symbol. The method according to claim 1,
The predetermined blocks include,
A main stream unpacker receiving the main stream signal and releasing packing of the main stream signal;
A first - in first - out unit; And
And a main stream processing unit for storing the packed main stream signal in the first-in-first-out unit. an eDP interface device having an eDP transmission circuit, an eDP reception circuit, and a plurality of link lanes for transmitting control symbols and data symbols having a main data signal and an additional data packet output from the eDP transmission circuit to the eDP reception circuit;
Timing controller; And
And a system for supplying video data information to the timing controller through the eDP interface device;
The eDP receiving circuit includes:
A main stream attribute processing unit for receiving an MSA (Main Stream Attribute) signal included in the additional data packet and deriving first control information from the MSA signal;
A control symbol detection & timing control unit for detecting second control information included in the control symbols;
Based on the first and second control information, first information indicating an active pixel period during which an active pixel symbol is received, second information indicating a stuffing period during which an active pixel symbol is not received, A control unit; And
Generating a main stream unpacked clock which is activated only in the active pixel period and inactive in the stuffing period based on the first and second information, and supplies the main stream unpacked clock to predetermined blocks related to the main stream signal processing And a generation unit for generating a control signal. The method according to claim 6,
Wherein the first control information includes a number of main link lanes, a number of active pixel symbols per horizontal line, and a total number of symbols per horizontal line. The method according to claim 6,
Wherein the second control information comprises:
A horizontal blank end symbol indicating the end of the horizontal blank section,
A blank blank start symbol indicating the start of a blank section,
A filling start symbol indicating the start of the stuffing period,
And a filling end symbol indicating an end of the stuffing period. 9. The method of claim 8,
a plurality of transmission units are arranged between the nth horizontal blanking end symbol and the (n + 1) th horizontal blanking start symbol;
Each transmitting unit comprising a stuffing symbol defined by the filling starting symbol and a filling end symbol and the active pixel symbol. The method according to claim 6,
The predetermined blocks include,
A main stream unpacker receiving the main stream signal and releasing packing of the main stream signal;
A first - in first - out unit; And
And a main stream processing unit for storing the main stream signal from which the packing is released in the first-in-first-out unit.

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