KR101842426B1 - Embedded die package, method of fabricating chip package, multilayer interposer and chip package - Google Patents

Embedded die package, method of fabricating chip package, multilayer interposer and chip package Download PDF

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KR101842426B1
KR101842426B1 KR1020160108039A KR20160108039A KR101842426B1 KR 101842426 B1 KR101842426 B1 KR 101842426B1 KR 1020160108039 A KR1020160108039 A KR 1020160108039A KR 20160108039 A KR20160108039 A KR 20160108039A KR 101842426 B1 KR101842426 B1 KR 101842426B1
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layer
chip
die
package
photoresist
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KR20170026214A (en
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디러 허위츠
후앙 알렉스
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주하이 어드밴스드 칩 캐리어스 앤드 일렉트로닉 서브스트레이트 솔루션즈 테크놀러지즈 컴퍼니 리미티드
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Priority claimed from US14/836,111 external-priority patent/US9589920B2/en
Application filed by 주하이 어드밴스드 칩 캐리어스 앤드 일렉트로닉 서브스트레이트 솔루션즈 테크놀러지즈 컴퍼니 리미티드 filed Critical 주하이 어드밴스드 칩 캐리어스 앤드 일렉트로닉 서브스트레이트 솔루션즈 테크놀러지즈 컴퍼니 리미티드
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/07—Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/08—Structure, shape, material or disposition of the bonding areas after the connecting process of an individual bonding area
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    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/05198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/05298—Fillers
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/1601—Structure
    • H01L2224/16012—Structure relative to the bonding area, e.g. bond pad
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

An integrated die package and method of manufacture comprising a die package having I / O contact pads in a passivation layer, the die contact pad coupled to a first side of the feature layer by an adhesive / barrier layer, Wherein the die, the feature layer, and the filler layer are encapsulated by a dielectric material, the feature layer is disposed along the I / O contact pad and the package edge of the die, A built-in die package is disclosed that includes routing lines each drawn by laser exposure of a photoresist according to a guide of an optical imaging system for proper alignment of the filler.

Description

FIELD OF THE INVENTION [0001] The present invention relates to an embedded die package, a method of manufacturing a chip package, a multilayer interposer, and a chip package.

The present invention relates to electronic chip packaging and a manufacturing method thereof.

Consumer electronics such as computing and communications devices include integrated circuit chips.

A classical way to enable chip bonding to the outside world is to include an IC substrate as part of the chip package. The packaged chip has a connection for coupling to a printed circuit board (PCB) such as a ball grid array (BGA) or a land grid array (LGA) or other substrate to which other components are coupled.

The IC substrate needs to have high flatness to ensure good contact between the PCB and other underlying substrates, and to have stiff and warp resistant properties. Reliability and appropriate electrical performance, thin thickness, rigidity, flatness, good heat dissipation and competitive cost are required, especially for IC substrates, and generally for chip packaging.

A well-established generic type of chip package that is relatively inexpensive and allows the IC circuit to communicate with the outside world is the lead frame. The lead frame uses a metal lead extending out of the housing. Leadframe technology returns to the original DIP chip, but is still widely used in many different packages.

The leadframe serves as the ' skeleton ' of an IC package that provides mechanical support to the die during assembly into the finished product.

It consists of a die paddle to which the die is attached, and a lead that serves as a means for external electrical connection to the outside world. The die is connected to the leads by wire through wire bonding or by tape automation bonding.

When attached to the leadframe by a connecting wire, the die or chip is covered with a plastic protective material known as a molding compound.

Techniques used in the more advanced multilayer substrate fabrication include layers connecting the pads or features embedded in the dielectric material. Vias are provided through the dielectric material to electronically couple the features of the different layers together.

One method of manufacturing such vias is by drilling and filling, where holes are typically drilled through the dielectric using a laser, and a conductive material such as copper fills the holes To create vias.

An alternative approach to fabricating vias is to selectively expose the lamp to a suitable wavelength, such as ultraviolet light, by selectively exposing it to a lamp through a stencil, or by recording a pattern using a laser scribe, And depositing copper or other metal in the pattern generated on the resist. This technique of electroplating a pattern developed with a photo-resist is known as " pattern plating. &Quot; The photo-resist is then removed and the upright via posts are laminated with a dielectric material, preferably a polymer-impregnated glass fiber matte pre-preg for enhanced strength.

During pattern plating, a seed layer is first deposited. A photo-resist layer is then deposited thereon and exposed to produce a pattern that is selectively removed to create a trench that exposes the seed layer. The via posts are created by depositing copper on the trenches of the photo-resist. The remaining photo-resist is then removed, the seed layer is etched away, and again a dielectric material, typically a polymer-impregnated glass fiber mat pre-preg, is laminated on and around it to surround the via post. Various techniques and processes can then be used to thin the dielectric by exposing the tops of the via posts to planarize it and establish a conductive connection to ground or reference planes to build the next metal layer thereon. The next metal conductor layer and the via posts can be deposited thereon by repeating the process to build the desired multi-layer structure.

Alternatively, but in the closely connected technique known below as " panel plating ", a continuous layer of metal or alloy is deposited over the substrate. A photo-resist layer is deposited on top of it, and the pattern is developed in the photoresist. The developed photo-resist is then selectively stripped, selectively exposing the underlying metal, which can be removed by etching. Undeveloped photo-resist protects the underlying metal from being etched away, leaving a pattern of upstanding features and vias. After the undeveloped photo-resist is stripped, a dielectric material, such as a polymer-impregnated glass fiber mat, may be laminated on and around the standing copper feature and / or the via post. In yet another variation, the undeveloped photoresist pattern is stripped off leaving the developed photoresist functioning as a mask.

The via layer created by the pattern plating or panel plating method as described above is typically known as a " via post. &Quot; Feature layers can be fabricated using similar techniques.

One flexible technique for fabricating high density interconnects is to build a patterned or panel plated multilayer structure consisting of features of metal vias or dielectric matrices. The metal used for the vias and features may be copper, and the dielectric may comprise a fiber-reinforced polymer matrix. Generally, for example, a polymer having a high glass transition temperature (T g ) such as polyimide is used. Such an interconnect may be core or coreless and may include a cavity for depositing the components. They may have odd or even layers. A possible technique is described in the prior patents issued to Amitec-Advanced Multilayer Interconnect Technologies Ltd. For example, U.S. Patent No. 7,682,972 to Hurwitz et al., Entitled " Improved multilayer coreless support structure and method of manufacturing the same, " discloses a free electron structure including a via array in a dielectric for use as a precursor in the construction of a good electronic support structure. Describes a method for producing a free standing membrane. The method includes fabricating a film of conductive vias around the dielectric on the sacrificial carrier, separating the sacrificial carrier from the sacrificial carrier to form a free upstanding stack of arrays. An electronic substrate based on a free upright film can be formed by subsequently thinning and planarizing a stacked array that terminates the vias. The above publication is incorporated herein in its entirety.

U.S. Patent No. 7,635,641 to Hurwitz et al., Entitled " Integrated Circuit Support Structure and Fabrication thereof, " describes a method of manufacturing an electronic substrate, the method comprising the steps of: (A) selecting a first base layer; (B) depositing a first etch resistant barrier layer over the first underlying layer; (C) constructing a first half stack by alternating the conductive layer and the insulating layer, the conductive layer being interconnected through the insulating layers by a via; (D) applying a second base layer onto the first half stack; (E) applying a protective coating of a photo-resist to the second base layer; (F) etching and removing the first base layer; (G) removing said protective coating of photo-resist; (H) removing said first etch resistant barrier layer; (I) constructing a second half stack by alternating between a conductive layer and an insulating layer, the conductive layers being interconnected by a via through the insulating layer, and the second half stack comprising: Laying substantially symmetrically to the stack; (J) applying an insulating layer onto the second half stack, the conductive layer and the insulating layer alternating with each other; (K) removing the second base layer; And (L) terminating the substrate by exposing an end of the via on the outer surface of the stack and applying an end to the end. The above publication is incorporated herein by reference in its entirety.

The multilayer board enables high-density connection and is used with a more complex IC chip. This is more expensive than a simple single-layer leadframe, and for many electronic applications, a more economical leadframe is suitable.

Even with a relatively simple chip packaging suitable for a single layer, the leadframe technology is limited. The chip is attached to the lead frame by wire bonding, and the longer the connection wire, the greater the risk of breaking the wire, leading to a breakdown, leading to failure. In addition, the more closely the wires are packaged together, the greater the likelihood of a short circuit.

Via posts in a dielectric material approach are suitable for multi-layer substrates, but are generally too thin for use in a single layer because they understand that torsion and curvature lead to deteriorated contact, instability and short circuit.

U.S. Patent No. 8,866,286 to Hurwitz et al. Entitled " Monolayer Coreless Substrate " describes an electronic chip package comprising at least one chip bonded to a routing layer of an interposer comprised of a routing layer and a via post layer, wherein The via post layer is surrounded by a dielectric material comprising glass fibers in the polymer resin and a chip and a routing layer are embedded in a second layer of dielectric material encapsulating the chip and the routing layer. In this packaging technique, the copper ends of the via posts flush with the dielectric material.

The co-pending application number USSN 14 / 789,165 describes an embedded chip package comprising a die having a die contact pad on the passivation layer, the die contact pad being bonded to the first side of the feature layer by an adhesive / barrier layer, A layer of pillar extends from a second side of the feature layer, and the die, feature layer, and filler layer are encapsulated by a dielectric material.

Further, a method including the following steps for fabricating such a structure is also described.

Obtaining a grid of sockets surrounded by the polymer frame;

Placing a grid of chip sockets on the tape;

Placing the chip face down (flip chip) in the socket of the grid;

- depositing a dielectric material on the die and the grid;

Applying a carrier over the dielectric;

Depositing an adhesion layer comprising at least one of titanium, tantalum, tungsten, chromium and / or nickel on a newly exposed surface followed by a copper seed layer;

Applying a layer of photoresist of the first layer and developing the pattern into the layer of features;

Electroplating copper in a pattern for feature formation;

Peeling the photoresist of the first layer;

Applying a second layer of photoresist patterned in a pattern of via fillers;

Electroplating copper in a pattern for via filler formation;

Peeling the photoresist of the second layer;

Etching and removing the exposed portions of the adhesive layer and the copper seed layer;

Applying a copper barrier, filler and a dielectric barrier layer covering the underside of the chip;

Removing the carrier;

Stacking a thin dielectric layer of black dielectric on the back side of the die array;

Thinning the dielectric to expose the copper filler;

Applying the termainations; And

Dicing the grid into individual packaged chips;

This method is a building step. The routing tracks of the feature layer are stacked over the pads of the embedded chip, and after the routing tracks are stacked, the pads are created as additional layers terminated in a land grid array or ball grid array.

A layered manufacturing method of this packaging method has been previously known, but there is a problem of alignment which increases gain and unit loss. Despite alignment issues, this technique can be used to limit application to relatively simple and large die packaging techniques with low termination to increase gain. If the die arrays are to be processed simultaneously, each die is placed in its socket and after the layers are stacked, the feature layer comprising the routing lines is applied to the entire array. The socket must be larger than the die, i. E. There must be room to place the die. Generally, the manufacturing margin is about 10 microns for the sockets when made by dissolution of the sacrificial copper, and about 5 microns for the die cut from the wafers. The cutting technique may be a laser or a blade, or may have inherent deviations. In addition to the manufacturing tolerances of the die size and the manufacturing tolerances of the socket, it is necessary to allow the die to be picked and placed in the socket. As a result, each socket must be at least 15 microns larger than the die in each direction to ensure that the die is smaller than the socket, and as a result must be 30 microns smaller. This means that the actual placement of the die's I / O connections can be moved over a distance of 30 microns to one edge or the other of the socket. Additionally, each die may rotate slightly relative to the socket.

The die must be individually picked up and placed in a socket, with current technology having tolerances of 50 microns and Pick and Place robots have a limited placement accuracy.

If the chip package array is fabricated by developing a pattern of routing lines in a photoresist using a mask, the routing lines can be aligned with the chip sockets exactly (this alignment can be 10 microns). However, it can not be optimally aligned with the I / O filler of each die that can move about 50 microns. This can adversely affect the reliability, gain and / or unit loss of contact between the die input, the output pad and the routing line.

One way to overcome this limitation is to use this technique as a reliable trajectory with a large chip termination for reliable chip I / O fillers, regardless of whether they are moved or rotated in a socket before being secured by a dielectric pillar. And to use it on a relatively simple chip with fewer outlets. However, as is known from Moore's Law, the industry is struggling to achieve greater complexity, size reduction and increased reliability.

It is necessary to overcome these obstacles in order to package the embedded technology, which is similar to the built-in package technology of USSN 14 / 789,165, inexpensively to reliable and more complex IC chips. Embodiments of the present invention address this issue.

The package is very robust, but can get overheated. In addition, such packages may have drift inductance due to wire bonds and may be expensive to manufacture due to the assembly process and materials required for die attach, wire bonding and molding.

Embodiments of the present invention aim to provide a new chip packaging solution.

The first aspect is an embedded die package comprising a die having I / O contact pads in a passivation layer, wherein the die contact pad is bonded to the first side of the feature layer by an adhesion / barrier layer, Wherein the die, feature layer, and filler layer are encapsulated by a dielectric material, and wherein the feature layer is routed from the second side of the feature layer to the die, Line.

Optionally, the die has a stack of reliable routing lines that are misaligned with acceptable errors beyond the sides and edges of the package and subsequent to stencil exposure of the photoresist.

Optionally, the side of the die is offset at an angle to the side of the package.

Optionally, the pair of sides of the die is shifted from 3 to 8 microns from a symmetrical position relative to a pair of parallel sides of the package.

Optionally, the pair of two sides of the die are each shifted 3 to 8 microns from a position symmetrical about the two pairs of parallel sides of the package.

Typically, the die contact pad comprises aluminum.

Optionally, the passivation layer comprises PI or SiN.

Optionally, the adhesion / barrier layer is selected from the group consisting of Ti / Cu, Ti / W / Cu, Ti / Ta / Cu.

Optionally, the adhesion / barrier layer has a thickness in the range of 0.05 microns to 1 micron.

Typically, the feature layer comprises copper.

Typically, the feature layer has a thickness in the range of 1 micron to 25 microns.

Optionally, the filler layer has a height in the range of 15 microns to 50 microns.

Optionally, the feature layer has a fan-out shape.

Optionally, the feature layer has a fan-in shape.

In some embodiments, the chip and filler are embedded in a different polymer dielectric material.

In some embodiments, the filler layer provides a grid array of pads that serves as a contact for joining the die to a substrate.

Optionally, the substrate is a PCB.

Optionally, the substrate is a package for manufacturing a Package on Package.

In some embodiments, the grid array of pillars extends beyond the dielectric to 10 microns or the same horizontal plane as the dielectric to provide an LGA pad.

Optionally, the grid array of pillars is terminated with a termination selected from the group consisting of Ni / Au, ENIG or ENEIG.

In some embodiments, the grid array of pillars is recessed down to 10 microns below the dielectric, or in the same horizontal plane as the dielectric, to provide a BGA pad.

In some embodiments, the grid array of posts is terminated with Organic Solderability Preservative (OSP).

A second aspect relates to a method of making a novel chip package as described herein:

a. Obtaining a grid of sockets surrounded by the polymer frame;

b. Placing a grid of chip sockets on a tape;

c. Disposing a chip face down (flip chip) on a socket of the grid;

d. Stacking a dielectric material over the die and the grid;

e. Applying a carrier over the dielectric;

f. Removing the tape to expose a contact of the chip;

g. Depositing on the newly exposed surface an adhesive layer comprising at least one of titanium, tantalum, tungsten, chromium and / or nickel, followed by a copper seed layer;

h. Applying a layer of photoresist of the first layer and developing the pattern into a layer of features;

i. Electroplating copper in a pattern for feature formation;

j. Peeling the photoresist of the first layer;

k. Applying a second layer of photoresist patterned in a pattern of via fillers;

l. Electroplating copper in a pattern for via filler formation;

m. Peeling the photoresist of the second layer;

n. Etching and removing the exposed portions of the adhesive layer and the copper seed layer;

o. Applying a copper barrier, a filler, and a dielectric barrier layer covering the underside of the chip;

p. Thinning the polymer to expose the frame;

q. Removing the carrier;

r. Stacking a thin film layer of a black dielectric on the back side of the die array;

p. Thinning the dielectric to expose the copper filler;

t. Applying termainations; And

u. Dicing the grid with individual packaged chips;

.

Typically, an array of chips is placed in each socket.

Optionally, a wafer having an array of chips on its top is located in at least one socket.

Optionally, the copper filler comprises an LGA (Land Grid Array), the following limitations:

A square or rectangular shape;

- an outer surface plated with a final metal plating including electroless nickel / electroless palladium / immersion gold (ENEPIG) or electroless nickel / immersion gold (ENIG) or electrolytic nickel and gold (nickel / gold) termination techniques; And

- optionally protruding from the surrounding dielectric to 10 microns;

 ≪ / RTI >

Optionally, the copper fillers are selected from the group consisting of:

- sinking to 10 microns for the surrounding dielectric;

- having a cylindrical shape with a circular end that is easily wetted by the solder ball; And

- coated with Organic Solder Preservative (OSP);

(Ball grid array) of pads characterized by at least one of the following.

A further aspect is a multilayer interposer for connecting a chip to a circuit, comprising: a routing layer connecting a filler of a peripheral layer aligned with an array of I / O connections of a chip on one side of the routing layer; And a filler arranged in the sub-array.

Typically, the multi-layer interposer includes constraints selected from the following group

The array of terminations is a ball grid array;

The array of terminations is a land grid array;

The routing layer comprises a copper routing line made by electroplating the patterned photoresist selectively exposed by a laser;

.

A further aspect is a chip package for packaging a chip for connection to a circuit comprising: a routing layer for connecting fillers of a peripheral layer aligned with an array of I / O connections of a chip on one side of the routing layer; And fillers arranged in an array of terminations for connection to the circuit.

Typically, the chip package includes the following restrictions:

The array of terminations is a ball grid array;

The array of terminations is a land grid array;

The routing layer comprises a copper routing line made by electroplating the patterned photoresist selectively exposed by a laser;

.

The package is very robust, but can get overheated. In addition, such packages may have drift inductance due to wire bonds and may be expensive to manufacture due to the assembly process and materials required for die attach, wire bonding and molding. This problem can be solved.

BRIEF DESCRIPTION OF THE DRAWINGS For a better understanding of the present invention and to show how the same may be carried into effect effectively, reference is made to the accompanying drawings in purely illustrative manner.
DETAILED DESCRIPTION OF THE DRAWINGS Reference will now be made, by way of example, to the drawings in which: FIG. 1 is a perspective view of a first embodiment of the present invention; FIG. Are presented to provide what is considered to be a description. In this regard, no attempt has been made to show the structural details of the invention in more detail than is necessary for a basic understanding of the invention; The description taken with reference to the drawings will be apparent to those skilled in the art in light of the manner in which the many forms of the invention may be practiced.
BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified cross-sectional view through an electronic chip package according to one embodiment that enables bonding chip packaged on a substrate by a land grid array (LGA);
2 is a simplified cross-sectional view through an electronic chip package according to one embodiment to enable bonding of chips packaged on a substrate by a ball grid array (BGA);
FIG. 3A shows a simplified top view of the embedded chip package 250A viewed from the termination side.
The die 200 is centrally located in the socket 204 of the frame 206 and the routing layer 220 in the feature layer and the termination 230 laminated to subsequent layers thereon are self- Which are correctly aligned with the die 200 and the dielectric filler 208 that couples the die 200 to the walls of the socket 204 may be a transparent polymer.
Figure 3B illustrates a side view of an exemplary embodiment of the present invention in which the die 200 'moves to the side 205 of the IC socket 204 before being secured to the dielectric pillar 208' Is a simplified plan view of the die package 250B seen in FIG. The routing layer 220 of the feature layer and the termination 230 of the die package 250B are stacked thereon by a subsequent layer and the I / O terminal 210 'of the die 200' And the routing line and end filler are electroplated onto the developed pattern in the photoresist layer using a mask to selectively expose the photoresist.
3C is moved relative to the IC socket 204 before the die 200 " is fixed and rotated so that the routing line 220 " of the feature layer and the I / O connection 210 "Lt; RTI ID = 0.0 > 250C < / RTI >
The routing line 220 " and the termination filler 230 are typically fabricated by electroplating the developed pattern by irradiating the photoresist layer with a light source through a photomask to selectively expose the photoresist. The pattern for the terminal chip 220 and the termination pillar 230 are aligned with the array 240 of the sockets 240 and the frame 206 so that the termination 230 is accurately positioned with respect to the edge of the integrated chip package 250, Line 220 " can be accurately and reliably connected to termination 230. However, the die can cause misalignment due to misalignment (movement and rotation) with the socket.
FIG. 4A is a schematic plan view of the embedded chip package 350A viewed from the terminus, and the die 200 'is moved to one side of the socket 240, as shown in FIG. 3B.
A pattern is used to electroplate the routing layer 220 'of the feature layer, optionally followed by a photoresist using a laser, and the termination filler 230 is printed on the socket layer and printed using a mask, The end pillar 230 of the package 350A is correctly aligned to the edge of the package 350A. Unfortunately, however, some routing lines 220 'are not connected to the terminating pillar 230 when the termination 230 is misaligned with the routing line 220' as shown.
4B is a schematic plan view of the embedded chip package 350B viewed at the end and the routing line 220'of the feature layer is a die (not shown) that is moved to one side of the socket 204 as in FIG. 3A or 3B For example, a laser is used to draw the routing line 220 ', aligned with the actual placement of the I / O connections 210' of the routing table 200 '. And the end pillar 230 is also aligned to the routing layer by laser patterning. Routing line 220'or chip 200'for alignment creates a good connection between routing line 220'and connection termination pillar 230 but does not allow termination 230'to the side of chip package 350B. ) And make it difficult or impossible to connect the chip package 350B to the substrate.
4C is a schematic plan view of the embedded chip package 350C seen at the end and the routing line 220 " of the feature layer is moved in the socket 204 and partially rotated (Fig. Quot; 200 ") of the I / O connector 210 ". This is followed by a pattern to create the routing line 220 " and a laser to selectively expose the electroplated photoresist layer . ≪ / RTI > Here, the termination filler 230 is patterned into an optional photoresist layer using a mask aligned with the frame 206 and the array of sockets 204 to create a pattern that is resisted into the sockets 204 and subsequently electroplated If fabricated in a conventional manner by exposure, the resulting embedded chip package 350C will have an end portion 230 that is precisely aligned at the edge of the package 350C. Unfortunately, however, some of the termination pillars 230 are not connected to the routing line 220 " at all, as shown by poorly aligned routing lines 220 " of the feature layer, causing failure.
4D is a schematic plan view of the embedded chip package 350D viewed at the end and the routing line 220 " of the feature layer is moved in the socket 204 and partially rotated (as shown in FIG. 3C) O connection 210 " of the routing line 220 ". This uses a laser to draw the routing line 220 ", and the termination filler 230 likewise uses the Laser Writing Technique And selectively exposing the photoresist using a routing layer 320 for alignment. This may create an embedded chip package 350D having a termination 230 " aligned precisely with the die 200 ", but unfortunately is poorly aligned to the edge of the package 350D, Making it difficult to mount.
5A is a schematic top view of the embedded chip package 450A seen at the end and has a die 200 'moved in the socket 204. FIG. The routing layer 220 " of the feature layer may be laser-marked on the photoresist to selectively expose the photoresist forming the trench for the copper electroplating pattern and may be moved to one side of the socket ) Connection of the actual placement of the I / O connections 110 'of the die 200' and the precise placement of the end pillar 230 to match the socket 204 and the frame 206, It is possible to make a good connection between the secondary filler 230 and whether the termination filler 230 is manufactured by selective photoresist exposure using a mask or a laser writer.
Figure 5B is a schematic top view of the embedded chip package 450B viewed at the end and has a partially rotated die 200 '" in the socket 204, as in Figure 3C. May be aligned at one end to match the actual placement of the I / O connection 210 " and may be aligned at the other end with a mask or laser writer Quot; is aligned to the exact location of the end pillar 230 that is made by exposing the photoresist and is aligned precisely at the edges of the I / O connections and die package 450D of the routing line and die & And provides a good connection between the pillars 230.
Fig. 6 shows a manufacturing process of the electronic chip package structure of Figs. 5A and 5B.
6 (a) through 6 (u) are cross-sectional views of a side view of an intermediate structure according to the steps of the flow chart of FIG. 6
Like reference numbers and designations in the various drawings indicate like elements.
The term micron means 1 x 10 -6 meters and may be denoted by "탆".
Chips and dies belong to the industry as regards unpackaged IC circuits and are used interchangeably, and the term embedded chip package refers to packaged and terminated chips.

In the following description, a support structure consisting of a metal vias in the dielectric matrix, in particular a polyimide, epoxy or bismaleimide / triazine (BT), polyphenylene ether (PPE), polyphenylene oxide (PPO) Copper via posts in a polymer matrix, such as mixtures thereof, are contemplated.

Referring to Figure 1, there is shown a simplified cross-section through an electronic chip package 8 according to one embodiment that allows the chip 10 to be coupled to a substrate by a land grid array (LGA) 20, 22, Are shown.

The electronic chip package 8 consists of a die or chip 10 having an aluminum filler 12 in a passivation layer 14 comprising PI or SiN.

The chip 10 with the aluminum filler 12 in the passivation layer 14 may be a film or a polyimide, epoxy or BT (bismaleimide / triazine), poly And a first dielectric material 16 having a polymer matrix such as phenylene ether (PPE), polyphenylene oxide (PPO), or mixtures thereof.

The pad 18 is joined to the aluminum filler 12.

A layer of copper fillers 20, 22, 24 is fabricated on the opposite side of the pad 18 from where the IC 10 is placed.

In effect, the pads 18 fan out and one or more of these fillers 22, 24 are placed out of the bounds of the IC chip 10, where generally a coarser scale contact is made Is a fan-out configuration that facilitates coupling to a substrate, such as a printed circuit board (PCB).

One or more of these fillers 20 provide electrical connections to the selected filler 12 and in addition to being able to connect such a plurality of fillers 12 together to ground, it also removes heat from the chip 10, The dielectric material 16, 26 is generally a good thermal insulator, i.e., a poor thermal conductor, and the flip chip configuration can cause data corruption or noise It is noted that it may experience overheating.

It will be appreciated that, instead of a fan-out configuration, the technology may provide a pan-in configuration if desired. Additionally, it will also be appreciated that, where the process is a process of a plurality of chips 'on the wafer', rather than a process of an individual chip, prior to segmentation, a fanout configuration is generally impossible.

The pad 18 and the fillers 20,22 and 24 may be encapsulated in a dielectric material 26 which may be another dielectric material different from the dielectric 16 encapsulating the chip 10. A thin film layer of black dielectric 28 may be deposited on top of the die package 8 to aid in laser marking visibility. The black dielectric layer 28 may be provided as a prepreg or polymer film.

The pad 18 and the fillers 20,22 and 24 may be encapsulated in a dielectric material 26 which may be another dielectric material different from the dielectric 16 encapsulating the chip 10. A thin film layer of black dielectric 28 may be deposited on top of the die package 8 to aid in laser marking visibility. The black dielectric layer 28 may be provided as a prepreg or polymer film.

In order to have a land grid array (LGA) and to couple to a substrate, such as a printed circuit board (PCB), the columns 20,22, 24 are generally square or rectangular but nevertheless have other shapes, .

To facilitate attachment to the substrate, the ends of the columns 20, 22, 24 may protrude up to 10 microns out of the dielectric. The exposed ends of the columns 20, 22 and 24 are coated with an electrolyte Ni / Au, commonly known as Electroless Nickel Immersion Gold (ENIG), or in a process known as ENEPIG, Will be coated with the final metal plating 30 on their outer surface of Ni / Pd / Au, which is a layer with palladium on it.

Referring to FIG. 2, an electronic chip package 108 according to one embodiment, which enables bonding of a die or chip 110 to a substrate by a ball grid array (BGA) 120, 122, 124, A second simplified sectional view is shown.

The electronic chip package 108 consists of a die or chip 110 having an aluminum filler 112 in a passivation layer 114 comprising PI or SiN.

The chip 110 having the aluminum filler 112 in the passivation layer 114 may be a film or a polyimide, epoxy or BT (bismaleimide / triazine), poly And a first dielectric material 116 having a polymer matrix, such as phenylene ether (PPE), polyphenylene oxide (PPO), or mixtures thereof.

The pad 118 is coupled to the aluminum filler 112.

A layer of copper filler 120, 122, 124 is fabricated on the opposite side of pad 118 from where IC 110 is placed.

The pad 118 substantially fanned out and one or more of these pillars 122 and 124 are disposed off the boundary of the IC chip 110 where it is typically a PCB with coarser scale contact To facilitate coupling to a substrate such as a < / RTI > One or more of these fillers 120 may provide electrical contact to the selected filler 112 and in addition to being able to couple such a plurality of fillers 112 together to the ground also removes heat from the chip 110, The dielectric material 116, 126 is generally a good thermal insulator, i.e., a poor thermal conductor, and the flip chip configuration can be a superfluous heat that causes data damage or noise, ≪ / RTI >

It will be appreciated that, instead of a fan-out configuration, the technology may provide a pan-in configuration if desired. It will be appreciated that if a plurality of chips are packaged and terminated on the wafer prior to segmentation, then the fanout configuration is generally impossible.

The pad 118 and the fillers 120,122 and 124 may be encapsulated within a dielectric material 126 which may be another dielectric material different from the dielectric material 116 encapsulating the chip 110. [ A thin layer of black dielectric 128 may be deposited on top of the die package 108 to aid in laser marking visibility. The black dielectric layer 128 may be provided as a prepreg or polymer film.

When the solder ball is attached to the end of the column and spreads out therefrom into a hemisphere cap to bond the substrate with a ball grid array (BGA), such as a printed circuit board (PCB), the columns 120, 122, 124 may be cylindrical with a round cross-section to be easily wetted by the solder ball, but the columns 120, 122, 124 may nevertheless have other shapes and may be, for example, elliptical, square or rectangular.

Unlike the projecting ends of the columns 20, 22 and 25 of Figure 1, for BGA, the ends of the columns 120, 122 and 124 generally extend beyond the ends of the columns 120, 122 and 124, And is countersinked with a dielectric 126 that includes a solder ball and which is subsequently applied to complete the package. The ends of the columns 120, 122 and 124 are generally covered with an Organic Solderability Preservative (OSP) 130 to prevent tarnishing of the solder ball prior to application of the ball grid array (BGA) ≪ / RTI >

Both copper posts that function as LGA and BGA pads, respectively, in the packages described in Figures 1 and 2, each have a post structure at least 200 microns wide (or diameter), typically 15 microns to 50 microns thick . For high power die applications in particular, the dimensions of the copper posts may help to reduce the DC resistance to current input or output to the chip, further increasing the functional range of reliability of the chip and the overall package.

Referring to Figures 3A-3C, the arrangement of the die in the socket may vary somewhat. This is due to variations in die size and socket size due to manufacturing limitations. Pick and Place robots have more limitations. As a result, the layout of the die pad can vary by 25 microns from the optimal layout.

Referring to FIG. 3A, a simplified top view of the embedded chip package 250A viewed from the termination side is shown. The dielectric frame 206 may be a fiber reinforced composite having a polymer matrix and the dielectric filler 208 that couples the die 200 to the wall of the socket 204 may be a transparent polymer, The terminal end filler 230 can be laminated. On the other hand, it is generally known that the dielectric material may be a polymer or a fiber-reinforced polymer. The die 200 is centrally located in the socket 204 of the frame 206 and the routing layer 220 in the feature layer and the termination 230 laminated to subsequent layers thereon are self- Which are properly aligned with the die 200. They are in fact aligned with the I / O connections 210 of the die 200.

Because the socket 204 is larger than the die 200, due to the precision of the pick and place robot and the accuracy of the socket 204 fabrication and die 200 segmentation, the die 200 can be configured as a central and die package 250A) is not achieved with a reliable level.

Referring to Figure 3B, the die 200 'moves to the side 205 of the IC socket 204 prior to being secured to the dielectric pillar 208' and is moved and positioned relative to the socket 204 of the frame 206 , A simplified top view of the die package 250B seen at the end.

The routing layer 220 of the feature layer and the terminating portion 230 of the die package 250B are stacked thereon by a subsequent layer and a mask is formed thereon that is aligned with the array of sockets 204 and the frame 260 on the panel processing , The I / O terminal 210 'of the die 200' is poorly connected to the routing line 220 ', resulting in reduced gain and increased loss of the unit. There may be a reliability problem in less severe travel, such as when any routing line 220 'is not completely disconnected from the I / O connection 210' but is poorly connected.

3C, the die 200 " is moved and rotated relative to the IC socket 204 before the fixture layer 220 " is aligned with the routing line 220 " of the feature layer and the I / The routing line 220 " and the termination pillar 230 may optionally be coupled to the photoresist via a photomask to expose the photoresist. ≪ RTI ID = 0.0 > Layer is irradiated with a light source and electroplated on the developed pattern. The pattern for the routing line 220 "and the termination pillar 230 is aligned with the array 240 of the sockets 240 and the frame 206 so that the termination 230 is accurately positioned relative to the edge of the embedded chip package 250C And the routing line 220 " can be accurately and reliably connected to the termination 230. However, some routing lines 220 " can < / RTI > fall off and not be accommodated from the I / O connections 210 " of the die 200 ". This reduces gain and increases the manufacturing loss of the unit. And rotation, the routing line 220 " may be badly connected to the I / O connection 210 " to pass initial inspection and quality control, but may have poor reliability resulting in service failure These problems can be overcome by using large dies with fewer connections, but this is undesirable and limits their application to simple, low-demand applications.

Referring to FIG. 4A, there is shown a schematic top view of the embedded chip package 350A viewed from the terminus, and the die 200 'is moved to one side of the socket 204, as shown in FIG. 3B. However, instead of placing the routing layer 220 'and the frame 206 of the feature layer in alignment with the socket 204 by registering the photomask with the array of sockets 204 and the frame 206, 220 'are aligned to the actual placement of the I / O connections 210' of the die 200 '. This can be achieved by selectively " writing " a pattern of electroplating the routing layer 220 'of the feature layer followed by optional photoresist using a laser to expose the photoresist.

The placement of the termination pillar 230 may be determined by selective exposure of the photoresist using a photomask that registers the socket 204 and the frame 206. This, in turn, ensures that the end pillar 230 of the embedded chip package 350A is correctly aligned with the edge of the package 350A. However, unfortunately, the end portion 230, as shown, And one or more end-piece fillers 230 are not connected to the routing line 220 '. This causes operational errors, which increase the gain and reduce the unit manufacturing losses. In addition, a poor connection can result in poor reliability of the component function test and malfunction in use.

Referring to FIG. 4B, a schematic top view of the embedded chip package 350B is shown at the end, and the routing line 220 'of the feature layer includes a die (not shown) For example, a laser is used to draw the routing line 220 ', aligned with the actual placement of the I / O connections 210' of the routing table 200 '. The termination pillar 230 is also aligned to the routing layer by laser patterning. Routing line 220'or chip 200'for alignment creates a good connection between routing line 220'and connection termination pillar 230 but does not allow termination 230'to the side of chip package 350B. ) And make it difficult or impossible to connect the chip package 350B to the substrate. In other words, decreasing the gain and increasing the unit loss, or even a mountable chip, can adversely affect reliability.

Referring to Figure 4C, a schematic top view of the embedded chip package 350C is shown at the end and the routing line 220 " of the feature layer is moved within the socket 204 and partially rotated Quot; I / O < / RTI > connection 210 " of the die 200 " ≪ / RTI > Here, the termination filler 230 is patterned into an optional photoresist layer using a mask aligned with the frame 206 and the array of sockets 204 to create a pattern that is resisted into the sockets 204 and subsequently electroplated If fabricated in a conventional manner by exposure, the resulting embedded chip package 350C will have an end portion 230 that is precisely aligned at the edge of the package 350C. Unfortunately, however, some of the termination pillars 230 are not connected to the routing line 220 " at all, as shown by poorly aligned routing lines 220 " of the feature layer, causing failure. Thus, the I / O connection 210 " of the package 350C is reliably connected to the routing layer 220 " of the feature layer, but can be poorly connected to the termination 230 pillar, Loss and / or reliability may be deteriorated.

Referring to Figure 4D, a schematic top view of the embedded chip package 350D is shown at the end, and the routing line 220 " of the feature layer is moved within the socket 204, as in Figure 3C, Quot ;, and is aligned to the actual placement of the I / O connections 210 " of the die 200 ". This uses a laser to draw the routing line 220 ", and the end- By exposing the photoresist selectively using a routing layer 320 for alignment by a Laser Writing Technique as shown in Figure 2. This is accomplished by using an integrated chip package (not shown) having a terminating portion 230 " 350D, but unfortunately it is poorly aligned to the edge of package 350D, making it difficult to subsequently mount the package on a substrate such as a PCB.

There is overall movement to reduce more complexity and size, allowing more circuits to be packaged on each chip, and integrated circuits have been consistently smaller feature sizes for more than a few years. Increased capacity per unit area can be used to reduce costs or extend functionality. An empirical rule known as Moore's Law states that the number of transistors in an integrated circuit doubles every two years. In general, as the feature size decreases, almost everything is improved, with lower cost per unit and switching power consumption, and higher speed. Both high gain and reliability are very important.

Until now, the only way to overcome the alignment and reliability problems of the above-mentioned embedded chip package is to connect very few relatively large I / O connections in the chip to a relatively small number of relatively large terminations in the package And to make such an embedded chip package unsuitable for applications with smaller chips and higher junction densities.

In particular, the placement of routing lines and fillers needs to be adjusted to within 12.5 microns, but the pick and place robot has a 25 micron limit when optimized.

Referring to Fig. 5A, there is shown a schematic top view of the embedded chip package 450A at the end and has a die 200 'moved in the socket 204. Fig. The routing layer 220 " of the feature layer may be laser-marked on the photoresist to selectively expose the photoresist forming the trench for the copper electroplating pattern and may be moved to one side of the socket ) Connection of the actual placement of the I / O connections 110 'of the die 200' and the precise placement of the end pillar 230 to match the socket 204 and the frame 206, It is possible to make a good connection between the secondary filler 230 and whether the termination filler 230 is manufactured by selective photoresist exposure using a mask or a laser writer.

Referring to Figure 5B, there is shown a schematic top view of the embedded chip package 450B at the end and has a partially rotated die 200 '" in the socket 204, as in Figure 3C. 5B may be aligned at one end so that the routing line 220 '' of the feature layer corresponds to the actual placement of the I / O connection 210 '', followed by a mask or laser writer at the other end, To the exact location of the end pillar 230 that is made by selectively exposing the photoresist using the photolithography technique and the I / O connection of the routing line and die 200 " and the edge of the die package 450D. And provide a good connection between terminated pillars 230 that are precisely aligned.

Thus connecting the actual placement of the ends of the die 200 ', 200 " by the laser drawing the feature lines 220', 220 " and the preferred placement of the end package 230 of the die package, And reliability are increased and the chip having the high-density termination is reliably packaged.

As shown in Figures 3A-D, 4A-B, 5A-B, the end pillar may be cylindrical with rounded ends and preferably subsequently attached to the substrate using a ball grid array (BGA). Alternatively, however, the termination filler may have a square or rectangular profile and a square / rectangular end and may preferably be laminated to the substrate using, for example, a land grid array (LGA).

Referring to Figures 6 and 6 (a) -6 (u), the manufacturing process of the structure of Figures 5A and 5B is shown.

6 (a) to 6 (u), there is shown a schematic cross-sectional view of a socket 6 array and a chip 10 in the polymer frame 4, in terms of embedding and connection. The method of manufacturing the structures of FIGS. 1 and 2 will be described in detail below.

A first grid of sockets 6 surrounded by a polymer frame 4 is provided (step 5c). Figure 6 (a) shows a couple of adjacent sockets. In practice, a large two-dimensional array of sockets can be handled together. Also, in a deformation process, a single socket can have a chip grid on it that can be subsequently split Can be used to process wafers having a wafers.

The frame 6 may be composed of a polymer coated as a polymer film, or may be a glass fiber-reinforced polymer applied as a prepreg. It can have one or more layers. The thickness through socket 4 may be perforated or the frame 6 may be manufactured on a sacrificial copper foil which is subsequently melted to provide a through-thickness socket 4. [

The panel of Zhuhai Access may be 21 "X 25", and the packaged chip may be 5 mm X 5 mm. Thus, this fabrication technique is capable of packaging 10,000 chips in each panel.

However, it will be appreciated that not all blocks of the panel need to have chip sockets of the same size. In addition, not only can one or more blocks be used for sockets of different sizes to accommodate chips of different sizes, but any sub-array of any size may be used to manufacture a particular die package, , It is also possible that a small number of die packages are manufactured to handle different die packages at the same time for a particular customer, or it is possible for different packages to be manufactured for different customers. Thus, the panel has a socket having a first area with a socket having a first set of dimensions for receiving at least a first type of chip, and a second set size for receiving a second type of chip And a second area. The array of chips on the wafer can be placed in a socket that fits the wafer size in such a panel, and the chip can subsequently be packaged before the wafer is divided.

As shown in FIG. 6 (a), each chip socket 4 is surrounded by a polymer frame 6. The grid of chip sockets 4 is placed on the tape 30 - step 6 (b) (Fig. 6 (b)). The chip 10 is mounted in the socket frame 4 of the frame 6 in a face down manner so that the aluminum contacts 12 (see Figs. 1 and 2) of the passivation layer 14 contact the tape 30 ) - step 6c (Fig. 6 (c)).

6 (d) (Fig. 6 (d)) the dielectric material 16, typically a polymer film or a fiber within the polymer pre-preg, is laminated onto the die 10 and the grid 6. Fig.

The carrier 32 is now applied over the dielectric 16 - step 6 (e) (FIG. 6 (e)). The tape 30 is now removed-step 6 (f) (FIG. 6 (f)) to expose the chip contact 12. (G) (Fig. 6 (g)) is deposited on the newly exposed surface, followed by a copper seed layer, the adhesion layer 34 comprising at least one of titanium, tantalum, tungsten, chromium and / ). Physical vapor deposition (PVD) is typically used. The choice of the adhesive metal 34 follows the polymer 6 and the passivation layer 14. Typical combinations for the adhesive layer 34 are Ti / Cu, Ti / W / Cu, Ti / Ta / Cu and Cr / Cu with a thickness of 0.05 microns to 1 micron.

The photoresist 36 layer is applied and patterned to form a layer of features. However, instead of patterning the entire array with a stencil using a chip socket for alignment, the actual placement and alignment of each chip with respect to the socket may be imaged prior to image processing through the photoresist or stacking of the photoresist, It is determined using reference points that can be discriminated later. Patterning of the feature layer then uses a laser and draws each routing line to connect with the actual placement of the I / O connections of the chip and the desired placement of the package termination for the frame. Step 6 (h) (FIG. 6 (h) ). The copper is then electroplated into the pattern to form a layer of features 18 - step 6 (i) (FIG. 6 (i)). Typically, the features 18 have a thickness ranging from 1 micron to 25 microns. The features 18 may fan out from the die or may be fan inward. Some features may be fan outward, and some may extend inward. When processing a chip array on a wafer, a fan-out configuration is generally not possible.

6 (k) (FIG. 6 (k)), the photoresist 36 is stripped and the second layer of photoresist 38 is applied and patterned with a via filler - step 6 (j) )). Here, the patterning can be obtained again using a laser for writing a pattern, but a photomask can be used so that the filler placement is determined along the grid of the frame 6. [ The process using a photomask is generally more economical than Laser Writing for an array of individual pillars 20 in a fixed arrangement relative to the grid of the frame 6.

Copper is electroplated in a pattern to form the via filler layers 20, 22, 24 - step 6 (1) (FIG. 6 (l)). Typically, the via filler 20 is in the range of 15 microns to 50 microns in length.

The second layer of photoresist 38 is then stripped-step 6 (m) (FIG. 6 (m)) and then the sputtered adhesive layer with one or more copper seed layers of Ti, Ta, Ni, Cr, 34) are etched away and removed - step 6 (n).

The dielectric barrier layer 26 is then applied to cover the bottoms of the copper features 18 and fillers 20,22 and 24 and the chip 10-step 6 (o) (Fig. 6 (o)).

Next, the carrier 32 is removed. Generally, the carrier is copper and is simply etched away. It may be a two-layer copper carrier comprising a thin layer that is releasably adhered to the thick layer in the event of the thick layer being stripped off and the thinner layer being etched to remove - step 6 (p) (p)).

To expose the frame, the polymer may be thinned by grinding, grinding or chemical mechanical polishing (CMP) - step 6 (q).

In this step, a thin film layer of black dielectric 28 (film or pre-preg) may be deposited on the back side of the array of die 10 and frame 6 - step 6 (r) ).

A photoresist or other polymer dielectric 26 is thinned to expose the copper fillers 20, 22, 24 - step 6 (s) (FIG. 6 (s)).

6 (t) (Fig. 6 (t)), the array is divided into individual packaged chips 8 (dicing) - step 6 (u) (u).

As shown in Fig. 6 (u) and Fig. 1, the copper pillar 20, 22, 24 includes a grid array of pads functioning as contacts in the form of a land grid array (LGA) 26), or it may flush (Fig. 6 (u)) with the top surface of the copper filler (20, 22, 24), which can protrude up to about 10 microns As the final metal plating on their outer surfaces including electroless nickel / electroless palladium / immersion gold (ENEPIG) or electroless nickel / immersion gold (ENIG) or electrolytic nickel and gold (nickel / gold) Plated. In the land grid array structure, the pillars 20, 22, 24 may be square or rectangular.

Thus, a method of manufacturing the structure of FIG. 1 is shown. Characteristically, the chip package may comprise two or three different dielectrics, the frame 6, the filler 16 being the same or a different polymer or a fiber-reinforced polymer, and the dielectric surrounding the filler 26 Becomes a third dielectric.

As a result of the method of Figure 3, it will be appreciated that the structure shown in Figure 6 (u) can be modified to include a grid array of pads that serve as contacts in the form of a ball grid array (BGA) . 2, the outer surface of the copper filler 120, 122, 124 may be flush with the surrounding dielectric 126 or may extend from the surface of the surrounding dielectric 126, It can sink to 10 microns. BGA fillers are typically cylindrical with rounded ends for ease of wetting by solder balls.

When constructed as a ball grid array, the ends of the pillars are typically coated with OSP 130 (organic solder preservative).

Thus, by computer imaging and laser writing of photoresists, the described embedded chip package modification process is optimized for high-end applications.

In addition, sequential time loss in the highly automated laser writing stage is largely compensated by reduced quality control requirements.

Fundamentally, after applying the photoresist layer, each and every chip is imaged in a socket via a photoresist, or before each photoresist is applied using a registration marker to draw a routing line starting at the correct position with the laser, Are mapped. To overcome the variation in chip size, the actual placement of each I / O connection is mapped to the reference point and frame of the socket array, and the optimal starting and ending points of each routing trajectory in the feature layer are determined, . In other words, stencil patterning of the photoresist using a mask that allows all traces simultaneously patterned is sacrificed to draw each individual routing line individually. One end of the routing line is precisely positioned and centered at the actual I / O end of the chip, and the routing line is drawn away from the other routing line. Instead of blindly copying the routing lines of a standard solution, however, we assume the optimal alignment between the chip and the socket, simply move the routing lines so that all routing lines on all the die in the array look the same, The correct alignment of the end of the routing layer is determined according to the socket frame and the routing lines are drawn in this arrangement for stacking of the following terminations. In this way, the reliability of a product of a state-of-the-art embedded chip package is maximized in a chip with a high connection density and the gain is maximized. The termination can be patterned using a mask or a laser on the subsequent photoresist layer.

Although described herein with respect to the fabrication of a very simple built-in chip package that has previously been disclosed in USSN 14 / 789,165, the laser writing can be performed in a reliable manner at one layer lower than the optimal placement, It will be understood that the present invention can be used to pattern routing lines that can connect the elements together. As such, the process steps and structures described herein can be modified for more complex processes, such as multi-layer chip packaging solutions.

Laser writing to the routing layer can be used to address the chip misalignment problem with the package, which allows for proper alignment of the termination to the edges and sides of the chip package in the embedded package.

Those skilled in the art will appreciate that the invention is not limited to the details shown and described above. Rather, the scope of the present invention is defined by the appended claims, and includes all variations and modifications of the various features described above as well as modifications and variations that come to mind to those skilled in the art upon reading the foregoing description.

In the claims, the words " comprise " and variations thereof, such as " comprises " and " comprising ", include the listed elements and generally do not exclude other elements.

Claims (31)

An integrated die package comprising a die having I / O contact pads in a passivation layer,
The die contact pad is bonded to the first side of the feature layer by an adhesion / barrier layer, a layer of pillar extends from a second side of the feature layer, and the die, feature layer, , ≪ / RTI >
The feature layer comprising a respective routing line for alignment of an I / O contact pad and a filler of the die,
Wherein the die is misaligned with an acceptable error relative to the side and edges of the package and has a stack of reliable routing lines followed by stencil exposure of the photoresist,
Wherein the routing line is configured to image the die in a socket after lamination of the photoresist, or to map the actual arrangement and alignment of the die using registration markers prior to stacking the photoresist, Wherein the routing lines are drawn independently of each other using the first and second routing lines. delete The method according to claim 1,
Wherein a side of the die is offset at an angle to a side of the package. The method according to claim 1,
Wherein the pair of sides of the die are shifted from 3 to 8 microns from symmetrical positions relative to a pair of parallel sides of the package. The method according to claim 1,
Wherein a pair of the two sides of the die are each shifted 3 to 8 microns from a position symmetric about the two pairs of parallel sides of the package. The method according to claim 1,
Wherein the die contact pad comprises aluminum. The method according to claim 6,
Wherein the passivation layer comprises < RTI ID = 0.0 > PI < / RTI > or SiN. The method according to claim 1,
Wherein the adhesion / barrier layer is selected from the group consisting of Ti / Cu, Ti / W / Cu, Ti / Ta / Cu, Cr / Cu. 9. The method of claim 8,
Wherein the adhesive / barrier layer has a thickness in the range of 0.05 microns to 1 micron. The method according to claim 1,
Wherein the feature layer comprises copper. 11. The method of claim 10,
Wherein the feature layer has a thickness ranging from 1 micron to 25 microns. 11. The method of claim 10,
Wherein the filler layer has a height in the range of 15 microns to 50 microns. The method according to claim 1,
Wherein the feature layer has a fan-out shape. The method according to claim 1,
Wherein the feature layer has a fan-in shape. The method according to claim 1,
Wherein the die and the filler layer are embedded in a different polymer dielectric material. The method according to claim 1,
Wherein the filler layer comprises a grid array of fillers that serve as contacts for joining the die to the substrate. 17. The method of claim 16,
Wherein the substrate is a PCB. 17. The method of claim 16,
Wherein the substrate is a package for manufacturing a Package on Package. 17. The method of claim 16,
Wherein the grid array of fillers extends out of the dielectric to up to 10 microns or to provide an LGA pad in the same horizontal plane as the dielectric. 20. The method of claim 19,
Wherein the grid array of fillers is terminated to an end selected from the group consisting of an electrolyte Ni / Au, ENIG or ENEIG. 17. The method of claim 16,
Wherein the grid array of fillers is recessed down to 10 microns below the dielectric or in the same horizontal plane as the dielectric to provide a BGA pad. 22. The method of claim 21,
Wherein the grid array of fillers is terminated with an organic solderability preservative (OSP). The present invention relates to a method of manufacturing a novel chip package,
a. Obtaining a grid of sockets surrounded by the polymer frame;
b. Placing a grid of the socket on a tape;
c. Disposing a chip face down (flip chip) on a socket of the grid;
d. Stacking a dielectric material over the chip and the grid;
e. Applying a carrier over the dielectric;
f. Removing the tape to expose a contact of the chip;
g. Depositing on the newly exposed surface an adhesive layer comprising at least one of titanium, tantalum, tungsten, chromium and nickel followed by a copper seed layer;
h. Applying a layer of photoresist of the first layer and developing the pattern into a layer of features;
i. Electroplating copper in a pattern for feature formation;
j. Peeling the photoresist of the first layer;
k. Applying a second layer of photoresist patterned in a pattern of via fillers;
l. Electroplating copper in a pattern for via filler formation;
m. Peeling the photoresist of the second layer;
n. Etching and removing the exposed portions of the adhesive layer and the copper seed layer;
o. Applying a copper barrier, a filler, and a dielectric barrier layer covering the underside of the chip;
p. Thinning the polymer to expose the frame;
q. Removing the carrier;
r. Stacking a thin film layer of a black dielectric on the back side of the die array;
p. Thinning the dielectric to expose the filler;
t. Applying termainations; And
u. Dicing the grid with individual packaged chips;
≪ / RTI > 24. The method of claim 23,
Wherein an array of chips is located within each socket. 24. The method of claim 23,
Wherein a wafer having an array of chips on its top is positioned within each socket. 24. The method of claim 23,
The filler includes an LGA (Land Grid Array) and has the following limitations:
A square or rectangular shape;
- an outer surface plated with a final metal plating including electroless nickel / electroless palladium / immersion gold (ENEPIG) or electroless nickel / immersion gold (ENIG) or electrolytic nickel and gold (nickel / gold) termination techniques; And
- optionally protruding from the surrounding dielectric to 10 microns;
≪ / RTI > characterized in that it is characterized by at least one of the following. 24. The method of claim 23,
The fillers may be selected from the following:
- sinking to 10 microns for the surrounding dielectric;
- having a cylindrical shape with a circular end that is easily wetted by the solder ball; And
- coated with Organic Solderability Preservative (OSP);
(Ball grid array) of pads characterized by at least one of the following: < RTI ID = 0.0 > a < / RTI > A multi-layer interposer for connecting a chip to a circuit,
A routing layer connecting the filler of the surrounding layer to be aligned with the array of I / O connections of the chip on one side of the routing layer; And
A filler aligned in the end array for connection to the circuit,
Wherein the chip is misaligned with an acceptable error in the multilayer interposer and has a subsequent reliable routing layer by stencil exposure of the photoresist,
Wherein the routing layer is configured to image the chip in a socket after the photoresist is laminated or to map the actual placement and alignment of the chip by using a registration marker before lamination of the photoresist, Wherein the routing lines are drawn independently of each other. 29. The method of claim 28,
Limitations selected from the following group
The array of terminations is a ball grid array;
The array of terminations is a land grid array;
The routing layer comprises a copper routing line made by electroplating the patterned photoresist selectively exposed by a laser;
Lt; RTI ID = 0.0 > interposer. ≪ / RTI > A chip package for packaging a chip for connection to a circuit,
A routing layer connecting the fillers of the peripheral layer aligned with the array of I / O connections of the chip on one side of the routing layer; And
And fillers arranged in an array of terminations for connection to the circuit,
Wherein the chip is misaligned beyond acceptable tolerances in the chip package and has a subsequent reliable routing layer by stencil exposure of the photoresist,
Wherein the routing layer is configured to image a chip in a socket after the photoresist is laminated or to map the actual arrangement and alignment of the chip by using a registration marker before lamination of the photoresist, And the routing lines are drawn independently of each other. 31. The method of claim 30,
Limitations selected from the following group
The array of terminations is a ball grid array;
The array of terminations is a land grid array;
The routing layer comprises a copper routing line made by electroplating the patterned photoresist selectively exposed by a laser;
The chip package further comprising:
KR1020160108039A 2015-08-26 2016-08-25 Embedded die package, method of fabricating chip package, multilayer interposer and chip package KR101842426B1 (en)

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Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2014096547A (en) * 2012-11-12 2014-05-22 Ps4 Luxco S A R L Semiconductor device and method of manufacturing the same
CN104332414A (en) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 Embedded chip manufacture method

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
JP2014096547A (en) * 2012-11-12 2014-05-22 Ps4 Luxco S A R L Semiconductor device and method of manufacturing the same
CN104332414A (en) * 2014-04-09 2015-02-04 珠海越亚封装基板技术股份有限公司 Embedded chip manufacture method

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