KR101820703B1 - Thin film transistor, method for manufacturing the same, and display device including the same - Google Patents

Abstract

The present invention relates to a thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a manufacturing method thereof, and a display device including the same. The thin film transistor according to an embodiment of the present invention includes a first gate electrode arranged on a substrate, a first gate insulating film covering the first gate electrode, a semiconductor layer arranged on the first gate insulating film, a second gate insulating film covering the semiconductor layer, and a second gate electrode arranged on the second gate insulating film. A part of the semiconductor layer overlaps the first gate electrode, and another part of the semiconductor layer overlaps the second gate electrodes. The semiconductor layer includes the N-type semiconductor layer and the P-type semiconductor layer. Accordingly, the present invention can obtain an N-type semiconductor characteristic and a P-type semiconductor characteristic and reduce a size of a gate driving unit.

Description

TECHNICAL FIELD [0001] The present invention relates to a thin film transistor, a method of manufacturing the thin film transistor, a display device including the thin film transistor, a display device including the thin film transistor,

The present invention relates to a thin film transistor, a method of manufacturing the same, and a display device including the thin film transistor.

2. Description of the Related Art [0002] As an information-oriented society develops, there have been various demands for a display device for displaying images. Recently, a liquid crystal display (LCD), a plasma display panel (PDP) Various display devices such as an OLED (Organic Light Emitting Diode) are being utilized.

The display device includes a display panel, a gate driving circuit, a data driving circuit, and a timing controller. The display panel includes a plurality of pixels formed at intersections of the data lines, the gate lines, the data lines and the gate lines, and supplied with the data voltages of the data lines when the gate signals are supplied to the gate lines. The pixels emit light at a predetermined brightness according to the data voltages.

The display device uses a thin film transistor as a switching element to drive the pixels and the gate driving circuit. The thin film transistor may be a metal oxide semiconductor field effect transistor (MOSFET) that controls the flow of electric current by an electric field.

A complementary metal oxide semiconductor (CMOS), which is an inverter, may be used for a gate driving circuit or a data driving circuit of a display device to appropriately output an input signal. CMOS requires both N-type and P-type MOSFETs. That is, since the CMOS includes at least two thin film transistors, there is a limitation in reducing the size of the CMOS.

A thin film transistor including both an N-type semiconductor layer and a P-type semiconductor layer, a method of manufacturing the same, and a display device including the same.

A thin film transistor according to an embodiment of the present invention includes a first gate electrode disposed on a substrate, a first gate insulating film covering the first gate electrode, a semiconductor layer disposed on the first gate insulating film, a second gate An insulating film, and a second gate electrode disposed on the second gate insulating film. A portion of the semiconductor layer overlaps the first gate electrode and another portion of the semiconductor layer overlaps the second gate electrodes. The semiconductor layer includes an N-type semiconductor layer and a P-type semiconductor layer.

A method of manufacturing a thin film transistor according to an embodiment of the present invention includes forming a first gate electrode on a substrate, forming a first gate insulating film covering the first gate electrode, forming an N-type semiconductor Layer and a P-type semiconductor layer, forming a second gate insulating film covering the semiconductor layer, and forming a second gate electrode on the second gate insulating film. The step of forming the semiconductor layer is formed such that a part of the semiconductor layer overlaps with the first gate electrode. The step of forming the second gate electrode is formed such that the second gate electrode overlaps with another part of the semiconductor layer.

In the embodiment of the present invention, since the thin film transistor includes both the N-type semiconductor layer and the P-type semiconductor layer, a region where the first gate electrode and the N-type semiconductor layer overlap between the first source electrode and the first drain electrode And a region where the second gate electrode and the P-type semiconductor layer overlap between the second source electrode and the second drain electrode may be formed as a second channel region. As a result, embodiments of the present invention can realize a thin film transistor having both N-type semiconductor characteristics and P-type semiconductor characteristics.

In addition, the embodiment of the present invention connects the first drain electrode and the second drain electrode through the connection electrode. As a result, embodiments of the present invention can implement a thin film transistor with a complementary metal oxide semiconductor (CMOS).

Further, in the embodiment of the present invention, the N-type semiconductor layer and the P-type semiconductor layer are continuously deposited in a vacuum while maintaining the vacuum state in the chamber, and the P-type semiconductor layer is formed under the condition of 0% to 3% oxygen partial pressure. As a result, the embodiment of the present invention not only can stably form the interface between the N-type semiconductor layer and the P-type semiconductor layer, but also can form the P-type semiconductor layer with Cu ₂ O instead of CuO. Therefore, the embodiment of the present invention can manufacture a thin film transistor having both N-type semiconductor characteristics and P-type semiconductor characteristics.

Furthermore, the embodiment of the present invention may connect only one of the first and second gate electrodes to a predetermined line or electrode. As a result, the embodiment of the present invention can selectively implement the thin film transistor with either the N-type thin film transistor or the P-type thin film transistor.

Furthermore, the embodiment of the present invention can utilize the thin film transistor as a pull-up transistor of the gate driver and an output control transistor serving as a pull-down transistor. In this case, since the functions of the two transistors can be realized by one thin film transistor, the size of the gate driver can be reduced.

In addition to the effects of the present invention mentioned above, other features and advantages of the present invention will be described below, or may be apparent to those skilled in the art from the description and the description.

1 is a plan view showing a thin film transistor according to an embodiment of the present invention.
2 is a cross-sectional view showing details of I-I 'of FIG.
3 is a graph showing N-type semiconductor characteristics and P-type semiconductor characteristics of a thin film transistor according to an embodiment of the present invention.
4 is a graph showing P-type semiconductor characteristics depending on the thickness of the P-type semiconductor layer.
5 is a plan view showing a thin film transistor according to another embodiment of the present invention.
6 is a cross-sectional view showing II-II 'of FIG. 5 in detail.
7 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention.
8A to 8F are cross-sectional views taken along line I-I 'for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention.
9 is a graph showing the N-type semiconductor characteristics and the P-type semiconductor characteristics of the thin film transistor when the vacuum brake is present when the N-type semiconductor layer and the P-type semiconductor layer are formed.
10 is a flowchart illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention.
11A to 11D are cross-sectional views of II-II 'for explaining a method of manufacturing a thin film transistor according to another embodiment of the present invention.
12 is a perspective view showing a display device according to an embodiment of the present invention.
13 is a plan view showing the first substrate, the gate driver, the source drive IC, the flexible film, the circuit board, and the timing controller of Fig.
14 is a circuit diagram showing an example of a pixel of a display device according to an embodiment of the present invention.
15 is a circuit diagram showing another example of a pixel of a display device according to an embodiment of the present invention.
16 is a circuit diagram showing another example of the pixel of the display device according to the embodiment of the present invention.
17 is a circuit diagram showing an example of a gate driver according to an embodiment of the present invention.

BRIEF DESCRIPTION OF THE DRAWINGS The advantages and features of the present invention, and the manner of achieving them, will be apparent from and elucidated with reference to the embodiments described hereinafter in conjunction with the accompanying drawings. The present invention may, however, be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. To fully disclose the scope of the invention to a person skilled in the art, and the invention is only defined by the scope of the claims.

The shapes, sizes, ratios, angles, numbers, and the like disclosed in the drawings for describing the embodiments of the present invention are illustrative, and thus the present invention is not limited thereto. Like reference numerals refer to like elements throughout the specification. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

Where the terms "comprises," "having," "consisting of," and the like are used in this specification, other portions may be added as long as "only" is not used. Unless the context clearly dictates otherwise, including the plural unless the context clearly dictates otherwise.

In interpreting the constituent elements, it is construed to include the error range even if there is no separate description.

In the case of a description of the positional relationship, for example, if the positional relationship between two parts is described as 'on', 'on top', 'under', and 'next to' Or " direct " is not used, one or more other portions may be located between the two portions.

In the case of a description of a temporal relationship, for example, if the temporal relationship is described by 'after', 'after', 'after', 'before', etc., May not be continuous unless they are not used.

The first, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are used only to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical spirit of the present invention.

The terms "X-axis direction "," Y-axis direction ", and "Z-axis direction" should not be construed solely by the geometric relationship in which the relationship between them is vertical, It may mean having directionality.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, May refer to any combination of items that may be presented from more than one.

It is to be understood that each of the features of the various embodiments of the present invention may be combined or combined with each other, partially or wholly, technically various interlocking and driving, and that the embodiments may be practiced independently of each other, It is possible.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a plan view showing a thin film transistor according to an embodiment of the present invention. 2 is a cross-sectional view showing details of I-I 'of FIG.

1 and 2, a thin film transistor 10 according to an embodiment of the present invention includes a first gate electrode 110, a semiconductor layer 130, a first source electrode 141, a first drain electrode 142, a second source electrode 143, a second drain electrode 144, and a second gate electrode 160.

The thin film transistor 10 is formed on the substrate 100. [ The substrate 100 may be made of plastic or glass.

A buffer film may be formed on the substrate 100 to protect the thin film transistor 10 from moisture penetrating through the substrate 100. The buffer film may be composed of a plurality of stacked inorganic films. For example, the buffer film 210 may be formed of multiple films in which one or more inorganic films of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), and SiON are alternately stacked.

The first gate electrode 110 of the thin film transistor 10 may be formed on the substrate 100 or the buffer film. The first gate electrode 110 may be formed of one of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

A first gate insulating layer 120 may be formed on the first gate electrode 110. The first gate insulating film 120 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

The first gate electrode 110 may block the light incident on the first channel region CH1 from the substrate 100. [ As a result, the first channel region CH1 can be protected from light by the first gate electrode 110. [ 2, a light shield layer 111 may be additionally formed in a region corresponding to the second channel region CH2 in order to block light incident on the second channel region CH2 . The light blocking layer 111 may be formed of the same material as the first gate electrode 110 in the same layer as the first gate electrode 110.

A semiconductor layer 130 may be formed on the first gate insulating layer 120. A part of the semiconductor layer 130 may be formed to overlap with the first gate electrode 110.

The semiconductor layer 130 may include an N-type semiconductor layer 131 and a P-type semiconductor layer 132. The N-type semiconductor layer 131 may be formed on the first gate insulating film 120 and the P-type semiconductor layer 132 may be formed on the N-type semiconductor layer 132. In this case, a region where the N-type semiconductor layer 131 and the first gate electrode 110 disposed under the N-type semiconductor layer 131 are overlapped is formed as the first channel region CH1, and the P- A region where the first gate electrode 132 and the second gate electrode 160 disposed on the P-type semiconductor layer 132 overlap each other may be formed as the second channel region CH2.

The N-type semiconductor layer 131 may be an N-type oxide semiconductor layer, and the P-type semiconductor layer 132 may be a P-type oxide semiconductor layer. When the N-type semiconductor layer 131 is made of an N-type oxide semiconductor layer, it may be made of IGZO, IZO, IGO, ITZO, GTO, ZTO, IAZO, AZO, ITO, ATO or GZO. If the P-type semiconductor layer 132 is formed of a P-type semiconductor _{layer, Cu 2 O, SnO, NiO} , CuMO 2 (Delafossite, M = Al, Ga, In, Sr, Y, Sc, Cr), ZnM 2 O (La-Lu), Ch = Se, S, Te), or Cu-Nanowire with a ratio of 1 to ₄ (Spinel, M = Co, Rh, Ir), Ln / Cu / O / Ch (oxycalogenide, Ln = lanthanide .

When the N-type semiconductor layer 131 is formed of an N-type oxide semiconductor layer and the P-type semiconductor layer 132 is formed of a P-type oxide semiconductor layer, the thickness of the P- As shown in FIG. For example, the thickness of the N-type semiconductor layer 131 may be 30 nm or less, and the thickness of the P-type semiconductor layer 132 may be 10 nm or less. The grain boundary of the P-type semiconductor layer 132 affects the device characteristics. Specifically, as the grain boundary surface increases, the device characteristics can be improved. When the P-type semiconductor layer 132 is formed as a thin film with a thickness of 10 nm or less in the upper layer portion of the N-type semiconductor layer 131, the grain size of the P-type semiconductor layer 132 becomes smaller, Thereby improving the characteristics of the P-type semiconductor layer 132. More specifically, when the ionized defect and the grain boundary characteristics of the P-type semiconductor layer 132 are improved, as shown in FIG. 3, a low threshold voltage near 0 V and a saturation state Saturation mobility can be improved to more than 4.0 cm ² / Vs. A detailed description of the thickness and the effect of the P-type semiconductor layer 132 will be given later with reference to FIGS. 3 and 4. FIG.

Alternatively, the N-type semiconductor layer 131 may be an N-type polysilicon layer and the P-type semiconductor layer 132 may be a P-type polysilicon layer.

First and second source electrodes 141 and 143 and first and second drain electrodes 142 and 144 may be formed on the semiconductor layer 130. The first source electrode 141 and the first drain electrode 142 may be formed to overlap with the first gate electrode 110.

The first drain electrode 142 may be connected to the second drain electrode 144 through the connection electrode 145. In this case, the thin film transistor 10 can function as a CMOS (Complementary Metal Oxide Semiconductor). The connection electrode 145 may be omitted.

A second gate insulating layer 150 is formed on the semiconductor layer 130, the first and second source electrodes 141 and 143, the first and second drain electrodes 142 and 144, . The second gate insulating film 150 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

A second gate electrode 160 may be formed on the second gate insulating layer 150. The second gate electrode 160 may be formed to overlap with the second source electrode 143 and the second drain electrode 144. The second gate electrode 160 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

The first gate electrode 110 may be formed to overlap a portion of the semiconductor layer 130 and the second gate electrode 160 may be overlapped with another portion of the semiconductor layer 130.

Specifically, a region where the first gate electrode 110 and the N-type semiconductor layer 131 of the semiconductor layer 130 overlap between the first source electrode 141 and the first drain electrode 142 is an N-type semiconductor characteristic (CH1) having a first channel region (CH1). In this case, the channel length L 1 of the first channel region CH 1 may be defined as a distance between the first source electrode 141 and the first drain electrode 142. The channel width W1 of the first channel region CH1 may be defined as the width of the first source and drain electrodes 141 and 142. [

The region where the second gate electrode 160 and the P-type semiconductor layer 132 of the semiconductor layer 130 are overlapped between the second source electrode 144 and the second drain electrode 144 has a P-type semiconductor property And the second channel region CH2 having the first channel region CH2. In this case, the channel length L2 of the second channel region CH2 may be defined as a distance between the second source electrode 143 and the second drain electrode 144. [ And the channel width W2 of the second channel region CH2 may be defined as the width of the second source and drain electrodes 143 and 144. [

As described above, the thin film transistor 10 according to an embodiment of the present invention includes both the N-type semiconductor layer 131 and the P-type semiconductor layer 132 to form the first source electrode 141, A region where the first gate electrode 110 and the N-type semiconductor layer 131 overlap each other is formed as the first channel region CH1 between the electrodes 142 and the second source electrode 143 and the second drain electrode The second gate electrode 160 and the P-type semiconductor layer 132 may overlap each other in the second channel region CH2. As a result, embodiments of the present invention can realize a thin film transistor having both N-type semiconductor characteristics and P-type semiconductor characteristics.

3 is a graph showing N-type semiconductor characteristics and P-type semiconductor characteristics of a thin film transistor according to an embodiment of the present invention. 3 shows the relationship between the gate-source voltage Vgs of the first channel region CH1 and the current I1 of the first channel region CH1 when the channel width W1 of the first channel region CH1 is 980 mu m and the channel length L1 is 150 mu m. The value Ids1 is shown. 3 shows the second channel region CH2 according to the gate-source voltage Vgs when the channel width W2 of the second channel region CH2 is 1960 mu m and the channel length L2 is 960 mu m. (Ids2). In FIG. 3, the X-axis represents the gate-source voltage (Vgs), and the Y-axis represents the current value (Ids) of the channel region.

Referring to FIG. 3, the first channel region CH1 corresponds to the N-channel region. When the gate-source voltage Vgs has a positive voltage, the current value Ids1 of the first channel region CH1 is And has an N-type semiconductor characteristic that rises in proportion to the gate-source voltage Vgs.

When the gate-source voltage Vgs has a negative voltage, the current value Ids2 of the second channel region CH2 is higher than the current value Ids2 between the gate and the source, And has a P-type semiconductor characteristic that rises in proportion to the voltage Vgs. Referring to Figure 3 the movement of saturation current value (Ids1) Fig (Saturation mobility) is 7cm ² / Vs and movement of the saturation current (Ids2) Fig (Saturation mobility) is a 4.5cm ² / Vs, N-type semiconductor It can be seen that the thin film transistor according to the present invention including both the layer 131 and the P-type semiconductor layer 132 effectively exhibits the two semiconductor characteristics.

The thin film transistor 10 according to an embodiment of the present invention includes the first gate electrode 110 and the N-type semiconductor layer (not shown) between the first source electrode 141 and the first drain electrode 142, 131 are formed in the first channel region CH1 and the second gate electrode 160 and the P-type semiconductor layer 132 are formed between the second source electrode 143 and the second drain electrode 144, And the overlapping region can be formed as the second channel region CH2. As a result, the embodiment of the present invention can be implemented such that the first channel region CH1 has the N-type semiconductor characteristic and the second channel region CH2 has the P-type semiconductor characteristic.

4 is a graph showing P-type semiconductor characteristics depending on the thickness of the P-type semiconductor layer. 4, when the N-type semiconductor layer 131 and the P-type semiconductor layer 132 are oxide semiconductors, for example, the N-type semiconductor layer 131 is IGZO and the P-type semiconductor layer 132 is Cu ₂ > is a graph of P-type semiconductor characteristics depending on the thickness of the P-type semiconductor layer. 4 shows the relationship between the gate-source voltage Vgs and the second channel region CH2 when the thickness of the P-type semiconductor layer 132 is 10 nm, 20 nm, and 30 nm when the drain- (Ids2) < / RTI > In Fig. 4, the X-axis represents the gate-source voltage (Vgs), and the Y-axis represents the current value Ids of the second channel region CH2.

4, when the thickness of the P-type semiconductor layer 132 is 20 nm or 30 nm, even if the gate-source voltage Vgs changes, the current continues to flow, and thus the P-type semiconductor characteristics can not be realized properly . On the other hand, when the thickness of the P-type semiconductor layer 132 is 10 nm, an off current characteristic appears near the gate-source voltage Vgs of 0 V, so that the P-type semiconductor characteristics can be realized.

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As described above, when the thickness of the P-type semiconductor layer 132 is 10 nm or less, the P-type semiconductor characteristics of the thin film transistor 10 according to the embodiment of the present invention can be realized. Therefore, the thickness of the P-type semiconductor layer 132 can be made thinner than the thickness of the N-type semiconductor layer 131.

5 is a plan view showing a thin film transistor according to another embodiment of the present invention. 6 is a cross-sectional view showing II-II 'of FIG. 5 in detail.

5 and 6, a thin film transistor 10 according to another embodiment of the present invention includes a first gate electrode 110, a semiconductor layer 130, a first source electrode 141, a first drain electrode 142, a second source electrode 143, a second drain electrode 144, and a second gate electrode 160.

The first gate electrode 110, the light blocking layer 111 and the semiconductor layer 130 of the thin film transistor 10 shown in FIGS. 5 and 6 are formed on the first gate electrode 110 ), The light blocking layer 111, and the semiconductor layer 130, detailed description thereof will be omitted.

A second gate insulating layer 150 may be formed on the semiconductor layer 130. The second gate insulating film 150 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

A second gate electrode 160 may be formed on the second gate insulating layer 150. The second gate electrode 160 may be formed to overlap with the second source electrode 143 and the second drain electrode 144. The second gate electrode 160 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

The first gate electrode 110 may be formed to overlap a portion of the semiconductor layer 130 and the second gate electrode 160 may be overlapped with another portion of the semiconductor layer 130.

An interlayer insulating layer 170 may be formed on the second gate electrode 160. The interlayer insulating film 170 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof.

First and second source electrodes 141 and 143 and first and second drain electrodes 142 and 144 may be formed on the interlayer insulating layer 170. The first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 pass through the second gate insulating layer 160 and the interlayer insulating layer 170 to form the semiconductor layer 130, Type semiconductor layer 132 of the semiconductor layer 130 through the contact hole CNT exposing the P-type semiconductor layer 132 of the semiconductor layer 130. [

The first source electrode 141 and the first drain electrode 142 may be formed to overlap with the first gate electrode 110. The second source electrode 143 and the second drain electrode 144 may be formed so as not to overlap the second gate electrode 120.

The first drain electrode 142 may be connected to the second drain electrode 144 through the connection electrode 145. In this case, the thin film transistor 10 can function as a CMOS (Complementary Metal Oxide Semiconductor). The connection electrode 145 may be omitted.

A region where the first gate electrode 110 and the N-type semiconductor layer 131 of the semiconductor layer 130 overlap with each other between the first source electrode 141 and the first drain electrode 142 has an N-type semiconductor characteristic The first channel region CH1 having the first channel region CH1. In this case, the channel length L 1 of the first channel region CH 1 may be defined as a distance between the first source electrode 141 and the first drain electrode 142. The channel width W1 of the first channel region CH1 may be defined as the width of the first source and drain electrodes 141 and 142. [

The region where the second gate electrode 160 and the P-type semiconductor layer 132 of the semiconductor layer 130 are overlapped between the second source electrode 144 and the second drain electrode 144 has a P-type semiconductor property And the second channel region CH2 having the first channel region CH2. In this case, the channel length L2 of the second channel region CH2 may be defined as a distance between the second source electrode 143 and the second drain electrode 144. [ And the channel width W2 of the second channel region CH2 may be defined as the width of the second source and drain electrodes 143 and 144. [

As described above, the thin film transistor 10 according to another embodiment of the present invention includes both the N-type semiconductor layer 131 and the P-type semiconductor layer 132 to form the first source electrode 141 and the first drain A region where the first gate electrode 110 and the N-type semiconductor layer 131 overlap each other is formed as the first channel region CH1 between the electrodes 142 and the second source electrode 143 and the second drain electrode The second gate electrode 160 and the P-type semiconductor layer 132 may overlap each other in the second channel region CH2. As a result, embodiments of the present invention can realize a thin film transistor having both N-type semiconductor characteristics and P-type semiconductor characteristics.

That is, in the thin film transistor 10 according to another embodiment of the present invention, the first channel region CH1 has the N-type semiconductor characteristic and the second channel region CH2 has the P-type semiconductor characteristic, Can be implemented.

4, the thickness of the P-type semiconductor layer 132 is controlled to 10 nm or less in order to control the turn-off of the second channel region CH2. .

7 is a flowchart illustrating a method of manufacturing a thin film transistor according to an embodiment of the present invention. 8A to 8F are cross-sectional views taken along line I-I 'for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention. 8A to 8F relate to the manufacturing method of the thin film transistor shown in Figs. 1 and 2 described above, the same reference numerals are given to the same constituents. Hereinafter, a method of manufacturing a thin film transistor according to an embodiment of the present invention will be described in detail with reference to FIG. 7 and FIGS. 8A to 8F.

First, a first gate electrode 110 is formed on a substrate 100 as shown in FIG. 8A. Specifically, a first metal layer is formed on the entire surface of the substrate 100 by sputtering. Then, the first gate electrode 110 is formed by patterning the first metal layer using a mask process of forming a photoresist pattern on the first metal layer and then etching the first metal layer. The first gate electrode 110 may be formed of one of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

A buffer film may be formed on the substrate 100 to protect the TFT 10 from moisture penetrating through the substrate 100 and a first gate electrode 110 may be formed on the buffer film. The buffer film may be composed of a plurality of stacked inorganic films. For example, the buffer film 210 may be formed of multiple films in which one or more inorganic films of a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), and SiON are alternately stacked. The buffer film may be formed using a PECVD (Plasma Enhanced Chemical Vapor Deposition) method. (S101 in Fig. 7)

Second, a first gate insulating layer 120 may be formed on the first gate electrode 110 as shown in FIG. 8B. The first gate insulating film 120 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof. The first gate insulating layer 120 may be formed using a PECVD method. (S102 in Fig. 7)

Third, the semiconductor layer 130 may be formed on the first gate insulating layer 120 as shown in FIG. 8C. The semiconductor layer 130 may include an N-type semiconductor layer 131 and a P-type semiconductor layer 132.

First, a first semiconductor layer is formed on the entire surface of the first gate insulating film 120 by sputtering or MOCVD (Metal Organic Chemical Vapor Deposition), and then a second semiconductor layer is formed on the entire surface of the first semiconductor layer. Layer. Then, the first and second semiconductor layers are simultaneously patterned by using a mask process using a photoresist pattern to form the N-type semiconductor layer 131 and the P-type semiconductor layer 132. A part of the semiconductor layer 130 may be formed to overlap with the first gate electrode 110.

The N-type semiconductor layer 131 may be an N-type polysilicon layer or an N-type oxide semiconductor layer. When the N-type semiconductor layer 131 is made of an N-type oxide semiconductor layer, it may be made of IGZO, IZO, IGO, ITZO, GTO, ZTO, IAZO, AZO, ITO, ATO or GZO.

The P-type semiconductor layer 132 may be a P-type polysilicon layer or a P-type oxide semiconductor layer. If the P-type semiconductor layer 132 is formed of a P-type semiconductor _{layer, Cu 2 O, SnO, NiO} , CuMO 2 (Delafossite, M = Al, Ga, In, Sr, Y, Sc, Cr), ZnM 2 O (La-Lu), Ch = Se, S, Te), or Cu-Nanowire with a ratio of 1 to ₄ (Spinel, M = Co, Rh, Ir), Ln / Cu / O / Ch (oxycalogenide, Ln = lanthanide .

Hereinafter, the case where the P-type semiconductor layer 132 is made of Cu ₂ O will be mainly described.

When the P-type semiconductor layer 132 is made of Cu ₂ O, the N-type semiconductor layer 131 and the P-type semiconductor layer 132 are formed so that the thin film transistor 10 has both N-type semiconductor characteristics and P- Must be formed with the vacuum maintained. That is, the N-type semiconductor layer 131 and the P-type semiconductor layer 132 can be continuously deposited while maintaining a vacuum state in one chamber. For example, when forming the N-type semiconductor layer 131 and the P-type semiconductor layer 132, the vacuum may be maintained at 5 to 10 mTorr.

If the vacuum state is not maintained when the N-type semiconductor layer 131 and the P-type semiconductor layer 132 are formed, the N-type semiconductor layer 131 may be oxidized by oxygen in the atmosphere. Thus, the interface between the N-type semiconductor layer 131 and the P-type semiconductor layer 132 may be unstable.

Further, the P-type semiconductor layer 132 can be formed under the condition that the oxygen partial pressure is 3% or less. When the oxygen partial pressure exceeds 3%, the P-type semiconductor layer 132 may not be made of Cu ₂ O but may be made of CuO. If the vacuum state is not maintained when the N-type semiconductor layer 131 and the P-type semiconductor layer 132 are formed, the P-type semiconductor layer 132 is made of Cu ₂ O by oxygen in the atmosphere, And may be made of CuO.

When the P-type semiconductor layer 132 is made of CuO, the electron mobility can be significantly lowered as compared with the case where the P-type semiconductor layer 132 is made of Cu ₂ O. That is, when the P-type semiconductor layer 132 is made of CuO, the electron mobility in the second channel region CH2 is very low, not more than 1 cm2 / Vs. In this case, since the P-type semiconductor characteristics of the thin film transistor 10 are greatly deteriorated as shown in FIG. 9, it is difficult to realize the P-type semiconductor characteristics by using the second channel region CH2.

Further, the P-type semiconductor layer 132 made of CuO can be heat-treated at a high temperature in order to convert the P-type semiconductor layer 132 made of Cu ₂ O into the P-type semiconductor layer 132. For example, the P-type semiconductor layer 132 made of CuO can be heat-treated in a vacuum state at a high temperature of 300 DEG C or more for 30 minutes or more. However, in the case of performing the heat treatment at a high temperature in a vacuum state, since the N-type semiconductor layer 131 is desorbed from oxygen to increase the conductivity, a problem that an off current increases as shown in FIG.

The N-type semiconductor layer 131 may be formed in an oxygen-rich state. For example, when the N-type semiconductor layer 131 is formed, the oxygen partial pressure may be 3% to 10%. However, when it is necessary to improve the electron mobility according to the material of the N-type semiconductor layer 131, the condition of the oxygen partial pressure for forming the N-type semiconductor layer 131 may be 0% to 3%.

On the other hand, when the P-type semiconductor layer 132 is formed using Cu ₂ O as a target, it is preferable that the oxygen partial pressure is 0% to 3%. However, when the P-type semiconductor layer 132 is formed by the O ₂ reaction method using Cu as a target, the oxygen partial pressure is preferably 40% or more.

The N-type semiconductor layer 131 is preferably 30 nm or less in order to improve electron mobility. In addition, the P-type semiconductor layer 132 must be formed to have a thickness of 10 nm or less to control the turn-off of the second channel region CH2 as shown in FIG. 4, ₂ < / RTI > Therefore, the thickness of the P-type semiconductor layer 132 may be 10 nm or less. (S103 in Fig. 7)

Fourth, the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 may be formed on the semiconductor layer 130 as shown in FIG. 8D. Specifically, a second metal layer is formed on the entire surface of the semiconductor layer 130 by sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). Then, the second metal layer is patterned using a mask process using a photoresist pattern to form the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144. The first source electrode 141 and the first drain electrode 142 may be formed to overlap with the first gate electrode 110.

In addition, a connection electrode 145 connecting the first and second drain electrodes 142 and 144 may be formed. In this case, the thin film transistor 10 can function as a CMOS (Complementary Metal Oxide Semiconductor). The connection electrode 145 may be omitted.

The first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 and the connection electrode 145 may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr) Layer or multilayered structure made of any one of gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. However, since the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 are in contact with the P-type semiconductor layer 132, (Pd, 5.22 eV to 5.6 eV), platinum (Pt, 5.12 eV to 5.93 eV), gold (Au, 5.1 eV to 5.47 eV), nickel (Ni, 5.04 eV to 5.35 eV) Or a multi-layer structure. (S104 in Fig. 7)

Fifthly, on the semiconductor layer 130, the first and second source electrodes 141 and 143, the first and second drain electrodes 142 and 144, and the connection electrode 145 as shown in FIG. 8E, 2 gate insulating film 150 may be formed. The second gate insulating film 150 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof. The second gate insulating layer 150 may be formed using a PECVD method. (S105 in Fig. 7)

Sixth, a second gate electrode 160 may be formed on the second gate insulating layer 150 as shown in FIG. 8F. Specifically, a third metal layer is formed on the entire surface of the second gate insulating layer 150 by sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). Then, the third gate electrode 160 is formed by patterning the third metal layer using a mask process using a photoresist pattern. The second gate electrode 160 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

The second gate electrode 160 may be formed to overlap with the second source electrode 143 and the second drain electrode 144. When the first gate electrode 110 is formed to overlap with a part of the semiconductor layer 130, the second gate electrode 160 may be formed to overlap with another part of the semiconductor layer 130. (S106 in Fig. 7)

As described above, in the embodiment of the present invention, the N-type semiconductor layer 131 and the P-type semiconductor layer 132 are continuously deposited in one chamber while maintaining a vacuum state, and the P- 0% to 3% oxygen partial pressure. As a result, in the embodiment of the present invention, not only the interface between the N-type semiconductor layer 131 and the P-type semiconductor layer 132 can be stably formed, but also the P-type semiconductor layer 132 is made of Cu ₂ O . Therefore, the embodiment of the present invention can manufacture a thin film transistor having both N-type semiconductor characteristics and P-type semiconductor characteristics.

10 is a flowchart illustrating a method of manufacturing a thin film transistor according to another embodiment of the present invention. 11A to 11D are cross-sectional views of II-II 'for explaining a method of manufacturing a thin film transistor according to another embodiment of the present invention. 11A to 11D relate to the manufacturing method of the thin film transistor shown in Figs. 5 and 6, and thus the same reference numerals are assigned to the same constitution. Hereinafter, a method of manufacturing a thin film transistor according to another embodiment of the present invention will be described in detail with reference to FIGS. 10 and 11A to 11D.

Steps S201 to S203 of FIG. 10 are substantially the same as steps S101 to S103 of FIG. 7, and detailed descriptions of steps S201 to S203 of FIG. 10 are omitted.

Referring to FIG. 10, a fourth gate insulating layer 150 may be formed on the semiconductor layer 130 as shown in FIG. The second gate insulating film 150 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof. The second gate insulating layer 150 may be formed using a PECVD method. (S204 in Fig. 10)

Fifth, a second gate electrode 160 may be formed on the second gate insulating layer 150 as shown in FIG. 11B. Specifically, a second metal layer is formed on the entire surface of the second gate insulating film 150 by sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). Then, the second gate electrode 160 is formed by patterning the second metal layer using a mask process using a photoresist pattern. The second gate electrode 160 may be formed of one selected from the group consisting of Mo, Al, Cr, Au, Ti, Ni, Ne, Or an alloy thereof.

When the first gate electrode 110 is formed to overlap with a part of the semiconductor layer 130, the second gate electrode 160 may be formed to overlap with another part of the semiconductor layer 130. (S205 in Fig. 10)

Sixth, an interlayer insulating layer 170 may be formed on the second gate electrode 160 as shown in FIG. 11C. The interlayer insulating film 170 may be formed of an inorganic film, for example, a silicon oxide film (SiO _x ), a silicon nitride film (SiN _x ), or a multilayer film thereof. The interlayer insulating film 170 may be formed by a PECVD method.

Then, contact holes may be formed to penetrate the second gate insulating layer 150 and the interlayer insulating layer 170 to expose the P-type semiconductor layer 132 of the semiconductor layer 130. (S206 in Fig. 10)

7D, the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 may be formed on the interlayer insulating layer 170 as shown in FIG. 11D. Specifically, a third metal layer is formed on the entire surface of the interlayer insulating film 170 by using sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). Then, the third metal layer is patterned using a mask process using a photoresist pattern to form the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144. The first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 are connected to the P-type semiconductor layer 132 of the semiconductor layer 130 through the contact hole CNT Can be connected.

The first source electrode 141 and the first drain electrode 142 may be formed to overlap with the first gate electrode 110. The second source electrode 143 and the second drain electrode 144 may be formed so as not to overlap the second gate electrode 120.

A connection electrode 145 connecting the first drain electrode 142 and the second drain electrode 144 may be formed. In this case, the thin film transistor 10 can function as a CMOS (Complementary Metal Oxide Semiconductor). The connection electrode 145 may be omitted.

The first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 and the connection electrode 145 may be formed of a metal such as molybdenum (Mo), aluminum (Al), chromium (Cr) Layer or multilayered structure made of any one of gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or an alloy thereof. However, since the first and second source electrodes 141 and 143 and the first and second drain electrodes 142 and 144 are in contact with the P-type semiconductor layer 132, (Pd, 5.22 eV to 5.6 eV), platinum (Pt, 5.12 eV to 5.93 eV), gold (Au, 5.1 eV to 5.47 eV), nickel (Ni, 5.04 eV to 5.35 eV) Or a multi-layer structure. (S207 in Fig. 10)

12 is a perspective view showing a display device according to an embodiment of the present invention. 13 is a plan view showing the first substrate, the gate driver, the source drive IC, the flexible film, the circuit board, and the timing controller of Fig.

12 and 13, an OLED display 1000 according to an exemplary embodiment of the present invention includes a display panel 1100, a gate driver 1200, an integrated circuit (IC) A flexible film 1400, a circuit board 1500, and a timing control unit 1600. The flexible film 1400 includes a flexible printed circuit board (not shown). A display device according to an exemplary embodiment of the present invention may include a liquid crystal display device, an organic light emitting display device, a field emission display device, an electrophoresis display device, But may be implemented in any one of them.

The display panel 1100 includes a first substrate 1110 and a second substrate 1120. The second substrate 1120 may be an encapsulating substrate. The first substrate 1110 and the second substrate 1120 may be plastic or glass.

On one side of the first substrate 1110 facing the second substrate 1120, gate lines, data lines, and pixels are formed. The pixels are provided in an area defined by the intersection structure of the gate lines and the data lines. A detailed description of the structure of each of the pixels will be given later in conjunction with FIG. 14 to FIG.

The display panel 1100 can be divided into a display area DA for displaying an image formed with pixels and a non-display area NDA for not displaying an image as shown in Fig. Gate lines, data lines, and pixels may be formed in the display area DA. A gate driver 1200 and pads may be formed in the non-display area NDA.

The gate driver 1200 supplies gate signals to the gate lines according to a gate control signal input from the timing controller 1600. The gate driver 1200 may be formed in a non-display area DA on one side or both sides of the display area DA of the display panel 1100 in a gate driver in panel (GIP) manner. When the gate driver 1200 is formed by the GIP method, a detailed description of the gate driver 1200 will be given later with reference to FIG. Alternatively, the gate driver 1200 may be formed of a driving chip, mounted on a flexible film, and mounted on a non-display area DA on one side or both sides of the display area DA of the display panel 1100 by a tape automated bonding (TAB) As shown in FIG.

The source driver IC 1300 receives digital video data and a source control signal from the source driver IC 1300. The source driver IC 1300 converts the digital video data into analog data voltages according to the source control signal and supplies the analog data voltages to the data lines. When the source drive IC 1300 is manufactured as a driving chip, it can be mounted on the flexible film 1400 in a COF (chip on film) or COP (chip on plastic) manner.

In the non-display area NDA of the display panel 1100, pads such as data pads may be formed. The flexible film 1400 may be formed with wirings that connect the pads to the source drive IC 1300, and wirings that connect the pads to the wirings of the circuit board 1500. The flexible film 1400 is attached on the pads using an anisotropic conducting film, whereby the pads and the wirings of the flexible film 1400 can be connected.

The circuit board 1500 may be attached to the flexible films 1400. The circuit board 1500 may be implemented with a plurality of circuits implemented with driving chips. For example, the timing control section 1600 may be mounted on the circuit board 1500. The circuit board 1500 may be a printed circuit board or a flexible printed circuit board.

The timing controller 1600 receives digital video data and a timing signal from an external system board through a cable of the circuit board 1500. The timing controller 1600 generates a gate control signal for controlling the operation timing of the gate driver 1200 and a source control signal for controlling the source driver ICs 1300 based on the timing signal. The timing controller 1600 supplies a gate control signal to the gate driver 1200 and a source control signal to the source driver ICs 1300. [

14 is a circuit diagram showing an example of a pixel of a display device according to an embodiment of the present invention. Referring to FIG. 14, a pixel P of a display device according to an embodiment of the present invention may include a thin film transistor T, a pixel electrode 11, and a storage capacitor Cst.

The thin film transistor T applies the data voltage of the jth (j is a positive integer equal to or greater than 2) data line Dj to the pixel electrode Dk in response to the gate signal of the kth (k is a positive integer of 2 or more) (11). Each of the pixels P drives the liquid crystal of the liquid crystal layer 13 by an electric field generated by a potential difference between the data voltage supplied to the pixel electrode 11 and the common voltage supplied to the common electrode 12 The amount of light transmitted from the backlight unit can be adjusted. The common electrode 12 receives a common voltage from the common voltage line VcomL and the backlight unit is disposed below the display panel 10 to irradiate the display panel 10 with uniform light. The storage capacitor Cst is provided between the pixel electrode 11 and the common electrode 12 to keep the voltage difference between the pixel electrode 11 and the common electrode 12 constant.

The embodiment of the present invention can selectively implement the thin film transistor T with either the N-type thin film transistor or the P-type thin film transistor by connecting only one of the first and second gate electrodes to a predetermined line or electrode . In FIG. 14, only the first gate electrode 110 of the thin film transistor T is connected to the k-th gate line Gk, and the thin film transistor T is implemented as an N-type thin film transistor.

14, since the thin film transistor T has only the N-type semiconductor characteristic, the first channel region CH1 having the N-type semiconductor characteristic is used to connect the j-th data line Dj and the pixel electrode 11 Switch the connection. The first gate electrode 110 of the thin film transistor T is connected to the kth gate line Gk and the first source electrode 141 is connected to the pixel electrode 11 and the first drain electrode 142 Are connected to the jth data line Dj. The second gate electrode 160 of the thin film transistor T is not electrically connected to any line. The second source electrode 143 of the thin film transistor T may be connected to the jth data line Dj and the second drain electrode 144 may be connected to the pixel electrode 11, 2 source electrode 143 and the second drain electrode 144 may not be electrically connected to any line.

As described above, the thin film transistor according to the embodiment of the present invention has both the N-type semiconductor characteristic and the P-type semiconductor characteristic, but can be applied to the thin film transistor of the pixel P of the liquid crystal display device by using only the N- have.

On the other hand, in FIG. 14, only the N-type semiconductor characteristic is illustrated as the thin film transistor T, but both the N-type semiconductor characteristic and the P-type semiconductor characteristic can be used. In this case, the second gate electrode 160 of the thin film transistor T may be connected to a signal line other than the kth gate line Gk.

15 is a circuit diagram showing another example of a pixel of a display device according to an embodiment of the present invention. 15, a pixel P of a display device according to an exemplary embodiment of the present invention includes an organic light emitting diode OLED, a driving transistor DT, first and second transistors ST1 and ST2, And a capacitor Cst.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED may be connected to the source electrode of the driving transistor DT and the cathode electrode may be connected to the first power supply voltage line VSSL to which the first power supply voltage is supplied. The first power supply voltage line VSSL may be a low potential voltage line to which a low potential power supply voltage is supplied.

The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The driving transistor DT is arranged between the second power supply voltage line VDDL to which the second power supply voltage is supplied and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the second power supply voltage line VDDL to the organic light emitting diode OLED in accordance with a voltage difference between the gate electrode and the source electrode. The second power supply voltage line VDDL may be a high potential voltage line to which the high potential power supply voltage is supplied.

The first transistor ST1 is turned on by the k-th gate signal of the k-th gate line Gk to supply the voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. The second transistor ST2 is turned on by the kth sensing signal of the kth sensing line Sk to connect the qth reference voltage line Rq to the source electrode of the driving transistor DT.

The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

The embodiment of the present invention can selectively implement the thin film transistor T with either the N-type thin film transistor or the P-type thin film transistor by connecting only one of the first and second gate electrodes to a predetermined line or electrode . In FIG. 15, only the first gate electrode 110 of the thin film transistor T is connected to a predetermined line or electrode, and the thin film transistor T is implemented as an N-type thin film transistor.

15, the first gate electrode 110 of the driving transistor DT is connected to the first source electrode 141 of the first transistor ST1 and the first source electrode 141 is connected to the organic light emitting diode OLED, and the first drain electrode 142 may be connected to the second power supply voltage line VDDL. The second gate electrode 160 of the driving transistor DT is not electrically connected to any line. The second source electrode 143 of the driving transistor DT may be connected to the second power supply voltage line VDDL and the second drain electrode 144 may be connected to the anode electrode of the organic light emitting diode OLED. And the second source electrode 143 and the second drain electrode 144 may not be electrically connected to any line.

The first gate electrode 110 of the first transistor ST1 is connected to the kth gate line Gk and the first source electrode 141 is connected to the first gate electrode 110 of the driving transistor DT. And the first drain electrode 142 may be connected to the jth data line Dj. The second gate electrode 160 of the first transistor ST1 is not electrically connected to any line. The second source electrode 143 of the first transistor ST1 is connected to the jth data line Dj and the second drain electrode 144 is connected to the first gate electrode 110 of the driving transistor DT However, the second source electrode 143 and the second drain electrode 144 may not be electrically connected to any line.

The first gate electrode 110 of the second transistor ST2 is connected to the kth sensing line Sk and the first source electrode 141 is connected to the q th reference voltage line Rq, And the drain electrode 142 may be connected to the first source electrode 141 of the driving transistor DT. The second gate electrode 160 of the second transistor ST2 is not electrically connected to any line. The second source electrode 143 of the second transistor ST2 is connected to the first source electrode 141 of the driving transistor DT and the second drain electrode 144 is connected to the q th reference voltage line Rq The second source electrode 143 and the second drain electrode 144 may not be electrically connected to any of the lines.

As described above, the thin film transistor according to the embodiment of the present invention has both the N-type semiconductor characteristic and the P-type semiconductor characteristic, but can be applied to the thin film transistor of the pixel P of the OLED .

In FIG. 15, the driving transistor DT and the first and second transistors ST1 and ST2 use only N-type semiconductor characteristics. However, both the N-type semiconductor characteristics and the P-type semiconductor characteristics may be used. In this case, the second gate electrode 160 of the driving transistor DT can be electrically connected to a predetermined line. The second gate electrode 160 of each of the first and second transistors ST1 and ST2 may be connected to a signal line other than the kth gate line Gk and the kth sensing line Sk.

16 is a circuit diagram showing another example of the pixel of the display device according to the embodiment of the present invention. 16, a pixel P of a display device according to an exemplary embodiment of the present invention includes an organic light emitting diode OLED, a driving transistor DT, first and second transistors ST1 and ST2, And a capacitor Cst.

The organic light emitting diode OLED emits light according to the current supplied through the driving transistor DT. The anode electrode of the organic light emitting diode OLED may be connected to the drain electrode of the driving transistor DT and the cathode electrode may be connected to the first power supply voltage line VSSL to which the first power supply voltage is supplied. The first power supply voltage line VSSL may be a low potential voltage line to which a low potential power supply voltage is supplied.

The organic light emitting diode OLED may include an anode electrode, a hole transporting layer, an organic light emitting layer, an electron transporting layer, and a cathode electrode. have. In the organic light emitting diode (OLED), when a voltage is applied to the anode electrode and the cathode electrode, holes and electrons move to the organic light emitting layer through the hole transporting layer and the electron transporting layer, respectively.

The driving transistor DT is arranged between the second power supply voltage line VDDL to which the second power supply voltage is supplied and the organic light emitting diode OLED. The driving transistor DT adjusts a current flowing from the second power supply voltage line VDDL to the organic light emitting diode OLED in accordance with a voltage difference between the gate electrode and the source electrode. The second power supply voltage line VDDL may be a high potential voltage line to which the high potential power supply voltage is supplied.

The first transistor ST1 is turned on by the k-th gate signal of the k-th gate line Gk to supply the voltage of the j-th data line Dj to the gate electrode of the driving transistor DT. The second transistor ST2 is turned on by the kth sensing signal of the kth sensing line Sk to connect the gate electrode and the drain electrode of the driving transistor DT.

The capacitor Cst is formed between the gate electrode and the source electrode of the driving transistor DT. The capacitor Cst stores the difference voltage between the gate voltage of the driving transistor DT and the source voltage.

The embodiment of the present invention can selectively implement the thin film transistor T with either the N-type thin film transistor or the P-type thin film transistor by connecting only one of the first and second gate electrodes to a predetermined line or electrode . In FIG. 16, only the second gate electrode 160 of the thin film transistor T is connected to a predetermined line or electrode, and the thin film transistor T is implemented by a P-type thin film transistor.

16, the second gate electrode 160 of the driving transistor DT is connected to the second drain electrode 144 of the first transistor ST1, the second source electrode 143 is connected to the second power source voltage Line VDDL and the second drain electrode 144 may be connected to the anode electrode of the organic light emitting diode OLED. The first gate electrode 110 of the driving transistor DT is not electrically connected to any line. The first source electrode 141 of the driving transistor DT may be connected to the anode electrode of the organic light emitting diode OLED and the first drain electrode 142 may be connected to the second power supply voltage line VDDL, And the first source electrode 141 and the first drain electrode 142 may not be electrically connected to any line.

The second gate electrode 160 of the first transistor ST1 is connected to the kth gate line Gk and the second source electrode 143 is connected to the jth data line Dj. The electrode 144 may be connected to the first gate electrode 110 of the driving transistor DT. The first gate electrode 110 of the first transistor ST1 is not electrically connected to any line. The first source electrode 141 of the first transistor ST1 is connected to the first gate electrode 110 of the driving transistor DT and the first drain electrode 142 is connected to the jth data line Dj However, the present invention is not limited thereto, and the first source electrode 141 and the first drain electrode 142 may not be electrically connected to any line.

The second gate electrode 160 of the second transistor ST2 is connected to the kth sensing line Sk and the second source electrode 143 is connected to the second drain electrode 144 of the driving transistor DT. And the second drain electrode 144 may be connected to the second gate electrode 160 of the driving transistor DT. The first gate electrode 110 of the second transistor ST2 is not electrically connected to any line. The first source electrode 141 of the second transistor ST2 is connected to the second gate electrode 160 of the driving transistor DT and the first drain electrode 142 is connected to the second drain electrode of the driving transistor DT. The first source electrode 141 and the first drain electrode 142 may not be electrically connected to any of the lines.

As described above, the thin film transistor according to the embodiment of the present invention has both the N-type semiconductor characteristic and the P-type semiconductor characteristic, but can be applied to the thin film transistor of the pixel P of the OLED .

In FIG. 16, the driving transistor DT and the first and second transistors ST1 and ST2 use only the P-type semiconductor characteristics. However, both the N-type semiconductor characteristics and the P-type semiconductor characteristics may be used. In this case, the first gate electrode 110 of the driving transistor DT may be electrically connected to a predetermined line. The first gate electrode 110 of each of the first and second transistors ST1 and ST2 may be connected to a signal line other than the kth gate line Gk and the kth sensing line Sk.

17 is a circuit diagram showing an example of a gate driver according to an embodiment of the present invention. Referring to FIG. 17, a gate driver according to an embodiment of the present invention includes a plurality of stages for sequentially outputting gate signals. Each of the plurality of stages includes a pull-up node Q, an output control thin film transistor PUD, and a node control circuit NC.

The node control circuit (NC) controls the voltage of the pull-up node (Q) to a high-potential voltage or a low-potential voltage in response to a control signal input via a control terminal. For example, the node control circuit NC charges the pull-up node Q to a high potential voltage in response to a signal input through the first terminal TM1. The node control circuit NC can discharge the pull-up node Q to a low potential voltage in response to a signal input through the second terminal TM2.

The output control thin film transistor PUD is turned on when the pull-up node Q is charged with a high potential voltage and the first channel region CH1 is turned on so that the high potential voltage (or the clock terminal CLK ) Supplied through the clock signal line). The output control thin film transistor PUD discharges the output terminal OUT to a low potential when the pull-up node Q is charged with a low potential voltage, and the second channel region CH2 is turned on.

Each of the first gate electrode 110 and the second gate electrode 160 of the output control thin film transistor PUD is connected to the pull-up node Q and the first source electrode 141 and the second drain electrode 144 May be connected to the output terminal OUT and the first drain electrode 142 may be connected to the high potential voltage source VDD and the second source electrode 143 may be connected to the low potential voltage source VSS.

Up node and a pull-up node that is turned on when the pull-up node Q is charged with a high potential voltage and supplies a high potential voltage to the output terminal OUT, A gate signal is outputted using a pull-down transistor which is turned on and discharges the output terminal OUT to a low potential voltage. However, in the embodiment of the present invention, the first channel region CH1 having the N-type semiconductor characteristic serves as a pull-up transistor and the second channel region CH2 having the P- So that it is possible to output a gate signal by using one thin film transistor. Therefore, the embodiment of the present invention can eliminate the pull-down node and reduce the size of the thin film transistor. Thus, the embodiment of the present invention can reduce the size of the gate driver, and thus the size of the non-display area of the display device can be reduced when the gate driver is formed by the GIP method.

Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, it is to be understood that the present invention is not limited to those embodiments and various changes and modifications may be made without departing from the scope of the present invention. . Therefore, the embodiments disclosed in the present invention are intended to illustrate rather than limit the scope of the present invention, and the scope of the technical idea of the present invention is not limited by these embodiments. Therefore, it should be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of protection of the present invention should be construed according to the claims, and all technical ideas within the scope of equivalents should be interpreted as being included in the scope of the present invention.

10: thin film transistor 110: first gate electrode
111: light blocking layer 120: first gate insulating film
130: semiconductor layer 141: first source electrode
142: first drain electrode 143: second source electrode
144: second drain electrode 150: second gate insulating film
160: second gate electrode 170: interlayer insulating film
CNT: Contact hole CH1: First channel region
CH2: second channel region

Claims (21)

A first gate electrode disposed on the substrate;
A first gate insulating film covering the first gate electrode;
A semiconductor layer disposed on the first gate insulating film and including a stacked N-type semiconductor layer and a P-type semiconductor layer;
A second gate insulating film covering the semiconductor layer; And
And a second gate electrode disposed on the second gate insulating film,
A first channel region is formed in a region where the semiconductor layer and the first gate electrode are overlapped with each other, a second channel region is formed in a region where the semiconductor layer and the second gate electrode are overlapped,
The first channel region and the second channel region do not overlap with each other,
Wherein when the P-type semiconductor layer is disposed on the N-type semiconductor layer, the N-type semiconductor layer overlaps at least the first gate electrode, the P-type semiconductor layer overlaps at least the second gate electrode, The first channel region has an N-type semiconductor characteristic, the second channel region has a P-type semiconductor characteristic,
Type semiconductor layer, the N-type semiconductor layer overlaps at least the second gate electrode, the P-type semiconductor layer overlaps at least the first gate electrode, and the P- Wherein the first channel region has the P-type semiconductor characteristic and the second channel region has the N-type semiconductor characteristic. The method according to claim 1,
And the P-type semiconductor layer is disposed on the N-type semiconductor layer. delete delete The method according to claim 1,
And a light blocking layer disposed on the same layer as the first gate electrode and overlapping the second channel region. The method according to claim 1,
And first and second source electrodes and first and second drain electrodes disposed on the semiconductor layer. The method according to claim 6,
Wherein the first source electrode and the first drain electrode overlap the first gate electrode, and the second source electrode and the second drain electrode overlap the second gate electrode. The method according to claim 6,
Wherein at least one of the first and second source electrodes and the first and second drain electrodes comprises a metal material having a work function of 5.0 eV. The method according to claim 6,
And a connection electrode connecting the first drain electrode and the second drain electrode. The method according to claim 1,
An interlayer insulating film covering the second gate electrode; And
Further comprising first and second source electrodes and first and second drain electrodes disposed on the interlayer insulating film,
Wherein each of the first and second source electrodes and the first and second drain electrodes is connected to the semiconductor layer through a contact hole passing through the interlayer insulating layer and the second gate insulating layer. 11. The method of claim 10,
Wherein at least one of the first and second source electrodes and the first and second drain electrodes comprises a metal material having a work function of 5.0 eV. 11. The method of claim 10,
Wherein the first source electrode and the first drain electrode overlap the first gate electrode, and the second gate electrode is disposed between the second source electrode and the second drain electrode. 11. The method of claim 10,
And a connection electrode connecting the first drain electrode and the second drain electrode. The method according to claim 1,
Wherein the N-type semiconductor layer is made of an N-type oxide semiconductor layer, and the P-type semiconductor layer is made of a P-type oxide semiconductor layer. 15. The method of claim 14,
The P-type semiconductor layer is a thin film transistor, characterized in that consisting of Cu ₂ O. The method according to claim 1,
Wherein the N-type semiconductor layer is made of N-type polysilicon, and the P-type semiconductor layer is made of P-type polysilicon. Forming a first gate electrode on the substrate;
Forming a first gate insulating film covering the first gate electrode;
Forming a semiconductor layer including an N-type semiconductor layer and a P-type semiconductor layer stacked on the first gate insulating film;
Forming a second gate insulating film covering the semiconductor layer; And
And forming a second gate electrode on the second gate insulating film,
A first channel region is formed in a region where the semiconductor layer and the first gate electrode are overlapped with each other, a second channel region is formed in a region where the semiconductor layer and the second gate electrode are overlapped,
The first channel region and the second channel region do not overlap with each other,
Wherein when the P-type semiconductor layer is disposed on the N-type semiconductor layer, the N-type semiconductor layer overlaps at least the first gate electrode, the P-type semiconductor layer overlaps at least the second gate electrode, The first channel region has an N-type semiconductor characteristic, the second channel region has a P-type semiconductor characteristic,
Type semiconductor layer, the N-type semiconductor layer overlaps at least the second gate electrode, the P-type semiconductor layer overlaps at least the first gate electrode, and the P- Wherein the first channel region has the P-type semiconductor characteristic and the second channel region has the N-type semiconductor characteristic. 18. The method of claim 17,
Wherein forming the semiconductor layer comprises:
And the N-type semiconductor layer and the P-type semiconductor layer are continuously deposited under the same vacuum condition in the same chamber. A display panel including data lines, gate lines, and pixels disposed at intersections of the data lines and the gate lines;
A data driving circuit for supplying data voltages to the data lines; And
And a gate driving circuit for supplying gate signals to the gate lines,
Wherein each of the pixels includes the thin film transistor according to any one of claims 1, 2, and 5 to 16. A display panel including data lines, gate lines, and pixels disposed at intersections of the data lines and the gate lines;
A data driving circuit for supplying data voltages to the data lines; And
And a gate driving circuit for supplying gate signals to the gate lines,
The gate drive circuit includes:
A thin film transistor according to any one of claims 1 to 10;
A control node connected to the first and second gate electrodes of the thin film transistor; And
And a charge / discharge control unit for charging / discharging the voltage of the control node. 11. The method according to claim 6 or 10,
The N-type semiconductor layer is made of an N-type oxide semiconductor layer, the P-type semiconductor layer is made of a P-type oxide semiconductor layer,
Wherein the thickness of the P-type semiconductor layer is thinner than the thickness of the N-type semiconductor layer.

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