KR101820233B1 - Interconnection structure, fabricating method thereof, and semiconductor device using the same - Google Patents

Abstract

The semiconductor device includes a semiconductor substrate, a contact region on the semiconductor substrate, and a silicide on the texture surface of the contact region. There is a plurality of sputter ions between the silicide and the contact regions. Since the surface of the contact area is textured, the contact area provided by the silicide is accordingly increased, thus reducing the resistance of the interconnect structure of the semiconductor device.

Description

TECHNICAL FIELD [0001] The present invention relates to an interconnect structure, a method of manufacturing the same, and a semiconductor device using the same. BACKGROUND OF THE INVENTION [0002]

Related application

This application claims priority to U.S. Provisional Application No. 62 / 216,902, filed September 10, 2015, which is incorporated herein by reference.

The semiconductor integrated circuit (IC) industry has undergone rapid growth. Modern integrated circuits consist of literally millions of active devices such as transistors and capacitors. Technological advances in IC materials and design have created IC generations, with each generation having smaller and more complex circuits than previous generations. These devices are initially isolated from each other, but later interconnected via a plurality of metal layers to form functional circuits. As ICs become increasingly complex, interconnect structures are also becoming more complex, increasing the number of metal layers as a result.

The interconnect structure may include lateral interconnects, such as metal lines (interconnects), and vertical interconnects, such as conductive vias and contacts. However, complex interconnections limit the density and performance of modern integrated circuits.

The semiconductor device includes a semiconductor substrate, a contact region on the semiconductor substrate, and a silicide on the texture surface of the contact region. There is a plurality of sputter ions between the silicide and the contact regions. Since the surface of the contact area is textured, the contact area provided by the silicide is accordingly increased, thus reducing the resistance of the interconnect structure of the semiconductor device.

The aspects of the disclosure are best understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. Indeed, the dimensions of the various features may be increased or decreased arbitrarily to clarify the description.
Figures 1A-1E are schematic perspective views of a method of manufacturing a FinFET device at various stages in accordance with some embodiments of the present disclosure.
Figures 2a-2f are local cross-sectional views of a method of manufacturing an interconnect structure of a FinFET device.
3 is a partial cross-sectional view of an interconnect structure of some embodiments of the present disclosure;
Figures 4A-4F are schematic perspective views of a method of fabricating a semiconductor device at various stages in accordance with some embodiments of the present disclosure.
5 is a partial cross-sectional view of an interconnect structure of some embodiments of the present disclosure;

The following disclosure is to provide many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of devices and configurations are described below to simplify the present disclosure. These are, of course, merely examples and not intended to be limiting. For example, forming the first feature on or on the second feature in the following description may include an embodiment in which the first and second features are formed in direct contact, and the first and second features, 2 feature may be formed between the first feature and the second feature such that the feature is not in direct contact with the second feature. In addition, the present disclosure may repeat the reference numerals and / or characters in various examples. This repetition is for the sake of simplicity and clarity and does not in itself represent a relationship between the various embodiments and / or configurations described.

It will also be appreciated that spatially relative terms such as "under", "under", "under", "above", "above", etc., ) Or to describe the relationship to the feature (s). Spatially relative terms are intended to include different orientations of the device at the time of use or in operation, in addition to the orientations shown in the figures. The device can be oriented differently (90 degrees rotation or other orientation), and the spatially relative descriptor used herein can be interpreted accordingly.

As semiconductor device sizes continue to shrink, it becomes increasingly difficult to meet reliability requirements as well as conductivity requirements in multiple metallization fabrication. For example, the formation of interconnection structures that include conductive lines, interconnecting metal lines, and metal lines from different layers of an integrated circuit (IC) device generally require low resistance, since the conductive metal of the conductive via is an ILD A barrier layer is required to prevent diffusion into the layer. To lower the RC delay in the IC device, the barrier layer also serves to control the resistance of the interconnect. The present disclosure relates to a method of reducing the resistance of an interconnect structure in a semiconductor device such as a FinFET device.

Figures 1A-1E are schematic perspective views of a method of manufacturing a FinFET device at various stages in accordance with some embodiments of the present disclosure. Please refer to Fig. A substrate 110 is provided. In some embodiments, the substrate 110 can be a semiconductor material and include known structures including, for example, buried oxide or a gradient layer. In some embodiments, the substrate 110 comprises bulk silicon that may be undoped or doped (e.g., p-type, n-type, or a combination thereof). Other materials suitable for forming semiconductor devices may be used. Other materials such as germanium, quartz, sapphire, and glass may alternatively be used for the substrate 110. Alternatively, the silicon substrate 110 may be a multilayer structure, such as a silicon-germanium layer formed on the active layer or bulk silicon layer of a semiconductor-on-insulator (SOI) substrate.

A plurality of p-well regions 116 and a plurality of n-well regions 112 are formed in the substrate 110. One of the n well regions 112 is formed between two of the p well regions 116. The p well region 116 is implanted with a P dopant material such as boron ions and the n well region 112 is implanted with an N dopant material such as arsenic ions. During implantation of the p-well region 116, the n-well region 112 is covered with a mask (such as a photoresist) and during implantation of the n-well region 112, the p-well region 116 ) Mask.

A plurality of semiconductor fins 122 and 124 are formed on the substrate 110. A semiconductor pin 122 is formed on the p-well region 116 and a semiconductor fin 124 is formed on the n-well region 112. [ In some embodiments, the semiconductor pins 122 and 124 comprise silicon. It should be noted that the number of semiconductor pins 122, 124 in FIG. 1A is exemplary and should not limit the claimed scope of the disclosure. Those of ordinary skill in the art will be able to select an appropriate number for semiconductor pins 122 and 124, depending on the actual situation.

The semiconductor pins 122 and 124 may be formed by patterning and etching the substrate 110 using, for example, photolithographic techniques. In some embodiments, a layer of photoresist material (not shown) is deposited over the substrate 110. A layer of photoresist material is irradiated (exposed) according to the desired pattern (in this case, semiconductor pins 122 and 124) and developed to remove a portion of the photoresist material. The remaining photoresist material protects the underlying material from subsequent processing steps such as etching. It should be noted that other masks such as oxides or silicon nitride masks may also be used in the etching process.

A plurality of isolation structures (130) are formed on the substrate (110). Isolation structures 130 acting as shallow trench isolation (STI) around semiconductor pins 122 and 124 are formed by chemical vapor deposition (CVD) using tetra-ethyl-ortho-silicate (TEOS) or chemical vapor deposition techniques. In some other embodiments, isolation structure 130 is an insulator layer of an SOI wafer.

See FIG. 1B. At least one dummy gate 142 is formed on a portion of the semiconductor fin 122, 124 and exposes another portion of the semiconductor fin 122, 124. The dummy gate 142 may be formed to cross the plurality of semiconductor fins 122 and 124. A plurality of gate spacers 140 are formed over the substrate 110 and along the side of the dummy gate 142. In some embodiments, the gate spacers 140 may comprise silicon oxide, silicon nitride, silicon oxynitride, or other suitable material. The gate spacer 140 may comprise a single layer or multi-layer structure. A blanket layer of gate spacer 140 may be formed by CVD, PVD, ALD, or other suitable technique. Anisotropic etching is then performed on the front layer to form a pair of gate spacers 140 on the two sides of the dummy gate 142. In some embodiments, the gate spacers 140 are used to offset subsequent formed doped regions, such as source / drain regions. The gate spacers 140 may further be used to design or modify the source / drain region (junction) profile.

See FIG. The portions of the semiconductor fins 122 and 124 that are both exposed by the dummy gate 142 and the gate spacer 140 are partially removed to form the trench 126 in the semiconductor fins 122 and 124 Trenched). In some embodiments, the trench 126 is formed as a dielectric fin side wall structure 125 as its upper portion. In some embodiments, the sidewalls of the trenches 126 are substantially vertical and parallel to one another. In some other embodiments, the trenches 126 are formed in a profile that is not vertically parallel.

1C, the semiconductor fin 122 includes at least one trenched portion 122r and at least one channel portion 122c. The trench 126 is implanted on the trenched portion 122r and the dummy gate 142 covers a portion of the channel portion 122c. The semiconductor pin 124 includes at least one trenched portion 124r and at least one channel portion 124c. Trench 126 is formed on trenched portion 124r and dummy gate 142 covers a portion of channel portion 124c.

The trench formation process may include a dry etch process, a wet etch process, and / or a combination thereof. The trench formation process may also include selective wet etching or selective dry etching. The wet etch solution includes tetramethylammonium hydroxide (TMAH), HF / HNO ₃ / CH ₃ COOH solution, or other suitable solution. The dry and wet etch processes can be adjusted to provide adjustable etch parameters such as etchant, etch temperature, etch solution concentration, etch pressure, source power, RF bias voltage, RF bias power, etchant flow rate, . For example, the wet etch solution may comprise NH ₄ OH, KOH (potassium hydroxide), HF (hydrofluoric acid), tetramethylammonium hydroxide (TMAH), other suitable wet etching solutions, or combinations thereof. The dry etch process includes a biased plasma etch process using chlorine-based chemicals. Other dry etchant gases include CF ₄ , NF ₃ , SF ₆ , and He. Dry etching can also be performed anisotropically using a mechanism such as deep reactive-ion etching (DRIE).

See FIG. A plurality of epitaxial structures 160 are each formed in the trench 126 of the semiconductor fin 124 and a plurality of epitaxial structures 150 are formed in the trench 126 of the semiconductor fin 122, The epitaxial structure 160 is separated from the adjacent epitaxial structure 150. The epitaxial structure 150 protrudes from the trench R. The epitaxial structure 160 may be an n-type epitaxial structure and the epitaxial structure 150 may be a p-type epitaxial structure. The epitaxial structures 150 and 160 may be formed using one or more epitaxial or epitaxial processes so that Si features, SiGe features, and / 124). ≪ / RTI > In some embodiments, the lattice constants of the epitaxial structures 150 and 160 are different from the lattice constants of the semiconductor fins 122 and 124, and the epitaxial structures 150 and 160 enable the carrier mobility of the SRAM device And strained and strained to improve device performance. The epitaxial structures 150 and 160 may comprise a semiconductor material such as germanium (Ge) or silicon (Si); Or a compound semiconductor material such as GaAs, AlGaAs, SiGe, SiC, or GaAsP.

In some embodiments, epitaxial structures 150 and 150 are formed with different epitaxial processes. The epitaxial structure 160 may comprise SiGe, SiGeC, Ge, Si, Si (III), SiC, SiC, Si, III-V compound semiconductor materials, or combinations thereof. -V compound semiconductor material, or a combination thereof. During the formation of the epitaxial structure 160, n-type impurities such as phosphorous or arsenic can be doped with the progress of the epitaxy. For example, when the epitaxial structure 160 comprises SiC or Si, an n-type impurity is doped. Also, during the formation of the epitaxial structure 150, p-type impurities such as boron or BF ₂ may be doped with the progress of the epitaxy. For example, when the epitaxial structure 150 comprises SiGe, the p-type impurity is doped. The epitaxial process may be performed using CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy and / Process. The epitaxial process may use a gas and / or a liquid precursor that reacts with the composition of the semiconductor fins 122 and 124 (e.g., silicon). Thus, a modified channel can be achieved to increase carrier mobility and improve device performance. The epitaxial structures 150 and 160 may be in-situ doped. If the epitaxial structures 150 and 160 are not doped in-situ, a second implantation process (i. E., A junction implant process) is performed to dope the epitaxial structures 150 and 160. One or more annealing processes may be performed to activate the epitaxial structures 150 and 160. The annealing process includes rapid thermal annealing (RTA) and / or laser annealing processes.

In some embodiments, the epitaxial structure 150 has a body portion disposed between the top portion and the top portion and the substrate 110. The width of the upper portion is wider than the width of the body portion. The epitaxial structure 160 has a body portion disposed between the upper portion and the upper portion and the substrate 110. The width of the upper portion is wider than the width of the body portion. The epitaxial structures 150 and 160 are used as the source / drain electrodes of the FinFET device 100.

In some embodiments, the epitaxial structures 150 and 160 have different shapes. The upper portion of the epitaxial structure 160 may have at least a substantially facet surface present on the isolation structure 130 and the upper portion of the epitaxial structure 150 may be present on the isolation structure 130 At least one non-facet (or rounded) surface that does not limit the scope of the invention.

See FIG. After the epitaxial structures 150 and 160 are formed, the dummy gate 142 is removed, and thus a trench is formed between the gate spacers 140. A portion of isolation structure 130 and semiconductor pins 122 and 124 is exposed from the trenches. The dummy gate 142 may be removed by performing one or more etch processes. A gate stack 170 is formed to fill the trenches. The gate stack 170 includes a gate electrode and a gate dielectric disposed between the gate electrode and the isolation structure 130. The gate dielectric and the gate electrode may each be formed by a deposition process such as an ALD process, a CVD process, a PVD process, or a sputter deposition process. The gate dielectric is made of a dielectric material, such as silicon nitride, silicon oxynitride, a dielectric with a high dielectric constant (high-k), and / or combinations thereof. In some embodiments, the gate electrode is a metal electrode. In some embodiments, the gate stack 170 further includes a cap layer on the gate electrode.

After the FinFET device 100 is fabricated, an interconnect structure is formed to interconnect the electrodes of the FinFET device to other devices. The details of fabricating the interconnection structure are illustrated in Figures 2A-2F, and Figures 2A-2F are local cross-sectional views of a method of fabricating an interconnection structure in a FinFET device.

Please refer to FIG. A dielectric layer 220 is formed on the FinFET device. Dielectric layer 220 covers epitaxial structure 210 and fin 120 around epitaxial structure 210. The pin 120 may be any one of the pins 122 and 124 of Figure ID and the epitaxial structure 210 may be any one of the epitaxial structures 150 and 160 as illustrated in Figure ≪ / RTI > Dielectric layer 220 may be an interlayer dielectric (ILD) and may include an oxide material or a low k material. The dielectric layer 220 may be formed by, for example, a chemical vapor deposition (CVD) processing step, a spin-on processing step, or a combination thereof. A dielectric layer 220 is provided to isolate the conductive features formed on the different layers and / or the same layer.

An opening 222 is formed in the dielectric layer 220. In some embodiments, there are a plurality of openings formed in the dielectric layer 220. The opening 222 may be, for example, a contact opening, a via opening, a single damascene opening, a dual damascene opening, or a combination thereof. The opening 222 may be formed, for example, by forming a patterned photoresist layer (not shown) over the dielectric layer 220 and etching the patterned photoresist layer (not shown) as a mask using a dry etch processing step And removing the portion of the dielectric layer 220 to define the opening 222 by use. A variety of suitable dry etch processes may be used. After the dry etch processing step, the patterned photoresist layer (not shown) is removed, for example, by a photolithographic removal process. A portion of the epitaxial structure 210 is also removed during formation of the opening 222. An oxide layer 212 is formed on the surface of the epitaxial structure 210 when the epitaxial structure 210 is exposed and reacting with air.

Referring to FIG. 2B, a removal process is performed to remove the oxide layer 212 present on the exposed epitaxial structure 210. The removal process may be a physical removal process such as a sputter process. During the physical removal process, energetic ions 214 bombard the exposed portions of the epitaxial structure 210 and erode the oxide layer 212 thereon. The energy ions 214 may be, for example, argon (Ar) ions, neon (Ne) ions, krypton (Kr), or xenon (Xe) ions.

The oxide layer 212 and the particles of the epitaxial structure 210 are dislodged due to the impact of the energy ions 214. The remaining oxide layer 212 is broken and discontinuous after the removal process. Dislodgement of the oxide layer 212 and the particles of the epitaxial structure 210 results in a rough and irregular surface of the epitaxial structure 210. In some embodiments, a plurality of recesses R are formed on top of the epitaxial structure 210. The recesses R are randomly arranged on the surface of the epitaxial structure 210. The density of the recesses R on the surface of the epitaxial structure 210 is also made random. Each depth of the recesses R ranges from about 1.5 nm to about 3.5 nm and the depth difference of the recesses R ranges from about 0.5 nm to about 3 nm, . In some embodiments, the RF power of the sputter process is higher than 500 W and the depth difference of the recess R on the epitaxial structure 210 is in the range of about 1.5 nm to about 3 nm. In some embodiments, the RF power of the sputter process is lower than 400 W, and the depth difference of the recess (R) ranges from about 0.5 nm to about 1.5 nm. The depth difference of the p-type FinFET device is about 2 nm to about 2 nm more than in the case of the n-type FinFET due to the etching rate of the p-type epitaxial structure such as SiGe being larger than the etching rate of the n-type epitaxial structure, It is about 20 nm higher.

During the physical removal process, a portion of energy ions 214, such as argon (Ar) ions, neon (Ne), krypton (Kr), or xenon (Xe) ions, 0.0 > 210 < / RTI > The distribution including the depth, density, or amount of ions 214 present on the surface of the epitaxial structure 210 is random and irregular. The distribution of ions 214 may be related to the RF power providing energy ions 214.

See FIG. 2C. The oxide layer 212 (as shown in Figure 2B) remaining on the epitaxial structure 210 is removed by performing a chemical removal process. The chemical removal process may be performed by using a chemical mixture comprising NF ₃ and NH ₃ . However, other suitable chemicals for removing the oxide layer 212 without destroying the epitaxial structure 210 may be used in the chemical removal process.

The oxide layer 212 is removed by performing both a physical removal process and a chemical removal process. The physical removal process is used to texture the surface of the epitaxial structure 210 to form a rough and irregular surface of the epitaxial structure 210. A recess R is formed on the surface of the epitaxial structure 210 and a small amount of ions 214 are ejected into the epitaxial structure 210 during the physical removal process. The surface area of the epitaxial structure 210 is increased due to the presence of the recess R. A chemical removal process is used to remove the oxide layer 212. The ions 214 are not reactive with the chemical and are still present in the epitaxial structure 210 after the chemical removal process is performed.

See Figure 2D. A metal layer 230 is formed over the dielectric layer 220 to lining the sidewalls and bottom of the opening 222. In some embodiments, the metal layer 230 may be a metal alloy layer. The metal layer 230 includes a metal for use in self-aligned silicide (salicide) technology such as titanium (Ti), cobalt (Co), nickel (Ni), platinum (Pt), or tungsten . The metal layer 230 is formed by a deposition process such as a CVD process, a PVD process, or a sputter deposition process.

A barrier layer 240 is further formed on the metal layer 230. The barrier layer 240 may serve as a barrier to prevent the subsequently formed conductor from diffusing into the underlying dielectric layer 220. In some embodiments, the barrier layer 240 includes tantalum (Ta), titanium (Ti), and the like. In some embodiments, the barrier layer 240 has a thickness of from about 10 angstroms to about 250 angstroms. In some embodiments, the combined thickness of metal layer 230 and barrier layer 240 is less than about 120 angstroms to prevent gap fill issues during subsequent open filling processes. The barrier layer 240 is deposited by using PVD, CVD, PECVD, LPCVD, or other well known deposition techniques.

See FIG. 2E. An annealing process is performed to form the silicide 250 on the epitaxial structure 210. The annealing process is used to convert the amorphous silicide film to a lower resistance polycrystalline phase. Salicide processes are sometimes used to form silicide contacts in the source and drain regions to solve the problem of critical dimension tolerances. In some embodiments, the metal layer is a titanium layer and is annealed to be titanium silicide 250. The annealing process is performed to form a high-resistance Ti rich phase, and the thickness of the titanium silicide ranges from about 30 angstroms to about 160 angstroms. In some embodiments, the titanium silicide 250 may be TiSi ₂ because the epitaxial structure 210 is an n-type epitaxial structure. In some embodiments, the titanium silicide 250 may be TiSiGe, since the epitaxial structure 210 is a p-type epitaxial structure.

The interface between the epitaxial structure 210 and the silicide 250 is irregular and rough because the surface of the epitaxial structure 210 is textured and the recess R is formed on the epitaxial structure 210, The surface area of the epitaxial structure 210 in contact with the silicide 250 is accordingly increased. Ions 214 from the physical removal process remain in the silicide 250. The depth difference at the interface between the epitaxial structure 210 and the silicide 250 ranges from about 1.5 nm to about 3.5 nm.

See Figure 2f. A conductor 260 is formed over the barrier layer 240 to fill the opening 222. In some embodiments, the conductors 260 are formed as interconnect structures in the dielectric layer 220. In some embodiments, the conductor 260 is formed by a deposition process, such as a CVD process, a PVD process, or a sputter deposition process. In some embodiments, the conductor 260 comprises tungsten (W), copper (Cu), or cobalt (Co).

The bottom of the metal layer 230 is reacted with the epitaxial structure 210 and becomes the silicide 250. The remaining metal layer 230 is between the barrier layer 240 and the sidewalls of the opening 222 and is not present between the silicide 250 and the barrier layer 240. That is, the bottom of the barrier layer 240 is in direct contact with the silicide 250, thus reducing the contact resistance of the interconnect structure.

A portion of the conductor 260 on the dielectric layer 220 is removed. In some embodiments, the removal process is performed to remove excess portions of conductor 260, barrier layer 240, and metal layer 230 outside opening 222, thus exposing the upper surface of dielectric layer 220 And a planarized surface is achieved.

An interconnect structure comprising conductor 260 and silicide 250 is formed in dielectric layer 230 and is connected to epitaxial structure 210. As the interface between the silicide 250 and the epitaxial structure 210 becomes coarse and irregular, the contact area therebetween increases accordingly. Thus, the resistance of the interconnect structure is reduced due to the increased contact area.

Reference is now made to Fig. 3, which is a local cross-sectional view of the interconnect structure of some other embodiments of the present disclosure. The pin 120 may have a plurality of epitaxial structures 210 thereon. As described in Figures 2A-2F, the physical removal process and the chemical process are performed to texture the surface of the epitaxial structure 210 and remove the oxide layer on the exposed portion of the epitaxial structure 210 . The resulting epitaxial structure 210 forms a top surface such as a mountain and the depth difference of the top surface of the epitaxial structure 210 is greater than that of the single epitaxial structure 210. For example, the depth difference of the top surface of the epitaxial structure 210 ranges from about 3 nm to about 25 nm, which corresponds to the RF power generating the energy ions 214. In some embodiments, the RF power of the sputter process is higher than 500 W and the depth difference of the surface of the epitaxial structure 210 is in the range of about 15 nm to about 25 nm. In some embodiments, the RF power of the sputter process is lower than 400 W, and the depth difference of the surface of the epitaxial structure 210 is in the range of about 3 nm to about 15 nm.

The thickness of the silicide 250 between the barrier layer 240 and the epitaxial structure 210 is not uniform and the width of each epitaxial structure 210 is not the same. The difference between adjacent epitaxial structures 210 is from about 3 nm to about 20 nm. The difference in thickness of the silicide 250 ranges from about 3 nm to about 25 nm.

The above-described interconnect structures are not limited to those used in a FinFET device having an epitaxial structure, but may be used in any suitable semiconductor device having a silicide contact. For example, the interconnection structure described above can be used, for example, in a nanowire component, as described in Figures 4A-4F.

4A to 4F. Figures 4A-4F are schematic perspective views of a method of fabricating a semiconductor device at various stages in accordance with some embodiments of the present disclosure. Referring to FIG. 4A, the method begins with a semiconductor-on-insulator (SOI) structure 310. The SOI structure 310 includes a semiconductor substrate 312, a buried oxide (BOX) layer 314, and an SOI layer 316. In some embodiments, the SOI layer 316 is formed from a semiconductor material such as silicon. BOX layer 314 may comprise silicon oxide, silicon nitride, or silicon oxynitride. A BOX layer 314 is present between the semiconductor substrate 312 and the SOI layer 316. More specifically, a BOX layer 314 may be under the SOI layer 316 and above the semiconductor substrate 312, and the BOX layer 314 may be formed by implanting a high energy dopant into the SOI structure 310 And then annealing the structure to form a buried oxide layer. In some other embodiments, the BOX layer 314 may be deposited or grown prior to formation of the SOI layer 316. In still other embodiments, the SOI structure 310 may be formed using wafer bonding techniques, wherein the bonded wafer pair is formed using a glue, adhesive polymer, or direct bonding.

See FIG. 4B. SOI layer 316 is patterned to form pads 322, 324, 326, and 328 and connection structures 332 and 334. For example, the pads 322, 324, 326, and 328 and the connection structures 332 and 334 may be fabricated using suitable processes such as photolithography and etching. The connection structure 332 connects the pads 322 and 324. The connection structure 334 connects the pads 326 and 328. In other words, at least one of the connection structures 332 may have separate pads 322 and 324 on its opposite side and at least one of the connection structures 334 may have separate pads 326 and 328 on its opposite side, Lt; / RTI >

4C. The connection structures 332 and 334 are partially removed to form a first nanowire 342 and a second nanowire 344. In some embodiments, the lower portion of the connection structures 332 and 334 and the lower portion of the BOX layer 314 are removed by an isotropic etching process so that the first nanowire 342 is between the pads 322 and 324 And a second nanowire 344 is formed between the pads 326 and 328 in a floating state. Isotropic etching is a type of etching that does not include a preferential direction. One example of isotropic etching is wet etching. The isotropic etch process forms an undercut region in which the first and second nanowires 342 and 344 are suspended above. In some embodiments, isotropic etching may be performed using diluted hydrofluoric acid (DHF). After the isotropic etching process, the first and second nanowires 342 and 344 may be smoothed to form an elliptical (and in some cases, cylindrical) configuration. In some embodiments, the smoothing process may be performed by an annealing process. The exemplary annealing temperature may range from about 600 ° C to about 1000 ° C, and the hydrogen pressure in the annealing process may range from about 7 torr to about 600 torr.

4D. Spacers 352 are formed on the opposing sidewalls of the dummy gate material layer 362 and spacers 354 are formed on the opposing sidewalls of the dummy gate material layer 364. [ The method of forming the spacers 352 and 354 includes forming an dielectric layer and then performing an etching process to remove a portion of the dielectric layer.

Following formation of spacers 352 and 354, an n-type dopant may be introduced into the exposed portion of first nanowire 342 adjacent spacer 352 to form an n-type source / drain extension region. Likewise, a p-type dopant may be introduced into the exposed portion of the second nanowire 344 adjacent to the spacer 354 to form a p-type source / drain extension region. Examples of p-type dopants may include, but are not limited to, boron, aluminum, gallium, and indium. Examples of n-type dopants include, but are not limited to, antimony, arsenic, and phosphorus.

In some embodiments, the source / drain extension region may be formed by an in situ doping epitaxial growth process followed by a first nanowire 342 and a second nanowire 344 to provide an extension region. Is formed in the first nanowire 342 and the second nanowire 344 using an annealing process to drive the dopant from the first nanowire 342 and the second nanowire 344. [ In some embodiments, the in-situ doping semiconductor material is formed using an epitaxial growth process. "In-situ doping" means that the dopant is incorporated into the in-situ doped semiconductor material during the epitaxial growth process to deposit the semiconductor-containing material of the in-situ doping semiconductor material. When the chemical reactants are controlled, the film-forming atoms reach the surfaces of the first and second nanowires 342 and 344 and the pads 322, 324, 326 and 328 with sufficient energy to penetrate the surface, Aligns itself with the crystal arrangement of FIG. Epitaxial growth may be achieved by depositing portions of first nanowires 342 and second nanowires 344 that are not covered by dummy gate material layers 362 and 364 and spacers 352 and 354 and portions of pads 322, 326 and 328 are thickened.

Thereafter, ion implantation may be performed on the pads 322, 324, 326 and 328 to form a deep source / drain region. The deep source / drain regions may be formed using ion implantation. During ion implantation that provides a deep source / drain region, portions of the device that are not desired to be implanted may be protected by a mask such as a photoresist mask. The deep source / drain regions of the pads 322 and 324 have the same conductive dopant as the source / drain extension regions of the first nanowire 342, such as an n-type dopant, The drain region has a larger dopant concentration than the source / drain extension region of the first nanowire 342. Similarly, the deep source / drain regions of the pads 326 and 328 have the same conductive dopant as the source / drain extension regions of the second nanowire 344, such as a p-type dopant, The source / drain region has a larger dopant concentration than the source / drain extension region of the second nanowire 344. [

See FIG. 4E. An interlayer dielectric (ILD) layer 370 is formed to cover the dummy gate material layers 362 and 364, the first nanowire 342, and the second nanowire 344. The ILD layer 370 may comprise silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, a low-k dielectric material, or a combination thereof. The ILD layer 370 may be formed by a deposition process such as a CVD process. A portion of the ILD layer 370 is then removed to expose the upper surface of the dummy gate material layer. The removing step may include performing a chemical-mechanical polishing (CMP) process. The dummy gate material layer is further removed by using a suitable process such as wet etching. After removal of the dummy gate material layer a first trench 382 is formed between the spacers 352 and a second trench 384 is formed between the spacers 354 and the first and second trenches 382 and 384 Are spatially isolated from each other by the spacers 352 and 354 and the ILD layer 370. [

4f. Gate stacks 390 and 392 are formed to fill the trenches 382 and 384. The gate stacks 390 and 392 each include a gate dielectric surrounding the nanowire, a gate electrode surrounding the gate dielectric, and a cap layer surrounding the gate electrode.

After the semiconductor device 300 is formed, a plurality of interconnect structures are formed in the ILD layer 370 to connect to the pads 322, 324, 326, and 328. A cross-sectional view of the interconnect structure and pad is illustrated in FIG.

As shown in FIG. 5, an interconnect structure 400 is formed in the ILD layer 370 and contacts the pad 320. The pad 320 may be any one of the pads 322, 324, and 326 and 328. The interconnect structure 400 includes a metal layer 410, a silicide layer 420, a barrier layer 430, and a conductor 440. The details of fabricating the interconnect structure 400 are substantially the same as those described in Figures 2A-2G. After the openings are formed in the ILD layer 370, the exposed portions of the pad 320 are textured by performing a physical removal process, such as a sputter process. Some of the reactive ions 412 for the sputter process, such as Ne, Ar, Kr, Xe, stay on the surface of the pad 320. A metal layer 410 is deposited on the opening of the ILD layer 370 and the bottom of the metal layer is reacted with the pad 320 to become the silicide 320. [ The ions 412 remain in the silicide 420. The metal layer 410 is between the barrier layer 430 and the sidewall of the ILD layer 370 and is not present between the barrier layer 430 and the silicide 420. The barrier layer 430 is in direct contact with the silicide 420. A conductor 440 is formed filling the opening.

The surfaces of the contact regions, such as epitaxial structures and semiconductor pads, are textured by performing a physical removal process. Some of the ions used in the physical removal process remain in the contact area. The contact region is reacted with the metal layer deposited thereon to form a silicide therebetween. As the surface of the contact region is textured, the contact region provided by the silicide is accordingly increased, thus reducing the resistance of the interconnect structure.

According to some embodiments of the present disclosure, a semiconductor device includes a semiconductor substrate, a contact region in the semiconductor substrate, and a silicide on the contact region. The contact region includes a textured surface, and a plurality of sputter residues are present between the silicide and the contact regions.

According to some other embodiments of the present disclosure, a silicide on the contact region, a conductor on the silicide, and a barrier layer between the conductor and the silicide are included. The interface between the contact region and the silicide is textured and a plurality of sputter residues are present in the silicide.

According to some other embodiments of the present disclosure, a method of fabricating an interconnect structure includes forming an opening in a dielectric layer to expose a portion of a contact region, performing a physical removal process to texture the surface of the contact region, Forming a metal layer on the texture surface of the contact region, forming a barrier layer on the metal layer, and performing an annealing process, wherein the metal layer is reacted with the contact region, To form a silicide therebetween.

The foregoing presents features of various embodiments in order that those skilled in the art may better understand aspects of the disclosure. Those skilled in the art will readily appreciate that the present disclosure can readily be used as a basis for designing or modifying other processes and structures to accomplish the same purpose and / or to achieve the same advantages as the embodiments disclosed herein You should know. It should be understood by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of this disclosure and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the disclosure.

Claims (10)

A semiconductor device comprising:
A semiconductor substrate;
A contact region within the semiconductor substrate, the contact region including a textured surface;
A silicide on the contact region; And
A plurality of residues at the interface between the silicide and the contact region
/ RTI >
Wherein the contact region is an epitaxial structure or a semiconductor pad. The semiconductor device of claim 1, wherein the residue is an argon (Ar) ion, a neon (Ne) ion, a krypton (Kr), or a xenon (Xe) ion. delete delete The semiconductor device of claim 1, wherein the interface between the silicide and the contact region is irregular. The semiconductor device of claim 1, further comprising a dielectric layer on the semiconductor substrate, wherein the dielectric layer includes an opening to expose a portion of the silicide. The method of claim 6,
A conductor filling said opening; And
And a barrier layer on the sidewalls of the opening and on the silicide. The method of claim 7,
Further comprising a metal layer between the barrier and the sidewall of the opening, wherein the metal layer is not between the silicide and the barrier layer. In the interconnect structure,
A silicide on the contact region, the interface between the contact region and the silicide being textured, and a plurality of residues being at the interface between the contact region and the silicide;
A conductor on the silicide; And
A barrier layer between the conductor and the silicide
/ RTI >
Wherein the contact region is an epitaxial structure or a semiconductor pad. A method of manufacturing an interconnect structure,
Forming an opening in the dielectric layer to expose a portion of the contact region;
Performing a physical removal process to texture the surface of the contact area;
Forming a metal layer on a textured surface of the contact region;
Forming a barrier layer on the metal layer; And
Performing the annealing process
Lt; / RTI >
The metal layer reacts with the contact region to form a silicide between the contact region and the barrier layer,
Wherein a plurality of residues are at the interface between the contact region and the silicide,
Wherein the contact region is an epitaxial structure or a semiconductor pad.

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