KR101818461B1 - Display device - Google Patents

Abstract

The present invention relates to a display device having a multiplexer capable of minimizing a luminance deviation between pixels by equalizing the charging characteristics between pixels, the display device comprising: a data driver for outputting image data; And a plurality of first switching elements for maintaining a turn-on state for a first period of one horizontal period and a plurality of second switching elements for maintaining a horizontal A multiplexer including a plurality of second switching elements that maintain a turn-on state during a second period of the period; And data lines of the same kind to which pixels displaying at least one kind of color of the same pattern are connected are connected to only one kind of the switching elements of the first switching elements and the second switching elements.

Description

Display device {DISPLAY DEVICE}

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a display device, and more particularly, to a display device having a multiplexer capable of minimizing a luminance deviation between pixels by making charge characteristics between pixels the same.

A multiplexer provided in a conventional display device supplies image data using two kinds of switching elements which are turned on in different periods between pixels of the same color. As a result, the charging time points of the pixels of the same color are different from each other, causing a luminance deviation between the pixels. The luminance deviation between such pixels leads to image quality deterioration.

SUMMARY OF THE INVENTION The present invention has been made in order to solve the problems described above, and it is an object of the present invention to provide a liquid crystal display device capable of preventing luminance deviation between pixels by connecting at least one kind of data lines having the same characteristics to switching elements turned on in the same period The present invention provides a display device including a multiplexer.

According to an aspect of the present invention, there is provided a display device having a multiplexer including a data driver for outputting image data; And a plurality of first switching elements for maintaining a turn-on state for a first period of one horizontal period and a plurality of second switching elements for maintaining a horizontal A multiplexer including a plurality of second switching elements that maintain a turn-on state during a second period of the period; And data lines of the same kind to which pixels displaying at least one kind of color of the same pattern are connected are connected to only one kind of the switching elements of the first switching elements and the second switching elements.

The pixels comprising a plurality of red pixels for displaying a red image, a plurality of green pixels for displaying a green image and a plurality of blue pixels for displaying a blue image; The plurality of data lines may include a plurality of red data lines connected to the plurality of red pixels, a plurality of green data lines connected to the plurality of green pixels and a plurality of blue data lines connected to the plurality of blue pixels, Data lines; The data lines of at least one of the red, green, and blue data lines are connected to only one of the first and second switching elements.

Data lines of any one of the red, green, and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; Data lines of any one of the red, green and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; The data lines of the other one of the red, green, and blue data lines are connected to the first and second switching elements in a divided manner.

Th data lines are the green data lines, and the (3n + 3) th data lines are the blue data lines. Lines; The plurality of first switching elements may include a plurality of first switching elements independently connected to each of the (3n + 1) th data lines and a plurality of first switching elements independently connected to some of the data lines of the (3n + A plurality of first switching elements; The plurality of second switching elements may include a plurality of second switching elements independently connected to each of the (3n + 2) th data lines and a plurality of second switching elements independently connected to the remaining data lines of the (3n + A plurality of second switching elements; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver; A second switching element connected to the (6n + 3) th data line and a first switching element connected to the (6n + 4) th data line are connected in common to one of the output channels of the data driver; The second switching element connected to the (6n + 5) th data line and the first switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver .

Th data lines are the green data lines, and the (3n + 3) th data lines are the blue data lines. Lines; The plurality of first switching elements may include a plurality of first switching elements independently connected to each of the (3n + 1) th data lines and a plurality of first switching elements independently connected to some of the data lines of the (3n + A plurality of first switching elements; The plurality of second switching elements may include a plurality of second switching elements independently connected to each of the (3n + 2) th data lines and a plurality of second switching elements independently connected to the remaining data lines of the (3n + A plurality of second switching elements; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver; A second switching element connected to the (6n + 3) th data line and a first switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver; The second switching element connected to the (6n + 4) -th data line and the first switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver .

The (6n + 3) th data lines of the (3n + 3) th data lines are connected to the respective second switching elements; The (6n + 6) th data lines among the (3n + 3) th data lines are connected to the first switching elements.

Data lines of any one of the red, green, and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; Data lines of any one of the red, green and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; And data lines of the other one of the red, green and blue data lines are directly connected to each of the output channels of the data driver independently.

Th data lines are the green data lines, and the (3n + 3) th data lines are the blue data lines. Lines; The plurality of first switching elements includes a plurality of first switching elements independently connected to each of the (3n + 1) th data lines; The plurality of second switching elements includes a plurality of second switching elements independently connected to each of the (3n + 2) th data lines; Each of the (3n + 3) -th data lines is directly and independently connected to each of the output channels of the data driver; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver; The first switching device connected to the (6n + 4) th data line and the first switching device connected to the (6n + 5) th data line are connected in common to one of the output channels of the data driver .

The same image data is supplied to the (3n + 3) th data line during the first period and the second period, or the different image data is supplied during the first period and the second period.

Wherein the multiplexer further comprises a plurality of first dummy switching elements that maintain a turn-on state during the first period and a plurality of second dummy switching elements that maintain a turn-on state during the second period; Data lines of any one of the red, green, and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; Data lines of any one of the red, green and blue data lines are connected to the switching elements of any one of the first switching elements and the second switching elements; The data lines of the other one of the red, green, and blue data lines are connected to the first dummy switching elements and the second dummy switching elements, respectively.

Th data lines are the green data lines, and the (3n + 3) th data lines are the blue data lines. Lines; The plurality of first switching elements includes a plurality of first switching elements independently connected to each of the (3n + 1) th data lines; The plurality of second switching elements includes a plurality of second switching elements independently connected to each of the (3n + 2) th data lines; Each of the (3n + 3) th data lines is dividedly connected to the first dummy switching elements and the second dummy switching elements; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver; A first switching device connected to the (6n + 4) th data line and a first switching device connected to the (6n + 5) th data line are connected in common to one of the output channels of the data driver; And the first dummy switching elements and the second dummy switching elements connected to the (3n + 3) th data lines are independently connected to arbitrary output channels of the data driver.

The (6n + 3) th data lines of the (3n + 3) th data lines are connected to the respective second dummy switching elements; The 6n + 6th data lines among the 3n + 3th data lines are connected to the first dummy switching elements, respectively.

The pixels comprising a plurality of red pixels for displaying a red image, a plurality of green pixels for displaying a green image and a plurality of blue pixels for displaying a blue image; Wherein the plurality of data lines includes a plurality of red / blue data lines divided by the plurality of red and blue pixels, a plurality of green / red data lines dividedly connected with the plurality of green and red pixels, And a plurality of blue / green data lines to which the green pixels are connected in series; At least one of the data lines of the red / blue, green / red, and blue / green data lines is connected to only one of the first and second switching elements .

Wherein the multiplexer further comprises a plurality of first dummy switching elements that maintain a turn-on state during the first period; Wherein any one of the data lines of the red / blue, green / red, and blue / green data lines is connected to any one of the first switching elements and the second switching elements; The other one of the red / blue, green / red, and blue / green data lines is connected to any one of the first switching elements and the second switching elements; The other one of the red / blue, green / red, and blue / green data lines is connected to the first dummy switching elements.

(3n + 2) th data lines are the green / red data lines, and the (3n + 2) th data lines are the red / Are the blue / green data lines; The plurality of first switching elements includes a plurality of first switching elements independently connected to each of the (3n + 1) th data lines; The plurality of second switching elements includes a plurality of second switching elements independently connected to each of the (3n + 2) th data lines; The plurality of first dummy switching elements includes a plurality of first dummy switching elements independently connected to each of the (3n + 3) th data lines; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver; A first switching device connected to the (6n + 4) th data line and a first switching device connected to the (6n + 5) th data line are connected in common to one of the output channels of the data driver; Each of the first dummy switching elements connected to the 3n + 3 < th > data lines is independently connected to any output channels of the data driver.

And a control signal generator for generating a first control signal for controlling the operation of the plurality of first switching elements and a second control signal for controlling the operation of the plurality of second switching elements.

The first control signal having an active state during the first period and the second control signal having an inactive state; The first control signal has an inactive state during the second period, and the second control signal has an active state during the second period.

The first control signal has an active state during a first period of a 2k-1 (k is a natural number) horizontal period, and the second control signal has an inactive state; The first control signal has an inactive state during a second period of the (2k-1) -th horizontal period, and the second control signal has an active state; The first control signal has an inactive state during a first period of a 2k-th horizontal period, and the second control signal has an active state; The first control signal has an active state during a second period of the 2k-th horizontal period, and the second control signal has an inactive state.

A second control signal in an active state output during a second period of the (2k-1) -th horizontal period and a first control signal in an active state output during a first period of the 2k-th horizontal period form one continuous pulse; The first control signal in the active state output in the second period of the 2k-th horizontal period and the second control signal in the active state outputted in the first period of the (2k + 1) -th horizontal period form one continuous pulse .

And the time lengths of the first period and the second period are different from each other.

A part of the first period and a part of the second period are overlapped in time.

And an idle time exists between an ending point of the first period and a starting point of the second period.

And the total length of time of the first period and the length of the second period is less than the length of the horizontal period.

And the first period is located temporally before the second period.

And the second period is located temporally before the first period.

The display device provided with the multiplexer according to the present invention has the following effects.

In the present invention, at least one kind of data lines having the same characteristics are connected to the switching elements which are turned on in the same period. Therefore, the luminance deviation between the pixels of the same color connected to the data lines having the same characteristics can be minimized. Therefore, the image quality can be improved.

1 is a view illustrating a display device according to a first embodiment of the present invention;
2 is a diagram showing waveforms of control signals supplied to the multiplexer of FIG. 1 and waveforms of some gate signals output from a gate driver
3 is a diagram showing a detailed configuration of a multiplexer according to the first embodiment in Fig. 1
4 is a view showing a charging method of pixels according to the structure of the multiplexer in FIG. 3
5 is a diagram showing a detailed configuration of a multiplexer according to the second embodiment in Fig. 1
6 is a view showing a charging method of pixels according to the structure of the multiplexer in FIG. 5
7 is a diagram showing a detailed configuration of a multiplexer according to the third embodiment in Fig. 1
FIG. 8 is a diagram showing a detailed configuration of a multiplexer according to the fourth embodiment in FIG. 1; FIG.
9 is a diagram showing a charging method of pixels according to the structure of the multiplexer
10 is a view showing a display device according to a second embodiment of the present invention
11 is a diagram showing waveforms of control signals supplied to the multiplexer of FIG. 10 and waveforms of some gate signals output from the gate driver in FIGS. 11A and 11B;
12 is a diagram showing a detailed configuration of a multiplexer according to the first embodiment in Fig. 10
13 is a diagram showing a charging method of pixels according to the structure of the multiplexer in Fig.
14 is a view showing a charging method of pixels according to the structure of the multiplexer in the modified embodiment of Fig. 12
Fig. 15 is a view showing a filling direction having a direction opposite to the filling direction in Fig. 14

FIG. 1 is a diagram illustrating a display device according to a first embodiment of the present invention. FIG. 2 is a diagram showing waveforms of control signals supplied to the multiplexer of FIG. 1 and waveforms of some gate signals output from a gate driver.

1, the display device according to the first embodiment of the present invention includes a display panel DSP, a data driver DD, a gate driver GD, a multiplexer MP, and a timing controller TC, .

The display panel DSP includes i * j pixels (PXLs) for displaying an image and i (i is a natural number) gate lines GL1 to GLi connected to these pixels and j (j is a natural number) And data lines DL1 to DLj. J pixels arranged along one horizontal line are commonly connected to one gate line and i pixels arranged along one vertical line are connected in common to one data line. The i * j pixels PXL include a plurality of red pixels R for displaying a red image, a plurality of green pixels G for displaying a green image, And blue pixels (B). The red pixels R, the green pixels G and the blue pixels B are arranged in a matrix form on the display portion of the display panel DSP. Each of the red, green and blue pixels R, G and B includes a thin film transistor and a pixel electrode. The gate electrode of the thin film transistor is connected to the corresponding gate line. The drain electrode is connected to the corresponding data line, And the source electrode is connected to the pixel electrode. Wherein one side of each of the pixel electrodes is commonly connected to a common line. A liquid crystal is formed between the pixel electrode and the common electrode. The liquid crystal, the pixel electrode, and the common electrode form a liquid crystal capacitance capacitor. Each of the pixels further includes a storage capacitor, which is formed at a portion of the pixel electrode provided in the pixel and a gate line (a front gate line) preceding the gate line to which the pixel is connected .

The data driver DD supplies j image data for displaying an image to j data lines DL1 to DLj via a multiplexer MP. The data driver DD converts the red, green, and blue image data supplied from the timing controller TC into analog signals and supplies these analog red, green, and blue image data to j data lines (DL1 to DLj). That is, the data driver DD converts the red, green, and blue image data corresponding to the pixels (j pixels) of one horizontal line driven by the gate driver GD into an analog signal, And outputs j pieces of image data of one horizontal line through p output channels (OC1 to OCp) having a number smaller than p (p is a natural number smaller than j). At this time, the data driver DD sequentially outputs the j pieces of image data divided into two for one horizontal period (1H). That is, some of the j pieces of image data are simultaneously outputted through the p output channels (OC1 to OCp) during the first half period (first half / 2H) of one horizontal period, (OC1 to OCp) during the latter half (late 1/2 / 2H) of the output period (OC1 to OCp).

The multiplexer MP time-divides and outputs j picture data from the data driver DD to a plurality of data lines. To this end, the multiplexer MP includes a plurality of first-half switching elements that maintain a turn-on state during a first half period of one horizontal period, and a plurality of second-half switching elements that maintain a turn-on state during a latter half of the horizontal period . 2, the multiplexer MP receives a first control signal CS1 and a second control signal CS2. The first control signal CS1 is input to the first control line CL1, And the second control signal CS2 is supplied to the gate electrodes of the second-stage switching elements through the second control line CL2. 2, the first control signal CS1 has an active state (high state), while the second control signal CS2 has an inactive state (a low state) during a first half period. Conversely, during the second half of the period, the first control signal CS1 is in an inactive state while the second control signal CS2 is in an active state.

The gate driver GD sequentially drives i gate lines GL1 through GLi for one frame period to drive j pixels connected in common to the corresponding gate line in every horizontal period in which each gate line is driven. To this end, the gate driver GD sequentially supplies gate signals to the respective gate lines. FIG. 2 shows gate signals (SP1 to SP4) supplied to arbitrary four gate lines (GL1 to GL4), in which pulse widths of gate signals adjacent to each other are overlapped for a certain period of time. For example, as shown in Fig. 2, the pulse width of the (q-1) th gate signal supplied to the (q-1) th gate line and the pulse width of the q- do. As another embodiment, these gate signals may be output without being overlapped.

Each gate signal maintains an active state for at least one horizontal period. During the horizontal period, the first control signal CS1 and the second control signal CS2 sequentially become active states as long as the gate signal remains active . For example, as long as the first gate signal SP1 remains active, the first control signal CS1 is active during the first half horizontal period of the horizontal period, and the second control signal CS2 during the second half horizontal period And has an active state.

According to the present invention, the data lines DL1 to DLj are classified into several types according to the connection pattern of the pixels connected thereto, and at least one kind of the same data lines are connected to the first and second switching elements It is connected only to one kind of switching elements. In other words, the same kind of data lines to which pixels displaying at least one kind of color of the same pattern are connected are connected to only one kind of switching elements of the first switching elements and the second switching elements.

For example, as shown in FIG. 1, the pixels include a plurality of red pixels R, a plurality of green pixels G, and a plurality of blue pixels B, A plurality of green data lines DL2, DL5, DL8, DL8, DL8, DL8, DL8, ..., ..., and a plurality of blue data lines DL3, DL6, DL9, ... connected to the plurality of blue pixels B, respectively. At this time, the data lines of at least any one of the red, green, and blue data lines may be connected only to the switching elements of any one of the first switching elements and the second switching elements.

As a more specific example, the data lines (for example, red data lines) of any one of the red, green and blue data lines are connected to any one of the switching elements of the first switching elements and the second switching elements (E. G., Half-switching elements); (For example, green data lines) of any one of the red, green, and blue data lines are connected to the other one of the first switching elements and the second switching elements , The latter switching elements); Then, the data lines (for example, blue data lines) of the other one of the red, green and blue data lines can be dividedly connected to the first switching elements and the second switching elements.

Hereinafter, a specific example thereof will be described with reference to the drawings.

FIG. 3 is a detailed block diagram of a multiplexer according to the first embodiment of FIG.

The j pixels arranged along one horizontal line in FIG. 1 may have a structure in which six pixels are repeatedly arranged, as shown in FIG.

The data lines DL1, DL4, DL7, ... of the j data lines are red data lines, and the (3n + 2) th data lines DL2, DL3, DL4, DL5, DL8, ... are the green data lines, and the (3n + 3) th data lines DL3, DL6, DL9, ... are the blue data lines. For example, as shown in FIG. 3, the first and fourth data lines DL1 and DL4 are red data lines, and the second and fifth data lines DL2 and DL5 are green data lines, And the third and fifth data lines DL3 and DL5 are blue data lines, respectively.

The plurality of first-phase switching elements may include a plurality of first switching elements independently connected to each of the (3n + 1) -th data lines and a plurality of first-order switching elements independently connected to each of the plurality of data lines, Lt; / RTI > For example, as shown in FIG. 3, the first-half switching elements include a first half-switching element TF1 connected to the first data line DL1, a second half-switching element connected to the fourth data line DL4, (TF2), and a third half switching element (TF3) connected to the sixth data line (DL6).

The plurality of second-stage switching elements include a plurality of second-stage switching elements independently connected to each of the (3n + 2) -th data lines and a plurality of second-stage switching elements independently connected to the remaining ones of the Switching elements. For example, as shown in FIG. 3, the second-stage switching elements include a first half-period switching element TS1 connected to the second data line DL2, a second half-period switching element connected to the third data line DL3, (TS2), and a third late switching element (TS3) connected to the fifth data line (DL5).

Here, the (6n + 3) -th data lines of the (3n + 3) -th data lines are connected to the respective second-stage switching elements, and the (6n + 6) -th data lines of the Respectively. 3, the third data line DL3 is connected to the second half switching element TS2, and the sixth data line DL6 is connected to the third half switching element TF3, for example. Respectively.

Here, the half switching elements connected to the (6n + 1) -th data line and the latter-half switching elements connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 3, the first half switching element TF1 and the first half switching element TS1 are connected in common to the first output channel OC1 as a pair.

In addition, a half switching element connected to the (6n + 3) -th data line and a half-switching element connected to the (6n + 4) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in Fig. 3, the second half switching element TF2 and the second half switching element TS2 are connected in common to the second output channel OC2 as a pair.

In addition, a half switching element connected to the (6n + 5) th data line and a half switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 3, the third half switching element TF3 and the third half switching element TS3 are connected in common to the third output channel OC3 as a pair.

The operation of the multiplexer according to the first embodiment will now be described in detail.

First, the operation in the first half period of one horizontal period will be described.

The first control signal CS1 in the active state output in the first half period of one horizontal period is supplied to the gate electrodes of the first through third half switching elements TF1 and TF3. Also in this first half period, the data driver DD outputs the first red image data through the first output channel OC1, outputs the second red image data through the second output channel OC2, And outputs the second blue image data through the output channel OC3. Further, in this first half period, the gate driver GD supplies the first gate signal GL1 having the active state to the first gate line GL1 during this one horizontal period to the first gate line GL1. Accordingly, the first to third half switching elements TF1 to TF3 are turned on in this first half period. Then, the turned-on first half switching element TF1 supplies the first red image data to the first red pixel R1 through the first data line DL1, and the second half switching element TF2 ) Supplies the second red image data to the second red pixel (R2) through the fourth data line (DL4), and the turned-on third switching element (TF3) supplies the second blue image data to the sixth data And supplies it to the second blue pixel B2 through the line DL6. As described above, it can be seen that the first and fourth data lines DL1 and DL4 having the same characteristics are driven simultaneously during the first half period. This is because the first and fourth data lines DL1 and DL4 are connected to the first and second half switching elements TF1 and TF2 which are turned on by the first control signal CS1 in the first half period. In other words, the first and fourth data lines DL1 and DL4 correspond to a red data line, and red pixels are connected to each of the red data lines. Specifically, the first red pixels R1 are connected to the first data line DL1 and the second red pixels R2 are connected to the fourth data line DL4. Thus, during the first half period, the first and fourth data lines DL1 and DL4 having the same characteristics (i.e., characteristics with pixels of the same color) have the same characteristic (i.e., the characteristic that they are turned on during the same first half period) The charge state between the pixels of the same color connected to the first and fourth data lines DL1 and DL4 is the same as that of the pixels of the same color connected to the first and fourth data lines DL1 and DL4 by the first and second half switches TF1 and TF2, . Therefore, it is possible to prevent a deterioration in image quality due to a charge deviation between pixels caused when the multiplexer MP is used.

Next, the operation in the second half period of one horizontal period will be described.

The active second control signal CS2 outputted in the second half of one horizontal period is supplied to the gate electrodes of the first through third late switching elements TS1 through TS3. Also in this latter half period, the data driver DD outputs the first green image data through the first output channel OC1, the first blue image data through the second output channel OC2, And outputs the second green image data through the output channel OC3. During the second half of this period, the gate driver GD supplies a first gate signal SP1 having an active state to the first gate line GL1 during the one horizontal period to the first gate line GL1. Accordingly, the first to third late switching elements TS1 to TS3 are turned on in the second half period. Then, the turned-on first half-period switching element TS1 supplies the first green image data to the first green pixel G1 through the second data line DL2, and turns on the second turn-on switching element TS2 ) Supplies the first blue image data to the first blue pixel B1 via the third data line DL3 and the third later half switching element TS3 that is turned on supplies the second green image data to the fifth data And supplies it to the second green pixel G2 through the line DL5. As described above, it can be seen that the second and fifth data lines DL2 and DL5 having the same characteristics are simultaneously driven during the second half period. This is because the second and fifth data lines DL2 and DL5 are respectively connected to the first and third later-stage switching elements TS1 and TS3 which are turned on by the second control signal CS2 in the latter half period . In other words, the second and fifth data lines DL2 and DL5 correspond to green data lines, and green data lines are all connected to green pixels. Specifically, the first green pixels G1 are connected to the second data line DL2, and the second green pixels G2 are connected to the fifth data line DL5. Thus, during the second half period, the second and fifth data lines DL2 and DL5 having the same characteristic (i.e., characteristics with pixels of the same color) have the same characteristic (i.e., the characteristic of being turned on during the same second half period ), The charge state between the pixels of the same color connected to the second and fifth data lines DL2 and DL5 is all the same . Therefore, it is possible to prevent a deterioration in image quality due to a charge deviation between pixels caused when the multiplexer MP is used.

 The third and sixth data lines DL3 and DL6 which are blue data lines are driven in different periods. That is, the third data line DL3 is driven in the first half period, while the fourth data line DL4 is driven in the second half period. Accordingly, the first blue pixel B1 is supplied with the first blue image data in the first half period, while the second blue pixel B2 is supplied with the second blue image data in the latter half period.

As described above, the multiplexer according to the first embodiment of the present invention allows red pixels and green pixels to receive image data in the same period, and maintains the same charged state between the red pixels and the green pixels.

4 is a diagram illustrating a charging method of pixels according to the structure of the multiplexer in FIG.

In Fig. 4, the tail portion of the arrow and the numeral 1 signify the first half period, and the head portion and the numeral 2 of this arrow signify the second half period. 4, the red pixels R connected to the red data lines are charged in the first half period, the green pixels G connected to the green data lines are charged in the second half period, Are charged in the first half period and the second half period.

As a modified embodiment of the first embodiment, the first green pixel G1 and the second green pixel G2 are arranged such that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the latter half period, The first blue pixel B1 is supplied with the image data in the first half period and the second blue pixel B2 is supplied in the latter half period so that the pixel G2 receives the image data in the first half period, To configure the first and second half switching elements of the multiplexer (MP).

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first red pixel R1 and the second red pixel R2 receive the image data in the first half period The first green pixel G1 is supplied with the image data in the second half period and the second green pixel G2 is supplied with the image data in the first half period so that the image data is supplied to the multiplexer MP The latter half switching elements can be constituted.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period, The first green pixel G1 is supplied with the image data in the first half period and the second green pixel G2 is supplied with the image data in the latter half period so that the first green pixel G1 is supplied with the image data, The latter half switching elements can be constituted.

As another method, the first green pixel G1 and the second green pixel G2 are controlled so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the first half period, The first blue pixel B1 is supplied with the image data in the second half period and the second blue pixel B2 is supplied with the image data in the first half period so that the first blue pixel B1 is supplied with the image data, The latter half switching elements can be constituted.

As another example, the first green pixel G1 and the second green pixel G2 are arranged in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period. The first blue pixel B1 is supplied with the image data in the first half period and the second blue pixel B2 is supplied with the image data in the latter half period so that the first blue pixel B1 is supplied with the image data, The latter half switching elements can be constituted.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first green pixel G1 and the second green pixel G2 receive the image data in the first half period The first red pixel R1 is supplied with the corresponding image data in the second half period and the second red pixel R2 is supplied in the first half period so that the image data is supplied to the first half of the multiplexer MP, The latter half switching elements can be constituted.

FIG. 5 is a detailed block diagram of a multiplexer according to the second embodiment of FIG. 1. Referring to FIG.

The j pixels arranged along one horizontal line in FIG. 1 may have a structure in which six pixels are repeatedly arranged, as shown in FIG.

Here, 3n + 1th (n is a natural number including 0) data lines are red data lines, 3n + 2th data lines are green data lines, and 3n + 3th data lines are blue data Lines. For example, as shown in FIG. 3, the first and fourth data lines DL4 are each a red data line, the second and fifth data lines DL5 are green data lines, And the fifth data lines DL5 are blue data lines, respectively.

The plurality of first-phase switching elements may include a plurality of first switching elements independently connected to each of the (3n + 1) -th data lines and a plurality of first-order switching elements independently connected to each of the plurality of data lines, Lt; / RTI > 5, the first-half switching elements include a first half-switching element TF1 connected to the first data line DL1, a second half-switching element T5 connected to the fourth data line DL4, (TF2), and a third half switching element (TF3) connected to the sixth data line (DL6).

The plurality of second-stage switching elements include a plurality of second-stage switching elements independently connected to each of the (3n + 2) -th data lines and a plurality of second-stage switching elements independently connected to the remaining ones of the Switching elements. For example, as shown in FIG. 5, the second-half switching elements are connected to the first half-period switching element TS1 connected to the second data line DL2, the second half-period switching element connected to the third data line DL3, (TS2), and a third late switching element (TS3) connected to the fifth data line (DL5).

Here, the (6n + 3) -th data lines of the (3n + 3) -th data lines are connected to the respective second-stage switching elements, and the (6n + 6) -th data lines of the Respectively. 5, the third data line DL3 is connected to the second half switching element TS2, and the sixth data line DL6 is connected to the third half switching element TF3. Respectively.

Here, the half switching elements connected to the (6n + 1) -th data line and the latter-half switching elements connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 5, the first half switching element TF1 and the first half switching element TS1 are connected in common to the first output channel OC1 as a pair.

In addition, a half switching element connected to the (6n + 3) th data line and a half switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver. For example, as shown in Fig. 5, the third half switching element TF3 and the second half switching element TS2 are connected in common to the second output channel OC2 as a pair.

In addition, a half switching element connected to the (6n + 4) th data line and a half switching element connected to the (6n + 5) th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 5, the second half switching element TF2 and the third half switching element TS3 are connected in common to the third output channel OC3 as a pair.

The driving method of the second embodiment is almost the same as the first embodiment described above. However, according to the second embodiment, the first blue pixel B1 and the second blue pixel B2 are driven in different periods. At this time, the first blue pixel B1 and the second blue pixel B2 Receive the image data from the same output channel (the third output channel OC3).

FIG. 6 is a diagram illustrating a charging method of pixels according to the structure of the multiplexer in FIG.

In Fig. 6, the tail portion and the numeral 1 of the arrow indicate the first half period, and the head portion and the numeral 2 of this arrow means the second half period. 6, the red pixels R connected to the red data lines are charged in the first half period, the green pixels G connected to the green data lines are charged in the second half period, Are charged in the first half period and the second half period.

On the other hand, as a modified embodiment of the second embodiment, the first green pixel G1 and the second green pixel G2 are arranged such that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the latter half period, The second blue pixel B2 is supplied in the second half so that the first blue pixel B1 is supplied with the image data in the first half period so that the pixel G2 receives the image data in the first half period, And the first and second blue pixels B1 and B2 may be connected to the same output channel.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first red pixel R1 and the second red pixel R2 receive the image data in the first half period The second green pixel G2 is supplied with the image data in the first half period so that the first green pixel G1 is supplied with the image data in the second half period and the first green pixel G1 ) And the second green pixel G2 are connected to the same output channel.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period, The second green pixel G2 is supplied with the image data in the second half period so that the first green pixel G1 receives the image data in the first half period and the first green pixel G1 ) And the second green pixel G2 are connected to the same output channel.

As another method, the first green pixel G1 and the second green pixel G2 are controlled so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the first half period, The second blue pixel B2 is supplied with the image data in the first half period so that the first blue pixel B1 is supplied with the image data in the second half period and the first blue pixel B1 ) And the second blue pixel B2 are connected to the same output channel.

As another example, the first green pixel G1 and the second green pixel G2 are arranged in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period. The second blue pixel B2 is supplied with the image data in the second half period so that the first blue pixel B1 is supplied with the image data in the first half period and the first blue pixel B1 ) And the second blue pixel B2 are connected to the same output channel.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first green pixel G1 and the second green pixel G2 receive the image data in the first half period The second red pixel R2 is supplied with the image data in the first half period so that the first red pixel R1 is supplied with the image data in the second half period and the first red pixel R1 ) And the second red pixel R2 are connected to the same output channel.

1, data lines (e.g., red data lines) of any one of the red, green, and blue data lines may be connected to any one of the switching elements of the first switching elements and the second switching elements (E. G., Half-switching elements); (E.g., green data lyes) of any one of the red, green, and blue data lines are coupled to the other switching elements of the first and second switching elements (e.g., , The latter switching elements); And the data lines (e.g., blue data lines) of the other one of the red, green, and blue data lines may be directly connected to each of the output channels of the data driver independently. This example will be described in detail with reference to specific drawings.

FIG. 7 is a detailed block diagram of a multiplexer according to the third embodiment of FIG. 1. Referring to FIG.

The j pixels arranged along one horizontal line in FIG. 1 may have a structure in which six pixels are repeatedly arranged, as shown in FIG.

Here, 3n + 1th (n is a natural number including 0) data lines are red data lines, 3n + 2th data lines are green data lines, and 3n + 3th data lines are blue data Lines. For example, as shown in FIG. 3, the first and fourth data lines DL1 and DL4 are red data lines, the second and fifth data lines DL2 and DL5 are green data lines, And the third and fifth data lines DL3 and DL5 are blue data lines, respectively.

The plurality of first switching elements include a plurality of first switching elements independently connected to each of the (3n + 1) th data lines. 7, the first-half switching elements include a first half-switching element TF1 connected to the first data line DL1 and a second half-switching element TF1 connected to the third data line DL3. (TF2).

The plurality of second-stage switching elements include a plurality of second-stage switching elements independently connected to each of the (3n + 2) -th data lines. For example, as shown in FIG. 7, the second-stage switching elements TS1 and TS5 are connected to the second data line DL2 and the second data line DL5, respectively, (TS2).

Each of the 3n + 3 < th > data lines is independently connected directly to each of the output channels of the data driver. 7, the third data line DL3 is directly connected to the second output channel OC2, and the sixth data line DL6 is connected directly to the fourth output channel OC4, for example, Respectively.

Here, the half switching elements connected to the (6n + 1) -th data line and the latter-half switching elements connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 7, the first half switching element TF1 and the first half switching element TS1 are connected in common to the first output channel OC1 as a pair.

In addition, a half-switching element connected to the (6n + 4) -th data line and a half-switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 7, the second half switching element TF2 and the second half switching element TS2 are connected in common to the third output channel OC3 as a pair.

The operation of the multiplexer according to the third embodiment will now be described in detail.

First, the operation in the first half period of one horizontal period will be described.

The first control signal CS1 in the active state outputted in the first half period of one horizontal period is supplied to the gate electrodes of the first and second half switching elements TF1 and TF2. Also in this first half period, the data driver DD outputs the first red image data through the first output channel OC1, the first blue image data through the second output channel OC2, Outputs the second red image data through the channel OC3, and outputs the second blue image data through the fourth output channel OC4. Further, in this first half period, the gate driver GD supplies the first gate signal GL1 having the active state to the first gate line GL1 during this one horizontal period to the first gate line GL1. Accordingly, the first and second half switching elements TF1 and TF2 are turned on in this first half period. Then, the turned-on first half switching element TF1 supplies the first red image data to the first red pixel R1 through the first data line DL1, and the second half switching element TF2 Supplies the second red image data to the second red pixel R2 via the fourth data line DL4. At this time, the data driver DD directly supplies the first blue image data to the first blue pixel B1 through the second output channel OC2, and the second blue image data to the fourth output channel OC4 through the fourth output channel OC4 And supplies it directly to the second blue pixel B2.

Next, the operation in the second half period of one horizontal period will be described.

The active control second control signal CS2 outputted in the latter half of one horizontal period is supplied to the gate electrodes of the first and second control switching elements TS1 and TS2. Also in this latter half period, the data driver DD outputs the first green image data through the first output channel OC1, the first blue image data through the second output channel OC2, Outputs the second green image data through the channel OC3, and outputs the second blue image data through the fourth output channel OC4. During the second half of this period, the gate driver GD supplies a first gate signal SP1 having an active state to the first gate line GL1 during the one horizontal period to the first gate line GL1. Accordingly, the first and second late switching elements TS1 and TS2 are turned on in the second half period. Then, the turned-on first half-period switching element TS1 supplies the first green image data to the first green pixel G1 through the second data line DL2, and turns on the second turn-on switching element TS2 Supplies the second green image data to the second green pixel G2 through the fifth data line DL5. At this time, the data driver DD directly supplies the first blue image data to the first blue pixel B1 through the second output channel OC2, and the second blue image data to the fourth output channel OC4 through the fourth output channel OC4 And supplies it directly to the second blue pixel B2.

As described above, according to the multiplexer MP according to the third embodiment of the present invention, the red pixels R1 and R2 and the blue pixels B1 and B2 are driven in the first half period, and the green pixels G1, G2, and blue pixels B1 and B2 are driven. In particular, since the blue pixels B1 and B2 are driven by the data lines having the same characteristics (i.e., data lines directly connected to the output channel of the data driver) in both the first half period and the second half period, B2 also have the same charge state regardless of the location of the data lines to which they are connected. Thus, according to the multiplexer according to the third embodiment of the present invention, red, green and blue pixels all have the same charge state.

At this time, the blue pixels B1 and B2 may receive different image data in the first half period and the second half period. For example, both the first blue pixel and the second blue pixel are supplied with red or green image data instead of blue image data in the first half period, and in the latter half period, the actual image data (i.e., the first blue image data and the second Blue image data) can be supplied.

On the other hand, as a modified embodiment of the third embodiment, the first green pixel G1 and the second green pixel G2 are arranged such that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the latter half period, The first blue pixel B1 is directly connected to the corresponding output channel in the first half period and the second half period to receive the corresponding image data so that the pixel G2 receives the image data in the first half period and the second blue pixel B2 Are directly connected to the corresponding output channel in the first half period and the second half period to configure the first half and second half switching elements of the multiplexer MP to receive the corresponding image data.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first red pixel R1 and the second red pixel R2 receive the image data in the first half period The first green pixel G1 is directly connected to the corresponding output channel in the first half period and the second half period to receive the image data so that the second green pixel G2 is supplied in the first half period and the second half period It is possible to configure the first half and second half switching elements of the multiplexer MP so as to be directly connected to the corresponding output channel and receive the corresponding image data.

As another method, the first green pixel G1 and the second green pixel G2 are controlled so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the first half period, The first blue pixel B1 is directly connected to the corresponding output channel in the first half period and the second half period to receive the corresponding image data and the second blue pixel B2 is supplied in the first half period and the second half period It is possible to configure the first half and second half switching elements of the multiplexer MP so as to be directly connected to the corresponding output channel and receive the corresponding image data.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first green pixel G1 and the second green pixel G2 receive the image data in the first half period The first red pixel R1 is directly connected to the corresponding output channel in the first half period and the second half period to receive the image data so that the second red pixel R2 is supplied in the first half period and the second half period It is possible to configure the first half and second half switching elements of the multiplexer MP so as to be directly connected to the corresponding output channel and receive the corresponding image data.

FIG. 8 is a detailed block diagram of the multiplexer according to the fourth embodiment of FIG. 1. Referring to FIG.

The j pixels arranged along one horizontal line in FIG. 1 may have a structure in which six pixels are repeatedly arranged, as shown in FIG.

Here, 3n + 1th (n is a natural number including 0) data lines are red data lines, 3n + 2th data lines are green data lines, and 3n + 3th data lines are blue data Lines. 8, the first and fourth data lines DL1 and DL4 are red data lines, and the second and fifth data lines DL2 and DL5 are green data lines, respectively. And the third and fifth data lines DL3 and DL5 are blue data lines, respectively.

The plurality of first switching elements include a plurality of first switching elements independently connected to each of the (3n + 1) th data lines. 8, the first-half switching elements include a first half-switching element TF1 connected to the first data line DL1 and a second half-switching element TF1 connected to the third data line DL3. (TF2).

The plurality of second-stage switching elements include a plurality of second-stage switching elements independently connected to each of the (3n + 2) -th data lines. For example, as shown in FIG. 8, the second-half switching elements are connected to the first and second half-time switching elements TS1 and DL5 connected to the second data line DL2, (TS2).

Meanwhile, the multiplexer MP according to the fourth embodiment of the present invention further includes a first half dummy switching device and a second half dummy switching device DS.

Each of the (3n + 3) -th data lines is directly and independently connected to the first half dummy switching element DF and the second half dummy switching element DS to each of the output channels of the data driver DD. 8, the third data line DL3 is connected to the second output channel OC2 via the second dummy switching device DS, and the sixth data line DL6 is connected to the second output channel OC2 through the first half And is connected to the fourth output channel OC4 through the dummy switching element DF.

Here, the first dummy switching element DF may be connected to the third data line DL3, and the second half dummy switching element DS may be connected to the sixth data line DL6.

Here, the half switching elements connected to the (6n + 1) -th data line and the latter-half switching elements connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in FIG. 8, the first half switching element TF1 and the first half switching element TS1 are connected in common to the first output channel OC1 as a pair.

In addition, a half-switching element connected to the (6n + 4) -th data line and a half-switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in Fig. 8, the second half switching element TF2 and the second half switching element TS2 are connected in common to the third output channel OC3 as a pair.

The operation of the first and second half switching elements TF1 and TF2 and the first and second half switching elements TS1 and TS2 in FIG. 8 is the same as that of the first and second half switching elements (TF1, TF2) and the first and second late switching elements (TS1, TS2). The operation of the first half dummy switching device DF in Fig. 8 is the same as the operation of the first and second half switching devices TF1 and TF2 in Fig. 7, and the operation of the second half dummy switching device DS Is the same as the operation of the first and second terminal switching elements TS1 and TS2 in Fig.

FIG. 9 is a diagram showing a charging method of pixels according to the structure of the multiplexer (FIG. 8).

In Fig. 9, the tail portion of the arrow and the numeral 1 signify the first half period, and the head portion and the numeral 2 of this arrow signify the second half period. 9, the red pixels R connected to the red data lines are charged in the first half period, the green pixels G connected to the green data lines are charged in the second half period, It can be seen that the blue pixels B connected to the first half are charged in the first half period and the second half period.

On the other hand, as a modified embodiment of the fourth embodiment, the first green pixel G1 and the second green pixel G2 are arranged such that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period, The first blue pixel B1 is supplied with the image data in the first half period and the second blue pixel B2 is supplied in the latter half period so that the pixel G2 receives the image data in the first half period, The half-switching elements DF and the half-dummy switching elements DS can be configured so as to receive the half-duplex switching elements MP, MP.

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first red pixel R1 and the second red pixel R2 receive the image data in the first half period The first green pixel G1 is supplied with the image data in the second half period and the second green pixel G2 is supplied with the image data in the first half period so that the image data is supplied to the multiplexer MP, Elements, second-half switching elements, first-half dummy switching elements (DF), and second-half dummy switching elements (DS).

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period, The first green pixel G1 is supplied with the image data in the first half period and the second green pixel G2 is supplied with the image data in the latter half period so that the image data is supplied to the multiplexer MP, Elements, second-half switching elements, first-half dummy switching elements (DF), and second-half dummy switching elements (DS).

As another method, the first green pixel G1 and the second green pixel G2 are controlled so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the first half period, The first blue pixel B1 is supplied with the image data in the second half period and the second blue pixel B2 is supplied with the image data in the first half period so that the image data is supplied to the multiplexer MP, Elements, second-half switching elements, first-half dummy switching elements (DF), and second-half dummy switching elements (DS).

As another example, the first green pixel G1 and the second green pixel G2 are arranged in the first half period so that the first red pixel R1 and the second red pixel R2 are supplied with the image data in the second half period. The first blue pixel B1 is supplied with the image data in the first half period and the second blue pixel B2 is supplied with the image data in the latter half period so that the image data is supplied to the multiplexer MP, Elements, second-half switching elements, first-half dummy switching elements (DF), and second-half dummy switching elements (DS).

As another method, the first blue pixel B1 and the second blue pixel B2 are supplied in the second half period so that the first green pixel G1 and the second green pixel G2 receive the image data in the first half period The first red pixel R1 is supplied with the image data in the second half period and the second red pixel R2 is supplied with the image data in the first half period so that the image data is supplied to the multiplexer MP, Elements, second-half switching elements, first-half dummy switching elements (DF), and second-half dummy switching elements (DS).

FIG. 10 shows a display device according to the second embodiment of the present invention. FIG. 11 shows waveforms of control signals supplied to the multiplexer of FIG. 10 and waveforms of some gate signals output from the gate driver. Fig.

The display device according to the second embodiment of the present invention includes a display panel DSP, a data driver DD, a gate driver GD, a multiplexer MP, and a timing controller TC, as shown in Fig. . The configuration and operation of the data driver (DD), the gate driver (GD), and the timing controller (TC) included in the display device according to the second embodiment are the same as those of the data driver DD, the gate driver GD, and the timing controller TC.

The display panel DSP includes i * j pixels (PXLs) for displaying an image and i (i is a natural number) gate lines GL1 to GLi connected to these pixels and j (j is a natural number) And data lines DL1 to DLj. J pixels arranged along one horizontal line are commonly connected to one gate line and i pixels arranged along one vertical line are connected in common to one data line. The i * j pixels PXL include a plurality of red pixels R for displaying a red image, a plurality of green pixels G for displaying a green image, And blue pixels (B). The red pixels R, the green pixels G and the blue pixels B are arranged in a matrix form on the display portion of the display panel DSP. Each of the red, green and blue pixels R, G and B includes a thin film transistor and a pixel electrode. The gate electrode of the thin film transistor is connected to the corresponding gate line. The drain electrode is connected to the corresponding data line, And the source electrode is connected to the pixel electrode. Wherein one side of each of the pixel electrodes is commonly connected to a common line. A liquid crystal is formed between the pixel electrode and the common electrode. The liquid crystal, the pixel electrode, and the common electrode form a liquid crystal capacitance capacitor. Each of the pixels further includes a storage capacitor, which is formed at a portion of the pixel electrode provided in the pixel and a gate line (a front gate line) preceding the gate line to which the pixel is connected .

Particularly, according to the display device of the second embodiment, pixels of the odd-numbered horizontal lines are connected to the data lines located on the left side of them, while pixels of the odd-numbered horizontal lines are connected to the data lines located on the right side thereof . Thus, i * j pixels are connected in zigzag form to each data line, and the pixels connected to one data line represent two different colors. For example, red pixels and green pixels are connected in a zigzag manner in the second data line DL2 in FIG. On the other hand, in the first data line DL1, the odd-numbered red pixels among the i number of red pixels and the i-th red pixels among the i-th blue pixels located on the leftmost side of the display panel are zigzag .

The multiplexer MP further includes a plurality of first half dummy switching elements DF that maintain the turn-on state during the first half period.

11A, the multiplexer MP is supplied with a first control signal CS1 and a second control signal CS2. The first control signal CS1 is applied to the gate electrodes of the first- And the second control signal CS2 is supplied to the gate electrodes of the second-stage switching elements.

11A, during the first half of the 2k-1 (k is a natural number) horizontal period, the first control signal CS1 is in the active state while the second control signal CS2 is in the inactive state . During the second half of the (2k-1) -th horizontal period, the first control signal CS1 has an inactive state while the second control signal CS2 has an active state.

On the other hand, during the first half of the 2k-th horizontal period, the first control signal CS1 has an inactive state while the second control signal CS2 has an active state. And, during the latter half of the 2k-th horizontal period, the first control signal CS1 is in the active state while the second control signal CS2 is in the inactive state.

In this case, as shown in FIG. 11B, the second control signal CS2 in the active state outputted during the second half of the (2k-1) -th horizontal period and the first control signal CS2 during the first half of the The signal CS1 can form one continuous pulse.

Similarly, the first control signal CS1 in the active state output in the second half of the 2k-th horizontal period and the second control signal CS2 in the active state in the first half of the 2k + Lt; / RTI >

The pixels include a plurality of red pixels R, a plurality of green pixels G, and a plurality of blue pixels B, and the plurality of data lines DL1 to DLj include a plurality of red and blue pixels A plurality of green / red data lines DL1, DL4, DL7, ..., a plurality of green and red pixels G, R connected in series, A plurality of blue / green data lines DL3, DL6, DL9,..., To which red data lines DL2, DL5, DL8, ... and a plurality of blue and green pixels B, ). At this time, at least one of the data lines of red / blue, green / red, and blue / green data lines may be connected only to any one of the switching elements of the first switching elements and the second switching elements.

Specifically, any one of the data lines (for example, red / blue data lines) of the red / blue, green / red and blue / green data lines is connected to either one of the first switching elements and the second switching elements Connected to one kind of switching elements (for example, the half switching elements); (For example, green / red data lines) of the red / blue, green / red and blue / green data lines are connected to one of the first switching elements and the second switching elements (E. G., Second-half switching elements) of the second switching element; The other one type of data lines (e.g., blue / green data lines) of the red / blue, green / red and blue / green data lines may be connected to the first half dummy switching elements DF .

Hereinafter, a specific example thereof will be described with reference to the drawings.

12 is a diagram showing a detailed configuration of a multiplexer according to the first embodiment of FIG.

The j pixels PXL arranged along one horizontal line in FIG. 10 may have a structure in which six pixels are repeatedly arranged, as shown in FIG.

Here, the 3n + 1th (n is a natural number including 0) data lines are red / blue data lines, the 3n + 2th data lines are green / red data lines, and the (3n + The lines are blue / green data lines. For example, as shown in FIG. 12, the first and fourth data lines DL1 and DL4 are red / blue data lines, and the second and fifth data lines DL2 and DL5 are green / Red data line, and the third and fifth data lines DL3 and DL5 are blue / green data lines, respectively.

The plurality of first switching elements include a plurality of first switching elements independently connected to each of the (3n + 1) th data lines. 12, the first-half switching elements include a first half-switching element TF1 connected to the first data line DL1 and a second half-switching element TF1 connected to the fourth data line DL4. (TF2).

The plurality of second-stage switching elements include a plurality of second-stage switching elements independently connected to each of the (3n + 2) -th data lines. For example, as shown in FIG. 12, the second-stage switching elements are connected to the first and second last-half switching elements TS1 and DL5 connected to the second data line DL2, (TS2).

Here, each of the (3n + 3) th data lines is connected to the first half dummy switching element DF. For example, the third data line DL3 is connected to the first output channel OC1 through the first half dummy switching element, and the sixth data line DL6 is connected to the second half dummy switching element DF To the second output channel OC2.

Here, the half switching elements connected to the (6n + 1) -th data line and the latter half switching elements connected to the (6n + 2) -th data line are commonly connected to one output channel of the data driver as a pair. For example, as shown in FIG. 12, the first half switching element TF1 and the first half switching element TS1 are connected in common to the first output channel OC1 as a pair.

A half-switching element connected to the (6n + 4) -th data line and a half-switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver. For example, as shown in Fig. 12, the second half switching element TF2 and the second half switching element TS2 are connected in common to the third output channel OC3 as a pair.

13 is a diagram illustrating a charging method of pixels according to the structure of the multiplexer in FIG.

13, the tail portion of the arrow and the numeral 1 signify the first half period, and the head portion and the numeral 2 of this arrow signify the second half period. As shown in FIG. 13, all the red pixels R are charged in the first half period, and all the green pixels G are charged in the second half period. The blue pixels B located on the odd-numbered horizontal line among all the blue pixels B are charged in the latter half period, and the blue pixels B located on the even-numbered horizontal line are charged in the first half period.

The multiplexer MP in FIG. 12 may have the same structure as any one of the multiplexers (including the modified embodiments) shown in the first to third embodiments described above.

On the other hand, as a modified embodiment of the display device in the second embodiment, pixels of the odd-numbered horizontal lines are connected to the data lines located on the right side thereof, while pixels of the odd- Lt; / RTI >

14 is a diagram showing a charging method of pixels according to the structure of the multiplexer in the modified embodiment of FIG.

In Fig. 14, the tail portion of the arrow and the numeral 1 signify the first half period, and the head portion and the numeral 2 of this arrow signify the second half period. As shown in FIG. 14, all the red pixels R are charged in the first half period, and all the green pixels G are charged in the second half period. The blue pixels B located on the odd-numbered horizontal line among all the blue pixels B are charged in the latter half period, and the blue pixels B located on the even-numbered horizontal line are charged in the first half period.

Fig. 15 is a view showing a filling direction having a direction opposite to that of Fig. 14; Fig.

In Fig. 15, the tail portion and the numeral 1 of the arrow indicate the first half period, and the head portion and the numeral 2 of this arrow means the second half period. As shown in FIG. 15, all the red pixels R are charged in the first half period, and all the green pixels G are charged in the second half period. The blue pixels B located on the odd-numbered horizontal line among all the blue pixels B are charged in the latter half period, and the blue pixels B located on the even-numbered horizontal line are charged in the first half period.

Meanwhile, according to the present invention, time lengths of the first half period and the second half period may be different from each other. In other words, although the first half period and the second half period are shown to have the same time length in FIG. 2, the first half period and the latter half period may have different time lengths. For example, the time length of the first half period may be longer or shorter than the time length of the latter half period.

On the other hand, a part of the first half period and a part of the latter half period may overlap in time. For example, the 1/2 period located in the latter half of the first half period may overlap with the 1/2 period located in the first half of the latter half period.

On the other hand, there may be a vacant time between the end time of the first half period and the start time of the latter half period. That is, a blank period having a predetermined length of time can be set between the first half period and the second half period. In other words, the second half period after the blank period of a predetermined time after the first half period ends can be started. At this time, the total length of the time length of the first half period and the length of the second half period may be set to be smaller than the time length of the horizontal period. That is, as the one horizontal period is divided into the first half period, the blank period, and the second half period, the total time length of the first half period and the second half period is shorter than that of one horizontal period.

On the other hand, the first half period may be located temporally earlier than the second half period. That is, the second half period starts first, and then the first half period starts. In this case, the second half plays the role of the first half, and the first half plays the role of the latter half. In other words, the first period and the second period in the claims correspond respectively to the first half period and the second half period in the detailed description of the present invention, or conversely, the first period and the second period correspond to the latter half period and the first half, respectively have.

In a similar manner, the first switching element and the second switching element in the claim correspond to the first switching element and the second switching element, respectively, in the detailed description of the present invention, or conversely, the first switching element and the second switching element correspond to the second half And may correspond to a switching element and a half-switching element.

In a similar manner, the first dummy switching element and the second dummy switching element in the claims correspond to the first half dummy switching element and the second half dummy switching element, respectively, in the detailed description of the present invention, or conversely, the first dummy switching element and the second The dummy switching elements may correspond to the latter half dummy switching elements and the first half dummy switching elements, respectively.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. Will be clear to those who have knowledge of.

TF #: 1st half switching element TS #: 1st 2nd half switching element
CL #: Control line CS #: Control signal
DL #: 1st data line GL1: 1st gate line
R #: 1st red pixel G #: 1st green pixel
B #: Article # Blue pixel MP: Multiplexer
OC #: Output Channel DD: Data Driver

Claims (25)

A data driver for outputting image data; And
A plurality of first switching elements for maintaining a turn-on state during a first period of one horizontal period and a plurality of first switching elements for maintaining a turn-on state during a first period of one horizontal period, A multiplexer including a plurality of second switching elements that maintain a turn-on state during a second period;
The pixels include pixels of a first color having different colors, pixels of a second color, and pixels of a third color,
Wherein the data lines are connected to the data lines of the first color divided from the pixels of the first color, the data lines of the second color connected to the pixels of the second color, And the data lines of the first color are connected to the switching elements of any one of the first switching elements and the second switching elements;
The data lines of the second color are connected to the switching elements of the other one of the first switching elements and the second switching elements;
The data lines of the third color may be connected to the first and second switching elements not connected to the data lines of the first color and the second color among the first and second switching elements Or separately connected to each of a plurality of output channels of the data driver. delete delete The method according to claim 1,
(3n + 1) th data lines (n is a natural number including 0) of the data lines are red data lines of the first color, 3n + 2th data lines are green data lines of the second color, and 3n + Third data lines are the blue data lines of the third color;
The first switching elements are independently connected to each of the 3n + 1th data lines and some of the 3n + 3th data lines;
The second switching elements are independently connected to each of the (3n + 2) th data lines and the remaining data lines of the (3n + 3) th data lines;
A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver;
A second switching element connected to the (6n + 3) th data line and a first switching element connected to the (6n + 4) th data line are connected in common to one of the output channels of the data driver;
And a second switching element connected to the (6n + 5) th data line and a first switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver. The method according to claim 1,
(3n + 1) th data lines (n is a natural number including 0) of the data lines are red data lines of the first color, 3n + 2th data lines are green data lines of the second color, and 3n + Third data lines are the blue data lines of the third color;
The first switching elements are independently connected to each of the 3n + 1th data lines and some of the 3n + 3th data lines;
The plurality of second switching elements are independently connected to each of the (3n + 2) th data lines and the remaining data lines of the (3n + 3) th data lines; A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver;
A second switching element connected to the (6n + 3) th data line and a first switching element connected to the (6n + 6) th data line are connected in common to one of the output channels of the data driver;
And a second switching element connected to the (6n + 4) -th data line and a first switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver. 6. The method according to any one of claims 4 and 5,
The (6n + 3) th data lines of the (3n + 3) th data lines are connected to the respective second switching elements;
And the (6n + 6) th data lines among the (3n + 3) th data lines are connected to the corresponding first switching elements. delete The method according to claim 1,
(3n + 1) th data lines (n is a natural number including 0) of the data lines are red data lines of the first color, 3n + 2th data lines are green data lines of the second color, and 3n + Third data lines are the blue data lines of the third color;
The first switching elements are independently connected to each of the (3n + 1) th data lines; The second switching elements are independently connected to each of the (3n + 2) th data lines;
Each of the (3n + 3) -th data lines is directly and independently connected to each of the output channels of the data driver;
A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver;
And the first switching element connected to the (6n + 4) -th data line and the first switching element connected to the (6n + 5) -th data line are connected in common to one of the output channels of the data driver. 9. The method of claim 8,
Wherein the same image data is supplied to the (3n + 3) th data line during the first period and the second period, respectively, and the different image data are supplied during the first period and the second period. delete delete 9. The method of claim 8,
The multiplexer further comprises dummy switching elements independently connected between some output channels of the data driver and the (3n + 3) th data lines;
Wherein the dummy switching elements include first dummy switching elements that maintain a turn-on state during the first period and second dummy switching elements that maintain a turn-on state during the second period;
The (6n + 3) th data lines of the (3n + 3) th data lines are connected to the respective second dummy switching elements; And the (6n + 6) th data lines among the (3n + 3) th data lines are connected to the first dummy switching elements. A data driver for outputting image data; And
A plurality of first switching elements for maintaining a turn-on state during a first period of one horizontal period and a plurality of first switching elements for maintaining a turn-on state during a first period of one horizontal period, A multiplexer including a plurality of second switching elements that maintain a turn-on state during a second period;
The pixels include pixels of a first color having different colors, pixels of a second color, and pixels of a third color,
Wherein the data lines include a first type of data lines in which some pixels of the first color and some pixels of the second color are connected in a divided manner, And a third type of data lines connected to the remaining pixels of the second color and the remaining pixels of the third color,
Wherein at least one of the first to third types of data lines is connected to only one of the first and second switching elements. 14. The method of claim 13,
The multiplexer further includes first dummy switching elements for maintaining a turn-on state during the first period;
Any one of the data lines of the first to third types of data lines is connected to any one of the first and second switching elements;
The other one of the first to third types of data lines is connected to the other one of the first switching elements and the second switching elements;
And the other one of the first to third types of data lines is connected to the first dummy switching elements. 15. The method of claim 14,
(3n + 1) th data lines (n is a natural number including 0) among the data lines are red / blue data lines corresponding to the first type of data lines, and the (3n + 2) Green / red data lines corresponding to data lines, and (3n + 3) th data lines are blue / green data lines for the third type of data lines;
The first switching elements are independently connected to each of the (3n + 1) th data lines;
The second switching elements are independently connected to each of the (3n + 2) th data lines;
The first dummy switching elements are independently connected to each of the (3n + 3) th data lines;
A first switching element connected to the (6n + 1) -th data line and a second switching element connected to the (6n + 2) -th data line are connected in common to one of the output channels of the data driver;
A first switching device connected to the (6n + 4) th data line and a first switching device connected to the (6n + 5) th data line are connected in common to one of the output channels of the data driver;
Each of the first dummy switching elements connected to the (3n + 3) th data lines is independently connected to the output channels of the data driver. The method according to any one of claims 1, 4, 5, 8, and 12 to 15,
Further comprising a control signal generator for generating a first control signal for controlling operations of the first switching elements and a second control signal for controlling operations of the second switching elements,
Wherein one of the first period and the second period is located temporally ahead of the remaining period. 17. The method of claim 16,
The first control signal having an active state during the first period and the second control signal having an inactive state;
Wherein the first control signal has an inactive state during the second period, and the second control signal has an active state during the second period. 17. The method of claim 16,
The first control signal has an active state during a first period of a 2k-1 (k is a natural number) horizontal period, and the second control signal has an inactive state;
The first control signal has an inactive state during a second period of the (2k-1) -th horizontal period, and the second control signal has an active state;
The first control signal has an inactive state during a first period of a 2k-th horizontal period, and the second control signal has an active state;
Wherein the first control signal has an active state during a second period of the 2k-th horizontal period, and the second control signal has an inactive state. 19. The method of claim 18,
A second control signal in an active state output during a second period of the (2k-1) -th horizontal period and a first control signal in an active state output during a first period of the 2k-th horizontal period form one continuous pulse;
And a second control signal in an active state outputted in the second period of the (2k) -th horizontal period and a second control signal in an active state outputted in a first period of the (2k + 1) Device. 17. The method of claim 16,
Wherein the time lengths of the first period and the second period are different from each other. 17. The method of claim 16,
Wherein a part of the first period and a part of the second period are overlapped temporally. 17. The method of claim 16,
There is an idle time between the end of the first period and the start of the second period,
Wherein the sum of the first period and the second period is smaller than the horizontal period. delete delete delete

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