KR101813178B1 - Stack structure having two-dimensional electron gas, semiconductor device including the stack structure and methods of manufacturing the same - Google Patents

Abstract

A stacked structure having a two-dimensional electron gas, a semiconductor device including the stacked structure, and a manufacturing method thereof are disclosed. The disclosed method of forming a stacked structure includes forming a first material layer, heat treating the first material layer, and depositing a two-dimensional electron gas on the first material layer RTI ID = 0.0 > 2DEG). ≪ / RTI > The heat treatment of the first material layer may be performed under conditions that increase surface roughness and / or surface states of the first material layer. A semiconductor device can be manufactured on the laminated structure formed by the above method.

Description

TECHNICAL FIELD [0001] The present invention relates to a stacked structure having a two-dimensional electron gas, a semiconductor device including the stacked structure, and a method of manufacturing the stacked structure.

A two-dimensional electron gas, a semiconductor device including the same, and a method of manufacturing the same.

2. Description of the Related Art A high electron mobility transistor (hereinafter referred to as HEMT) has a structure in which a two-dimensional electron gas (hereinafter referred to as 2DEG) generated at the interface of a heterojunction structure is used as a carrier It is a used device. In a heterojunction structure in which two semiconductor layers having different polarization ratios are bonded, a semiconductor layer having a relatively high polarization ratio may induce a 2DEG in another semiconductor layer bonded thereto. In 2DEG, the mobility of electrons can be very high. These 2DEGs can be used as channels in HEMTs.

The performance / characteristics of semiconductor devices using 2DEG, such as HEMT, are affected by the electron concentration and resistance of 2DEG. The higher the electron concentration of the 2DEG, the more advantageous it is to realize a high output / high performance device with high current density. For this reason, a technique for increasing the electron concentration of 2DEG is required.

Thereby providing a method of increasing the electron concentration of the 2DEG.

A method of forming a laminated structure to which the above method is applied is provided.

And a method of manufacturing a semiconductor device including the stacked structure.

A stacked structure having a 2DEG with a high electron concentration and a semiconductor device including the stacked structure are provided.

According to an aspect of the invention, there is provided a method comprising: forming a first material layer; Heat treating the first material layer; And forming a second material layer on the first material layer to induce a two-dimensional electron gas (2DEG) in the first material layer.

The heat treatment of the first material layer may be performed under conditions that increase the surface roughness of the first material layer.

The heat treatment of the first material layer may be performed under conditions that increase the surface states of the first material layer.

The heat treatment of the first material layer may be performed at a temperature between 500 and 1200 < 0 > C.

The heat treatment of the first material layer may be performed in a nitrogen atmosphere.

At least one of the first material layer and the second material layer may comprise a III-V semiconductor.

The first material layer may include at least one of GaN, InN, and GaAs.

The second material layer may include at least one of AlGaN, AlInN, and AlGaAs.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a stacked structure including a 2DEG by the above-described method; And forming an element using the 2DEG on the stacked structure.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a first material layer; Varying a surface morphology of the first material layer; And forming a second material layer on the first material layer to induce a two-dimensional electron gas (2DEG) in the first material layer.

The step of changing the surface morphology of the first material layer may be performed under conditions that increase the surface roughness of the first material layer.

The step of changing the surface morphology of the first material layer may be performed under conditions that increase the surface states of the first material layer.

The step of varying the surface morphology of the first material layer may include heat treating the first material layer.

At least one of the first material layer and the second material layer may comprise a III-V semiconductor.

The first material layer may include at least one of GaN, InN, and GaAs.

The second material layer may include at least one of AlGaN, AlInN, and AlGaAs.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a stacked structure including a 2DEG by the above-described method; And forming an element using the 2DEG on the stacked structure.

According to another aspect of the present invention, there is provided a semiconductor device comprising: a first material layer having a first surface with a surface roughness of 2 nm or more; A second material layer provided on the first surface of the first material layer to induce a 2DEG (2-dimensional electron gas) on the first material layer; And a device provided on the second material layer, the device using the 2DEG.

The electron concentration of the 2DEG may be 10 < ¹⁴ > / cm < 2 >

At least one of the first material layer and the second material layer may comprise a III-V semiconductor.

The first material layer may include at least one of GaN, InN, and GaAs.

The second material layer may include at least one of AlGaN, AlInN, and AlGaAs.

A stacked structure having a 2DEG with a high electron density can be formed.

When a semiconductor device is manufactured using the above laminated structure, a high performance / high output semiconductor device can be realized.

1 to 3 are cross-sectional views illustrating a method of forming a stacked structure according to an embodiment of the present invention.
3 is a cross-sectional view illustrating a stacked structure according to an embodiment of the present invention.
4 is a cross-sectional view showing an example of a semiconductor device manufactured on the stacked structure of FIG.
5 is a cross-sectional view showing a surface state of a semiconductor layer heat-treated in a method of forming a multilayer structure according to an embodiment of the present invention.
6 is an AFM (atomic force microscopy) surface image of a semiconductor layer (before heat treatment) according to a comparative example.
7 is an AFM (atomic force microscopy) surface image of a semiconductor layer (after heat treatment) according to an embodiment of the present invention.
Description of the Related Art [0002]
10: first semiconductor layer 20: second semiconductor layer
SUB1: substrate S1: source electrode
D1: drain electrode G1: gate electrode

Hereinafter, a laminated structure having a two-dimensional electron gas (2DEG) according to an embodiment of the present invention, a semiconductor device including the same, and a method of manufacturing the same will be described in detail with reference to the accompanying drawings. The widths and thicknesses of the layers or regions illustrated in the accompanying drawings are exaggeratedly shown for clarity of the description. Like reference numerals designate like elements throughout the specification.

1 to 3 are cross-sectional views illustrating a method of forming a stacked structure according to an embodiment of the present invention.

Referring to FIG. 1, a first semiconductor layer 10 may be formed on a substrate SUB1. The substrate SUB1 may be a substrate made of, for example, sapphire, Si, SiC, GaN or the like. The first semiconductor layer 10 may comprise a III-V semiconductor. For example, the first semiconductor layer 10 may include GaN, InN, GaAs, and the like. The first semiconductor layer 10 may be an undoped layer, but it may also be a layer doped with a certain impurity. The first semiconductor layer 10 may be formed by an epitaxial growth method. The first semiconductor layer 10 can be formed using, for example, MOCVD (metal-organic chemical vapor deposition) equipment. Although not shown, a predetermined buffer layer can be formed between the substrate SUB1 and the first semiconductor layer 10. [ The buffer layer may be provided to mitigate the difference in lattice constant and thermal expansion coefficient between the substrate SUB1 and the first semiconductor layer 10 to prevent the crystallinity of the first semiconductor layer 10 from deteriorating. The buffer layer can be formed of, for example, AlN, GaN, AlGaN, AlInN, AlGaInN or the like.

Referring to FIG. 2, the first semiconductor layer 10 may be heat-treated. The heat treatment may be performed under conditions that change the surface characteristics of the first semiconductor layer 10. For example, the heat treatment process may be performed under conditions that increase the surface roughness and / or surface states of the first semiconductor layer 10. The surface roughness of the first semiconductor layer 10 may be increased to about 2 nm or more by the heat treatment process. For example, the surface roughness of the heat-treated first semiconductor layer 10 may be about 2 to 50 nm. 2, the surface (upper surface) of the first semiconductor layer 10 may be rough at a nanoscale or atomic-scale level. On the other hand, an increase in the surface states of the first semiconductor layer 10 may mean an increase in the surface charge. The number of dangling bonds at the surface portion of the first semiconductor layer 10 can be increased by the heat treatment process, and thus the surface charge can be increased. For example, as shown in FIG. 5, a large amount of positive charge can be generated on the surface of the first semiconductor layer 10 by the heat treatment process. The increase in the surface states and / or the surface roughness of the first semiconductor layer 10 can be prevented by increasing the electron concentration of the 2DEG (2-dimensional electron gas) to be formed in the first semiconductor layer 10 It can be a factor to increase.

The heat treatment process of the first semiconductor layer 10 of FIG. 2 will be described in more detail. The heat treatment process may be performed at a temperature of about 500 to 1200 占 폚, for example. Also, the heat treatment process may be performed in a nitrogen atmosphere, and may be performed for several to several tens of minutes. This heat treatment process may be performed in-situ in the deposition equipment (e.g., MOCVD equipment) of the first semiconductor layer 10, or may be performed using a separate furnace other than the deposition equipment , Or may be performed by another method, for example, a laser annealing method.

Referring to FIG. 3, the second semiconductor layer 20 may be formed on the heat-treated first semiconductor layer 10. Similar to the first semiconductor layer 10, the second semiconductor layer 20 can also be formed by an epitaxial growth method. The second semiconductor layer 20 may be formed using MOCVD equipment. The second semiconductor layer 20 may be a layer of material that induces a 2DEG in the first semiconductor layer 10. The second semiconductor layer 20 may comprise a III-V semiconductor. For example, the second semiconductor layer 20 may include AlGaN, AlInN, AlGaAs, or the like. The AlGaN, AlInN, AlGaAs, and the like have a higher polarization ratio than the first semiconductor layer 10, and therefore 2DEG can be induced in the first semiconductor layer 10. When the first semiconductor layer 10 is a GaN layer, the second semiconductor layer 20 may be an AlGaN layer or an AlInN layer. When the first semiconductor layer 10 is an InN layer, the second semiconductor layer 20 may be an AlInN layer. When the first semiconductor layer 10 is a GaAs layer, the second semiconductor layer 20 may be an AlGaAs layer. However, the materials of the first semiconductor layer 10 and the second semiconductor layer 20 shown here are illustrative and can be variously changed. The second semiconductor layer 20 may be a layer doped with an n-type impurity. The n-type impurity may be Si, for example. The second semiconductor layer 20 may have a multi-layer structure including a plurality of different material layers.

The 2DEG formed in the first semiconductor layer 10 by the second semiconductor layer 20 may have a high electron concentration. The 2DEG formed in this embodiment can have an electron concentration 10 to 15 times higher than the electron concentration of the 2DEG formed by the conventional method. This is related to the heat treatment process of the first semiconductor layer 10 described with reference to FIG. According to embodiments of the present invention, the heat-treated first semiconductor layer 10 has a rather large surface roughness at a nanoscale or atomic scale level or has a relatively large surface charge (i.e., a high surface state) , Which suggests that the electron concentration of the 2DEG is increased. In addition, it is assumed that the first semiconductor layer 10 can be stressed by the heat treatment process, and that the electron concentration of the 2DEG can be increased by this stress. However, there may be other factors besides the electron concentration increasing mechanism (mechanism) of 2DEG described here.

A predetermined semiconductor element can be manufactured in the laminated structure of Fig. For example, a semiconductor element (HEMT) having a structure as shown in Fig. 4 can be manufactured.

4, the gate electrode G1 may be provided on a predetermined region of the second semiconductor layer 20 and the source electrode S1 may be formed on the second semiconductor layer 20 on both sides of the gate electrode G1. And a drain electrode (D1). The first semiconductor layer 10, the second semiconductor layer 20, the gate electrode G1, the source electrode S1, and the drain electrode D1 may constitute a HEMT. The 2DEG provided in the first semiconductor layer 10 can be used as a channel of the HEMT. In this regard, the first semiconductor layer 10 may be referred to as a " channel layer ".

FIG. 4 shows a basic structure of a HEMT according to an embodiment of the present invention, and this structure can be variously modified. For example, a gate insulating layer (not shown) or a depletion layer (not shown) may be further provided between the gate electrode G1 and the second semiconductor layer 20. A recessed region (not shown) is formed by recessing the portion of the second semiconductor layer 20 where the gate electrode G1 is formed to a predetermined depth, and then a gate electrode G1 is formed in the recessed region . In this case, the characteristics of the 2DEG corresponding to the recessed region can be changed, and consequently, the characteristics of the HEMT can be adjusted. Various other modifications may be possible.

In addition, the stacked structure including the 2DEG according to the embodiment of the present invention may be used for manufacturing a semiconductor device other than a HEMT. The other semiconductor element may be, for example, a Schottky diode element. In addition, the stacked structure according to the embodiment of the present invention can be applied to all devices using 2DEG.

6 and 7 are atomic force microscopy (AFM) surface images of the semiconductor layer according to the comparative example and the semiconductor layer according to the embodiment of the present invention, respectively. Fig. 6 shows the result for the semiconductor layer before the heat treatment, and Fig. 7 shows the result for the semiconductor layer after the heat treatment. The semiconductor layer of FIG. 6 may correspond to the first semiconductor layer 10 of FIG. 1, and the semiconductor layer of FIG. 7 may correspond to the first semiconductor layer 10 of FIG. The materials of the semiconductor layers in Figs. 6 and 7 were all GaN.

6 and 7, it can be seen that the surface of the semiconductor layer (FIG. 7) after the heat treatment is rougher than the surface of the semiconductor layer (FIG. 6) before the heat treatment. As a result of measuring the surface roughness, the surface roughness of the semiconductor layer before the heat treatment (FIG. 6) was about 1.67 nm, and the surface roughness of the semiconductor layer (FIG. 7) after the heat treatment was about 29.2 nm. From these results, it can be seen that the surface roughness of the semiconductor layer is increased by the heat treatment according to the embodiment of the present invention.

Table 1 below summarizes the results of measuring the electron concentration and the sheet resistance of 2DEG of the laminated structure according to the comparative example and the laminated structure according to the embodiment of the present invention. The laminated structure according to the comparative example is formed without heat treatment, and the laminated structure according to the embodiment is formed by the method of FIGS. 1 to 3, that is, after heat treatment. The stacked structures of the comparative examples and the examples all have a GaN / AlGaN structure. The electron concentration (ie, sheet carrier concentration) in Table 1 was measured by a capacitance-voltage (CV) method. In Table 1, the sheet resistivity is the sheet resistance of the interface between GaN and AlGaN.

Comparative Example
(without thermal treatment) Example
(with thermal treatment) Sheet carrier concentration 1.03 × 10 ¹³ / cm 2 1.47 × 10 ¹⁴ / cm 2 Sheet resistivity 414.9? / Sq 398 Ω / sq

Table 1 shows that the electron concentration (i.e., sheet carrier concentration) of the 2DEG of the laminated structure according to the comparative example is about 1.03 × 10 ¹³ / cm 2, and the electron concentration of the 2DEG of the laminated structure according to the embodiment carrier concentration) is about 1.47 × 10 ¹⁴ / cm 2. Therefore, the electron concentration of the 2DEG of the laminated structure according to the embodiment was 15 times higher than the electron concentration of the 2DEG of the laminated structure according to the comparative example. From these results, it can be seen that the electron concentration of 2DEG is greatly increased by the heat treatment according to the embodiment of the present invention. In addition, the sheet resistivity of the laminated structure according to the embodiment was lower than that of the laminated structure according to the comparative example.

Thus, when a semiconductor device such as a HEMT is formed using such a stacked structure, a high-performance / high-output semiconductor device can be obtained because a stacked structure having a 2DEG with a high electron concentration can be formed according to the embodiment of the present invention . At this time, the semiconductor device can be used, for example, as a power device, but it can be used for various purposes in various other fields. For example, the semiconductor device can be applied not only to power devices, but also to lighting, memory devices, and various circuit fields.

While many have been described in detail above, they should not be construed as limiting the scope of the invention, but rather as examples of specific embodiments. For example, those skilled in the art will appreciate that the method of forming the stacked structures of FIGS. 1 through 3 and the structure of FIG. 4 may be modified in various ways. In addition, it will be understood that a structure having a high electron concentration can be formed by using a method other than the above-described heat treatment process as shown in FIG. 3 and FIG. In addition, those skilled in the art will appreciate that the idea of the present invention is applicable to various semiconductor devices other than HEMTs. Therefore, the scope of the present invention should not be limited by the described embodiments but should be determined by the technical idea described in the claims.

Claims (20)

Forming a first layer of material;
Heat treating the first material layer; And
Forming a second material layer on the first material layer to induce a two-dimensional electron gas in the first material layer,
Wherein the heat treatment of the first material layer is performed under conditions that increase the surface roughness of the first material layer. delete The method according to claim 1,
Wherein the heat treatment of the first material layer is performed under conditions that increase surface states of the first material layer. The method according to claim 1,
Wherein the heat treatment of the first material layer is performed at a temperature between 500 and 1200 캜. The method according to claim 1,
Wherein the heat treatment of the first material layer is performed in a nitrogen atmosphere. The method according to claim 1,
Wherein at least one of the first material layer and the second material layer comprises a III-V semiconductor. The method according to claim 6,
Wherein the first material layer comprises at least one of GaN, InN, and GaAs. 8. The method according to claim 6 or 7,
Wherein the second material layer comprises at least one of AlGaN, AlInN, and AlGaAs. Forming a first layer of material;
Varying a surface morphology of the first material layer;
Forming a second material layer on the first material layer to induce a two-dimensional electron gas in the first material layer,
Wherein changing the surface morphology of the first material layer is performed under conditions that increase surface states of the first material layer. 10. The method of claim 9,
Wherein changing the surface morphology of the first material layer is performed under conditions that increase the surface roughness of the first material layer. delete 10. The method of claim 9,
Wherein changing the surface morphology of the first material layer comprises heat treating the first material layer. 10. The method of claim 9,
Wherein at least one of the first material layer and the second material layer comprises a III-V semiconductor. Forming a laminated structure including a 2DEG (2-dimensional electron gas) by the method according to claim 1; And
And forming an element using the 2DEG on the stacked structure. Forming a laminated structure including a 2DEG (2-dimensional electron gas) by the method according to claim 9; And
And forming an element using the 2DEG on the stacked structure. A first material layer having a first surface with a surface roughness of at least 2 nm;
A second material layer provided on the first surface of the first material layer to induce a 2DEG (2-dimensional electron gas) on the first material layer; And
And an element using the 2DEG, the element being provided on the second material layer,
And the electron concentration of the 2DEG is 10 ¹⁴ / cm 2 or more. delete 17. The method of claim 16,
Wherein at least one of the first material layer and the second material layer comprises a III-V semiconductor. 19. The method of claim 18,
Wherein the first material layer comprises at least one of GaN, InN, and GaAs. 19. The method of claim 18,
Wherein the second material layer comprises at least one of AlGaN, AlInN, and AlGaAs.

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