KR101808409B1 - Parallel connected non-volatile flip-flop and operating method for the same - Google Patents

Parallel connected non-volatile flip-flop and operating method for the same Download PDF

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KR101808409B1
KR101808409B1 KR1020160023074A KR20160023074A KR101808409B1 KR 101808409 B1 KR101808409 B1 KR 101808409B1 KR 1020160023074 A KR1020160023074 A KR 1020160023074A KR 20160023074 A KR20160023074 A KR 20160023074A KR 101808409 B1 KR101808409 B1 KR 101808409B1
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mtj
transistor
write
flop
approach
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KR1020160023074A
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KR20170100786A (en
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윤홍일
동활
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연세대학교 산학협력단
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/161—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • H01L27/228—
    • H01L43/08—
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/027—Generators characterised by the type of circuit or by the means used for producing pulses by the use of logic circuits, with internal or external positive feedback
    • H03K3/037—Bistable circuits
    • H03K3/0372—Bistable circuits of the master-slave type

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  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Static Random-Access Memory (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The present invention discloses a non-volatile flip-flop based on a parallel connection and an operation method thereof. More particularly, the present invention relates to an MTJ device comprising a MTJ element part including a first MTJ and a second MTJ connected to a slave latch of a flip-flop part, a first approach transistor part connected to the first MTJ, And a control circuit portion for controlling a state of the first approach transistor portion and the second approach transistor portion, wherein the first MTJ and the second MTJ are connected in series, The present invention relates to a parallel connection-based nonvolatile flip-flop and an operation method thereof, and more particularly, to a nonvolatile flip-flop and a method of operating the same using a large transistor and a small transistor having different turn- By controlling the state of the transistor in accordance with one operation, it is possible to solve the energy consumption problem and the write speed reduction problem.

Description

TECHNICAL FIELD [0001] The present invention relates to a parallel connection-based nonvolatile flip-flop and a method of operating the same.

The present invention relates to a parallel connection-based nonvolatile flip-flop and an operation method thereof.

A flip-flop is a basic element for temporarily storing information. However, since a conventional flip-flop loses the stored information when the supply of volatile power is interrupted, power must be continuously supplied to preserve the information.

In order to compensate for this problem, there is a need for a nonvolatile flip-flop capable of storing information even when the power supply voltage is cut off. There are many types of nonvolatile flip-flops depending on the device that stores the information, and a flip-flop using a magnetic tunnel junction (MTJ) device is one of the typical circuits among them.

Hereinafter, the basic structure of the MTJ-based nonvolatile flip-flop will be described in detail with reference to FIG.

FIG. 1 is a block diagram showing a basic structure of a conventional MTJ-based nonvolatile flip-flop.

1, a MTJ (Magnetic Tunnel Junction) based non-volatile flip-flop 100 includes a first MTJ 241 and a second MTJ 242 and includes a flip-flop operation mode, a write operation mode , A sleep operation mode, and a read operation mode.

To this end, the MTJ-based non-volatile flip-flop 100 includes a pair of information storage devices MTJ including a D-flip flop 200, a first MTJ 241 and a second MTJ 242, 221).

In the MTJ-based nonvolatile flip-flop 100, since the MTJs 241 and 242 and the write driver 221 are separated from the D flip-flop 200 in the flip-flop operation mode, the non-volatile flip- In the write operation mode, information is stored in the MTJs 241 and 242. In the sleep operation mode, all power is turned off, so no power consumption occurs. In the read operation mode, information stored in the MTJs 241 and 242 is stored Sent to the slave latch.

Conventional MTJ-based nonvolatile flip-flops have two writing schemes in the write operation mode. Hereinafter, two writing methods of a conventional MTJ-based non-volatile flip-flop will be described in detail with reference to FIGS. 2 and 3. FIG.

2 is a circuit diagram of a nonvolatile flip-flop using a conventional serial write method.

Referring to FIG. 2, the MTJ-based nonvolatile flip-flop using the conventional serial write method includes a master latch 210, a slave latch 220, a first MTJ 241, a second MTJ 242, 221).

The MTJ-based nonvolatile flip-flop using the conventional serial write method controls the first MTJ 241 and the second MTJ 242 connected in series during a write operation to simultaneously perform a write operation.

Referring to FIG. 2, the MTJ-based nonvolatile flip-flop using the conventional serial write method has the first transistor 222 turned off and the second transistor 222 turned off when the output Q value is 1, The second transistor 223 is turned on and the third transistor 224 is turned on and the fourth transistor 225 is turned off so that the write current flows from VDD 228 to the third transistor 224, 242, the first MTJ 241, the second transistor 223, and the GND 229. At this time, information 0 is stored in the second MTJ 242 and information 1 is stored in the first MTJ 241 according to the flowing write current direction.

On the contrary, when the value of the output Q is 0, the first transistor 222 is turned on, the second transistor 223 is turned off, the third transistor 224 is turned off, the fourth transistor 225 is turned on, The first MTJ 241, the second MTJ 242, and the fourth transistor 225 to the GND 231 from the first transistor 230 through the first transistor 222, the first MTJ 241, the second MTJ 242, At this time, information 0 is stored in the first MTJ 241 and information 1 is stored in the second MTJ2 242 according to the flowing write current direction.

In the MTJ-based nonvolatile flip-flop using the conventional serial write method, a pair of MTJs 241 and 242 are connected in series and a write operation is performed at the same time. Therefore, in order to supply a sufficient write current, a high VDD need. However, when the voltage is increased, a lot of energy is consumed during the write operation time.

Since write 0 operation is faster than write 1 operation due to the nature of MTJs 241 and 242, write 0 operation is still in progress while write 0 operation has already been completed. Therefore, unnecessary current is continuously supplied to MTJs 241 and 242, There is a problem that unnecessary energy consumption occurs.

In order to overcome the problem of the serial writing method, a two-step writing method was used.

3 is a circuit diagram of a nonvolatile flip-flop using a conventional two-stage write method.

Referring to FIG. 3, the MTJ-based nonvolatile flip-flop using the conventional two-stage write method includes a master latch 310, a slave latch 320, a write driver 330, a first MTJ 343, 344 and a control circuit 350.

The MTJ-based nonvolatile flip-flop using the conventional two-stage write method divides one write operation into two stages (one stage and two stages) and successively divides the write operation into the first MTJ 343 and the second MTJ 344 Write operation.

Referring to FIG. 3, the MTJ-based nonvolatile flip-flop using the conventional two-stage write method includes a write driver 330 and the write driver 330 controls the control of the control circuit 350 A first transistor 331, a second transistor 332, a third transistor 333 and a fourth transistor 334 controlled by signals A and B, respectively.

The MTJ-based nonvolatile flip-flop using the conventional two-stage write method performs one stage when the input signal C of the control circuit 350 is 1, and two stages when C is zero. When the WE (Write Enable) signal of the control circuit 350 is 1 and the information Q to be stored is 1, the outputs of the inverter 345 and the NAND gate 346 of the write driver 330 become 1, The third transistor 335 is turned off, the sixth transistor 336 is turned on, and the node X is connected to the GND 340.

In the MTJ-based nonvolatile flip-flop using the conventional two-stage writing method, when the input signal C becomes 1 in the first stage, A is 0 and B is 1 by the control circuit 350. Accordingly, the first transistor 331 and the fourth transistor 334 are turned on, the second transistor 332 and the third transistor 333 are turned off, and the node Y Is connected to VDD 337 and node Z is connected to GND 342.

Accordingly, since the write current flows from VDD 337 to the GND 340 via the first MTJ 343 and both the node X and the node Z are connected to GND, the voltage across the second MTJ 344 0 so that no write operation is performed on the second MTJ 344. [ Therefore, in the first stage, only the write 1 operation is performed for the first MTJ 343 only.

In the case of the second stage, the MTJ-based non-volatile flip-flop using the conventional two-stage write method, when the input signal C becomes 0, A is 1 and B is 0 through the control circuit 350. Accordingly, the first transistor 331 and the fourth transistor 334 are turned off, and the second transistor 332 and the third transistor 333 are turned on. At this time, the node Y is connected to the GND 338 And node Z is connected to VDD 341. [

Accordingly, since the write current flows from the VDD 341 to the GND 340 through the second MTJ 344 and both the node X and the node Y are connected to the VDD, the voltage across the first MTJ 343 The write operation is not performed. Therefore, in the second stage, only the write 0 operation is performed for the second MTJ 344 only.

In the conventional MTJ-based nonvolatile flip-flop, when the information Q to be stored is 0, the node X is connected to the VDD 335 so that A is 0 and B is 1 in the first stage. In addition, the write current flows from VDD 339 to the GND 342 through the X node and the second MTJ 344, and the write operation is not performed because the voltage across the first MTJ 343 is zero. Therefore, in the first stage, only the write 1 operation is performed for the second MTJ 344 only.

On the other hand, in the second stage, since A is 1 and B is 0, the write current flows from VDD 335 to the GND 338 through the X node and the first MTJ 343. The write operation is not performed because the voltage across both ends of the second MTJ 344 is zero. Therefore, in the second stage, only the write 0 operation is performed for the first MTJ 343 only.

As described above, since the conventional two-stage write method divides the write operation into two stages and performs a write operation only for one MTJ in each stage, the resistance connected to the write driver is smaller than that of the conventional serial write method. Therefore, even if a relatively low power supply voltage is used, sufficient write current can be ensured and power consumption can be reduced.

In addition, in the conventional two-stage writing method, since the opposite operation 1 (0) is performed in the second stage when the writing 0 (1) operation is performed in the first stage, the advantage of this method is that writing Since the operation time can be adjusted, efficient write operation is possible. However, there is a problem that the write operation speed is slow because the two MTJs sequentially perform the write operation.

Korean Patent Publication No. 10-2011-0078181 (entitled " Magnetic Memory and Operation Method Thereof " Korean Patent Laid-Open No. 10-2015-0110189 (titled magnetoresistive memory device having a folded memory array structure) Japanese Laid-Open Patent Application No. 2014-17042 (entitled " Nonvolatile Memory Cell, Nonvolatile Memory Cell Array, and Nonvolatile Memory)

An object of the present invention is to provide a parallel connection-based nonvolatile flip-flop and an operation method thereof, which can improve a write operation speed by including a symmetric parallel write driver capable of simultaneously performing a write operation on each of two MTJs connected in parallel .

It is also an object of the present invention to provide a parallel connection-based nonvolatile flip-flop that can reduce unnecessary energy consumption by resolving the asymmetry problem of writing 0 operation and writing 1 operation by adjusting the access transistor connected to each MTJ, .

It is another object of the present invention to provide a parallel connection-based nonvolatile flip-flop and an operation method thereof, which can use the same time for writing 0 operation and writing 1 operation using an access transistor connected to each MTJ.

It is another object of the present invention to provide a method and apparatus for controlling an operation of a transistor in accordance with write 0 operation and write 1 operation by using a large transistor and a small transistor having different sizes to constitute an access transistor portion connected to each MTJ, The present invention provides a nonvolatile flip-flop based on a parallel connection and a method of operating the same.

The nonvolatile flip-flop based on parallel connection according to an embodiment of the present invention includes an MTJ element part including a first MTJ (Magnetic Tunnel Junction) and a second MTJ (Magnetic Tunnel Junction) connected to a slave latch of a flip- And a second access transistor portion coupled in parallel with the first MTJ and the second MTJ and coupled to the first MTJ and a second access transistor portion coupled to the second MTJ, A write driver for driving the second MTJ, and a control circuit for controlling states of the first and second approach transistor units.

The nonvolatile flip-flop based on parallel connection according to an embodiment of the present invention includes a flip-flop unit including a master latch and a slave latch, an MTJ element unit including a first MTJ and a second MTJ connected to the slave latch, And a second access transistor portion coupled in parallel with the first MTJ and the second MTJ and coupled to the first MTJ and a second access transistor portion coupled to the second MTJ, And a write driver for driving the second MTJ.

A method of operating a parallel-connected nonvolatile flip-flop according to an embodiment of the present invention includes applying an operation signal to a first MTJ and a second MTJ connected to a slave latch of a flip-flop unit based on an operation mode, Controlling a state of a first approach transistor portion connected to the first MTJ and a second approach transistor portion connected to the second MTJ from an activated operation signal and based on the state of the first approach transistor portion and the second approach transistor portion And applying an electric current to the first MTJ and the second MTJ to perform an operation.

The parallel connection-based nonvolatile flip-flop and the operation method thereof may include a symmetric parallel write driver capable of simultaneously performing a write operation on each of the two MTJs connected in parallel, thereby improving the write operation speed.

In addition, according to the embodiment of the present invention, unnecessary energy consumption can be reduced by adjusting the approach transistor portion connected to each of the MTJs to solve the asymmetry problem of write 0 operation and write 1 operation.

Also, according to the embodiment of the present invention, the time required for the writing 0 operation and writing 1 operation can be equally used by using the access transistor connected to each MTJ.

According to the embodiment of the present invention, by controlling the states of the transistors according to the writing 0 operation and the writing 1 operation by using a large transistor and a small transistor having different sizes constituting the access transistor unit connected to each MTJ, And the write speed problem can be solved.

FIG. 1 is a block diagram showing a basic structure of a conventional MTJ-based nonvolatile flip-flop.
2 is a circuit diagram of a nonvolatile flip-flop using a conventional serial write method.
3 is a circuit diagram of a nonvolatile flip-flop using a conventional two-stage write method.
FIG. 4 is a block diagram illustrating a configuration of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention. Referring to FIG.
5 is a circuit diagram of an MTJ element part and an access transistor part of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.
FIG. 6 is a detailed circuit diagram of a parallel connection-based nonvolatile flip-flop according to an exemplary embodiment of the present invention. Referring to FIG.
FIG. 7 illustrates a simulation waveform based on an operation mode of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.
FIG. 8 is a block diagram illustrating a configuration of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.
9 is a flowchart illustrating a method of operating a parallel-connected nonvolatile flip-flop according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings and accompanying drawings, but the present invention is not limited to or limited by the embodiments.

The terminology used herein is for the purpose of illustrating embodiments and is not intended to be limiting of the present invention. In the present specification, the singular form includes plural forms unless otherwise specified in the specification. It is noted that the terms "comprises" and / or "comprising" used in the specification are intended to be inclusive in a manner similar to the components, steps, operations, and / Or additions.

As used herein, the terms "embodiment," "example," "side," "example," and the like should be construed as advantageous or advantageous over any other aspect or design It does not.

Also, the term 'or' implies an inclusive or 'inclusive' rather than an exclusive or 'exclusive'. That is, unless expressly stated otherwise or clear from the context, the expression 'x uses a or b' means any of the natural inclusive permutations.

Also, the phrase "a" or "an ", as used in the specification and claims, unless the context clearly dictates otherwise, or to the singular form, .

Furthermore, the terms first, second, etc. used in the specification and claims may be used to describe various elements, but the elements should not be limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

Unless defined otherwise, all terms (including technical and scientific terms) used herein may be used in a sense commonly understood by one of ordinary skill in the art to which this invention belongs. Also, commonly used predefined terms are not ideally or excessively interpreted unless explicitly defined otherwise.

In the following description of the present invention, a detailed description of known functions and configurations incorporated herein will be omitted when it may make the subject matter of the present invention rather unclear. The terminology used herein is a term used for appropriately expressing an embodiment of the present invention, which may vary depending on the user, the intent of the operator, or the practice of the field to which the present invention belongs. Therefore, the definitions of these terms should be based on the contents throughout this specification.

FIG. 4 is a block diagram illustrating a configuration of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention. Referring to FIG.

Referring to FIG. 4, a parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention includes a first MTJ 561 connected to a slave latch 520 of a flip- 2 MTJ 562 and drives the first MTJ 562 and the second MTJ 562 based on the mode of operation and controls the first MTJ 561 and the second MTJ 562 connected to the first MTJ 561, 562, < / RTI >

The nonvolatile flip-flop 400 according to an embodiment of the present invention includes an MTJ element unit 560, a write driver 530, and a control circuit unit 550.

The MTJ element portion 560 includes a first MTJ 561 and a second MTJ 562 connected to the slave latch 520 of the flip-flop portion 500.

The first MTJ 561 and the second MTJ 562 may have a sandwich structure in which an insulating layer is disposed between a fixed layer and a free layer, which are generally made of a ferromagnetic material. When the electrons pass through the ferromagnetic layer / insulating layer / ferromagnetic layer, the resistance component changes depending on the magnetization arrangement state of the ferromagnetic layer. Unlike the fixed layer having the fixed magnetization arrangement, the magnetization arrangement of the free layer varies depending on the specific write current Can be changed.

When the magnetization arrangement of the fixed layer and the free layer is in the same direction, they are named as parallel (P), and when the magnetization arrangement of the fixed layer and the free layer is in the opposite direction, they are called anti-parallel (AP) . The resistance in the P state has a smaller resistance value than the AP state, and the first MTJ 561 and the second MTJ 562 store information using this resistance difference.

The MTJ element part 560 may be connected in parallel to the flip flop including the master latch 510 and the slave latch 520 and may be connected to the first MTJ element 561 and the second MTJ element 560 of the MTJ element part 560. [ 562 may be in a directly unconnected form.

The non-volatile flip-flop 400 according to an exemplary embodiment of the present invention includes a first MTJ 561 and a second MTJ 562 for driving the first MTJ 561 and the second MTJ 562, respectively, unlike a conventional nonvolatile flip- 561 and the second MTJ 562 may be separated to form a parallel connection structure.

The write driver 530 is connected in parallel with the first MTJ 561 and the second MTJ 562 and includes first access transistor portions 531 and 533 and a second MTJ 562 connected to the first MTJ 561, And second MTJ 561 and second MTJ 562 based on the mode of operation.

The first approach transistor section may include a first large transistor and a first small transistor of different sizes, and the second approach transistor section may include a second large transistor and a second small transistor of different sizes.

At this time, the current for operation of the transistor may be proportional to the size of the transistor.

In other words, when the write 0 operation, the transistor can be turned on by a small current, and only the transistor having a relatively small size can be turned on.

In write 1 operation, a large current is required compared to write 0 operation. In write 1 operation, a large current is applied and both transistors having different sizes can be turned on.

For example, the ratio of the size of the first small transistor to the size of the first large transistor may be designed to be 1: 4.

For example, if the same current flows through the MTJ, the write 0 operation may take 0.1 seconds to turn on, and the write 1 operation may take 0.4 seconds to turn on.

In other words, a single MTJ requires a current of 0.1 amps to complete a write 0 operation for 0.1 second, and a current of 0.5 amps (0.1 + 0.4) or more may be needed to complete a write 1 operation for a second.

Eliminating the asymmetry in time of such a write operation can improve the write speed.

5, a first MTJ 561 and a second MTJ 562 are coupled to a first MTJ 561 and a second MTJ 562. A first MTJ 561 and a second MTJ 562 are coupled to a first MTJ 561 and a second MTJ 562, The configuration will be described in detail.

5 is a circuit diagram of an MTJ element part and an access transistor part of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.

5, a parallel connection based non-volatile flip flop 400 includes a first MTJ 561 and a second MTJ 562 and includes a first access transistor portion 531 connected to the first MTJ 561 533 coupled to the second MTJ 562, and second access transistor portions 532, 534 coupled to the second MTJ 562.

The first approach transistor units 531 and 533 are connected to the first large transistor 531 having a large turn-on voltage level (or size) and the first large transistor 531 having a turn-on voltage level (or size) And may include a small transistor 533.

The second approach transistor portions 532 and 534 are connected to the second large transistor 532 having a large turn-on voltage level (or size) and the second turn-on transistor 530 having a relatively low turn-on voltage level (or size) And a second small transistor 534.

The first large transistor 531 and the second large transistor 532 may be turned on at a predetermined first voltage level and the first small transistor 533 and the second small transistor 534 may be turned on at a second predetermined voltage level, May be turned on at a second predetermined voltage level that is less than the first voltage level.

Referring to FIG. 5, a parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention includes a first MTJ 561 and a second MTJ 562 connected in parallel, and the first MTJ 561 533 and second approach transistor portions 532, 534 respectively connected to the second MTJ 562 and the first small transistor 533 and the second small transistor 534 Can be operated by the same control signal.

Referring again to FIG. 4, the write driver 530 may drive the first MTJ 561 and the second MTJ 562 from the operation mode based on the control signal of the control circuit unit 550.

The control circuit portion 550 controls the states of the first approach transistor portions 531 and 533 and the second approach transistor portions 532 and 534.

The control circuit portion 550 turns on the first approach transistor portions 531 and 533 and the second approach transistor portions 532 and 534 to apply the write current to the MTJ element portion 560 in the write operation mode, And turn off the power supply.

At least one of the first small transistor 533 and the second small transistor 534 is turned on and at least one of the first large transistor 531 and the second large transistor 532 is turned off And in the write 1 operation, at least one of the first approach transistor portions 531, 533 and the second approach transistor portions 532, 534 may be turned on.

The first MTJ 561 and the second MTJ 562 of the parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention are connected to each other based on the write operation mode of write 0 operation and write 1 operation, Another write operation mode can be performed.

The first MTJ 561 and the second MTJ 562 are enabled to receive different write currents from the first approach transistor portions 531 and 533 and the second approach transistor portions 532 and 534 that are turned on and off based on the write operation mode .

For example, when a write 0 operation is performed in the first MTJ 561 based on the write operation mode, a small write current is required, so that the first small transistor 533 having a relatively small size is turned on, The large transistor 531 can be turned off. In addition, since write 0 operation has been performed in the first MTJ 561, write-1 operation is performed in the second MTJ 562, and the second MTJ 562 requires a large write current, 532, and 534 may be turned on.

Further, when the write 1 operation is performed in the first MTJ 561 based on the write operation mode, since the large write current is required, the first approach transistor portions 531 and 533 can be turned on, The second MTJ 562 can perform a write 0 operation and the second MTJ 562 requires a small write current because the write 1 operation has been performed in the second small transistor 561. Therefore, The third transistor 534 may be turned on, and the second large transistor 532 may be turned off.

Herein, the small write current may mean a preset value that can secure a sufficient write current even if a low power supply voltage is used, and a relatively small write current It can mean current. However, the predetermined reference value for classifying the small write current, the large write current, the low power supply voltage, and the high power supply voltage is not limited.

The control circuit 550 of the parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention controls the slave latch 520 to apply a read current to the MTJ element portion 560 in the read operation mode. On and off states of the first latch transistor and the second latch transistor included in the first latch transistor and the second latch transistor.

Different read currents may be applied from the first approach transistor units 531 and 533 and the second approach transistor units 532 and 534 which are turned on and off based on the read 0 operation and the read 1 operation.

The first MTJ 561 and the second MTJ 562 of the parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention are connected to each other on the basis of the read operation mode of the read 0 operation and the read 1 operation, Another read operation mode can be performed.

For example, based on the read operation mode, the slave latch 520 plays the role of a read circuit, and the first latch transistor and the second latch transistor included in the slave latch 520 are turned on, The nonvolatile flip-flop 400 based on the parallel connection according to the embodiment of the present invention includes the first MTJ 561 and the second MTJ 561 and the second MTJ 562, 562 may be moved to the slave latch 520.

In addition, the control circuit 550 of the parallel connection-based nonvolatile flip-flop 400 according to the embodiment of the present invention can perform the flip-flop operation mode. In the flip-flop operation mode, the clock (CLK) , It is possible to apply the value of the input D to the master latch 510 and to the output Q when the clock signal is 1 to perform the flip-flop operation.

In addition, the control circuit 550 of the parallel connection-based nonvolatile flip-flop 400 according to the embodiment of the present invention can perform the sleep operation mode. In the sleep operation mode, all the power is shut off, I never do that. Accordingly, all the information may be stored in the MTJ element unit 560 through the write operation mode.

FIG. 6 is a detailed circuit diagram of a parallel connection-based nonvolatile flip-flop according to an exemplary embodiment of the present invention. Referring to FIG.

Referring to FIG. 6, a parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention includes an MTJ element unit 560, a write driver 530, and a control circuit unit 550. In addition, the non-volatile flip-flop based on the parallel connection according to an embodiment of the present invention may further include a flip-flop unit 500 including a master latch 510 and a slave latch 520.

The parallel connection-based nonvolatile flip-flop 400 according to the embodiment of the present invention performs a write operation mode when the WE (Write Enable) signal is 1 and a read operation mode when the RE (Read Enable) Can be performed.

The parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention may perform a write operation mode on the MTJ element unit 560 to store information before the power is turned off. In addition, the first approach transistor portions 531 and 533 of the parallel connection-based nonvolatile flip-flop 400 according to an embodiment of the present invention are connected to the first MTJ 561 and the second approach transistor portion 532, and 534 may be coupled to the second MTJ 562.

The first approach transistor units 531 and 533 include a first large transistor 531 and a first small transistor 533 of different sizes and the second approach transistor units 532 and 534 include 2 < / RTI > large transistor 532 and a second small transistor 534.

In a non-volatile flip-flop 400 based on a parallel connection according to an embodiment of the present invention, since a small write current is required in a write 0 operation, the first small transistor 533 and the second small transistor 534, The first access transistor sections 531 and 533 and the second access transistor sections 532 and 534 may be both turned on because a large write current is required.

For example, if the output Q is 1, the second MTJ 562 may perform a write 0 operation, the first MTJ 561 may perform a write 1 operation, and the NOR The control signal S0 from the gate and the OR gate is 1, S1 is 1, and S2 can be 0.

Only a second small transistor 534 having a small size is turned on by the control signal and a second transistor 532 having a large size is turned off because a small write current is required for the write 0 operation. A small write current may be applied to the non-volatile flip-flop 400 based on the example parallel connection.

A zero is output from the second NAND gate 536 in the write driver 530 based on the small write current and the third transistor 539 may be turned on and a small write current may be applied from the VDD 543 to the second MTJ To the GND 523 included in the slave latch 520 through the first small transistor 562 and the second small transistor 534.

In addition, since a large write current is required for the write 1 operation, both the first large transistor 531 and the first small transistor 533 of different sizes are turned on by the control signal, A large write current may be applied to the non-volatile flip-flop 400 based on the parallel connection.

A 1 is output from the first NAND gate 535 in the write driver 530 based on the large write current and the second transistor 538 may be turned on and a large write current is included in the slave latch 520 May be applied to the GND 544 from the VDD 524 through the first approach transistor portions 531, 533 and the first MTJ 561.

In the parallel connection based nonvolatile flip-flop 400 according to an embodiment of the present invention, when the output Q is 0, on the other hand, the second approach transistor units 532 and 534 connected to the second MTJ 562 are turned on Write operation 1 is performed. Only the first small transistor 533 of the first approach transistor unit 531, 533 connected to the first MTJ 561 is turned on and the write 0 operation is performed .

In addition, the non-volatile flip-flop 400 based on the parallel connection according to the embodiment of the present invention can perform a read operation mode in which information stored in the MTJ element unit 560 is sent to the slave latch 520 .

For example, when the RE signal is 1 and the WE signal is 0, the control signal S0 from the NOR gate and the OR gate included in the control circuit unit 550 is 0, S1 is 1, and S2 is 0.

Since the outputs of the first NAND gate 535 and the second NAND gate 536 of the write driver 530 are both 1 and the second transistor 538 and the fourth transistor 540 are turned on, 1 MTJ 561 and second MTJ 562 may be connected to GND 544 and GND 546, respectively.

The first latch transistor 521 and the second latch transistor 522 included in the slave latch 520 are turned on because the slave latch 520 functions as a read circuit in the read operation mode, The read current may be applied to the GNDs 544 and 546 through the first MTJ 561 and the second MTJ 562. [

Since the first MTJ 561 and the second MTJ 562 of the parallel connection-based nonvolatile flip-flop 400 according to the embodiment of the present invention generate a discharge with a smaller resistance value quickly, the first MTJ 561 ) And the second MTJ 562 become a 0 state, and the other one can be in a 1 state by the feedback operation.

Accordingly, the parallel connection-based nonvolatile flip-flop 400 according to the embodiment of the present invention performs the flip-flop operation mode again after the read operation mode is performed, so that the flip-flop operation mode, the write operation mode, A cyclic operation including an operation mode and a read operation mode can be started.

FIG. 7 illustrates a simulation waveform based on an operation mode of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.

More specifically, the parallel connection-based nonvolatile flip-flop according to an exemplary embodiment of the present invention includes VDD, CLK, D, and CL according to an operation mode including a flip-flop operation mode, a write operation mode, a sleep operation mode, The first MTJ , the second MTJ , the S0, the S1, the S2, the first MTJ, and the second MTJ .

 Referring to FIG. 7, in a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention, when the CLK signal is 0 in the flip-flop operation mode, the value of the input D signal is sent to the master latch. When the CLK signal is 1 The value of the input D signal can be sent as the output Q signal.

In the write operation mode, when the WE signal is 1, the write operation is performed so that the I first MTJ signal becomes the 1 state and the I second MTJ signal becomes the 0 state. From the control circuit section, S0 is 1 and S1 is 1 , S2 is 0, the first MTJ performs a write 1 operation, and the second MTJ performs a write 0 operation. Also, it can be seen that the R second MTJ exhibits a low waveform because it uses a low write current when performing a write 0 operation.

In the sleep mode, no power is consumed because all the power is cut off. In the read operation mode, the RE signal becomes 1, the WE signal becomes 0, and S0 is 0, S1 is 1, S2 is 0 The information stored in the first MTJ and the second MTJ is transferred to the slave latch, so that it is confirmed that the state change of the first MTJ and the second MTJ do not occur.

The parallel connection-based nonvolatile flip-flop according to an exemplary embodiment of the present invention performs a cyclic operation by performing a flip-flop operation mode after a read operation mode.

That is, the nonvolatile flip-flop based on the parallel connection according to an embodiment of the present invention drives the first MTJ and the second MTJ in parallel, thereby improving the energy consumption and write operation speed of the write driver.

Referring to Table 1, the parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention has write energies of 71.6% and 41.7%, respectively, as compared with the conventional non-volatile flip-flop using two- , And the write speed is improved by 3 times and 3.5 times, respectively.

[Table 1]

Figure 112016018993405-pat00001

(In the parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention, when the magnetization arrangement state of the fixed layer and the free layer of the MTJ element portion is changed from the non-equilibrium state (AP) to the equilibrium state (P) , And the writing speed is 10 ns when changing from the equilibrium state (P) to the non-equilibrium state (AP).)

FIG. 8 is a block diagram illustrating a configuration of a parallel connection-based nonvolatile flip-flop according to an embodiment of the present invention.

Referring to FIG. 8, a parallel connection-based nonvolatile flip-flop 600 according to an embodiment of the present invention includes a first MTJ 711 connected to a slave latch 702 of a flip- (712), and drives the first MTJ (711) and the second MTJ (712) based on the operating mode.

To this end, the parallel connection-based nonvolatile flip-flop 600 according to the embodiment of the present invention includes a flip-flop unit 700, an MTJ element unit 710, and a write driver 720.

The flip-flop unit 700 includes a master latch 701 and a slave latch 702. For example, the flip-flop unit 700 may be a D-flip-flop.

The MTJ element portion 710 includes a first MTJ 711 and a second MTJ 712 connected to the slave latch 702 of the flip flop portion 700.

The first MTJ 711 and the second MTJ 712 may have a sandwich structure in which an insulating layer is disposed between a fixed layer and a free layer, which are generally made of a ferromagnetic material. When the electrons pass through the ferromagnetic layer / insulating layer / ferromagnetic layer, the resistance component changes depending on the magnetization arrangement state of the ferromagnetic layer. Unlike the fixed layer having the fixed magnetization arrangement, the magnetization arrangement of the free layer varies depending on the specific write current Can be changed.

When the magnetization arrangement of the fixed layer and the free layer is in the same direction, they are named as parallel (P), and when the magnetization arrangement of the fixed layer and the free layer is in the opposite direction, they are called anti-parallel (AP) . The resistance in the P state has a smaller resistance value than the AP state, and the first MTJ 711 and the second MTJ 712 store information by using the resistance difference.

The MTJ element portion 710 may be connected in parallel to the flip-flop portion 700 including the master latch 701 and the slave latch 702. The MTJ element portion 710 may be connected to the first MTJ element 711 of the MTJ element portion 710, The second MTJ 712 may be in a directly unconnected form.

Write drive 720 is coupled in parallel with the first MTJ 711 and the second MTJ 712 and has a first access transistor portion coupled to the first MTJ 711 and a second access transistor portion coupled to the second MTJ 712. [ Transistor portion, and drives the first MTJ 711 and the second MTJ 712 based on the operation mode.

For example, the write driver 720 may drive the first MTJ 711 and the second MTJ 712 from an operation mode based on a control signal of a control circuit (not shown).

The first MTJ 711 and the second MTJ 712 of the parallel connection-based nonvolatile flip-flop 600 according to the embodiment of the present invention are turned on in the write operation mode by turning on the first access transistor unit and the second access transistor unit And a different write current may be applied based on the turned-off state.

Also, in the read operation mode, the first MTJ 711 and the second MTJ 712 are turned on and off based on the states of the first latch transistor and the second latch transistor included in the slave latch 520, A different read current may be applied.

FIG. 9 is a flowchart illustrating a method of operating a parallel-connected nonvolatile flip-flop according to an embodiment of the present invention. Referring to FIG.

As shown in FIG. 9, in step 910, an operation signal is applied to the first MTJ and the second MTJ connected to the slave latch of the flip-flop based on the operation mode.

For example, step 910 may apply different write 0 operations and write 1 operations to the first MTJ and the second MTJ when in the write operation mode and different write 0 operations and write 1 operations to the first MTJ and the second MTJ, respectively, A read 0 operation and a read 1 operation.

In step 920, the state of the first approach transistor part connected to the first MTJ and the second approach transistor part connected to the second MTJ are controlled from the applied operation signal.

The first access transistor unit may include a first large transistor and a first small transistor of different sizes and the second access transistor unit may include a second large transistor and a second small transistor of different sizes.

Step 920 may be a step of controlling the turning on and off states of the first approach transistor unit and the second approach transistor unit to apply a write current to the first MTJ and the second MTJ when in the write operation mode.

In the write operation mode, the write operation mode may be such that at least one of the first small transistor and the second small transistor is turned on, and at least one of the first large transistor and the second large transistor is turned off.

On the other hand, in the write operation, the write operation mode may be a state in which at least one of the first approach transistor unit and the second approach transistor unit is turned on.

Also, step 920 is a step of controlling the turn-on and turn-off states of the first latch transistor and the second latch transistor included in the slave latch to apply the read current to the first MTJ and the second MTJ, Lt; / RTI >

In operation 930, current is applied to the first MTJ and the second MTJ based on the states of the first approach transistor portion and the second approach transistor portion to perform an operation.

In step 930, in the write operation mode, different write currents are applied to the first MTJ and the second MTJ from the first approach transistor portion and the second approach transistor portion that are turned on and off based on the write operation mode, Or the like.

Also, in step 930, in the read operation mode, different read currents are applied to the first MTJ and the second MTJ from the first approach transistor portion and the second approach transistor portion that are turned on and off based on the read operation mode And performing an operation.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. For example, it is to be understood that the techniques described may be performed in a different order than the described methods, and / or that components of the described systems, structures, devices, circuits, Lt; / RTI > or equivalents, even if it is replaced or replaced.

Therefore, other implementations, other embodiments, and equivalents to the claims are also within the scope of the following claims.

400: Parallel-based non-volatile flip-flop
500: flip flop part
560: MTJ element part
530:
550: Control circuit part
561: First MTJ
562: Second MTJ
531: first large transistor
532: second large transistor
533: first small transistor
534: second small transistor

Claims (20)

An MTJ element section including a first MTJ (Magnetic Tunnel Junction) and a second MTJ (Magnetic Tunnel Junction) connected to the slave latch of the flip-flop section;
A first access transistor connected in parallel with the first MTJ and the second MTJ and coupled to the first MTJ and a second access transistor coupled to the second MTJ, And a write driver for driving the second MTJ; And
And a control circuit unit for controlling the states of the first and second approach transistor units,
The first approach transistor portion includes a first large transistor and a first small transistor of different sizes,
The second approach transistor portion includes a second large transistor and a second small transistor of different sizes,
The write driver may be configured to perform a write operation or a different read operation on the first MTJ and the second MTJ based on different write currents or different read currents from the first approach transistor unit and the second approach transistor unit, To perform an operation
Parallel connection based nonvolatile flip flop. The method according to claim 1,
Wherein the ratio of the size of the first large transistor and the second large transistor to the size of the first small transistor and the second small transistor is 4: 1. The method according to claim 1,
The control circuit section
And controls the first and second approach transistor sections to turn on and turn off so as to apply a write current to the MTJ element section in a write operation mode,
Parallel connection based nonvolatile flip flop. The method of claim 3,
The write operation mode
In the write 0 operation, at least one of the first small transistor and the second small transistor is turned on, and at least one of the first large transistor and the second large transistor is turned off
Parallel connection based nonvolatile flip flop. 5. The method of claim 4,
The write operation mode
Write operation, at least one of the first and second approach transistor portions is turned on.
Parallel connection based nonvolatile flip flop. 6. The method of claim 5,
The first MTJ and the second MTJ
And the first and second access transistor sections are turned on and off based on the write operation mode, respectively.
Parallel connection based nonvolatile flip flop. The method according to claim 1,
The control circuit section
In the read operation mode, a state in which the first latch transistor and the second latch transistor included in the slave latch are turned on and off so as to apply a read current to the MTJ element portion
Parallel connection based nonvolatile flip flop. 8. The method of claim 7,
The first MTJ and the second MTJ
Wherein the first and second access transistor sections are turned on and off based on the read 0 operation and the read 1 operation, respectively.
Parallel connection based nonvolatile flip flop. A flip flop including a master latch and a slave latch;
An MTJ element part including a first MTJ and a second MTJ connected to the slave latch; And
A first access transistor connected in parallel with the first MTJ and the second MTJ and coupled to the first MTJ and a second access transistor coupled to the second MTJ, And a write driver for driving the second MTJ,
The write driver may be configured to perform a write operation or a different read operation on the first MTJ and the second MTJ based on different write currents or different read currents from the first approach transistor unit and the second approach transistor unit, To perform an operation
Parallel connection based nonvolatile flip flop. 10. The method of claim 9,
The first approach transistor portion includes a first large transistor and a first small transistor of different sizes,
The second approach transistor portion includes a second large transistor and a second small transistor of different sizes
Parallel connection based nonvolatile flip flop. 11. The method of claim 10,
The first MTJ and the second MTJ
In the write operation mode, different write currents are applied based on the states of the first and second approach transistor sections being turned on and off, respectively
Parallel connection based nonvolatile flip flop. 12. The method of claim 11,
The first MTJ and the second MTJ
In the read operation mode, different read currents are applied based on the states of the first latch transistor and the second latch transistor included in the slave latch being turned on and off, respectively
Parallel connection based nonvolatile flip flop. A method of operating a parallel-connected non-volatile flip-flop,
Applying an operating signal to a first MTJ and a second MTJ coupled to a slave latch of the flip-flop portion based on an operating mode;
Controlling a state of a first approach transistor portion connected to the first MTJ and a second approach transistor portion connected to the second MTJ from the applied operation signal; And
And applying an electric current to the first MTJ and the second MTJ based on a state of the first approach transistor unit and the second approach transistor unit,
The step of applying current to the first MTJ and the second MTJ to perform an operation includes:
Based on different write currents or different read currents from the first approach transistor portion and the second approach transistor portion, the first MTJ and the second MTJ perform different write operations or different read operations Step of driving
Wherein the first and second parallel connection-based non-volatile flip-flops operate in parallel. 14. The method of claim 13,
The first approach transistor portion includes a first large transistor and a first small transistor of different sizes,
The second approach transistor portion includes a second large transistor and a second small transistor of different sizes,
Wherein the ratio of the size of the first large transistor and the size of the second small transistor to the size of the first small transistor and the size of the second small transistor is 4: 1. . 15. The method of claim 14,
The step of applying the operating signal
Write operation, the write-0 operation and the write-1 operation are applied to the first MTJ and the second MTJ.
A method of operating a parallel - connected nonvolatile flip - flop. 16. The method of claim 15,
The step of controlling the state
Off state of the first approach transistor unit and the second approach transistor unit to apply a write current to the first MTJ and the second MTJ in a write operation mode,
A method of operating a parallel - connected nonvolatile flip - flop. 17. The method of claim 16,
The write operation mode
In the write 0 operation, at least one of the first small transistor and the second small transistor is turned on, and at least one of the first large transistor and the second large transistor is turned off
A method of operating a parallel - connected nonvolatile flip - flop. 18. The method of claim 17,
The write operation mode
Write operation, at least one of the first and second approach transistor portions is turned on.
A method of operating a parallel - connected nonvolatile flip - flop. 19. The method of claim 18,
The step of performing the operation
And a write operation is performed by applying different write currents to the first MTJ and the second MTJ from the first approach transistor portion and the second approach transistor portion that are turned on and off based on the write operation mode To
A method of operating a parallel - connected nonvolatile flip - flop. 16. The method of claim 15,
The step of applying the operating signal
In a read operation mode, applying different read 0 operations and read 1 operations to the first MTJ and the second MTJ.
A method of operating a parallel - connected nonvolatile flip - flop.
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