KR101802516B1 - Liquid Crystal Display Device and Driving Method of the same - Google Patents

Abstract

An embodiment of the present invention is a liquid crystal display device comprising: a liquid crystal panel; A driving unit for supplying a data signal and a gate signal to the liquid crystal panel; And FRC (Unit Rate Control) unit patterns including at least four sub dithering patterns according to a video signal input from the outside are arranged in the order of the vertical and vertical directions, And an FRC unit for circulating the at least four sub dithering patterns in the vertical direction in a predetermined period so as to overlap with each other.

Description

[0001] The present invention relates to a liquid crystal display device and a driving method thereof,

An embodiment of the present invention relates to a liquid crystal display and a driving method thereof.

As the information technology is developed, the market of display devices, which is a connection medium between users and information, is getting larger. Accordingly, a flat panel display (FPD) such as a liquid crystal display (LCD), an organic light emitting diode (OLED), and a plasma display panel (PDP) Usage is increasing.

A liquid crystal display device that is part of the above-described display devices repeatedly uses a FRC unit block pattern (8X8) that is designed in advance, thereby causing visual artifacts in image representation. In general FRC pattern arrangements, pre-designed 8 × 8 FRC unit patterns are applied vertically and horizontally in the same screen. As the number of frames increases, the 8 × 8 FRC unit pattern constituting one screen changes. As a result, the general FRC method generates a visual artifact due to interference between a specific input image pattern and the FRC pattern. In other words, the general FRC method causes visual artifacts because the FRC unit patterns are repeated in a small cycle, up and down and left and right, so that the FRC unit patterns are distributed on a certain pattern rather than being dispersed on average in the time and space regions.

In order to improve this, a method of changing the internal structure of the FRC unit pattern according to the image characteristic or the inversion method has been proposed. However, the conventional FRC method still has limitations in improving visual artifacts such as thin diagonal pattern, thin horizontal line pattern, and thin vertical line pattern which are generated at low gradations, and improvement thereof is required.

SUMMARY OF THE INVENTION An embodiment of the present invention for solving the above problems of the background art provides a liquid crystal display device capable of improving visual artifacts such as a thin diagonal pattern, a thin horizontal line pattern, a thin vertical line pattern, .

According to an embodiment of the present invention, there is provided a liquid crystal display device comprising: a liquid crystal panel; A driving unit for supplying a data signal and a gate signal to the liquid crystal panel; And FRC (Unit Rate Control) unit patterns including at least four sub dithering patterns according to a video signal input from the outside are arranged in the order of the vertical and vertical directions, And an FRC unit for circulating the at least four sub dithering patterns in the vertical direction in a predetermined period so as to overlap with each other.

The FRC unit includes a data expanding unit for expanding the input video signal by at least one bit to generate an expanded video signal, a counter unit for counting the number of pixels, the number of horizontal lines, and the number of frames based on the expanded video signal, And a pattern matching unit for performing pattern matching with the FRC unit pattern initially set in the spatial area using the number of pixels and the number of horizontal lines and selecting one of at least four FRC patterns according to the result have.

The pattern matching unit may select one of at least four FRC patterns to output the modified FRC unit pattern, and perform pattern matching using the changed FRC unit pattern in the subsequent pattern matching.

The pattern matching unit determines whether the upper 8 bits + 1 are to be performed by checking the overflow of the extended video signal when the patterns are matched, and bypasses the upper 8 bits when the patterns are mismatched.

The pattern matching unit determines the pattern arrangement in the spatial area according to the number of pixels and the remaining value obtained by dividing the number of horizontal lines by 8, wherein the remaining value obtained by dividing the number of pixels by 8 is 0 and the number of horizontal lines is divided by 8 If the remaining value is not 0, it is checked whether the extended video signal corresponds to the end of a specific frame. If the extended video signal is not the last video signal of the specific frame, overflow checking of the video signal determines whether the upper 8 bits + 1 And if the patterns are mismatched, the process of bypassing the upper 8 bits can be repeated.

The pattern matching unit determines the pattern arrangement in the spatial area according to the number of pixels and the remaining value obtained by dividing the number of horizontal lines by 8, wherein the remaining value obtained by dividing the number of pixels by 8 is 0 and the number of horizontal lines is divided by 8 If the remaining value is 0, it can be used as an index for selecting one of at least four FRC patterns by increasing the pattern array index by 1 and using the residual value obtained by dividing the pattern array index by 4.

The pattern matching unit can determine the gradation level according to the lower 3 bits in the extended video signal.

The pattern matching unit may select a path to perform pattern matching according to the remainder value obtained by dividing the number of frames by 4 and perform the same pattern matching at a period of 4 frames.

According to another aspect of the present invention, there is provided a method of generating a video signal, the method comprising: generating an extended video signal by expanding an input video signal by at least one bit; Generating a number of pixels, a number of horizontal lines, and a number of frames based on the extended video signal; Determining a gradation level according to lower 3 bits of the extended video signal; Selecting a path to perform pattern matching according to a remainder value obtained by dividing the number of frames by 4; Performing pattern matching with an FRC unit pattern initially set in a spatial area using the number of pixels and the number of horizontal lines; And determining a pattern array such that one of at least four FRC patterns is selected in the spatial domain according to the number of pixels and the remainder value obtained by dividing the number of horizontal lines by eight.

In the step of determining the pattern array in the spatial domain, if the remaining value obtained by dividing the number of pixels by 8 is 0, and the remaining value obtained by dividing the number of horizontal lines by 8 is not 0, it is checked whether the extended video signal corresponds to the end of a specific frame If the extended video signal is not the last video signal of a specific frame, it is determined whether the upper 8 bits + 1 are to be performed through the overflow check of the video signal. If the pattern is mismatched, the upper 8 bits are bypassed If the remainder value obtained by dividing the number of pixels by 8 is 0, the remainder value obtained by dividing the number of horizontal lines by 8 is 0, the pattern array index is incremented by 1, and the remaining value obtained by dividing the pattern array index by 4 is used It can be used as an index to select one of at least four FRC patterns.

Embodiments of the present invention provide a liquid crystal display device and a method of driving the same that can improve visual artifacts such as a thin diagonal pattern, a thin horizontal line pattern, and a thin vertical line pattern generated at low gradations.

1 is a schematic block diagram of a liquid crystal display according to an embodiment of the present invention;
2 is a schematic block diagram of a FRC part included in a timing control part of a liquid crystal display according to an embodiment of the present invention;
3 is a flowchart for explaining pattern matching by the FRC unit;
4 is a view for explaining a comparison between a FRC pattern matching method according to a comparative example and a FRC pattern matching method according to the present invention.
5 to 8 are views for explaining an FRC pattern according to the present invention in which noise generated in a FRC pattern according to a comparative example is improved.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic block diagram of a liquid crystal display according to an embodiment of the present invention.

1, the liquid crystal display includes a timing controller TCN, a data driver DDRV, a gate driver SDRV, a liquid crystal panel PNL, and a backlight unit BLU.

The timing control unit TCN receives a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, a clock signal CLK and a video signal RiGiBi from the outside.

The timing control unit TCN controls the driving unit including the data driving unit DDRV and the gate driving unit SDRV. In addition, the timing control unit TCN arranges FRC (Frame Rate Control) unit patterns including at least four sub dithering patterns in the order of up and down direction according to a video signal input from the outside, And an FRC unit for cyclically rotating at least four sub-dithering patterns at regular intervals in a vertical direction so as to overlap non-overlapping with the previous frame. The timing controller TCN controls the data driver DDRV and the data driver DDRV using timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable signal DE, and a clock signal CLK. And controls the operation timing of the driving unit including the driving unit SDRV. The timing control unit TCN can determine the frame period by counting the data enable signal DE in one horizontal period so that the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync supplied from the outside can be omitted. The control signals generated by the timing controller TCN include a gate timing control signal GDC for controlling the operation timing of the gate driver SDRV and a data timing control signal DDC for controlling the operation timing of the data driver DDRV. ) May be included. The gate timing control signal GDC includes a gate start pulse GSP, a gate shift clock GSC and a gate output enable signal GOE. The gate start pulse GSP is supplied to a gate drive IC (Integrated Circuit) generating the first gate signal. The gate shift clock GSC is a clock signal commonly input to the gate drive ICs, and is a clock signal for shifting the gate start pulse GSP. The gate output enable signal GOE controls the output of the gate drive ICs. The data timing control signal DDC includes source start pulses (Source, Start Pulse, SSP), Source Sampling Clock (SSC), Source Output Enable (SOE), and the like. The source start pulse SSP controls the data sampling start timing of the data driver DDRV. The source sampling clock SSC is a clock signal for controlling the sampling operation of data in the data driver DDRV based on the rising or falling edge. The source output enable signal SOE controls the output of the data driver DDRV.

The gate driving unit SDRV is responsive to the gate timing control signal GDC supplied from the timing control unit TCN so as to adjust the swing width of the gate driving voltage at which the transistors of the sub pixels SP included in the liquid crystal panel PNL can operate And sequentially generates the gate signal while shifting the level of the signal. The gate driver SDRV supplies the gate signal generated through the gate lines GL to the sub-pixels SP included in the liquid crystal panel PNL. The gate driver SDRV may be formed directly on both sides of the liquid crystal panel PNL formed on the transistor substrate at the same time as the subpixels SP by a GIP (Gate In Panel) process. Alternatively, the gate driver SDRV may be mounted on a TCP (Tape Carrier Package) and attached to a transistor substrate of the liquid crystal panel PNL by a TAB (Tape Automated Bonding) process.

The data driver DDRV samples and latches the digital video signal RrGrBr supplied from the timing control unit TCN in response to the data timing control signal DDC supplied from the timing control unit TCN, . The data driver DDRV converts a digital image signal RGB into a gamma reference voltage and converts the image signal RGB into an analog data voltage. The data driver DDRV supplies the data signal converted through the data lines DL to the sub-pixels SP included in the liquid crystal panel PNL. The data driver DDRV is mounted on a TCP (Tape Carrier Package), bonded to a transistor substrate of the liquid crystal panel PNL by a TAB process, and connected to a source PCB (Printed Circuit Board). Alternatively, the data driver DDRV may be mounted on a transistor substrate of the liquid crystal panel PNL by a COG (Chip On Glass) process.

The liquid crystal panel PNL includes sub-pixels SP arranged in a matrix form including a liquid crystal layer positioned between a thin film transistor substrate (hereinafter abbreviated as TFT substrate) and a color filter substrate. Data lines DL, gate lines GL, TFTs, storage capacitors, and the like are formed on the TFT substrate, and black matrices, color filters, and the like are formed on the color filter substrate. The subpixels SP may include red, green, and blue, which are defined as one pixel. On the other hand, one subpixel SP is defined by the intersecting data line D1 and the gate line G1. One subpixel SP includes a TFT driven by a gate signal supplied through a gate line G1, a storage capacitor Cst for storing a data signal supplied through a data line D1 as a data voltage, And a liquid crystal cell Clc driven by the data voltage stored in the data line Cst. The liquid crystal cell Clc is driven by the data voltage supplied to the pixel electrode 1 and the common voltage Vcom supplied to the common electrode 2. [ The common electrode 2 is formed on the TFT substrate together with the pixel electrode 1 in a horizontal electric field driving method such as an IPS (In Plane Switching) mode or an FFS (Fringe Field Switching) mode. The common electrode 2 receives the common voltage Vcom from the common voltage line. A polarizing plate is attached to the TFT substrate of the liquid crystal panel (PNL) and the color filter substrate, and an alignment film for setting a pre-tilt angle of the liquid crystal is formed. The liquid crystal panel PNL displays an image using light provided from a backlight unit BLU located below. The backlight unit BLU includes a direct type in which a light source is disposed below a liquid crystal panel PNL, an edge type in which a light source is disposed on one side of the liquid crystal panel PNL, And a dual type disposed on both sides of the PNL.

Hereinafter, a liquid crystal display according to an embodiment of the present invention will be described in more detail.

2 is a schematic block diagram of a FRC unit included in a timing control unit of a liquid crystal display according to an exemplary embodiment of the present invention.

As shown in FIG. 2, the FRC unit included in the timing control unit (TCN) includes a data extension unit 110 and an FRC control unit 140. The FRC control unit 140 includes a pattern matching unit 120, a counter unit 130, and a delay unit 145.

The data expander 110 expands the input video signal RiGiBi by at least one bit to generate an extended video signal ReGeBe. The data extension unit 110 generates a 11-bit extended video signal ReGeBe using a look-up table divided by RGB when a 10-bit video signal RiGiBi is inputted from the outside .

The counter 130 counts the number of pixels, the number of horizontal lines, and the number of frames based on the extended video signal. The counter section 130 includes a frame count section 131 for counting the number of frames, a pixel counter section 133 for counting the number of pixels, and a horizontal line counter section 135 for counting the number of horizontal lines.

The pattern matching unit 120 uses the number of pixels input from the pixel counter unit 133 and the number of horizontal lines input from the horizontal line counter unit 135 to generate a pattern with a FRC unit pattern initially set in a spatial area Performs matching and selects one of at least four FRC patterns according to the result. The pattern matching unit 120 includes a gradation level determination unit (or FRC pattern positioning unit) 121, an overflow determination unit 123, and an addition unit 125. The gradation level determination unit 121 determines the gradation level according to the lower 3 bits Re [2: 0], Ge [2: 0], and Be [2: 0] in the extended video signal ReGeBe do. The overflow determination unit 123 generates a signal for an overflow of the extended video signal ReGeBe. When the pattern is matched by the gradation level determination unit 121, the addition unit 125 determines whether or not the upper 8 bits + 1 are performed through an overflow check on the extended video signal ReGeBe. When the pattern is mismatched Bypass the upper 8 bits. The pattern matching unit 120 may select one of at least four FRC patterns to output the modified FRC unit pattern, and perform pattern matching using the changed FRC unit pattern at the subsequent pattern matching. The pattern matching unit 120 determines the pattern arrangement in the spatial region according to the remainder value obtained by dividing the number of pixels and the number of horizontal lines by 8, wherein the remaining value = 0 of the number of pixels divided by 8 and the number of horizontal lines 8, it is checked whether the extended video signal ReGeBe corresponds to the end of a specific frame. If the extended video signal ReGeBe is not the last video signal of the specific frame, it is determined whether the upper 8 bits + 1 are to be performed through an overflow check of the video signal. If the pattern is mismatched, Can be repeatedly performed. The pattern matching unit 120 determines the pattern arrangement in the spatial region according to the remainder value obtained by dividing the number of pixels and the number of horizontal lines by 8, wherein the remaining value = 0 of the number of pixels divided by 8 and the number of horizontal lines 8, it is used as an index for selecting one of at least four FRC patterns by increasing the pattern array index by 1 and using the residual value obtained by dividing the pattern array index by 4. The pattern matching unit 120 may select a path to perform pattern matching according to the remainder value obtained by dividing the number of frames by 4 and perform the same pattern matching at a period of 4 frames.

The delay unit 145 delays a system signal such as a vertical synchronizing signal Vsync, a horizontal synchronizing signal Hsync and a data enable signal DE by at least two clocks to output the video signal RrGrBr ).

The FRC unit included in the timing control unit TCN having the above-described configuration can expand the bits of the input video signal RiGiBi and arrange the FRC unit patterns so as to be non-overlapping through the above calculation process.

Hereinafter, the pattern matching method by the FRC unit will be described in more detail with reference to FIG.

3 is a flowchart for explaining pattern matching by the FRC unit.

First, 10-bit video signals (Ri, Gi, Bi) are inputted for each RGB (S101)

Next, the input video signals (Re, Ge, and Bi) of 10 bits are converted into 11-bit video signals Re, Ge, and Be using mapping functions Mapping (R), Mapping ) For each RGB (S103)

Next, the number of pixels L, the number of horizontal lines M, and the number of frames N are generated based on the extended video signals Re, Ge, and Be (S105). Here, High definition) Since the TV uses a resolution of 1920 x 1080, the number of horizontal lines M increases step by step every 1920, and the number of frames N increases every 1920 x 1080. Here, the pattern array index (K, K1) is used as an index for finding at least four FRC unit patterns. However, since the initial values corresponding to the number of pixels (L), the number of horizontal lines (M), the number of frames (N) and the pattern array index (K, K1) K1 = 1, L = 0, M = 0, N = 0.

Next, the gradation level is determined according to the lower 3 bits (Re [2: 0], Ge [2: 0], Be [2: 0]) in the extended video signals Re, Ge,

Next, a path to perform pattern matching is selected according to the remainder value (N1 = N% 4) obtained by dividing the number of frames (N) by 4, which performs the same pattern matching in at least four frame periods (S109) , The flow when the remainder value (N1) obtained by dividing the number of frames (N) by 4 is 0, 2, or 3 instead of 1 differs only from the FRC unit pattern in which pattern matching is first started and the remaining processes are the same as in the case of 1 Therefore, a description thereof will be omitted.

Next, a pattern matching {(L, M) = X ^K1 / 8} with the FRC unit pattern initially set in the spatial domain is performed using the number of pixels L and the number of horizontal lines M If the pattern is matched (Yes), the overflow check of the extended video signals Re, Ge, and Be is performed (S115) to determine whether or not the " upper 8 bits + 1 & If the patterns are mismatched (No), the " upper 8 bits " is bypassed and the execution of the " upper 8 bits + 1 " is skipped (S116) and the next step is performed.

Next, the pattern arrangement is determined in the spatial domain according to the residual value (L1 = L% 8, M1 = M% 8) obtained by dividing the number of pixels (L) by the number of horizontal lines (M) by 8. (S119) It is determined whether the remainder value L1 obtained by dividing the number of pixels L by 8 is 0 and the remainder value M1 obtained by dividing the number M of horizontal lines by 8 is 0. (S121) Based on the number of pixels (L) and the number of horizontal lines (M), if the remaining value (M1) obtained by dividing the remaining value (L1) divided by 8 by the number (M) If the extended video signal Re, Ge, Be is not the last data of the specific frame (No), it is checked whether or not the extended video signal Re, Ge, Be corresponds to the end of the specific frame (S123) S113 " If this is the case (Yes), the operation for one frame is ended. Alternatively, if the residual value L1 obtained by dividing the number of pixels L by 8 and the residual value M1 obtained by dividing the number M of horizontal lines by 8 is 0 (Yes), the pattern array index K is set to 1 (K1 = K% 4) by dividing K by 4 (S128). Then, the remaining value (K1 = K% 4) The FRC unit pattern is used as an index for selecting four FRC unit patterns (S130), and pattern matching is repeated using the changed FRC unit pattern (S113)

The FRC pattern structure according to the embodiment uses FRC unit patterns designed to be applied on a frame-by-frame basis in a spatial view, and each of the 8 × 8 FRC unit patterns is cyclically arranged so as not to overlap with previous frames.

Hereinafter, the FRC pattern matching according to the comparative example and the FRC pattern matching according to the present invention will be compared.

FIG. 4 is a view for explaining a comparison between the FRC pattern matching method according to the comparative example and the FRC pattern matching method according to the present invention, and FIGS. 5 to 8 illustrate the FRC pattern matching method according to the comparative example, And FIG.

In the FRC pattern of "2/8" according to the comparative example, as shown in FIG. 4A, in order to maximize the temporal and spatial optical illusions, pixels corresponding to the upper 8 bits + 1 & The FRC pattern according to the comparative example is formed by arranging the FRC pattern according to the pre-designed FRC pattern repeatedly so that the vertical line noise, the horizontal line noise, or the diagonal line Noise is induced.

5 is an example of vertical line noise caused by the FRC pattern according to the comparative example.

The FRC pattern according to the comparative example of FIG. 5 is a case in which the data polarity in the dithering pattern is dot inversion. In the FRC pattern according to the comparative example, the pixels corresponding to "upper 8 bits + 1" are arranged at intervals of two lines in the vertical direction of the "1/8" FRC pattern and correspond to " upper 8 bits + 1 " The positions of the pixels are shifted by two lines. Accordingly, in the FRC pattern according to the comparative example, the luminance increase is varied in units of two frames, resulting in flicker of a thin vertical line pattern, that is, vertical line noise.

6 is an example of the diagonal noise caused by the FRC pattern according to the comparative example.

The FRC pattern according to the comparative example of Fig. 6 is continuously arranged with the " upper 8 bits + 1 " pixels having the same polarity formed in the diagonal direction, thereby causing a local luminance variation. As a result, the position of the diagonal line changes as the number of frames increases, resulting in a diagonal noise that appears as a thin diagonal pattern on the display screen.

Alternatively, the embodiment is composed such that four sub-dither pattern of ^{"X 1/8" ~ "} X 4/8" are included as in the "X / 8" according to the example FRC pattern of Figure 4 (b), Since this corresponds to a 3-bit FRC unit pattern, X has a value between 1 and 7. In the pattern arrangement, four sub dithering patterns are arranged in the vertical direction in the vertical direction in the spatial domain, and at least four sub dithering patterns are simultaneously arranged spatially and temporally with a constant period.

7 is an example of the horizontal line noise improved by the FRC pattern according to the embodiment.

The FRC pattern according to the embodiment is rearranged in the time and space regions in the [4n + 1] and [4n + 2] frames as shown in FIG. The FRC pattern according to the comparative example generated a horizontal line pattern at two line intervals. However, since the FRC pattern according to the embodiment blocks the connection path between the FRC unit patterns as shown in "Link blocking ", the serrated pattern is retained only in the FRC internal pattern and is not propagated to the adjacent FRC unit pattern do. Therefore, the FRC pattern according to the embodiment can prevent vertical line noise as well as horizontal line noise.

8 is an example of diagonal noise improved by the FRC pattern according to the embodiment.

The FRC pattern according to the embodiment is different from the FRC pattern method according to the comparative example in that the pixels corresponding to the " upper 8 bits " between the " upper 8 bits + 1 " pixels having the same polarity formed in the diagonal direction Periodically. As a result, diagonal connections between FRC internal pattern arrays and FRC unit patterns are no longer extended by a number of circles marked with circles. Therefore, in the FRC pattern according to the embodiment, visual artifacts can be analytically removed through a new unit pattern arrangement method.

The present invention described above can be applied to various FRC patterns of 16x32, 24x32, 32x32, 16x40, and 16x44 sizes. However, the size of the dithering pattern can be set to 32 x 32 in order to effectively reduce the visual artifact while minimizing the resources according to the hardware implementation. The total size of the new pattern array is repeated with a constant period, and the size of the array of unit patterns that determine one period can be variously configured.

As described above, the present invention provides a liquid crystal display device and a method of driving the same that can improve visual artifacts such as a thin diagonal pattern, a thin horizontal line pattern, and a thin vertical line pattern generated at low gradations.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, It will be understood that the invention may be practiced. It is therefore to be understood that the embodiments described above are to be considered in all respects only as illustrative and not restrictive. In addition, the scope of the present invention is indicated by the following claims rather than the detailed description. Also, all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included within the scope of the present invention.

TCN: Timing control part DDRV: Data driving part
SDRV: gate driver PNL: liquid crystal panel
BLU: Backlight Unit
110: Data Extension Unit 140: FRC Control Unit
120: pattern matching unit 130:
145:

Claims (10)

A liquid crystal panel;
A driving unit for supplying a data signal and a gate signal to the liquid crystal panel; And
(FRC) unit pattern including at least four sub dithering patterns according to a video signal input from the outside, the FRC unit pattern being divided into a previous frame, And an FRC unit for cyclically shifting the at least four sub-dithering patterns in the up-down and up-down directions at regular intervals,
The FRC unit,
A data expander for expanding the input video signal by at least one bit to generate an expanded video signal,
A counter unit for counting the number of pixels, the number of horizontal lines, and the number of frames based on the extended video signal,
And a pattern matching unit for performing pattern matching with the initially set FRC unit pattern in the spatial domain using the number of pixels and the number of the horizontal lines and selecting one of the at least four FRC patterns according to a result of the pattern matching, ,
Wherein the pattern matching unit comprises:
If the pattern is matched, it is determined whether an upper 8 bits + 1 is performed through an overflow check of the extended video signal. If the patterns are mismatched, upper 8 bits are bypassed,
Wherein the pattern matching unit comprises:
Determining a pattern arrangement in a spatial region according to a residual value obtained by dividing the number of pixels and the number of horizontal lines by 8,
When the remainder value obtained by dividing the number of pixels by 8 is 0 and the remainder value obtained by dividing the number of the horizontal lines by 8 is 0, the pattern array index is incremented by 1 and the remaining value obtained by dividing the pattern array index by 4 is used Wherein the FRC pattern is used as an index for selecting one of the at least four FRC patterns. delete The method according to claim 1,
Wherein the pattern matching unit comprises:
And selecting one of the at least four FRC patterns to output a modified FRC unit pattern, and performing pattern matching using the changed FRC unit pattern in the subsequent pattern matching. delete The method according to claim 1,
Wherein the pattern matching unit comprises:
Determining a pattern arrangement in a spatial region according to a residual value obtained by dividing the number of pixels and the number of horizontal lines by 8,
If the remainder value obtained by dividing the number of pixels by 8 is 0 and the remainder value for the horizontal line is not 0, it is checked whether the extended video signal corresponds to the end of a specific frame, Determining whether the upper 8 bits + 1 are to be performed through an overflow check of the video signal if the last video signal is not included, and bypassing the upper 8 bits if the pattern is mismatched. delete The method according to claim 1,
Wherein the pattern matching unit comprises:
And determines the gradation level according to the lower 3 bits in the extended video signal. 8. The method of claim 7,
Wherein the pattern matching unit comprises:
A path to be pattern-matched is selected according to a remainder value obtained by dividing the number of frames by 4, and the same pattern matching is performed in a cycle of 4 frames. Expanding an input video signal by at least one bit to generate an expanded video signal;
Generating a number of pixels, a number of horizontal lines, and a number of frames based on the extended video signal;
Determining a gradation level according to lower 3 bits of the extended video signal;
Selecting a path to perform pattern matching according to a remainder value obtained by dividing the number of frames by 4;
Performing pattern matching with an FRC unit pattern initially set in a spatial region using the number of pixels and the number of horizontal lines; And
Determining a pattern array such that one of at least four FRC patterns is selected in the spatial domain according to a residual value obtained by dividing the number of pixels by the number of horizontal lines by eight,
Wherein the step of determining the pattern arrangement in the spatial area comprises:
If the remainder value obtained by dividing the number of pixels by 8 is 0 and the remainder obtained by dividing the number of horizontal lines by 8 is not 0, it is checked whether the extended video signal corresponds to the end of a specific frame, Determining whether an upper 8 bits + 1 is to be performed through an overflow check of the video signal if the last video signal is not the last video signal of the specific frame, and bypassing higher 8 bits when the pattern is mismatched;
When the remainder value obtained by dividing the number of pixels by 8 is 0 and the remainder value obtained by dividing the number of the horizontal lines by 8 is 0, the pattern array index is incremented by 1 and the remaining value obtained by dividing the pattern array index by 4 is used Wherein the FRC pattern is used as an index for selecting one of the at least four FRC patterns. delete

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