KR101800515B1

KR101800515B1 - Method For Manufacturing Nanowire Sensor Chip Integrated With CMOS Circuit

Info

Publication number: KR101800515B1
Application number: KR1020150188462A
Authority: KR
Inventors: 정석원; 최연식; 조영창; 손재기; 전기만; 성우경; 이국녕; 이민호; 홍혁기
Original assignee: 전자부품연구원
Priority date: 2015-12-29
Filing date: 2015-12-29
Publication date: 2017-11-24
Also published as: KR20170078186A

Abstract

An embodiment of the present invention integrates a manufacturing process of a nanowire sensor and a manufacturing process of a CMOS circuit to simultaneously integrate a nanowire sensor and a CMOS circuit on a single substrate to thereby simplify the manufacturing process and improve the noise performance And a method of manufacturing a nanowire sensor chip integrated with a CMOS circuit having improved reliability.

Description

TECHNICAL FIELD [0001] The present invention relates to a method of manufacturing a nanowire sensor chip integrated with a CMOS circuit,

The present invention relates to a method of manufacturing a nanowire sensor chip in which a CMOS circuit is integrated, and more particularly, to a method of manufacturing a nanowire sensor chip in which a CMOS circuit is integrated with a nano- To a method of manufacturing a wire sensor chip.

Nanoscale materials have unique electrical, optical, and mechanical properties. Because of these properties, nano-sized materials have recently emerged as important materials and are being studied in various fields.

In particular, silicon nanowires show potential as a new photonic device in the future due to properties such as quantum effects. Such a silicon nanowire is applied to various fields such as a single electron transistor, various chemical sensors, and a biosensor.

However, a device in which a conventional silicon nanowire is formed can be fabricated in a unique manner, such as manufacturing a silicon nanowire by VLS (vapor liquid solid) growth method and arranging the manufactured silicon nanowire on a dielectric substrate to form an electrode . Such a manufacturing method of a device in which a silicon nanowire is formed is different from a manufacturing method of a device in which a complementary metal-oxide semiconductor (CMOS) circuit is formed, and it is impossible to simultaneously form a nanowire sensor and a CMOS circuit on one substrate .

Accordingly, a device formed with a silicon nanowire and a device formed with a CMOS circuit were separately fabricated, and two devices were connected by wire bonding to fabricate a device having a nanowire and a CMOS circuit. However, the device fabricated in this way is difficult to miniaturize, and performance is deteriorated due to an increase in noise due to wire bonding. In addition, due to the increase in the packaging cost due to the wire bonding, the device manufactured in the above-described manner is not mass-producible.

Recently, a sensor chip has been developed as a smart sensor that simultaneously integrates a plurality of sensors on a single substrate. In such a smart sensor, a plurality of sensors and a signal processing circuit are simultaneously formed. In order to realize such a smart sensor, the manufacturing process of the sensor using the silicon nanowire needs to be integrated with the signal processing circuit manufacturing process.

KR 2011-0015603 A

A method of fabricating a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention includes: A preparation step of preparing an insulating base substrate including a nanowire formation region and a CMOS formation region; A nanowire forming step of forming at least two grooves on the base substrate on the nanowire forming region, wet oxidation of the base substrate between the grooves, and nanowires formed on the base substrate between the grooves; An oxide layer forming step of forming an oxide layer on the base substrate other than the nanowire forming area and the CMOS forming area; Forming an N-type well in one region of the CMOS formation region and forming a P-type well in an N-MOS region which is another region of the CMOS formation region apart from the P- Forming step; A gate forming step of forming polysilicon on the base substrate and patterning the polysilicon to form a first gate and a second gate in the P-MOS region and the N-MOS region, respectively; Forming a first source and a first drain on a side of the first gate by doping a P-type dopant to form a P-MOS on the P-MOS region so that N-MOS is formed on the N- Doped with an N-type dopant to form a second source and a second drain on the side of the second gate, doping a first dopant to a first conductive region on one side of the nanowire in the longitudinal direction, A dopant doping step of doping a second dopant having a conductivity different from that of the first dopant to a second conductive region on the other longitudinal side of the successive nanowires; And a dielectric layer on which the contact hole is formed on the base substrate; patterning a metal interconnection layer filled in the contact hole while being stacked on the dielectric layer to electrically connect the nanowire, P-MOS and N- And an electrical connection step of forming a connection terminal.

According to an embodiment of the present invention, there is provided a method of manufacturing a nanowire sensor chip integrated with a CMOS circuit, the nanowire forming step including sequentially stacking an oxide film and a nitride film on the base substrate; Patterning the oxide film and the nitride film on the nanowire-forming region; Forming at least two grooves by etching the patterned base substrate to a predetermined depth; Anisotropically etching the base substrate between the grooves so as to form a base substrate between the grooves so that a width gradually increases from a center width in the thickness direction toward an upper end and a lower end; Forming a nanowire on the base substrate by wet oxidation of the base substrate to break the upper and lower ends of the anisotropically etched base substrate; And removing the oxide film and the nitride film on the base substrate.

According to an embodiment of the present invention, there is provided a method of manufacturing a nanowire sensor chip integrated with a CMOS circuit, wherein the thickness of the nanowire can be adjusted according to a time of wet oxidation of the base substrate.

According to another aspect of the present invention, there is provided a method of fabricating a nanowire sensor chip integrated with a CMOS circuit, the method comprising: sequentially stacking an oxide layer and a nitride layer on the base layer; Exposing the base substrate region other than the nanowire forming region and the CMOS forming region by patterning the oxide film and the nitride film; Forming an oxide layer on the exposed base substrate region by a wet oxidation process; And removing the oxide film and the nitride film on the base substrate.

According to another aspect of the present invention, there is provided a method of manufacturing a nanowire sensor chip integrated with a CMOS circuit, the method comprising: forming an oxide film on a base substrate on the nanowire forming region and a CMOS forming region; Doping an N-type dopant to a P-MOS region, which is one region of the CMOS formation region, to form an N-type well; Forming a P-type well by doping a P-type dopant to an N-MOS region, which is another region of the CMOS formation region; Heat treating the P-MOS region and the N-MOS region; Doping the N-MOS region with a first type dopant; And doping the P-MOS region with a second type dopant.

The method of manufacturing a nanowire sensor chip in which a CMOS circuit is integrated according to an embodiment of the present invention is characterized in that the first type dopant may be of an N type conductivity type different from the P type dopant, a dopant of the second type may be of a conductivity type of dopant different from the P-type of the N type.

According to an embodiment of the present invention, there is provided a method of fabricating a nanowire sensor chip integrated with a CMOS circuit, the method comprising: stacking polysilicon on the base substrate; Removing the polysilicon in the nanowire-forming region by wet etching; It can include; and forming a first gate and second gate well and patterning the polysilicon in the top portion of the polysilicon while protecting the removal of the nanowires forming region in the photosensitive film coming from a well of the N-type and P-type have.

A method for fabricating a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention, the doping step comprising doping a P-type low concentration dopant on the P-mos region, Forming a lightly doped region doped with an N-type lightly doped dopant, doping a first lightly doped dopant to the first electrically conductive region, and doping a second lightly doped dopant having a conductivity different from the first lightly doped dopant to the second electrically conductive region; Forming an oxide film on the base substrate, patterning the oxide film to form a first spacer on both sides of the first gate on the P-MOS region, and forming a second spacer on the second gate side on the N- Forming a spacer; And a first high concentration dopant is doped on the P-MOS region and doped with an N-type high concentration dopant on the N-MOS region, and a first high concentration dopant is doped on one side of the first conductive region, And a high-concentration region forming step of doping a second high-concentration dopant having conductivity different from that of the first high-concentration dopant to the other side of the second conductive region that is not in contact with the first conductive region.

A method of fabricating a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention, wherein the first lightly doped dopant and the first highly doped dopant have a P-type conductivity type and the second lightly doped dopant and the second The high-concentration dopant may have an N-type conductivity type.

A method of manufacturing a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention is characterized in that the P conductive semiconductor region and the P conductive semiconductor region are sequentially formed in the longitudinal direction of the nanowire .

A method of manufacturing a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention is characterized in that the second conductive region includes an N-type semiconductor region and an N + -type semiconductor region successively from the P- Semiconductor regions may be sequentially formed in the longitudinal direction of the nanowires.

According to an embodiment of the present invention, there is provided a method of fabricating a nanowire sensor chip integrated with a CMOS circuit, the method comprising: doping a P-type low concentration dopant to the P-MOS region; Doping the N-MOS region with an N-type lightly doped dopant; Doping the first and second conductive regions of the nanowire with a first lightly doped dopant; And doping the second conductive region of the nanowire with a second lightly doped dopant having a concentration higher than that of the first lightly doped dopant.

In the method for fabricating a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention, the high-concentration region forming step may include doping a P-type high-concentration dopant into the P-MOSFET region, Doping a first high-concentration dopant having the same conductivity as the P-type high-concentration dopant to one side of the first conductive region; Doping an N-type high-concentration dopant to the N-MOS region and doping a second high-concentration dopant having the same conductivity as the N-type high-concentration dopant on the other side of the second conductive region that is not in contact with the first conductive region; And heat treating the first conductive region, the second conductive region, the P-MOS region and the N-MOS region.

The method of manufacturing a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention may further include forming a silicide before the electrical connection step after the dopant doping step, Patterning an oxide film on one side of the second conductive region extending from the other side of the first conductive region and the other side of the first conductive region in contact with the conductive region; Forming a silicide metal layer on the base substrate; A first gate of a P-MOS transistor, a first source, a first drain, and a first drain of the P-MOS transistor and a first drain of the P-MOS transistor, Forming a first silicide in a second gate, a second source, and a second drain of the first semiconductor layer; And forming a second silicide with the first silicide by performing a second heat treatment on the base substrate, wherein the contact hole of the electrical connection step is formed to expose the second silicide, The nanowire, P-MOS and N-MOS may be electrically connected by the contact between the silicide and the metal wiring layer.

According to an embodiment of the present invention, there is provided a method of fabricating a nanowire sensor chip integrated with a CMOS circuit, wherein the silicide metal layer may be formed of any one of Ti, Co, and Ni.

The features and advantages of the present invention will become more apparent from the following detailed description based on the accompanying drawings.

Prior to this, terms and words used in the present specification and claims should not be construed in a conventional and dictionary sense, and the inventor may appropriately define the concept of a term in order to best describe its invention The present invention should be construed in accordance with the spirit and scope of the present invention.

According to an embodiment of the present invention, the manufactured sensor chip includes a nanowire sensor chip and a CMOS circuit integrated on one substrate at the same time, and a wire bonding process required when a nanowire sensor chip and a CMOS circuit chip are separately manufactured is omitted So that the process can be simplified.

According to an embodiment of the present invention, the nanowire sensor and the CMOS circuit are simultaneously integrated on a single substrate to solve the problem of defective connection, thereby improving the noise performance of the manufactured sensor chip, Is improved.

Also, according to an embodiment of the present invention, a nanowire sensor and a CMOS circuit can be formed on a single substrate, so that a miniaturized sensor chip can be manufactured.

According to an embodiment of the present invention, a nanowire sensor and a CMOS circuit can be implemented at the same time, and a plurality of nanowire sensors and a signal processing circuit for each sensor can be implemented at the same time, Is possible.

In addition, according to an embodiment of the present invention, the silicon nanowire sensor can be used as an optical device, the CMOS circuit can be used as a signal processing circuit, and an image sensor using the silicon nanowire as an optical device .

1A is a perspective view showing a base substrate preparation step, and FIG. 1B is a sectional view taken along the line A-A 'in FIG. 1A.
2A is a perspective view illustrating a step of laminating an oxide film and a nitride film on the base substrate of FIG. 1A, and FIG. 2B is a cross-sectional view taken along line A-A 'of FIG. 2A.
3A is a perspective view showing a step of patterning the oxide film and the nitride film of FIG. 2A so that the base substrate is exposed, and FIG. 3B is a cross-sectional view taken along line A-A 'of FIG. 3A.
FIG. 4A is a perspective view illustrating a step of forming a groove in the base substrate along the patterned oxide film and the nitride film of FIG. 3A, and FIG. 4B is a cross-sectional view taken along line A-A 'of FIG. 4A.
5A is a perspective view illustrating a step of anisotropically etching the base substrate between the grooves in FIG. 4A, FIG. 5B is a cross-sectional view taken along line A-A 'in FIG. 5A, and FIG. 5C is a cross- Fig.
FIG. 6A is a cross-sectional view illustrating a step of forming a nanowire through the wet oxidation process in FIG. 5B, and FIG. 6B is a cross-sectional view taken along line B-B 'of FIG. 6A.
FIG. 7A is a perspective view illustrating a step of removing an oxide film and a nitride film in the base substrate of FIG. 6A, and FIG. 7B is a cross-sectional view taken along line A-A 'of FIG. 7A.
FIG. 8A is a perspective view illustrating a step of sequentially laminating an oxide film and a nitride film on the base substrate of FIG. 7A, and FIG. 8B is a cross-sectional view taken along line A-A 'of FIG. 8A.
FIG. 9A is a perspective view showing a step of patterning an oxide film and a nitride film of FIG. 8A to expose other regions, and FIG. 9B is a cross-sectional view taken along line A-A 'of FIG. 9A.
10A is a perspective view showing a step of forming an oxide layer by a wet oxidation process in the exposed other region of FIG. 9A, and FIG. 10B is a cross-sectional view taken along line A-A 'of FIG. 10A.
11A is a perspective view illustrating a step of removing the oxide film and the nitride film of FIG. 10A, and FIG. 11B is a cross-sectional view taken along line A-A 'of FIG. 11A.
12 is a cross-sectional view showing a step of forming an oxide film on the base substrate of FIG. 11B.
13A is a perspective view illustrating a step of doping an N-type dopant into the P-MOS region of FIG. 12, and FIG. 13B is a cross-sectional view taken along line A-A 'of FIG. 13A.
14A is a perspective view illustrating a step of doping a P-type dopant into the N-MOS region in FIG. 13A, and FIG. 14B is a cross-sectional view taken along the line A-A 'in FIG. 14A.
FIG. 15A is a perspective view showing a step of heat-treating the P-MOS region and the N-MOS region in FIG. 14A, and FIG. 15B is a sectional view taken along the line A-A 'in FIG. 15A.
FIG. 16A is a perspective view showing a step of doping the first-type dopant into the N-MOS region in FIG. 15A, and FIG. 16B is a cross-sectional view taken along the line A-A 'in FIG. 16A.
17A is a perspective view showing a step of doping the P-MOS region of FIG. 16A with a dopant of the second type, and FIG. 17B is a cross-sectional view taken along line A-A 'of FIG. 17A.
18A is a perspective view showing a step of stacking a gate oxide film and polysilicon on a base substrate after the process of FIG. 17A, and FIG. 18B is a cross-sectional view taken along line A-A 'of FIG. 18A.
FIG. 19A is a perspective view showing a step of exposing a portion where the polysilicon is laminated in the nanowire forming region of FIG. 18A, and FIG. 19B is a sectional view taken along line A-A 'of FIG. 19A.
20A is a perspective view showing a step of removing polysilicon in the exposed nanowire forming region of FIG. 19A, and FIG. 20B is a cross-sectional view taken along line A-A 'of FIG. 20A.
21A is a perspective view showing a step of patterning a photoresist film in a nanowire forming region and a CMOS forming region in FIG. 20A, and FIG. 21B is a cross-sectional view taken along line A-A 'in FIG. 21A.
22A is a perspective view showing a step of etching polysilicon in accordance with the patterning of FIG. 21A, and FIG. 22B is a cross-sectional view taken along line A-A 'of FIG. 22A.
23A is a perspective view showing a step of doping a P-type low concentration dopant into the P-MOS region in FIG. 22A, and FIG. 23B is a sectional view taken along line A-A 'in FIG. 23A.
24A is a perspective view showing a step of doping an N-type low concentration dopant into the N-MOS region in FIG. 23A, and FIG. 24B is a sectional view taken along the line A-A 'in FIG. 24A.
25A is a perspective view showing a step of doping the first and second conductive regions of the nanowire of FIG. 24A with a first lightly doped dopant, and FIG. 25B is a cross-sectional view taken along line A-A 'of FIG. 25A.
26A is a perspective view illustrating a step of doping a second lightly doped dopant into a second conductive region of the nanowire of FIG. 25A, and FIG. 26B is a cross-sectional view taken along line A-A 'of FIG. 26A.
FIG. 27A is a perspective view showing a step of laminating an oxide film on the base substrate of FIG. 26A, and FIG. 27B is a sectional view taken along line A-A 'of FIG. 27A.
FIG. 28A is a perspective view showing a step of dry etching the oxide film of FIG. 27A to form a spacer, and FIG. 28B is a sectional view taken along the line A-A 'in FIG. 28A.
29A is a perspective view showing a step of doping a first high-concentration dopant and a P-type high-concentration dopant to a part of the first conductive region and the P-MOS region of FIG. 28A, FIG. 29B is a cross- Sectional view.
30A is a perspective view showing a step of doping a portion of the second conductive region and the N-MOS region of FIG. 29A with the second high-concentration dopant and the N-type high-concentration dopant, FIG. 30B is a cross-sectional view taken along the line A-A ' Sectional view.
31 is a cross-sectional view showing the step of heat-treating the first and second conductive regions, the P-MOS region and the N-MOS region in FIG. 30B.
FIG. 32A is a perspective view showing a step of laminating an oxide film on the base substrate of FIG. 31, and FIG. 32B is a sectional view taken along line A-A 'of FIG. 32A.
FIG. 33A is a perspective view showing a step of patterning a photoresist film on a part of the nanowire forming region of FIG. 32A, and FIG. 33B is a cross-sectional view taken along line A-A 'of FIG. 33A.
FIG. 34A is a perspective view showing a step of etching an oxide film according to the patterned photoresist film of FIG. 33A, and FIG. 34B is a cross-sectional view taken along line A-A 'of FIG. 34A.
35 is a cross-sectional view showing a step of laminating a silicide metal layer on the base substrate of Fig. 34B.
FIG. 36 is a cross-sectional view illustrating a step of removing a silicide metal layer which is not in contact with silicon after the first heat treatment of the base substrate of FIG.
FIG. 37 is a cross-sectional view showing the step of secondary heat treatment of the base substrate of FIG. 36;
FIG. 38A is a perspective view showing a step of forming a dielectric layer on the base substrate of FIG. 37, and FIG. 38B is a sectional view taken along line A-A 'of FIG. 38A.
FIG. 39A is a perspective view showing a step of laminating a metal wiring layer on the base substrate of FIG. 38A, and FIG. 39B is a sectional view taken along line A-A 'of FIG. 39A.
40A is a perspective view showing a step of patterning the metal wiring layer in FIG. 39A, and FIG. 40B is a cross-sectional view taken along the line A-A 'in FIG. 40A.

BRIEF DESCRIPTION OF THE DRAWINGS The objectives, specific advantages and novel features of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which: FIG.

It should be noted that the reference numerals are added to the components of the drawings in the present specification with the same numerals as possible, even if they are displayed on different drawings, for the same components. In addition, some cross-sectional views in the drawing are not a straight line but, for example, along the line passing through the nanowire formation region, the P-moss region, and the N-Moss region, as indicated by line A-A ' It should be noted that it was revealed.

Also, the terms " one side, " " first, "" first," " second, "and the like are used to distinguish one element from another, no. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In the following description of the present invention, a detailed description of known arts which may unnecessarily obscure the gist of the present invention will be omitted.

A method of fabricating a nanowire sensor chip integrated with a CMOS circuit according to an embodiment of the present invention includes the steps of preparing an insulating base substrate including a nanowire forming region and a CMOS forming region; A nanowire forming step of forming at least two grooves on the base substrate on the nanowire forming region, wet oxidation of the base substrate between the grooves, and nanowires formed on the base substrate between the grooves; An oxide layer forming step of forming an oxide layer on the base substrate other than the nanowire forming area and the CMOS forming area; Forming an N-type well in one region of the CMOS formation region and forming a P-type well in an N-MOS region which is another region of the CMOS formation region apart from the P- Forming step; A gate forming step of forming polysilicon on the base substrate and patterning the polysilicon to form a first gate and a second gate in the P-MOS region and the N-MOS region, respectively; Forming a first source and a first drain on a side of the first gate by doping a P-type dopant to form a P-MOS on the P-MOS region so that N-MOS is formed on the N- Doped with an N-type dopant to form a second source and a second drain on the side of the second gate, doping a first dopant to a first conductive region on one side of the nanowire in the longitudinal direction, A dopant doping step of doping a second dopant having a conductivity different from that of the first dopant to a second conductive region on the other longitudinal side of the successive nanowires; And a dielectric layer on which the contact hole is formed on the base substrate. The metal wiring layer deposited on the dielectric layer and filled in the contact hole is patterned to electrically connect the nanowire, the P-MOS and the N- And an electrically connecting step of forming a connection terminal.

Accordingly, since the nanowire sensor and the CMOS circuit are simultaneously integrated on a single substrate, the process of wire bonding is omitted, and the process is simplified. In addition, since there is no need to separately connect the nanowire sensor and the CMOS circuit, the problem of the connection failure occurring in the wire bonding is solved, and the noise of the sensor chip is reduced and the reliability is improved. In addition, since a nanowire sensor and a CMOS circuit are implemented on a single substrate, a miniaturized sensor chip can be manufactured, and a nanowire sensor and a CMOS circuit can be simultaneously implemented. Thus, a smart sensor using a nanowire sensor can be implemented Do. In addition, the silicon nanowire sensor can be used as an optical device, and the CMOS circuit can be used as a signal processing circuit therefor. Thus, an image sensor using silicon nanowire as an optical device can be produced.

Hereinafter, each step of an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1A and 1B. FIG. 1A is a perspective view illustrating a step of preparing a base substrate 10, and FIG. 1B is a cross-sectional view taken along line A-A 'of FIG. 1A.

In preparation, an insulating base substrate 10 is prepared. The base substrate 10 is made of silicon (Si) and has a crystal orientation with a Miller Index of (100). The base substrate 10 includes a nanowire forming region 20 and a CMOS forming region 30. A nanowire sensor is formed in the nanowire forming region 20 by processes to be described later, A CMOS circuit is formed on the substrate 30. The CMOS forming region 30 includes one region which is the P-mos region 31 where the next P-MOS is to be formed and another region which is the N-MOS region 32 where the next N-MOS is to be formed. The P-morse region 31 and the N-MOS region 32 are spaced from each other. 1A, a single nanowire forming region 20 and a single CMOS forming region 30 are shown, but the number of the nanowire forming region 20 and the CMOS forming region 30 is not limited to this, And a plurality of units may be formed. The shapes of the nanowire forming region 20 and the CMOS forming region 30 may be variously changed to other shapes than the illustrated rectangular shapes. For convenience of explanation, the region of the base substrate 10 other than the nanowire forming region 20 and the CMOS forming region 30 may be referred to as an "other region 40" hereinafter.

The next step in the preparation step is to form at least two grooves G in the base substrate 10 on the nanowire forming region 20 and to form the base substrate 10 between the grooves G And the nanowires 21 are formed on the base substrate 10 between the grooves G by wet oxidation. Hereinafter, this will be described in detail with reference to Figs. 2A to 7B.

2A is a perspective view illustrating a step of laminating an oxide film O1 and a nitride film N1 on the base substrate 10 of FIG. 1A, and FIG. 2B is a cross-sectional view taken along line A-A 'of FIG. 2A.

First, the nanowire forming step may include sequentially stacking the oxide film 01 and the nitride film N1 on the base substrate 10 as shown in FIGS. 2A and 2B. The oxide films (SiO _2, O ₁ ) are first deposited on the base substrate 10 to a predetermined thickness through a dry oxidation process. Next, the nitride film (Si ₃ N ₄ , N ₁ ) is deposited on the oxide film 01 by low pressure chemical vapor deposition (LPCVD). The oxide film 01 can prevent the surface of the base substrate 10 from being damaged due to the deposition of the nitride film N1 and the nitride film N1 serves as a protective film for preventing the foreign substances from penetrating the base substrate 10 can do. However, the oxide film 01 and the nitride film N1 may not be stacked together, and only one nitride film N1 may be stacked.

3A is a perspective view showing a step of patterning the oxide film O1 and the nitride film N1 in FIG. 2A so that the base substrate 10 is exposed, and FIG. 3B is a cross-sectional view taken along the line A-A 'in FIG.

Next, the nanowire forming step may include patterning the oxide film O1 and the nitride film N1 on the nanowire forming region 20 after the lamination of the oxide film 01 and the nitride film N1. The patterning of the oxide film O1 and the nitride film N1 may be performed as follows. First, a photoresist P1 is coated on the base substrate 10, and a photolithography process is performed to form nanowires The photosensitive film P1 on the region 20 is patterned into a predetermined shape. The nitride film N1 of the portion where the photoresist film P1 is removed is exposed to the surface and the nitride film N1 and the oxide film O1 exposed to the surface are dry etched according to the patterning of the photoresist film P1, So that the oxide film O1 and the nitride film N1 on the nanowire forming region 20 can be patterned into a predetermined shape. At this time, the patterning shape serves as a mask of a subsequent process, and at least two grooves G are formed, and the groove G has a shape connecting the groove G and the groove G at both ends thereof . However, the shape of the patterning is not limited to this, and the shape of the patterning can be changed into various shapes in different shapes as long as at least two grooves G can be formed.

4A is a perspective view illustrating a step of forming a groove G in the base substrate 10 along the patterned oxide film O1 and the nitride film N1 of FIG. 3A, FIG. 4B is a cross- Fig.

4A and 4B, the nanowire forming step includes forming at least two grooves G on the base substrate 10 on the nanowire forming region 20. [ At this time, the groove G is formed on the base substrate 10 by using the patterned photoresist film P1, the oxide film 01 and the nitride film N1 as masks, At least two grooves G may be formed by etching. At this time, the number of the grooves G may be variously changed according to the number of the nanowires to be formed (21 of FIG. 6B), and may be formed parallel to each other to form the nanowires 21 having a constant size . After the groove G is formed in the base substrate 10, the photoresist film P1 for patterning the oxide film O1 and the nitride film N1 can be removed.

5A is a perspective view showing a step of anisotropically etching the base substrate 10 between the grooves G in FIG. 4A, FIG. 5B is a cross-sectional view taken along line A-A 'in FIG. 5A, B-B 'of Fig.

After forming at least two grooves G in the base substrate 10, the nanowire forming step may include anisotropically etching the base substrate 10 between the grooves G. This anisotropic etching can proceed as follows. First, the base substrate 10 is cleaned using SPM (Sulfuric Peroxide Mixture) solution, and the substrate cleaned for wet etching is immersed in BOE (Buffered Oxide Etch) solution for a predetermined time (for example, about 5 seconds) Remove the native oxide. Then, the base substrate 10 is wet-etched at about 80 캜 for about 15 seconds by using a KOH solution or a TMAH (TetraMethlymmonium Hydroxide) solution. When the wet etching is completed, the base substrate 10 between the grooves G is anisotropically etched due to the difference in the etching rate depending on the crystal direction of silicon. At this time, the base substrate 10 between the anisotropically etched grooves G is etched so as to be gradually wider from the central width in the thickness direction toward the upper and lower ends, and may be formed into an hourglass shape as shown in FIGS. 5B and 5C have. On the other hand, the shape after the etching of the base substrate 10 between the grooves G can be adjusted according to the wet time.

FIG. 6A is a cross-sectional view showing the step of forming the nanowires 21 through the wet oxidation process in FIG. 5B, and FIG. 6B is a cross-sectional view taken along the line B-B 'in FIG. 6A.

As shown in FIGS. 6A and 6B, the nanowire forming step includes wet oxidizing the base substrate 10, which may be performed after the base substrate 10 is anisotropically etched. Such a wet oxidation step may be performed by cleaning the base substrate 10 with an SPM solution and performing a wet oxide film formation process. When the wet oxide film formation process is performed on the base substrate 10 on which the grooves G are formed or anisotropically etched, all the silicon regions exposed on the surface are reacted, and the grooves G and the anisotropically etched portions of the base substrate 10 An oxide (SiO ₂ , 22) is formed. 6A and 6B, the oxide 22 is formed so as to penetrate through the central portion in the thickness direction of the base substrate 10 between the grooves G, and the upper and lower ends of the anisotropically etched base substrate 10 are cut off The nanowire 21 is formed on the upper portion of the groove (G) base substrate 10. On the other hand, the upper portion of the base substrate 10 is formed of nanowires 21. The nanowires 21 are made of silicon. Since the nanowires 21 are formed by the oxide 22 formed by the wet oxidation, the thickness of the nanowires 21 can be adjusted according to the wet oxidation time of the base substrate 10.

7A is a perspective view illustrating a step of removing the oxide film O1 and the nitride film N1 from the base substrate 10 of FIG. 6A, and FIG. 7B is a cross-sectional view taken along line A-A 'of FIG. 7A.

After the wet oxidation step of the base substrate 10, the nanowire forming step may include sequentially removing the nitride film and the oxide film (N1, O1 in FIGS. 6A and 6B) on the base substrate 10. First, the nitride film (N1) can be removed using a phosphoric acid (H3PO4) solution and the oxide film (O1) can be removed using a diluted hydrofluoric acid (HF) solution. Accordingly, the particles generated in the etching or oxidation step are removed, and the base substrate 10 can be uniformly arranged. However, in removing the oxide film 01, it is preferable to control the removal time of the oxide film 01 so that the oxide 22 around the nanowire 21 is not removed at the same time.

The next step of the nanowire forming step is to form the oxide layer 41 in the region of the base substrate 10 other than the nanowire forming region 20 and the CMOS forming region 30, 41 are formed. Hereinafter, this will be described in detail with reference to Figs. 8A to 11B.

8A is a perspective view illustrating a step of sequentially laminating an oxide film 02 and a nitride film N2 on the base substrate 10 of FIG. 7A, and FIG. 8B is a cross-sectional view taken along line A-A 'of FIG. 8A.

The oxide layer 41 may be formed by sequentially laminating an oxide film 02 and a nitride film N2 on the base substrate 10 first. At this time, the oxide film 02 and the nitride film N2 are also laminated in the groove G of the base substrate 10 as shown in Fig. 8B. The oxide film 02 and the nitride film N2 may be stacked by stacking an oxide film 02 by a dry oxidation process and then subjecting the nitride film N2 to an oxide film O2 ). &Lt; / RTI >

9A is a perspective view showing a step of patterning the oxide film 02 and the nitride film N2 of FIG. 8A to expose other regions 40, and FIG. 9B is a cross-sectional view taken along line A-A 'of FIG. 9A.

Next, the step of forming the oxide layer 41 may include the step of patterning the oxide film 02 and the nitride film N2, thereby forming the base substrate 20 other than the nanowire forming region 20 and the CMOS forming region 30. [ (10) region, that is, the other region (40) is exposed. The patterning of the oxide film 02 and the nitride film N2 is performed by coating a photoresist film on the base substrate 10 and then patterning the photoresist film by a photolithography process and etching the oxide film O2 ) And the nitride film (N2) may be dry-etched. At this time, patterning of the oxide film 02 and the nitride film N2 may be performed by removing the oxide film 02 and the nitride film N2 on the other regions 40 so that the other regions 40 are exposed.

FIG. 10A is a perspective view showing the step of forming the oxide layer 41 by the wet oxidation process in the exposed other region 40 of FIG. 9A, and FIG. 10B is a sectional view taken along line A-A 'of FIG. 10A.

Next, the step of forming the oxide layer 41 includes the step of forming the oxide layer 41 in the other region 40, which may be performed after the patterning of the oxide film O2 and the nitride film N2. The oxide layer O2 and the nitride layer N2 are exposed to the surface of the base substrate 10 other than the nanowire forming region 20 and the CMOS forming region 30, (41) can be formed. At this time, the silicon material is not exposed in the nanowire forming region 20 and the CMOS forming region 30, which are covered with the oxide film 02 and the nitride film N2, and the oxide layer 41 is not formed. On the other hand, the thickness of the oxide layer 41 formed in the other region 40 can be appropriately adjusted according to the time of the wet oxidation process. On the other hand, the oxide layer 41 formed in the other region 40 has insulating property even when doped, and may serve to insulate the nanowire forming region 20 and the CMOS forming region 30.

11A is a perspective view showing a step of removing the oxide film 02 and the nitride film N2 in FIG. 10A, and FIG. 11B is a cross-sectional view taken along the line A-A 'in FIG. 11A.

After the oxide layer 41 is formed in the other region 40, the oxide layer 41 is formed by forming the oxide film and the nitride film (see FIGS. 10A and 10B) remaining in the nanowire forming region 20 and the CMOS forming region 30 0.0 > O2, < / RTI > N2). 7A and 7B, the nitride film N2 is removed by using a phosphoric acid (H3PO4) solution, and the oxide film O2 is removed from the diluted hydrofluoric acid (HF) Followed by removal using a solution. In removing the oxide film 02, it is preferable to control the oxide film 02 removal time so that the oxide 22 around the nanowire 21 and the oxide film 41 of the other area 40 are not removed at the same time Do.

The next step of forming the oxide layer 41 is to form an N-type well 31a in the P-MOS region 31, which is one region of the CMOS formation region 30, in the well formation step, The P-type well 32a is formed in the N-MOS region 32, which is another region of the CMOS formation region 30, which is spaced apart from the MOS region 31. [ Hereinafter, this will be described in detail with reference to Figs. 12 to 17B.

12 is a cross-sectional view showing the step of forming an oxide film (O3) on the base substrate 10 of FIG. 11B.

The well formation step may include a step of first laminating an oxide film (O3) on the base substrate 10 on which the oxide layer 41 is formed. The oxide film O3 is deposited on the base substrate 10 by the dry oxidation process like the oxide films 01 and 02 described above. It is generally said that the lamination of the oxide film (O3) is formed thinly in the entire region of the base substrate 10. But may be formed only in regions other than the other regions 40 where the oxide layer 41 is formed. That is, as shown in FIG. 12, the oxide film O 3 may be formed only in the nanowire forming region 20 and the CMOS forming region 30. As the oxide film O3 is formed, a dopant is implanted into the region where the N-type and P-type wells 31a and 32a are to be formed, when doping the N-type and P-type dopants 51 and 52 As shown in FIG.

13A is a perspective view showing a step of doping an N-type dopant 51 into the P-MOS region 31 of FIG. 12, FIG. 13B is a cross-sectional view taken along line A-A ' 13A is a perspective view showing a step of doping a P-type dopant 52 into the N-MOS region 32, and FIG. 14B is a cross-sectional view taken along the line A-A 'in FIG. 14A.

In the well formation step, an N-type dopant 51 is doped into the P-mos region 31 to form an N-type well 31a, and a P-type dopant 52 is doped into the N- And forming a P-type well 32a by doping. This is because the base substrate 10 is formed of undoped silicon with no dopant, and forms a base of P-MOS and N-MOS. 13A and 13B, the N-type well 31a is formed by applying the photoresist film P2 on the base substrate 10 and exposing only the P-MOS region 31 to the exposed So as to pattern the photoresist film P2. Thereafter, an N-type dopant 51 of a predetermined concentration such as As or P is implanted toward the base substrate 10 to dop the N-type dopant 51 into the P-mos region 31, The photoresist film P2 is removed to form an N-type well 31a. As shown in FIGS. 14A and 14B, the P-type well 32a is formed by applying the photoresist P3 on the base substrate 10 and exposing only the N-MOS region 32 to the exposed So that the photosensitive film P3 is patterned. Thereafter, a P-type dopant 52 of a predetermined concentration such as B (boron) is injected toward the base substrate 10, the P-type dopant 52 is doped into the N-MOS region 32, P3 are removed to form a P-type well 32a. In the drawing, an N-type well 31a is formed first and a P-type well 32a is formed. However, the present invention is not limited to this, and a P-type well 32a may be formed first, The well 31a may be formed.

15A is a perspective view showing a step of heat-treating the P-MOS region 31 and the N-MOS region 32 of FIG. 14A, and FIG. 15B is a sectional view taken along the line A-A 'of FIG.

After the N-type and P-type dopants 51 and 52 are doped, the well formation step may further include a step of heat-treating the P-MOS region 31 and the N-MOS region 32. Due to the heat treatment step, N-type and P-type dopants 51 and 52 diffuse in the P-mos region 31 and the N-MOS region 32, and the doped base substrate 10 is re- (Recrystallization). This heat treatment step may be a diffusion process in which the base substrate 10 is heated to a high temperature (about 1000 캜 or higher) for a long time and cooled slowly. After the heat treatment of the P-MOS region 31 and the N-MOS region 32, the oxide film O3 is removed.

16A is a perspective view showing the step of doping the first-type dopant 53 into the N-MOS region 32 of FIG. 15A, FIG. 16B is a cross-sectional view taken along line A-A 'of FIG. 16A, 17A is a perspective view showing a step of doping the P-mos region 31 of FIG. 16A with the second type dopant 54, and FIG. 17B is a cross-sectional view taken along the line A-A 'of FIG. 17A.

The well formation step includes doping a first type dopant 53 into the N-MOS region 32 and doping the second type dopant 54 into the P-MOS region 31 after the heat treatment step . The doping of the first type dopant 53 into the N-MOS region 32 modulates the formation of an N-channel (not shown) connecting the source and drain of the subsequently formed N-MOS, Adjust the voltage (V _th ). The doping of the second type dopant 54 into the P-MOS region 31 also corresponds to the doping of the first type dopant 53 of the N-MOS region 32 with the threshold voltage V _th . At this time, the first-type dopant 53 is preferably composed of an N-type conductivity type which is different from the P-type dopant (52 in FIG. 14B) forming the P-type well 32a, Type conductivity type. The second-type dopant 54 is also preferably of a P-type conductivity type which is different from the N-type dopant 51 of the N-type well 31a (51 of FIG. 13B) And may be of a conductive type. In the specific process, the oxide film (04) is first deposited on the base substrate for uniform doping of the first and second type dopants (53, 54). 16A and 16B, the photoresist P4 is applied to the base substrate 10, and only the N-MOS region 32 is exposed by the photolithography process And then doping the first-type dopant 53 into the N-MOS region 32. The doping of the second type dopant 54 is performed by applying a photoresist film P5 to the base substrate 10 as shown in Figs. 17A and 17B, exposing only the P-MOS region 31 by a photolithography process, And doping the P-MOS region 31 with a dopant of the second type. In the drawing, the first type dopant 53 is first doped and the second type dopant 54 is doped. However, the present invention is not limited thereto, and the second type dopant 54 may be doped first And doped with the first type dopant 53 may be doped. After doping the first and second types of dopants 53 and 54, the oxide film 04 doped with the first and second types of dopants 53 and 54 is removed so that the surface of the base substrate 10 is covered with a dopant So that the clean state can be maintained.

The next step of the well formation step is to form the polysilicon PS on the base substrate 10 and pattern the polysilicon PS to form the P-MOS region 31 and the N- The first gate 31b and the second gate 32b are formed in the first gate electrode 32 and the second gate electrode 32, respectively. Hereinafter, this will be described in detail with reference to Figs. 18A to 22B.

18A is a perspective view showing a step of laminating a gate oxide film O5 and polysilicon PS on the base substrate 10 of FIG. 17A, and FIG. 18B is a cross-sectional view taken along line A-A 'of FIG. 18A.

The gate forming step may include a step of firstly depositing a gate oxide film 05 and polysilicon (PS) on the base substrate 10. After the doping process of FIGS. 17A and 17B, the base substrate 10 is cleaned, the gate oxide film 05 is laminated through the dry oxidation process, and the polysilicon (PS) is laminated on the stacked oxide film O5. Polysilicon (PS) may be deposited on a part of the base substrate 10 according to a lamination method, but is generally deposited on the base substrate 10 and laminated. The polysilicon (PS) has the same energy gap as the silicon channel, and the work function of the polysilicon (PS) is variable depending on the doping level. Therefore, when gate is formed by polysilicon (PS), the threshold voltage of P-MOS and N-MOS proportional to the difference of work function between gate material and channel material can be easily controlled.

19A is a perspective view showing a step of exposing a portion where the polysilicon (PS) is laminated in the nanowire forming region 20 of FIG. 18A, FIG. 19B is a cross-sectional view taken along line A-A ' 20A is a perspective view showing a step of removing the polysilicon PS of the exposed nanowire forming region 20 of FIG. 19A by wet etching, and FIG. 20B is a sectional view taken along line A-A 'of FIG. 20A.

After the polysilicon (PS) is deposited, the gate forming step exposes only the polysilicon (PS) in the nanowire forming region 20 and removes the polysilicon (PS) in the nanowire forming region 20 by wet etching Step < / RTI > If the polysilicon (PS) in the nanowire forming region 20 is removed by dry etching, the nanowires 21 under the polysilicon (PS) can be removed together. Therefore, it is preferable that the polysilicon (PS) in the nanowire forming region 20 is removed by wet etching prior to dry etching to form the gate. 19A and 19B, the photoresist film P6 is patterned by a photolithography process so that only the nanowire forming region 20 is exposed after the photoresist film P6 is laminated on the base substrate 10. Next, as shown in FIG. Then, as shown in FIGS. 20A and 20B, the exposed polysilicon (PS) in the nanowire forming region 20 is removed by using a KOH solution or a TMAH solution. In removing the polysilicon (PS), it is preferable to adjust the time of wet etching so that the nanowires 21 located under the polysilicon (PS) are not damaged.

21A is a perspective view showing a step of patterning the photosensitive film P7 on the nanowire forming region 20 and the CMOS forming region 30 of FIG. 20A, FIG. 21B is a sectional view taken along the line A-A 'of FIG. 22A is a perspective view showing a step of etching polysilicon (PS) according to the patterning of FIG. 21A, and FIG. 22B is a sectional view taken along line A-A 'of FIG. 22A.

In the gate forming step, the N-type well 31a and the polysilicon PS on the P-type well 32a are patterned to form the first and second polysilicon layers 31 and 32 in the P- 2 gate 31b, 32b, which may be performed after the polysilicon (PS) of the nanowire forming region 20 is removed by wet etching. Patterning of the polysilicon PS formed on the N-type well 31a and the P-type well 32a is performed by patterning the first gate 31b and the second gate 31b in the P-mos region 31 and the N- The photoresist film P7 is patterned in the form of the second gate 32b and the polysilicon PS on the N type well 31a and the P type well 32a is dry etched according to the patterning of the photoresist film P7 . The dry etching of the polysilicon PS may damage the nanowire 21 of the nanowire forming region 20 by dry etching the polysilicon PS by using a photoresist P7. It may proceed after covering the region 20. After the polysilicon PS is dry etched, the photoresist P7 is removed to form the first gate 31b of the P-MOS region 31 and the second gate 32b of the N-MOS region 32 Is completed.

The next step in the gate formation step is to deposit a P-type dopant 55 on the side of the first gate 31b to form a P-MOS transistor on the P-MOS region 31, 31d and a first drain 31e and doped with an N type dopant 56 to form an N-MOS on the N-MOS region 32 to form a second source 32b on the side of the second gate 32b A first dopant 57 is doped into the first conductive region 21a on one side of the nanowire 21 in the longitudinal direction and the first conductive region 21a and the first conductive region 21b are connected to the first conductive region 21a and the second drain 32e, A second dopant 58 having conductivity different from that of the first dopant 57 is doped in the second conductive region 21b on the other side of the nanowire 21 in the longitudinal direction. Hereinafter, this will be described in detail with reference to Figs. 23A to 31. Fig.

23A is a perspective view showing a step of doping the P-type low concentration dopant 55a into the P-MOS region 31 of FIG. 22A, and FIG. 23B is a sectional view taken along line A-A 'of FIG. 23A. 24A is a perspective view showing a step of doping the N-type low concentration dopant 56a into the N-MOS region 32 of FIG. 23A, and FIG. 24B is a sectional view taken along line A-A 'of FIG. 24A.

The dopant doping step is a step of doping the P-type low concentration dopant 55a into the P-mos region 31 and doping the N-type low concentration dopant 56a into the N-mos region 32 to form a lightly doped drain ). &Lt; / RTI > Since the LDD which is the low concentration region L is formed in the N type well 31a and the P type well 32a, even if the interval between the source and the drain is narrowed to downsize the CMOS, a malfunction Can be prevented. Specifically, first, as shown in FIGS. 23A and 23B, the base substrate 10 is laminated with a photoresist P8, only the P-MOS region 31 is exposed by a photolithography process, and then the P- The LDD as the low concentration region L can be formed in the N type well 31a by doping the P type low concentration dopant 55a. 24A and 24B, a photoresist film P9 is laminated on the base substrate 10, only the N-MOS region 32 is exposed by a photolithography process, and then the N-MOS region 32 is formed with an N- The low concentration dopant 56a is doped to form the LDD which is the low concentration region L in the P type well 32a. Alternatively, LDD may be formed first in the P-type well 32a and LDD may be formed later in the N-type well 31a.

25A is a perspective view showing the step of doping the first and second conductive regions 21a and 21b of the nanowire 21 of FIG. 24A with the first lightly doped layer 57a, FIG. 25B is a cross- &Quot; 26A is a perspective view showing the step of doping the second light conductive dopant 58a into the second conductive region 21b of the nanowire 21 of FIG. 25A, FIG. 26B is a cross-sectional view taken along line A-A ' Fig.

The dopant doping step may include doping the first and second lightly doped regions 57a and 58a with the first and second conductive regions 21a and 21b of the nanowire 21, ) Can function as an optical element such as a photodiode. The nanowire 21 lightly doped doping step may proceed after steps 23A-24B, or may proceed prior to steps 23A-24B, or 23A-24B. Therefore, the steps in FIGS. 23A to 26B can collectively be referred to as a low-concentration region forming step. On the other hand, the first and second low concentration dopants 57a and 58a are relatively low in concentration than the first and second high concentration dopants (57b in FIG. 29B and 58b in FIG. 30) The concentration may be different from that of the dopants 55a and 56a. 25A and 25B, the photosensitive film P10 is laminated on the base substrate 10, and the first and second conductive regions 21a and 21b of the nanowire 21 are exposed, The photosensitive film P10 is patterned. The first and second conductive regions 21a and 21b are doped with a first lightly doped layer 57a of a predetermined concentration. In this case, the first lightly doped layer 57a may have a p-type conductivity type. The first conductive region 21a refers to a region on one side of the nanowire 21 in the longitudinal direction and the second conductive region 21b refers to a region along the length direction of the nanowire 21 continuous with the first conductive region 21a Refers to the other area. After doping the first low concentration dopant 57a, the second low concentration dopant 58a is doped so that the second conductive region 21b of the nanowire 21 is exposed, as shown in FIGS. 26A and 26B, The photosensitive film P11 may be patterned by an etching process and the second lightly doped region 58a may be doped with a predetermined concentration to the second conductive region 21b. In this case, the second lightly doped layer 58a has a conductivity type different from that of the first lightly doped layer 57a, and may have an N-type conductivity type. The second low concentration dopant 58a may have a higher concentration than the first low concentration dopant 57a so that the second conductivity region 21b may have a conductivity type different from that of the first conductivity region 21a. 25A to FIG. 26B, the doped nanowires 21 are formed at junctions of the first conductivity type regions 21a and the second conductivity type regions 21b with junctions of different conductivity type dopants, Thereby forming a junction region between the gate electrode and the gate electrode. However, unlike FIG. 25A to FIG. 26B, only the first lightly doped region 57a is doped in the first conductive region 21a and only the second lightly doped region 58a is doped in the second conductive region 21b, (21) may be doped.

27A is a perspective view showing a step of laminating an oxide film O6 on the base substrate 10 of Fig. 26A, and Fig. 27B is a sectional view taken along the line A-A 'in Fig. 27A. 28A is a perspective view showing a step of dry etching the oxide film O6 of FIG. 27A to form a spacer, and FIG. 28B is a cross-sectional view taken along line A-A 'of FIG. 28A.

The dopant doping step may include a spacer forming step after the lightly doped region forming step. The spacers reduce the exposed areas of the N-type well 31a and the P-type well 32a so that the LDD functions in the N-type well 31a and the P-type well 32a, H are formed to be narrower than the horizontal area of the low-concentration region L (see Figs. 29A to 30B). In a specific process, an oxide film (O6) is stacked on the base substrate 10 as shown in Fig. 27B. At this time, the oxide film O6 may be deposited on the base substrate 10 to a predetermined thickness through a chemical vapor deposition (CVD) process. Thereafter, as shown in FIG. 28B, a first spacer 31c is formed on both sides of the first gate 31b, and a second spacer 32c is formed on both sides of the second gate 32b , And the oxide film (O6) are dry-etched. On the other hand, in this case, the gate oxide film O5 deposited in the step of FIG. 18B can also be removed together.

29A is a perspective view showing a step of doping a first high-concentration dopant 57b and a P-type high-concentration dopant 55b to a part of the first conductive region 21a and the P-MOS region 31 in FIG. 29B is a sectional view taken along the line A-A 'in FIG. 29A. 30A is a perspective view showing a step of doping the second high-concentration dopant 58b and the N-type high-concentration dopant 56b in the portion of the second conductive region 21b and the N-MOS region 32 in FIG. 29A , And Fig. 30B is a cross-sectional view taken along the line A-A 'in Fig. 30A. 31 is a cross-sectional view showing the step of heat-treating the first and second conductive regions 21a and 21b, the P-moss region 31 and the N-MOS region 32 of FIG. 30B.

29A to 31B may be referred to as a heavily doped region forming step, and the dopant doping step may include a heavily doped region forming step after the formation of the spacers. A first source 31d and a first drain 31e are formed on both sides of the first gate 31b and a second source 32d is formed on both sides of the second gate 32b by doping with a high concentration dopant. And the second drain 32e are formed, and a place for contacting the wiring (80 in FIG. 40) for electrical connection to the nanowire 21, P-MOS and N-MOS is provided. 29A and 29B, the photoresist P12 is patterned first to expose one side of the first conductive region 21a and the P-MOS region 31. In this process, In this case, one side of the first conductive region 21a refers to one end of the nanowire 21 that is not in contact with the second conductive region 21b. Thereafter, the P-type high concentration dopant 55b and the first high concentration dopant 57b are doped to one side of the first conductive region 21a and the P-MOS region 31 to remove the photosensitive film P12, 1 high-concentration dopant 57b may be substantially the same dopant as the P-type high-concentration dopant 55b. Next, as shown in FIGS. 30A and 30B, the photoresist film P13 is patterned to expose the other side of the second conductive region 21b and the N-MOS region 32. Next, as shown in FIGS. In this case, the other side of the second conductive region 21b refers to the other end of the nanowire 21 that is not in contact with the first conductive region 21a. Thereafter, the N-type high concentration dopant 56b and the second high concentration dopant 58b are doped to one side of the second conductive region 21b and the N-MOS region 32 to remove the photosensitive film P13, 2 high concentration dopant 58b may be substantially the same dopant as the N type high concentration dopant 56b. 29A to 30B show that the nanowire 21, the P-MOS region 31 and the N-MOS region 32 are simultaneously doped with a high concentration dopant, Lt; / RTI > 29A to 30B, the P + type semiconductor region and the P type semiconductor region may be sequentially formed in the longitudinal direction of the nanowire 21 in the first conductive region 21a. In this case, the P + Type implies doping at a higher concentration than P-type. The second conductive region 21b is formed continuously from the P-type semiconductor region of the first first conductive region 21a so that the N-type semiconductor region and the N + -type semiconductor region are sequentially formed in the longitudinal direction of the nanowire 21 . In this case, it means that the N + type is doped at a higher concentration than the N type. After the doping with the high concentration dopant, the first and second conductive regions 21a and 21b, the P-mos region 31 and the N-mos region 32 may be subjected to a heat treatment as shown in Fig. 30 , Which can be done by a Rapid Thermal Anneal (RTA) process.

The next step of the dopant doping step may further include the step of forming the silicide 60 to reduce the contact resistance with the wiring 80 made of metal before the electrical connecting step or the electrical connecting step, The steps of forming the silicide 60 will be described first.

32A is a perspective view showing a step of laminating an oxide film O7 on the base substrate 10 of FIG. 31, and FIG. 32B is a sectional view taken along line A-A 'of FIG. 32A. 33A is a perspective view showing a step of patterning the photosensitive film P14 on a part of the nanowire forming region 20 of FIG. 32A, and FIG. 33B is a sectional view taken along line A-A 'of FIG. 33A. 34A is a perspective view showing a step of etching the oxide film O7 according to the patterned photoresist film P14 in FIG. 33A, and FIG. 34B is a cross-sectional view taken along the line A-A 'in FIG. 34A.

The step of forming the silicide 60 may include a step of laminating an oxide film O7 on the base substrate 10, as shown in Figs. 32A and 32B. In this case, the oxide film O7 is uniformly deposited on the entire region of the base substrate 10 to a predetermined thickness, and can be formed through a chemical vapor deposition process. Next, in order to protect the portion of the nanowire 21 where the silicide 60 is not formed with the oxide film O7, the step of patterning the oxide film O7 proceeds. In this case, the oxide film O7 is first patterned by patterning the photoresist film P14 as shown in FIGS. 33A and 33B, and then the oxide film O7 is dry-etched according to the patterned photoresist film P14 as shown in FIGS. 34A and 34B And etching. On the other hand, the patterned oxide film O7 is formed so as to cover the portion of the nanowire 21 where the silicide 60 is not formed. The portion of the nanowire 21 where the silicide 60 is not formed is a portion of the first conductive region 21a contacting the second conductive region 21b and the other of the first conductive region 21a, Quot; means one side of the second conductive region 21b extending from the other side of the first conductive region 21b. Thus, the nanowire 21 can be protected in the process of forming the silicide 60 as the portion of the nanowire 21 where the silicide 60 is not formed is covered with the oxide film O7.

35 is a cross-sectional view showing the step of laminating a silicide metal layer 61 on the base substrate 10 of Fig. 34B.

After patterning the oxide film (O7), the step of forming the silicide 60 proceeds with the step of laminating the silicide metal layer 61 on the base substrate 10. [ In this case, the silicide metal layer 61 is laminated to the entire region of the base substrate 10 to a certain thickness. In addition, the silicide metal layer 61 may be formed of any one of metals such as Ti, Co, and Ni, or may be formed by combining two or more metals.

36 is a cross-sectional view showing a step of removing the silicide metal layer 61 which is not in contact with the silicon after the first heat treatment of the base substrate 10 shown in FIG. 35 and does not react to form the silicide 60, 37 is a cross-sectional view showing the step of performing the second heat treatment on the base substrate 10 of Fig.

The silicide 60 formation step is followed by the first and second thermal treatment steps after the silicide metal layer 61 is deposited. The first heat treatment may proceed to about 650 ° C, whereby a primary silicide 61a is formed at a portion where the silicide metal layer 61 is in contact with the silicon material. That is, the first silicide (TiSi) 61a is formed on the silicon portion that is not oxidized and exposed to the surface. In the nanowire forming region 20, the oxide film O7 is not in contact with the portion of the first conductive region 21a that is not covered with the second conductive region 21b, that is, the first conductive region 21a and the first conductive region 21a A first silicide 61a is formed on the other side of the second conductive region 21b. In the P-MOS region 31, the first silicide 61a is formed in the first gate 31b, the first source 31d and the first drain 31e. In the N-MOS region 32, The first silicide 61a is formed in the second gate 32b, the second source 32d, and the second drain 32e. After the formation of the primary silicide 61a, the silicide metal layer 61 having no primary silicide formed thereon is removed, and the base substrate 10 is subjected to a secondary heat treatment at about 850 ° C, Ti silicide (TiSi ₂ , 61b).

The next step is an electrical connection step where the electrical connection step forms a dielectric layer 70 on which a contact hole 70a is formed on the base substrate 10 and is stacked on the dielectric layer 70 to fill the contact hole 70a The metal wiring layer 81 is patterned to form a wiring 80 electrically connecting the nanowire 21, P-MOS and N-MOS. This will be described below with reference to Figs. 38A to 40B.

38A is a perspective view showing the step of forming the dielectric layer 70 on the base substrate 10 of FIG. 37, and FIG. 38B is a sectional view taken along line A-A 'of FIG. 38A. 39A is a perspective view showing a step of laminating the metal wiring layer 81 on the base substrate 10 of Fig. 38A, and Fig. 39B is a sectional view taken along line A-A 'of Fig. 39A. 40A is a perspective view showing a step of patterning the metal wiring layer 81 in FIG. 39A, and FIG. 40B is a cross-sectional view taken along the line A-A 'in FIG. 40A.

The electrical connection step is for electrically connecting the nanowire 21, P-MOS and N-MOS. First, as shown in FIGS. 38A and 38B, a dielectric layer 70 is formed on the base substrate 10 Laminated. In this case, the dielectric layer 70 has an insulating property and can be formed of a transparent material. Next, although not shown, a photoresist layer is coated on the dielectric layer 70, the photoresist layer is patterned by a photolithography process, and the dielectric layer 70 is dry-etched along the patterned photoresist layer to form contact holes 70a in the dielectric layer 70, . The contact hole 70a is formed such that a part of the silicide 60 is exposed, as shown in Fig. 38B. Then, as shown in Figs. 39A and 39B, the metal wiring layer 81 is deposited on the dielectric material while filling the contact holes 70a. As the metal wiring layer 81 is filled in the contact hole 70a, the metal wiring layer 81 contacts the silicide 60 and the nanowire 21, P-MOS and N-MOS can be electrically connected. Next, as shown in Figs. 40A and 40B, the wiring 80 can be formed by patterning the metal wiring layer 81 through a photolithography process and a dry-etching process. 40A and 40B show only one dielectric layer 70 and one metal wiring layer 81. However, the present invention is not limited to this, and the dielectric layer 70 and the metal wiring layer 81 of FIG. A dielectric layer and a metal wiring layer of a tertiary or higher order can be formed.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. It is clear that the present invention can be modified or improved.

It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present invention as defined by the appended claims.

10: base substrate
20: nanowire forming region 21: nanowire
21a: first conductive region 21b: second conductive region
22: oxide
30: CMOS forming region 31: P-MOS region
31a: N-type well 31b: First gate
31c: first spacer 31d: first source
31e: first drain 32: N-MOS region
32a: P-type well 32b: second gate
32c: second spacer 32d: second source
32e: second drain
40: other region 41: oxide layer
51: N-type dopant 52: P-type dopant
53: dopant of the first type 54: dopant of the second type
55: P-type dopant 55a: P-type low concentration dopant
55b: P-type high concentration dopant 56: N-type dopant
56a: N-type low concentration dopant 56b: N-type high concentration dopant
57: first dopant 57a: first low concentration dopant
57b: first high concentration dopant 58: second dopant
58a: second low concentration dopant 58b: second high concentration dopant
60: silicide 61: silicide metal layer
61a: primary silicide 61b: secondary silicide
70: dielectric layer 70a: contact hole
80: wiring 81: metal wiring layer
G: groove L: low concentration area
H: heavily doped regions O1 to O7: oxide film
N1 to N2: Nitride films P1 to P14:
PS: Polysilicon

Claims

A preparation step of preparing an insulating base substrate including a nanowire formation region and a CMOS formation region;
A nanowire forming step of forming at least two grooves on the base substrate on the nanowire forming region, wet oxidation of the base substrate between the grooves, and nanowires formed on the base substrate between the grooves;
An oxide layer forming step of forming an oxide layer on the base substrate other than the nanowire forming area and the CMOS forming area;
Forming an N-type well in one region of the CMOS formation region and forming a P-type well in an N-MOS region which is another region of the CMOS formation region apart from the P- Forming step;
A gate forming step of forming polysilicon on the base substrate and patterning the polysilicon to form a first gate and a second gate in the P-MOS region and the N-MOS region, respectively;
Forming a first source and a first drain on a side of the first gate by doping a P-type dopant to form a P-MOS on the P-MOS region so that N-MOS is formed on the N- Doped with an N-type dopant to form a second source and a second drain on the side of the second gate, doping a first dopant to a first conductive region on one side of the nanowire in the longitudinal direction, A dopant doping step of doping a second dopant having a conductivity different from that of the first dopant to a second conductive region on the other longitudinal side of the successive nanowires; And
Forming a dielectric layer on which the contact hole is formed on the base substrate, patterning the metal interconnection layer filled in the contact hole while being stacked on the dielectric layer to electrically connect the nanowire, the P-MOS and the N- And an electrically connecting step of forming a first electrode,
The dopant doping step
Doping a P-type low concentration dopant on the P-MOS region, doping an N-type low concentration dopant on the N-MOS region, doping the first conductive region with a first lightly doped dopant, A low concentration region forming step of doping a second low concentration dopant having conductivity different from the first low concentration dopant;
Forming an oxide film on the base substrate, patterning the oxide film to form a first spacer on both sides of the first gate on the P-MOS region, and forming a second spacer on the second gate side on the N- Forming a spacer; And
Type dopant is doped on the P-MOS region, an N-type high-concentration dopant is doped on the N-MOS region, and a first high-concentration dopant is doped on one side of the first conductive region that is not in contact with the second conductive region And a high concentration region forming step of doping a second high concentration dopant having conductivity different from that of the first high concentration dopant to the other side of the second conductive region which is not in contact with the first conductive region,
The high concentration region forming step
Doping a P-type high concentration dopant to the P-MOS region and doping a first high concentration dopant having the same conductivity as the P-type high concentration dopant to one side of the first conductive region that is not in contact with the second conductive region;
Doping an N-type high-concentration dopant to the N-MOS region and doping a second high-concentration dopant having the same conductivity as the N-type high-concentration dopant on the other side of the second conductive region that is not in contact with the first conductive region; And
And heat treating the first conductive region, the second conductive region, the P-MOS region, and the N-MOS region.

The method according to claim 1,
The nanowire forming step may include:
Sequentially stacking an oxide film and a nitride film on the base substrate;
Patterning the oxide film and the nitride film on the nanowire-forming region;
Forming at least two grooves by etching the patterned base substrate to a predetermined depth;
Anisotropically etching the base substrate between the grooves to form a base substrate between the grooves so that a width gradually increases from a center width in a thickness direction toward an upper end and a lower end;
Forming a nanowire on the base substrate by wet oxidation of the base substrate to break the upper and lower ends of the anisotropically etched base substrate; And
And removing the oxide film and the nitride film on the base substrate.

The method of claim 2,
Wherein the thickness of the nanowire is controlled in accordance with a time of wet oxidation of the base substrate.

The method according to claim 1,
In the oxide layer forming step,
Sequentially stacking an oxide film and a nitride film on the base substrate;
Exposing the base substrate region other than the nanowire forming region and the CMOS forming region by patterning the oxide film and the nitride film;
Forming an oxide layer on the exposed base substrate region by a wet oxidation process; And
And removing the oxide film and the nitride film on the base substrate.

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The method according to claim 1,
Wherein the gate forming step comprises:
Depositing polysilicon on the base substrate;
Removing the polysilicon in the nanowire-forming region by wet etching; And
CMOS circuit including; while protecting the poly nanowires forming region of the silicon is removed by the photosensitive film lead to form the first gate and the second gate by patterning the well above the polysilicon of the well and the P-type of the N type A method of manufacturing a nanowire sensor chip integrated with a nanowire.

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The method according to claim 1,
Wherein the first lightly doped dopant has a P-type conductivity type and the second lightly doped dopant is a CMOS circuit having an N-type conductivity type.

The method of claim 9,
Wherein the first conductive region comprises a first conductive region,
Wherein the P + type semiconductor region and the P type semiconductor region are sequentially formed in the longitudinal direction of the nanowire.

The method of claim 10,
The second conductive region may include a first conductive region,
Type semiconductor region and an N + -type semiconductor region are sequentially formed in the longitudinal direction of the nanowire from the P-type semiconductor region of the first conductive region, the N-type semiconductor region and the N + -type semiconductor region being sequentially formed in the longitudinal direction of the nanowire.

The method according to claim 1,
The low-concentration region forming step includes:
Doping the P-MOS region with a P-type lightly doped dopant;
Doping the N-MOS region with an N-type lightly doped dopant;
Doping the first and second conductive regions of the nanowire with a first lightly doped dopant; And
And doping a second lightly doped dopant at a concentration higher than that of the first lightly doped dopant to the second conductive region of the nanowire.

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The method according to claim 1,
Further comprising a silicide forming step prior to the electrical connecting step after the dopant doping step,
The silicide formation step may include:
Patterning an oxide film on the other side of the first conductive region in contact with the second conductive region and on the side of the second conductive region extending from the other side of the first conductive region;
Forming a silicide metal layer on the base substrate;
A first gate of a P-MOS transistor, a first source, a first drain, and a first drain of the P-MOS transistor and a first drain of the P-MOS transistor, Forming a first silicide in a second gate, a second source, and a second drain of the first semiconductor layer; And
Removing the silicide metal layer where the first silicide is not formed, and then changing the first silicide to a second silicide by heat treatment;
The contact hole of the electrical connection step is formed to expose the second silicide, and a CMOS circuit in which the nanowire, P-MOS and N-MOS are electrically connected by the contact of the second silicide and the metal wiring layer is integrated A method of manufacturing a nanowire sensor chip.

15. The method of claim 14,
Wherein the silicide metal layer is formed by integrating a CMOS circuit formed of any one of Ti, Co, and Ni.