KR101795754B1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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KR101795754B1
KR101795754B1 KR1020100114715A KR20100114715A KR101795754B1 KR 101795754 B1 KR101795754 B1 KR 101795754B1 KR 1020100114715 A KR1020100114715 A KR 1020100114715A KR 20100114715 A KR20100114715 A KR 20100114715A KR 101795754 B1 KR101795754 B1 KR 101795754B1
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pad
wiring
semiconductor device
address
power supply
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KR1020100114715A
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Korean (ko)
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KR20120053438A (en
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조희정
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에스케이하이닉스 주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

본 발명은 제1 패드, 상기 제1 패드의 제1 방향에 배치된 디코더 및 상기 제2 패드의 상기 제1 방향과 교차하는 제2 방향에 배치된 제1 버퍼를 포함하는 반도체 장치를 제공한다.The present invention provides a semiconductor device including a first pad, a decoder disposed in a first direction of the first pad, and a first buffer disposed in a second direction intersecting the first direction of the second pad.

Description

반도체 장치{SEMICONDUCTOR DEVICE}Technical Field [0001] The present invention relates to a semiconductor device,

본 발명은 반도체 장치에 관한 것으로서, 구체적으로 설명하면 집적도를 향상시킬 수 있는 반도체 장치에 관한 것이다.
The present invention relates to a semiconductor device, and more particularly, to a semiconductor device capable of improving the degree of integration.

반도체 장치는 인간의 기억, 기록능력을 전자적 수단에 의해 실현한 장치로서, 컴퓨터나 통신기기, 방송기기, 교육 및 오락기기 등에서 저장기기로 사용된다. 반도체 장치가 시장에 출시된 것은 1971년이며, 이때의 메모리용량은 1Kbit였다. 이후, 반도체 장치의 메모리용량은 2~3년에 4배씩 증가하는 등, 경이적인 발전을 거듭하고 있다. A semiconductor device is a device for realizing human memory and recording ability by electronic means, and is used as a storage device in a computer, a communication device, a broadcasting device, an educational device, and an entertainment device. The semiconductor device was introduced to the market in 1971, and the memory capacity at that time was 1 Kbit. Thereafter, the memory capacity of the semiconductor device is increased by four times in two to three years, and such phenomenal development has been repeated.

이와 같이 반도체 장치의 메모리용량이 증가하면 할수록, 대두되는 것이 반도체 장치의 집적도이다. 반도체 장치의 집적도는 일정한 면적에 얼마나 많은 소자들을 확보하느냐에 따라 결정된다. 이때, 반도체 장치의 집적도는 메모리용량을 결정하는 저장매체(cell)뿐만 아니라 데이터의 입, 출력을 제어하는 장치들의 배치에도 영향을 받는다. 특히, 반도체 장치의 집적도는 반도체 장치의 내부와 외부를 연결하기 위한 접점인 패드(pad) 및 패드와 연결되어 신호를 버퍼링하고 디코딩하는 회로들의 배치에 영향을 받는다.
As the memory capacity of the semiconductor device increases, the degree of integration of the semiconductor device increases. The degree of integration of a semiconductor device depends on how many devices are secured in a certain area. At this time, the degree of integration of the semiconductor device is affected not only by the storage medium for determining the memory capacity but also by the arrangement of the devices for controlling the input and output of data. In particular, the degree of integration of a semiconductor device is influenced by the arrangement of the pad and pad, which are the contacts for connecting the inside and the outside of the semiconductor device, and the circuits for buffering and decoding signals.

본 발명은 집적도를 향상시키는 반도체 장치를 제안한다.
The present invention proposes a semiconductor device for improving the degree of integration.

본 발명은 제1 패드, 상기 제1 패드의 제1 방향에 배치된 디코더 및 상기 제2 패드의 상기 제1 방향과 교차하는 제2 방향에 배치된 제1 버퍼를 포함하는 반도체 장치를 제공한다.
The present invention provides a semiconductor device including a first pad, a decoder disposed in a first direction of the first pad, and a first buffer disposed in a second direction intersecting the first direction of the second pad.

본 발명은 반도체 장치의 집적도를 향상시키기 위해 패드와 연계된 버퍼의 배치를 변경한다. 이때, 버퍼의 배치만의 변경으로는 집적도 향상이 어려우므로, 불필요한 배선을 제거한 후, 버퍼의 배치를 변경한다. 따라서, 본 발명은 반도체 장치의 집적도 향상을 통해 넷다이(net die)를 증가시키며, 이로써 경제적인 우수한 효과를 획득한다.
The present invention changes the arrangement of the buffers associated with the pads to improve the degree of integration of the semiconductor device. At this time, since it is difficult to improve the degree of integration by changing only the arrangement of the buffers, the arrangement of the buffers is changed after unnecessary wiring is removed. Therefore, the present invention increases the net die through the improvement of the integration degree of the semiconductor device, thereby obtaining economical excellent effect.

도 1은 본 발명을 설명하기 위해 도시한 반도체 장치의 레이아웃을 나타낸 도면이다.
도 2는 본 발명의 일실시예에 따른 반도체 장치를 나타낸 평면도이다.1 is a view showing a layout of a semiconductor device shown for explaining the present invention.
2 is a plan view showing a semiconductor device according to an embodiment of the present invention.

이하, 실시예를 통하여 본 발명을 더욱 상세히 설명하기로 한다. 이들 실시예는 단지 본 발명을 예시하기 위한 것이며, 본 발명의 권리 보호 범위가 이들 실시예에 의해 제한되는 것은 아니다.Hereinafter, the present invention will be described in more detail with reference to Examples. These embodiments are only for illustrating the present invention, and the scope of rights of the present invention is not limited by these embodiments.

도 1은 본 발명을 설명하기 위해 도시한 반도체 장치의 레이아웃을 나타낸 도면이다.1 is a view showing a layout of a semiconductor device shown for explaining the present invention.

도 1에 도시된 바와 같이, 반도체 장치는 상하방향(Y)으로 쌍을 이루는 제1 및 제2 어드레스패드(11, 12)와 다른 쌍을 이루는 제3 및 제4 어드레스패드(13, 14), 제1 및 제2 어드레스패드(11, 12) 사이에 배치된 제1 및 제2 버퍼(21, 22), 제3 및 제4 어드레스패드(13, 14) 사이에 배치된 제3 및 제4 버퍼(23, 24), 제1 어드레스패드(11)의 좌측에서 상하방향(Y)으로 연장된 제1 배선그룹(33A), 제1 어드레스패드(11)의 우측에서 상하방향(Y)으로 연장된 제2 배선그룹(33B), 제3 어드레스패드(13)의 좌측에서 상하방향(Y)으로 연장된 제3 배선그룹(33C), 제2 및 제3 배선그룹(33B, 33C) 사이에서 상하방향(Y)으로 쌍을 이루는 접지전압패드(41)와 전원전압패드(42), 제3 및 제4 버퍼(23, 24) 사이에 배치된 어드레스디코더(51)를 포함한다. 여기서, 상하방향(Y)과 좌우방향(X)는 서로 교차하는 방향이다. 제1 내지 제4 어드레스패드(11~14)는 어드레스신호를 입력받기 위한 패드이고, 제1 내지 제4 버퍼(21~24)는 각각 제1 내지 제4 어드레스패드(11~14)와 전기적으로 연결되어 각 어드레스패드(11~14)를 통해 입력된 어드레스신호를 버퍼링한다. 접지전압 패드(41)는 접지전압(VSS)을 입력받기 위한 패드이고, 전원전압 패드(42)는 전원전압(VDD)을 입력받기 위한 패드이다. 제1 내지 제3 배선그룹(33A~33C) 각각에는 데이터전송배선(31)과 전원배선(32)이 포함되어 있으며, 데이터전송배선(31)은 데이터를 전달하는 배선이고, 전원배선(32)은 접지전압(VSS), 전원전압(VDD) 및 내부전압(접지전압과 전원전압을 승압 또는 감압하여 내부에서 생성된 전압, 예를 들면 코어전압, 프리차지전압, 기판전압 및 셀전압이 있음)을 해당 장치에 전달하기 위한 배선이다. 이때, 전원배선(32)은 주전원배선(32A)과 더미전원배선(32B)으로 구분된다. 주전원배선(32A)은 접지전압(VSS), 전원전압(VDD) 및 내부전압을 해당 장치에 공급하기 위한 주된 배선을 의미하고, 더미전원배선(32B)은 주전원배선(32A)의 불량으로 인해 정상적으로 접지전압(VSS), 전원전압(VDD) 및 내부전압을 해당 장치에 공급하지 못할 경우를 대비한 여분의 전원배선이다. 마지막으로, 어드레스디코더(51)는 버퍼링된 어드레스신호를 디코딩하여 내부 어드레스신호를 생성하기 위한 회로로서, 디코딩을 위해 많은 논리회로가 밀집되기 때문에 큰 면적을 차지한다.As shown in FIG. 1, the semiconductor device includes first and second address pads 11 and 12 paired in the vertical direction Y, third and fourth address pads 13 and 14, The first and second buffers 21 and 22 disposed between the first and second address pads 11 and 12 and the third and fourth buffers 13 and 14 disposed between the third and fourth address pads 13 and 14, A first wiring group 33A extending in the vertical direction Y from the left side of the first address pad 11 and a second wiring group 33A extending in the vertical direction Y from the right side of the first address pad 11, The third wiring group 33C extending in the vertical direction Y from the left side of the second wiring group 33B and the third address pad 13 and the second wiring group 33B extending in the vertical direction And an address decoder 51 disposed between the ground voltage pad 41 and the power supply voltage pad 42 and the third and fourth buffers 23 and 24 paired with the first and second buffers Y and Y. [ Here, the vertical direction Y and the lateral direction X intersect each other. The first to fourth address pads 11 to 14 are pads for receiving an address signal and the first to fourth buffers 21 to 24 are electrically connected to the first to fourth address pads 11 to 14, And buffers an address signal input through each of the address pads 11-14. The ground voltage pad 41 is a pad for receiving a ground voltage VSS and the power supply voltage pad 42 is a pad for receiving a power supply voltage VDD. Each of the first to third wiring groups 33A to 33C includes a data transfer wiring 31 and a power supply wiring 32. The data transfer wiring 31 is a wiring for transferring data, (Including a voltage generated internally by stepping up or down the ground voltage and the power supply voltage, for example, the core voltage, the precharge voltage, the substrate voltage, and the cell voltage), the ground voltage VSS, the power supply voltage VDD, To the device. At this time, the power supply wiring 32 is divided into a main power supply wiring 32A and a dummy power supply wiring 32B. The main power source wiring 32A means a main wiring for supplying the ground voltage VSS, the power source voltage VDD and the internal voltage to the device, and the dummy power source wiring 32B is normally connected to the main power source wiring 32A (VSS), power supply voltage (VDD), and redundant power wiring in case the internal voltage can not be supplied to the device. Finally, the address decoder 51 is a circuit for decoding the buffered address signal to generate an internal address signal, and occupies a large area because many logic circuits are dense for decoding.

이와 같은 반도체 장치 내 각 어드레스패드(11~14) 사이에는 제1 내지 제4 버퍼(21~24)가 배치된다. 그리고, 제3 및 제4 버퍼(23, 24) 사이에는 많은 로직회로를 포함하는 어드레스디코더(51)가 배치된다. 이 경우, 제3 어드레스패드(13)와 제3 버퍼(23)와 어드레스디코더(51)와 제4 버퍼(24) 및 제4 어드레스패드(14)가 차지하는 상하방향(Y)으로의 길이는 382um이다. 이때, 제1 및 제3 어드레스패드(11, 13), 접지전압(VSS), 데이터전송배선(31) 및 전원배선(32)가 차지하는 좌우방향(X)으로의 길이는 382um이다.The first to fourth buffers 21 to 24 are disposed between the address pads 11 to 14 in the semiconductor device. Between the third and fourth buffers 23 and 24, an address decoder 51 including a lot of logic circuits is disposed. In this case, the length in the vertical direction (Y) occupied by the third address pad 13, the third buffer 23, the address decoder 51, the fourth buffer 24 and the fourth address pad 14 is 382 um to be. The length of each of the first and third address pads 11 and 13, the ground voltage VSS, the data transfer wiring 31 and the power supply wiring 32 in the left and right directions X is 382 um.

본 발명은 위와 같은 반도체 장치에서 어드레스패드(11~14), 버퍼(21~24) 및 어드레스디코더(51)를 재배치하여 상하방향(Y)의 길이를 감소시키는 것을 특징으로 한다.The present invention is characterized in that the length of the vertical direction Y is reduced by rearranging the address pads 11 to 14, the buffers 21 to 24, and the address decoder 51 in the above semiconductor device.

도 2는 본 발명의 일실시예에 따른 반도체 장치를 나타낸 평면도이다.2 is a plan view showing a semiconductor device according to an embodiment of the present invention.

도 2에 도시된 바와 같이, 반도체 장치는 상하방향(Y)으로 쌍을 이루는 제1 및 제2 어드레스패드(111, 112)와 다른 쌍을 이루는 제3 및 제4 어드레스패드(113, 114), 제1 어드레스패드(111)의 좌측면에 배치된 제1 버퍼(121), 제2 어드레스패드(112)의 좌측면에 배치된 제2 버퍼(122), 제3 어드레스패드(113)의 좌측면에 배치된 제3 버퍼(123), 제4 어드레스패드(114)의 좌측면에 배치된 제4 버퍼(124), 제1 버퍼(121)의 좌측에서 상하방향(Y)으로 연장된 제1 배선그룹(133A), 제1 어드레스패드(111)의 우측에서 상하방향(Y)으로 연장된 제2 배선그룹(133B), 제3 버퍼(123)의 좌측에서 상하방향(Y)으로 연장된 제3 배선그룹(133C), 제2 및 제3 배선그룹(133B, 133C) 사이에서 상하방향(Y)으로 쌍을 이루는 접지전압패드(141)와 전원전압패드(142), 제3 및 제4 버퍼(123, 124) 사이에 배치된 어드레스디코더(151)를 포함한다. 여기서, 상하방향(Y)과 좌우방향(X)는 서로 교차하는 방향이다. 제1 내지 제4 어드레스패드(111~114)는 어드레스신호를 입력받기 위한 패드이고, 제1 내지 제4 버퍼(121~124)는 각각 제1 내지 제4 어드레스패드(111~114)와 전기적으로 연결되어 각 어드레스패드(111~114)를 통해 입력된 어드레스신호를 버퍼링한다. 접지전압 패드(141)는 접지전압(VSS)을 입력받기 위한 패드이고, 전원전압 패드(142)는 전원전압(VDD)을 입력받기 위한 패드이다. 제1 배선그룹(133A)은 주전원배선(132A)과 데이터전송배선(131)을 포함하고, 제2 배선그룹(133B)은 주전원배선(132A)과 더미전원배선(132B)로 구성된 전원배선(132)과 데이터전송배선(131)을 포함하며, 제3 배선그룹(133C)은 주전원배선(132A)과 데이터전송배선(131)을 포함한다. 여기서, 주전원배선(32A)은 접지전압(VSS), 전원전압(VDD) 및 내부전압을 해당 장치에 공급하기 위한 주된 배선을 의미하고, 더미전원배선(32B)은 주전원배선(32A)의 불량으로 인해 정상적으로 접지전압(VSS), 전원전압(VDD) 및 내부전압을 해당 장치에 공급하지 못할 경우를 대비한 여분의 전원배선이다. 마지막으로, 어드레스디코더(51)는 버퍼링된 어드레스신호를 디코딩하여 내부 어드레스신호를 생성하기 위한 회로로서, 디코딩을 위해 많은 논리회로가 밀집되기 때문에 큰 면적을 차지한다.As shown in FIG. 2, the semiconductor device includes first and second address pads 111 and 112 paired in the vertical direction Y, third and fourth address pads 113 and 114, A first buffer 121 disposed on the left side of the first address pad 111, a second buffer 122 disposed on the left side of the second address pad 112, a second buffer 122 disposed on the left side of the third address pad 113, A fourth buffer 124 disposed on the left side of the fourth address pad 114, a second buffer 123 extending in the vertical direction Y from the left side of the first buffer 121, A second wiring group 133B extending in the vertical direction Y from the right side of the first address pad 111 and a third wiring group 133B extending in the vertical direction Y from the left side of the third buffer 123, The ground voltage pad 141 and the power supply voltage pad 142 that are paired in the vertical direction Y between the wiring group 133C and the second and third wiring groups 133B and 133C and the third and fourth buffer 123, and 124. The address decoder 15 1). Here, the vertical direction Y and the lateral direction X intersect each other. The first to fourth address pads 111 to 114 are pads for receiving an address signal and the first to fourth buffers 121 to 124 are electrically connected to the first to fourth address pads 111 to 114, And buffer the address signals inputted through the respective address pads 111 to 114. The ground voltage pad 141 is a pad for receiving the ground voltage VSS and the power supply voltage pad 142 is a pad for receiving the power voltage VDD. The first wiring group 133A includes the main power wiring 132A and the data transfer wiring 131 and the second wiring group 133B includes the power wiring 132 consisting of the main power wiring 132A and the dummy power wiring 132B And a data transfer wiring 131. The third wiring group 133C includes a main power source wiring 132A and a data transfer wiring 131. [ Here, the main power supply wiring 32A denotes a main wiring for supplying the ground voltage (VSS), the power supply voltage (VDD) and the internal voltage to the device, and the dummy power supply wiring 32B is a main power supply wiring 32A (VSS), the power supply voltage (VDD), and the redundant power wiring in case the internal voltage can not be supplied to the device. Finally, the address decoder 51 is a circuit for decoding the buffered address signal to generate an internal address signal, and occupies a large area because many logic circuits are dense for decoding.

이와 같은 본 발명의 일실시예에 따른 반도체 장치의 제1 내지 제4 버퍼(121~124) 각각은 대응하는 제1 내지 제4 어드레스패드(111~114)의 측면에 배치된다. 즉, 본 발명의 일실시예에 따른 반도체 장치는 제1 내지 제4 버퍼(121~124) 각각을 제1 내지 제4 어드레스패드(111~114)의 좌측면에 배치함으로써, 상하방향(Y)으로의 길이를 도 1의 반도체 장치 대비 감소시킨다. 도 1의 반도체 장치의 상하방향(Y) 길이가 382um인데 반해, 본 발명의 일실시예에 따른 반도체 장치의 상하방향(Y) 길이는 제1 및 제2 버퍼의 크기만큼 감소된 362um가 된다. 이때, 본 발명의 일실시예에 따른 반도체 장치는 좌우방향(X) 길이는 증가하지 않는다. 그 이유는 도 1의 제1 및 제3 배선그룹(33A, 33C) 내 더미전원배선(32B)을 제거하였기 때문이다. 공정 기술의 발달로 인해 전원배선의 불량 발생 확률은 매우 낮아졌다. 즉, 주전원배선(132A)만으로도 충분히 내부전압을 전달할 수 있다. 따라서, 본 발명의 일실시예와 같이 더미전원배선(132B)을 제거하여도 내부전압의 전달에는 어떠한 영향도 주지 못한다. 더욱이, 접지전압패드(141)의 좌측의 전원배선(132)에는 더미전원배선(132B)이 구비되어 있기 때문에, 주전원배선(132A)에 불량이 발생하여도 대체할 배선이 있기 때문에 안정적으로 내부전압을 공급할 수 있다.Each of the first to fourth buffers 121 to 124 of the semiconductor device according to an embodiment of the present invention is disposed on the side surfaces of the corresponding first to fourth address pads 111 to 114. That is, the semiconductor device according to the embodiment of the present invention includes the first to fourth buffers 121 to 124 on the left side of the first to fourth address pads 111 to 114, To the semiconductor device of FIG. (Y) length of the semiconductor device of FIG. 1 is 382 .mu.m, the vertical length (Y) of the semiconductor device according to an embodiment of the present invention is 362 .mu.m reduced by the sizes of the first and second buffers. At this time, the length of the semiconductor device according to the embodiment of the present invention does not increase in the lateral direction X. This is because the dummy power supply wiring 32B in the first and third wiring groups 33A and 33C in Fig. 1 is removed. Due to the development of process technology, the probability of failure of the power supply wiring has become very low. That is, the internal voltage can be sufficiently transmitted by only the main power supply wiring 132A. Therefore, even if the dummy power supply line 132B is removed as in the embodiment of the present invention, it has no effect on the transfer of the internal voltage. In addition, since the dummy power supply wiring 132B is provided in the power supply wiring 132 on the left side of the ground voltage pad 141, even if a failure occurs in the main power supply wiring 132A, Can be supplied.

전술한 내용들을 정리해보면, 본 발명의 일실시예에 따른 반도체 장치는 좌우방향(X)의 길이는 그대로 유지한 상태에서 상하방향(Y)의 길이를 감소시켜, 집적도를 향상시킨다. 이를 위해, 버퍼(121~124)를 어드레스패드(111~114)의 좌우측면에 배치하되, 버퍼(121~124)를 더미전원배선이 제거된 영역에 배치함으로서 좌우방향(X)의 길이증가를 방지한다.
In summary, the semiconductor device according to an embodiment of the present invention reduces the length of the vertical direction Y while maintaining the length of the lateral direction X, thereby improving the degree of integration. For this, the buffers 121 to 124 are disposed on the left and right sides of the address pads 111 to 114. By arranging the buffers 121 to 124 in the area where the dummy power supply wiring is removed, prevent.

111~114: 어드레스패드 121~124: 버퍼
131: 데이터전송배선 132: 전원배선
132A: 주전원배선 132B: 더미전원배선
141: 접지전압패드 142: 전원전압패드111 to 114: address pads 121 to 124: buffers
131: Data transmission wiring 132: Power supply wiring
132A: main power supply wiring 132B: dummy power supply wiring
141: ground voltage pad 142: power voltage pad

Claims (4)

제1 어드레스신호를 입력받기 위한 제1 패드;
상기 제1 패드의 제1 방향에 배치된 디코더; 및
상기 제1 패드의 상기 제1 방향과 교차하는 제2 방향에 배치되고, 상기 제1 패드를 통해 입력된 상기 제1 어드레스신호를 버퍼링하는 제1 버퍼
를 포함하고,
상기 디코더는 상기 제1 버퍼에 버퍼링된 상기 제1 어드레스신호를 디코딩하는 것을 특징으로 하는 반도체 장치.
A first pad for receiving a first address signal;
A decoder disposed in a first direction of the first pad; And
A first pad disposed in a second direction intersecting the first direction of the first pad and buffering the first address signal input through the first pad,
Lt; / RTI >
Wherein the decoder decodes the first address signal buffered in the first buffer.
[청구항 2은(는) 설정등록료 납부시 포기되었습니다.][Claim 2 is abandoned upon payment of the registration fee.] 제 1 항에 있어서,
상기 디코더의 상기 제1 방향에 배치되고, 제2 어드레스신호를 입력받기 위한 제2 패드; 및
상기 제2 패드의 상기 제2 방향에 배치되고, 상기 제2 패드를 통해 입력된 상기 제2 어드레스신호를 버퍼링하는 제2 버퍼
를 더 포함하고,
상기 디코더는 상기 제2 버퍼에 버퍼링된 상기 제2 어드레스신호를 디코딩하는 것을 특징으로 하는 반도체 장치.
The method according to claim 1,
A second pad disposed in the first direction of the decoder for receiving a second address signal; And
A second buffer disposed in the second direction of the second pad for buffering the second address signal input through the second pad,
Further comprising:
And the decoder decodes the second address signal buffered in the second buffer.
[청구항 3은(는) 설정등록료 납부시 포기되었습니다.][Claim 3 is abandoned upon payment of the registration fee.] 제 2 항에 있어서,
상기 제2 버퍼의 상기 제2 방향에 배치된 배선; 및
상기 배선의 상기 제2 방향에 배치된 전원전압패드
를 더 포함하는 반도체 장치.
3. The method of claim 2,
A wiring disposed in the second direction of the second buffer; And
A power supply voltage pad arranged in the second direction of the wiring,
Further comprising:
[청구항 4은(는) 설정등록료 납부시 포기되었습니다.][Claim 4 is abandoned upon payment of the registration fee.] 제 1 항에 있어서,
상기 제1 버퍼의 상기 제2 방향에 배치된 배선; 및
상기 배선의 상기 제2 방향에 배치된 접지전압 패드
를 더 포함하는 반도체 장치.
The method according to claim 1,
A wiring disposed in the second direction of the first buffer; And
A ground voltage pad arranged in the second direction of the wiring;
Further comprising:
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