KR101790861B1 - Copper-alloy barrier layers and capping layers for metallization in electronic devices - Google Patents

Abstract

In various embodiments, an electronic device such as a thin film transistor and / or a touch panel display includes a conductor layer and a conductor layer disposed over or under the conductor layer, the conductor layer comprising a metal selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, And a barrier and / or barrier layer comprising an alloy of one or more refractory metal elements selected from the group consisting of Ru, Rh, Ti, V, Cr and Ni.

Description

[0001] COPPER ALLOY BARRIER LAYERS AND CAPPING LAYERS FOR METALLIZATION IN ELECTRONIC DEVICES [0002] BACKGROUND OF THE INVENTION [0003]

<Related application>

This application claims the benefit and priority of U.S. Provisional Patent Application No. 61 / 831,865, filed June 6, 2013, the entire disclosure of which is incorporated herein by reference.

In various embodiments, the invention relates to metallization of electronic devices, such as flat panel displays and touch panel displays, and more particularly to capping and barrier layers for such metallization.

Flat panel displays are rapidly becoming ubiquitous in a variety of markets and are now commonly used in a variety of devices, televisions, computers, cell phones and other electronic devices. An example of a commonly used flat panel display is a thin film transistor (TFT) liquid crystal display (LCD), or a TFT-LCD. Typical TFT-LCDs each contain an array of TFTs that control the emission of light from the pixels or subpixels of the LCD. 1A is a cross-sectional view of a conventional TFT 100 as can be found in a TFT-LCD. As shown, the TFT 100 includes a gate electrode 105 formed on a glass substrate 110. The gate insulator 115 electrically isolates the gate electrode 105 from the overlying conductive structure. The active layer 120, typically composed of amorphous silicon, conducts charge between the source electrode 125 and the drain electrode 130 under the electrical control of the gate electrode 105, and the conducted charge is coupled to a pixel or sub- (Not shown). The source / drain insulator 132 electrically isolates the source electrode 125 from the drain electrode 130 and protectively seals the TFT 100. As shown, each of the gate electrode 105, the source electrode 125, and the drain electrode 130 typically includes a barrier metal layer 135 and a metal conductor layer 140 thereon. The barrier 135 provides good adhesion between the conductor 140 and underlying glass and / or silicon and reduces or prevents diffusion therebetween.

Over time, LCD panel sizes are increasing, TFT-based pixel sizes are decreasing, and the demand for conductors in TFT-LCD structures is increasing substantially. In order to increase the electrical signal propagation in TFT-LCDs by reducing the resistance in the conductors, current manufacturers utilize metals with low resistivity, such as copper (Cu), for the conductors 140 in the display. A metal such as molybdenum (Mo), titanium (Ti), or molybdenum titanium alloy (Mo-Ti) is utilized for the barrier 135 underlying the Cu conductor 140; These metals have one or more defects that limit the performance of the TFT-LCD and / or difficulties in the manufacturing method of the TFT-LCD. For example, some conventional barriers 135 have a relatively high resistivity, thus impairing the total conductivity of the electrodes. 1B, during etching of the electrode, e.g., the gate electrode 105, residues 145 or etch discontinuities (in one or both electrode materials) 150), for example, a stepped or non-linear profile (caused by a non-uniform etch rate of the two different electrode materials) can be generated.

Similarly, touch panel displays are becoming more common in electronic devices, which can even be utilized with TFT-LCDs. A typical touch panel display is arranged in rows and columns and includes an array of sensors that sense touch (or proximity) of the finger, for example, through capacitive coupling. Figure 2a illustrates a plurality of conductive column sensors 210 interconnected to form a column 220 as well as a plurality of conductive row sensors 210 interconnected to form a row 240 230 for a touch panel display. &Lt; RTI ID = 0.0 &gt; [0040] &lt; / RTI &gt; Sensors 210 and 230 are formed on substrate 250 to sense changes in the electrostatic coupling that represent "touch &quot;, and to apply such signals to a device (e.g., a computer or mobile computing device To other electronic components in the processor (e. G., &Lt; / RTI &gt; Sensors 210 and 230 may be formed of a transparent conductor, such as indium tin oxide (ITO), and substrate 250 may be glass or any other suitable rigid (and / or transparent) support material.

FIG. 2B is an enlarged perspective view of a point in the sensor array 200 where interconnected column sensors 210 intersect with interconnected row sensors 230. To avoid electrical shorts between column 220 and row 240 (see FIG. 2A), the interconnections between column sensors 210 are isolated from underlying or overlying row sensors 230. For example, as shown in FIG. 2B, an insulator layer 270 may be disposed between the column 220 of the column sensor 210 and a conductive interconnect (not shown) that electrically connects the row sensor 230 within the row 240 Or "bridge" 2C, the interconnect 280 is typically comprised of an Al conductive layer 290 and an overlying barrier or capping layer 295 typically comprised of Mo, Ti or Mo-Ti. The capping layer 295 helps prevent diffusion from the conductive layer 290 and prevents the conductive layer 290 from corroding during processing and product use. The capping layer 295 can also improve adhesion to the overlying layer. However, as described above for TFT-LCD, the metal conventionally used for the capping layer 295 metal has one or more defects that limit its performance, and there are difficulties in the manufacturing method. For example, the capping layer 295 has a relatively high resistivity, impairing the total conductivity of the interconnects 280 and degrading electrical performance. In addition, during etching of the interconnect 280, the residue 296 or etch discontinuity 297 (of either or both of the conductive layer 290 or the capping layer 295) For example, a stepped or non-linear profile (caused by a non-uniform etch rate of two different materials) can be generated.

In view of the foregoing, it would be desirable to provide a method of manufacturing a semiconductor device that provides superior adhesion to underlying substrates, prevents diffusion of the conductive metal into adjacent layers, prevents corrosion of the conductive metal, And barrier metal layers and / or capping metal layers for electronic devices such as TFT-LCD and touch panel displays that are etched uniformly.

In accordance with various embodiments of the present invention, electronic devices such as TFT-LCD and touch panel displays, and metallic interconnects and electrodes therein, are fabricated from a combination of Cu and one or more refractory metal elements such as tantalum (Ta), niobium Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr) or nickel (Ni), or a capping layer and / or a barrier layer essentially consisting of or consisting of an alloy of nickel (Ni). One or more refractory elements may be present in the alloy at a weight concentration of 1 to 50 percent. In an exemplary embodiment, the alloy barrier layer is formed directly on a substrate layer, such as a glass and / or silicon based layer, and includes a highly conductive metal such as Cu, Ag, Al, or Au Or a conductive layer consisting essentially of it is formed thereon to form various electrodes within the TFT structure. In another exemplary embodiment, a highly conductive metal, such as Cu, Ag, Al, and / or Au, is utilized as a conductive interconnect in a touch panel display and includes Cu and one or more refractory metal elements such as Ta, Nb, Mo The capping layer is capped with a protective capping layer comprising or essentially consisting of an alloy of W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr or Ni. The one or more refractory elements may be present in the alloy at a weight concentration of 1 to 50 percent (by weight percent).

Surprisingly, the presence of the refractory metal alloy element (s), even though the barrier layer and the capping layer are predominantly Cu, is advantageous when Cu is utilized with adjacent layers, such as underlying silicon layers, as well as Cu conductor layers, Lt; RTI ID = 0.0 &gt; barrier layer. &Lt; / RTI &gt; Although not wishing to be bound by any particular theory or mechanism for this phenomenon, it is believed that refractory metal alloying elements react with the atoms of the silicon layer to form silicide regions that occupy grain boundaries within the barrier or capping metal, (Or other neighboring layer) along the crystal grain boundaries, and this grain boundary would otherwise be a rapid diffusion path.

In various embodiments, the barrier layer and / or the capping layer comprises or consists essentially of Cu and (i) Ta and Cr, (ii) Ta and Ti, or (iii) an alloy of Nb and Cr. For example, the barrier and / or capping layer may comprise (i) 1 wt% to 12 wt% Ta (preferably about 5 wt% Ta) and 1 wt% to 5 wt% Cr 2 wt% Cr), (ii) 1 wt% to 12 wt% Ta (preferably about 5 wt% Ta) and 1 wt% to 5 wt% Ti (preferably about 2 wt% Ti ), Or (iii) 1 to 10 wt% Nb (preferably about 5 wt% Nb) and 1 wt% to 5 wt% Cr (preferably about 2 wt% Cr) . In addition, when utilized with a high conductivity conductor layer, such as Cu, to form electrodes and / or interconnects, the barrier and / or capping layer and conductor layer may be mixed with a desired etchant, such as water, Exhibit substantially equivalent etch rates in a mixture of PAN etch, i. E. Phosphoric acid, acetic acid and nitric acid, which can be heated. Thus, etching related residues and discontinuities are minimized or eliminated by using a barrier layer and / or a capping layer in accordance with a preferred embodiment of the present invention.

In one aspect, an embodiment of the present invention features a thin film transistor comprising or essentially consisting of a substrate and an electrode. The substrate may comprise or consist essentially of silicon and / or glass. The electrode comprises: (i) a metal oxide selected from the group consisting of Cu and a metal selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Ag, Al, or Au disposed on or above the barrier layer, and (ii) a barrier layer comprising, consisting essentially of, or consisting of an alloy of at least two or more refractory metal elements, Or consists essentially of, or consists essentially of, a conductor layer made of, or consisting of, it.

Embodiments of the present invention may include any one or more of the following in any of a variety of different combinations. The substrate comprises, consists essentially of, or consists of glass. The substrate may comprise, consist essentially of, or consist of silicon, for example amorphous silicon. The barrier layer may comprise, consist essentially of, or be made of an alloy of Cu, Ta and Cr. The barrier layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of approximately 2 wt% Ta, approximately 1 wt% Cr, and the remainder of Cu. The barrier layer may comprise, consist essentially of, or consist of 2 wt% Ta, 1 wt% Cr, and the balance Cu.

The barrier layer may comprise, consist essentially of, or consist of an alloy of Cu, Ta and Ti. The barrier layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Ti, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Ti, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Ti, and the balance Cu.

The barrier layer may comprise, consist essentially of, or consist of an alloy of Cu, Nb and Cr. The barrier layer may comprise, consist essentially of, or consist of 1wt% to 10wt% Nb, 1wt% to 5wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of approximately 5% by weight of Nb, approximately 2% by weight of Cr, and the balance of Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Nb, 2 wt% Cr, and the balance Cu.

The electrode comprises or consists essentially of (a) the exposed portion of the barrier layer, (b) the exposed portion of the conductor layer, and (c) the interface between the exposed portion of the barrier layer and the exposed portion of the conductor layer Or may comprise sidewalls thereof. The sidewalls of the electrodes may be substantially or even totally free of the discontinuities in spite of the interface. The substrate may have substantially or even completely no Cu diffusion from the barrier layer. The barrier layer may comprise, consist essentially of, or consist of a plurality of crystal grains separated by grain boundaries. At least one of the grain boundaries may include fine particles therein. The particulate may comprise, consist essentially of, or consist of a reaction product of at least one of silicon and a refractory metal element.

In another aspect, an embodiment of the present invention features a method of forming an electrode of a thin film transistor. Thereby providing a substrate. The substrate may comprise, consist essentially of, or consist of silicon and / or glass. A barrier layer is deposited over the substrate and the conductor layer is deposited over the barrier layer. Wherein the barrier layer comprises an alloy of at least one refractory metal element selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Or is made essentially of, the same. The conductor layer comprises, consists essentially of, or consists of Cu, Ag, Al and / or Au. A mask layer is formed on the barrier layer, and the mask layer is patterned to reveal a part of the conductor layer. The remaining portion of the mask layer may at least partially define the shape of the electrode. An etchant is applied to remove portions of the conductor layer and the barrier layer that are not masked by the patterned mask layer to form the sidewalls of the electrode. The sidewall may comprise (or consist essentially of) an interface between (a) the exposed portion of the barrier layer, (b) the exposed portion of the conductor layer, and , Or the like. The sidewalls are substantially or even totally free of discontinuities in spite of the interface.

Embodiments of the present invention may include any one or more of the following in any of a variety of different combinations. The mask layer may comprise, consist essentially of, or consist of photoresist. The etchant can comprise, consist essentially of, or consist of a mixture of phosphoric acid, acetic acid, nitric acid and water. The etchant may comprise, consist essentially of, or consist of 50 to 60 wt.% Phosphoric acid, 15 to 25 wt.% Acetic acid, 3 to 5 wt.% Nitric acid, and the balance water. The etchant can comprise, consist essentially of, or consist of 50% by weight of phosphoric acid, 25% by weight of acetic acid, 3% by weight of nitric acid, and a residual amount of water. The remaining portion of the patterned mask layer may be removed, for example, after applying the etchant. The barrier layer may comprise, consist essentially of, or consist of a plurality of crystal grains separated by grain boundaries. The substrate may comprise, consist essentially of, or consist of silicon. The electrode can be annealed at a temperature (e.g., 200 캜 to 700 캜, or 300 캜 to 500 캜) sufficient to form fine particles in at least one of the grain boundaries. The particulate may comprise, consist essentially of, or consist of silicon and at least one reaction product of a refractory metal element (e.g., a refractory metal silicide). The substrate may comprise, consist essentially of, or consist of glass or amorphous silicon.

The barrier layer may comprise, consist essentially of, or be made of an alloy of Cu, Ta and Cr. The barrier layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of approximately 2 wt% Ta, approximately 1 wt% Cr, and the remainder of Cu. The barrier layer may comprise, consist essentially of, or consist of 2 wt% Ta, 1 wt% Cr, and the balance Cu.

The barrier layer may comprise, consist essentially of, or consist of an alloy of Cu, Ta and Ti. The barrier layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Ti, and the balance of Cu. The barrier layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Ti, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Ti, and the balance Cu.

The barrier layer may comprise, consist essentially of, or consist of an alloy of Cu, Nb and Cr. The barrier layer may comprise, consist essentially of, or consist of 1wt% to 10wt% Nb, 1wt% to 5wt% Cr, and the balance Cu. The barrier layer may comprise, consist essentially of, or consist of approximately 5% by weight of Nb, approximately 2% by weight of Cr, and the balance of Cu. The barrier layer may comprise, consist essentially of, or consist of 5 wt% Nb, 2 wt% Cr, and the balance Cu.

In yet another aspect, an embodiment of the present invention features a touch panel display comprising, or essentially consisting of a substrate, a plurality of conductive touch panel row sensors, a plurality of conductive touch panel column sensors, and interconnects. The row sensors are arranged on the substrate and arranged in lines extending along the first direction. The column sensors are arranged on the substrate and extend along the second direction and are arranged in lines intersecting the lines of the row sensor. The interconnects are arranged at the intersection between the line of the row sensor and the line of the column sensor, and the interconnections electrically connect the two column sensors or the two row sensors. The interconnections may be formed of a conductive layer comprising (i) a conductor layer comprising, consisting essentially of, or consisting of Cu, Ag, Al and / or Au, and (ii) Or consists essentially of an alloy of one or more refractory metal elements selected from the list consisting of Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Cr and Ni. Or consist essentially of, or consist of a capping layer formed thereon.

Embodiments of the present invention may include any one or more of the following in any of a variety of different combinations. The interconnections may extend above or below the row sensor to electrically couple the two column sensors. An insulating layer may be disposed between the interconnecting portion and the row sensor, thereby electrically insulating the interconnecting portion and the row sensor. The interconnections may extend above or below the column sensor to electrically couple the two row sensors. An insulating layer can be disposed between the interconnecting portion and the column sensor, so that the interconnecting portion and the column sensor can be electrically isolated. The substrate may comprise, consist essentially of, or be made of an insulating material, for example glass. The row sensor and / or the column sensor may comprise, consist essentially of, or consist of a substantially transparent conductive material, for example, indium tin oxide.

The capping layer may comprise, consist essentially of, or be made of an alloy of Cu, Ta and Cr. The capping layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Cr, and the balance of Cu. The capping layer may comprise, consist essentially of, or consist of approximately 5 wt% Ta, approximately 2 wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of approximately 2 wt% Ta, approximately 1 wt% Cr, and the remainder of Cu. The capping layer may comprise, consist essentially of, or consist of 2 wt% Ta, 1 wt% Cr, and the balance Cu.

The capping layer can comprise, consist essentially of, or consist of an alloy of Cu, Ta and Ti. The capping layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Ti, and the balance of Cu. The capping layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Ti, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Ti, and the remainder of Cu.

The capping layer may comprise, consist essentially of, or consist of an alloy of Cu, Nb and Cr. The capping layer may comprise, consist essentially of, or consist of 1wt% to 10wt% Nb, 1wt% to 5wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of approximately 5 wt% Nb, approximately 2 wt% Cr, and the remainder of Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Nb, 2 wt% Cr, and the balance Cu.

The interconnections may include (a) an exposed portion of the capping layer, (b) an exposed portion of the conductor layer, and (c) an interface between the exposed portion of the capping layer and the exposed portion of the conductor layer, Or may comprise sidewalls thereof. The sidewalls of the electrodes may be substantially or even totally free of the discontinuities in spite of the interface. The capping layer may comprise, consist essentially of, or consist of a plurality of crystal grains separated by grain boundaries. At least one of the grain boundaries may include fine particles therein. The particulate may comprise, consist essentially of, or consist of at least one agglomeration of the refractory metal element (e.g., an aggregation of atoms aggregated through diffusion). One or more of the grain boundaries may contain refractory metal element (s) in a concentration greater than the bulk volume of the particles of the capping layer.

In another aspect, an embodiment of the present invention features a method of forming an interconnecting portion of a touch panel display. There is provided a structure comprising, or essentially consisting of, a substrate, a plurality of conductive touch panel row sensors, and a plurality of conductive touch panel column sensors. The row sensors are arranged on the substrate and arranged in lines extending along the first direction. A column sensor is disposed on the substrate, and extends along the second direction and arranged in a line intersecting the line of the row sensor. An insulator layer is deposited at least at the intersection between the line of the row sensor and the line of the column sensor. A conductor layer is deposited over the insulator layer and the capping layer is deposited over the conductor layer or on the conductor. The conductor layer comprises, consists essentially of, or consists of Cu, Ag, Al and / or Au. Wherein the capping layer comprises an alloy of at least one refractory metal element selected from the group consisting of Ta, Nb, Mo, W, Zr, Hf, Re, Os, Ru, Rh, Ti, V, Or is made essentially of, the same. A mask layer is formed over the capping layer. The mask layer is patterned to expose a portion of the capping layer. The remaining portion of the mask layer may at least partially define the shape of the interconnect. An etchant is applied to remove portions of the capping layer and portions of the conductor layer that are not masked by the patterned mask layer to form the sidewalls of the interconnects. The sidewall may comprise or consist essentially of (a) an exposed portion of the capping layer, (b) an exposed portion of the conductor layer, and (c) an interface between the exposed portion of the capping layer and the exposed portion of the conductor layer Or made of it. The sidewalls are substantially or even totally free of discontinuities in spite of the interface.

Embodiments of the present invention may include any one or more of the following in any of various combinations. The mask layer may comprise, consist essentially of, or consist of photoresist. The etchant can comprise, consist essentially of, or consist of a mixture of phosphoric acid, acetic acid, nitric acid and water. The etchant may comprise, consist essentially of, or consist of 50 to 60 wt.% Phosphoric acid, 15 to 25 wt.% Acetic acid, 3 to 5 wt.% Nitric acid, and the balance water. The etchant can comprise, consist essentially of, or consist of 50% by weight of phosphoric acid, 25% by weight of acetic acid, 3% by weight of nitric acid, and a residual amount of water. Any residual portion of the patterned mask layer can be removed. The capping layer may comprise, consist essentially of, or consist of a plurality of crystal grains separated by grain boundaries. The interconnect may be annealed at a temperature sufficient (e.g., 200 캜 to 700 캜, or 300 캜 to 500 캜) to form fine grains within at least one of the grain boundaries. The fine particles may comprise, consist essentially of, or consist of at least one of the refractory metal elements. The substrate may comprise, consist essentially of, or be made of an insulating material, for example glass. The row sensor and the column sensor may comprise, consist essentially of, or be made of a substantially transparent conductive material, for example indium tin oxide.

The capping layer may comprise, consist essentially of, or be made of an alloy of Cu, Ta and Cr. The capping layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Cr, and the balance of Cu. The capping layer may comprise, consist essentially of, or consist of approximately 5 wt% Ta, approximately 2 wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of approximately 2 wt% Ta, approximately 1 wt% Cr, and the remainder of Cu. The capping layer may comprise, consist essentially of, or consist of 2 wt% Ta, 1 wt% Cr, and the balance Cu.

The capping layer can comprise, consist essentially of, or consist of an alloy of Cu, Ta and Ti. The capping layer may comprise, consist essentially of, or consist of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Ti, and the balance of Cu. The capping layer may comprise, consist essentially of, or consist of about 5 wt% Ta, about 2 wt% Ti, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Ta, 2 wt% Ti, and the remainder of Cu.

The capping layer may comprise, consist essentially of, or consist of an alloy of Cu, Nb and Cr. The capping layer may comprise, consist essentially of, or consist of 1wt% to 10wt% Nb, 1wt% to 5wt% Cr, and the balance Cu. The capping layer may comprise, consist essentially of, or consist of approximately 5 wt% Nb, approximately 2 wt% Cr, and the remainder of Cu. The capping layer may comprise, consist essentially of, or consist of 5 wt% Nb, 2 wt% Cr, and the balance Cu.

These and other objects, together with advantages and features of the invention disclosed herein will become more apparent from the following description, the accompanying drawings, and the appended claims. Additionally, it is to be understood that the features of the various embodiments described herein are not mutually exclusive, and may exist in various combinations and permutations. As used herein, the terms "approximately" and "substantially" mean +/- 10%, and in some embodiments, +/- 5%. The term " consisting essentially of "means excluding other materials contributing to the function unless otherwise defined herein. Nonetheless, these other materials can be present in small amounts collectively or individually. For example, a structure consisting essentially of a plurality of metals will generally only include these metals and only unintentional impurities that can be detected through chemical analysis but do not contribute to function (which may be metal or non-metal) . As used herein, "consisting essentially of at least one metal" refers to a metal that is not a metal and a nonmetal element or chemical species such as a compound between oxygen or nitrogen (e.g., a metal nitride or metal oxide) Refers to a mixture of the above metals; These nonmetallic elements or chemical species can be present in trace amounts, for example collectively or individually as impurities. As used herein, the terms "column" and "row" refer to components arranged in different directions (which may cross), and this is optional unless otherwise stated; That is, the arrangement of components may be low or column regardless of their orientation in space or within the device. As used herein, a "substrate" or "underlying layer" refers to a substrate (e.g., a semiconductor substrate such as silicon, GaAs, GaN, SiC, sapphire, or InP, Refers to, for example, a platform comprised of or consisting essentially of glass), or refers to one or more additional layers themselves disposed thereon, with the support member having or without one or more additional layers disposed thereon .

In the drawings, like reference numbers generally refer to the same parts throughout the different views. Furthermore, the drawings are not necessarily drawn to scale, emphasis instead being placed upon generally illustrating the principles of the invention. In the following description, various embodiments of the present invention will be described with reference to the following drawings.
1A is a schematic cross-sectional view of a thin film transistor for a liquid crystal display;
Figure 1b is a schematic cross-section of an etched conventional TFT electrode;
2A is a schematic plan view of a sensor array of a touch panel display;
Figure 2b is an enlarged perspective view of a portion of the sensor array of Figure 2a;
Figure 2c is a schematic cross-section of the sensor array portion of Figure 2b;
2d is a schematic cross-section along a plane perpendicular to that of FIG. 2c of the sensor array portion of FIG. 2b showing the etched conventional interconnects; FIG.
Figures 3 and 4 are schematic cross-sectional views of TFT electrodes during fabrication according to various embodiments of the present invention;
Figures 5 and 6 are schematic cross-sections of interconnects for a touch panel display according to various embodiments of the present invention;
FIGS. 7A and 7B are Auger spectrum graphs of interdiffusion of Cu and Si in the absence of a diffusion barrier between Cu and Si; FIG.
8A and 8B are Aug spectrum spectra of interdiffusion of Cu and Si between a Si layer and a Cu alloy capping layer or barrier layer, according to various embodiments of the present invention;
9A-9C illustrate the surface (FIG. 9A) of an unaltered Cu alloy capping layer or barrier layer (FIG. 9A), the surface of a Cu alloy capping layer or barrier layer after annealing at 300 DEG C 9b) and the surface of the Cu alloy capping layer or barrier layer after annealing at 500 占 폚 (Fig. 9c); Fig.
10A and 10B are a planar photograph (FIG. 10A) taken through a scanning electron microscope of an annealed Cu alloy capping layer or barrier layer on a Si phase (FIG. 10A) and an annealed Cu alloy capping layer or barrier (FIG. 10B) taken through a transmission electron microscope of the layer;
Figure 11 shows the corrosion levels after environmental corrosion testing of samples of pure Mo, pure Cu, CuTaCr alloy, and CuNbCr alloy, according to various embodiments of the present invention.

Figure 3 illustrates the initial stages of the fabrication of a TFT gate electrode in accordance with an embodiment of the present invention. The barrier layer 300 is deposited on the substrate 310 (e.g., a glass or silicon substrate) by, for example, sputtering or other physical deposition methods. The conductor layer 320 is then deposited on the barrier layer 300, for example, by sputtering or other physical deposition methods. Typically, the thickness of the barrier layer 300 will be between about 5% and about 25% (e.g., about 10%) of the thickness of the conductor layer 320. For example, the thickness of the barrier layer 300 may be approximately 50 nm, and the thickness of the conductor layer 320 may be approximately 500 nm. A mask layer 330 (e.g., photoresist) is formed over the conductor layer 320 and patterned by conventional photolithography.

4, the portion of the conductor layer 320 that is not covered by the mask layer 330 and the portion of the barrier layer 300 are then preferably etched in a single step wet etch to form the gate electrode 400 ). The metal layer may be etched at substantially the same rate utilizing a wet etchant (e.g., a PAN etch) to provide a substantially smooth and / or linear, interface 420 between the conductor layer 320 and the barrier layer 300, To produce side walls 410 that are substantially free of any discontinuities (e.g., stepped or non-linear profiles). The wet etchant may comprise, for example, a PAN etchant comprising or consisting essentially of 50 to 60 wt% phosphoric acid, 15 to 25 wt% acetic acid, 3 to 5 wt% nitric acid, and the remainder of deionized water, It can be done essentially. Some specific examples are provided in the following table. In a preferred embodiment, the wet etchant comprises or consists essentially of 50 wt% phosphoric acid, 25 wt% acetic acid, 3 wt% nitric acid, and the remaining amount (22 wt%) of deionized water.

After etching, the substrate 310 (as well as the electrode 400) preferably has substantially no etch residues of one or both of the conductor layer 320 and the barrier layer 300 in a region proximate to the gate electrode 400 I do not have. According to various embodiments of the present invention, the wet etch process is performed at room temperature. A wet etchant may be sprayed onto the substrate 310, or the substrate 310 may be partially or completely immersed in the wet etchant. The wet etch process may be performed as a batch (i.e., multiple substrate) process or as a single substrate process. In a preferred embodiment, the post etched sidewall 410 forms an angle 430 of approximately 50 [deg.] To approximately 70 [deg.], E.g., approximately 60 [deg.] With the underlying substrate 310 surface. After etching, the mask layer 330 may be removed by exposure to conventional means, such as acetone, a commercial photoresist stripping agent, and / or an oxygen plasma.

Figure 5 illustrates the initial steps of manufacturing a touch panel sensor interconnect according to an embodiment of the present invention. As shown, the conductive layer 500 may be patterned by a sensor 510 (e. G., A transparent conductor, a transparent conductor, etc.) on a substrate 520 (e. G., A glass or silicon substrate) by, for example, sputtering or other physical deposition method. Such as a row or column sensor, which may be composed of ITO, for example). The capping layer 530 is then deposited on the conductive layer 500, for example, by sputtering or other physical deposition method. Typically, the thickness of the capping layer 530 will be about 5% to about 25% (e.g., about 10%) of the thickness of the conductive layer 500. For example, the thickness of the capping layer 530 may be approximately 50 nm, and the thickness of the conductive layer 500 may be approximately 500 nm. A mask layer 540 (e.g., photoresist) may be formed over the capping layer 530 and patterned by conventional photolithography.

6, the capping layer 530 and the portion of the conductive layer 500 that are not covered by the masking layer 540 are then etched in a single step wet etch process, . The metal layer is etched at substantially the same rate utilizing a wet etchant (e.g., a PAN etch) to form a substantially smooth and / or linear shape, and the interface 620 between the capping layer 530 and the conductive layer 500, To produce side walls 610 that are substantially free of any discontinuities (e.g., stepped or non-linear profiles). The wet etchant may comprise, for example, a PAN etchant comprising or consisting essentially of 50 to 60 wt% phosphoric acid, 15 to 25 wt% acetic acid, 3 to 5 wt% nitric acid, and the remainder of deionized water, It can be done essentially. In a preferred embodiment, the wet etchant comprises or consists essentially of 50 wt% phosphoric acid, 25 wt% acetic acid, 3 wt% nitric acid, and the remaining amount (22 wt%) of deionized water.

After etching, the substrate 520 and the electrode 510 (as well as the interconnection 600) are preferably connected to one or both of the capping layer 530 and the conductive layer 500, Substantially free of etch residues. According to various embodiments of the present invention, the wet etch process is performed at room temperature. The wet etchant may be sprayed onto the substrate 520, or the substrate 520 may be partially or completely immersed in the wet etchant. The wet etch process may be performed as a batch (i.e., multiple substrate) process or as a single substrate process. In a preferred embodiment, the post etched side wall 610 forms an angle 630 of approximately 50 [deg.] To approximately 70 [deg.], E.g., approximately 60 [deg.] With the underlying surface of the substrate 520. [ After etching, the mask layer 540 may be removed by exposure to conventional means, such as acetone, a commercial photoresist stripping agent, and / or an oxygen plasma.

The barrier layer 300 and the capping layer 530 according to various embodiments of the present invention also serve as effective diffusion barriers for metal layers comprising, for example, Cu, Ag, Al, or Au, or consisting essentially of Au . Specifically, the alloy element (s) in the barrier layer 300 and / or the capping layer 530 may be heated even at elevated temperatures (e.g., up to about 200 캜, up to about 350 캜, up to about 500 캜, (E. G., Cu) to the underlying silicon substrate or neighboring layer even after, for example, a maximum of 2 hours of exposure. Figures 7a and 7b show a Cu / silicon interface (i.e., a barrier layer between Cu and silicon, as measured by Auger electron microscopy (AES) after annealing at 200 ° C to 500 ° C, as manufactured (without annealing) And the concentration of Cu and silicon across the substrate. As shown, the co-diffusion of Cu and silicon occurs at a temperature as low as (or even lower) than 200 ° C, and the interface is significantly diffused after annealing at 500 ° C. In addition, the Cu layer exhibits poor adhesion to silicon in the absence of a barrier layer between Cu and silicon.

8A and 8B illustrate the relationship between silicon and a barrier layer 300 or capping layer 530 comprising or consisting essentially of CuTaCr, as measured by AES after annealing and at 200 DEG C to 500 DEG C, And the concentration of Cu and silicon across the interface. In the illustrated embodiment, barrier layer 300 or capping layer 530 is comprised of 2 wt% Ta, 1 wt% Cr, and the remainder of Cu. (In another embodiment exhibiting similar behavior, barrier layer 300 or capping layer 530 comprises or consists essentially of 5 wt% Ta, 2 wt% Cr, and the balance Cu). In contrast to the results shown in Figures 7a and 7b, there is negligible diffusion of Cu or silicon across the interface, even after annealing for two hours at 500 ° C. Figures 9a-9c illustrate that the barrier layer 300 or capping layer 300 (Figure 9a), as deposited (Figure 9a), after annealing at 300 ° C for 1 hour (Figure 9b), and after annealing (SEM) photograph of the surface of the substrate 530. As shown, the particle structure and size of the barrier layer 300 or the capping layer 530 show no perceptible change and do not show any change in the formation of different phases (e. G., On copper silicide) There is no evidence. This result was confirmed by x-ray diffraction (XRD) of the annealed structure, where no silicide phase was detected after annealing at 500 DEG C for 2 hours. In contrast, the copper silicide phase is clearly apparent in SEM and XRD performed on a sample of a pure Cu layer on Si annealed at 500 &lt; 0 &gt; C for 2 hours.

10A and 10B illustrate SEM and transmission of barrier layer 300 or capping layer 530, respectively, placed in contact with silicon (e.g., silicon substrate and / or silicon top layer) and annealed at 350 & Electron microscope (TEM) images. The precipitate 1000 is visible in the barrier layer 300 or in the Cu grain boundary 1010 of the capping layer 530. In various embodiments, the precipitate comprises or consists essentially of at least one silicide of the refractory metal alloying elements of the barrier layer 300 or the capping layer 530, which precipitate diffuses the Cu diffusion along the grain boundaries into the neighboring silicon Reducing or substantially eliminating it.

Similarly, in various embodiments of the present invention, the refractory metal dopants of barrier layer 300 and / or capping layer 530 may be separated relative to the Cu grain boundaries to provide beneficial effects without reaction with silicon to form silicide. . For example, the Cu grain boundaries are filled with a refractory metal dopant and can be partially or substantially completely "blocked" with it to delay or substantially prevent oxygen diffusion along the Cu grain boundaries. In this manner, corrosion of the barrier layer 300, the capping layer 530, and / or the conductive layer in contact therewith is reduced or substantially prevented. Thus, in various embodiments of the present invention, the barrier layer 300 or the capping layer 530 may comprise or consist essentially of a polycrystalline Cu matrix doped with one or more refractory metal elements, wherein the doped Cu The grain boundaries of the layer between the particles contain a concentration of the refractory metal dopant (s) that is higher than the concentration in the particle itself. For example, the refractory metal concentration in the grain boundaries may be 5, 10, or even 100 times greater than the refractory metal concentration in the grain.

Figure 11 shows images of four different metal samples after environmental corrosion for 260 hours at 60 &lt; 0 &gt; C humidity and 80% humidity. As shown, samples of pure Cu and pure Mo experienced much more severe corrosion than those experienced with the Cu alloy samples according to embodiments of the present invention. The two types of Cu alloy samples were: (1) Cu with 10 wt% Ta and 2 wt% Cr (expressed as CuTaCr in Fig. 11), and (2) with 5 wt% Nb and 2 wt% Cr Cu (labeled CuNbCr in Fig. 11). The following table provides data relating to the amount of exposed surface area eroded during environmental erosion for each of the samples. As shown, a Cu alloy sample according to embodiments of the present invention underwent much less corrosion than pure Cu and Mo samples, indicating that this alloy is more beneficial than conventional Mo diffusion barrier and capping layers, as well as pure Cu.

Barrier layer 300 or capping layer 530 may have a resistivity of less than 10 micro ohms - even after annealing at low resistivity, e.g., up to 500 占 폚, up to 600 占 폚, or even higher, in a preferred embodiment of the present invention. cm, or even less than 5 micro ohm-cm. Moreover, in a preferred embodiment, barrier layer 300 or capping layer 530 exhibits good adhesion to glass, as measured, for example, by ASTM standard tape testing. Embodiments of the present invention also utilize materials that are highly conductive (e.g., Cu, Ag, Al, and / or Au) to form all or part of a conductor or electrode and have a barrier layer 300 underneath , And an electronic device (or portion thereof) having a capping layer 530 thereon.

The terms and expressions used herein are used as terms and expressions of the present invention rather than as limitations, and the use of such terms and expressions are not intended to exclude any equivalents of the features shown or described or portions thereof. It will also be apparent to those of ordinary skill in the art that, in describing certain embodiments of the invention described herein, other embodiments, including the concepts disclosed herein, may be used without departing from the spirit and scope of the invention. Accordingly, the described embodiments are to be considered in all respects as illustrative and not restrictive.

Claims (79)

Board;
(i) a plurality of conductive touch panel row sensors arranged in a line extending along a first direction and (ii) disposed on the substrate;
(i) a plurality of conductive touch panel column sensors extending along a second direction and arranged in a line intersecting the lines of the row sensors, (ii) disposed on the substrate; And
(i) at the intersection between the line of the row sensor and the line of the column sensor, and (ii) the two column sensors or the two row sensors,
A touch panel display,
Here,
(i) a conductor layer containing at least one of Cu, Ag, Al or Au, and
(ii) an alloy of at least one refractory metal element selected from the list consisting of Cu, Ta, Nb, Zr, Hf, Re, Os, Ru, Rh, Ti, Capping layer
/ RTI &gt;
(i) the capping layer comprises a plurality of crystal grains separated by grain boundaries, (ii) at least one of the grain boundaries comprises fine grains therein, (iii) the fine grains comprise at least one agglomeration of refractory metal elements, And a touch panel display. 2. The method of claim 1, wherein the interconnections extend above or below the row sensor to electrically couple the two column sensors, and an insulating layer disposed between the interconnect and the row sensor to electrically isolate the interconnect and the row sensor Further included touch panel display. 2. The column sensor of claim 1, wherein the interconnections extend above or below the column sensor to electrically couple the two row sensors, and an insulating layer disposed between the interconnect and the column sensor for electrically insulating the interconnect and column sensors Further included touch panel display. The touch panel display of claim 1, wherein the substrate comprises an insulating material. The touch panel display of claim 1, wherein the substrate comprises glass. The touch panel display of claim 1, wherein the row sensor and the column sensor comprise a transparent conductive material. The touch panel display of claim 1, wherein the row sensor and the column sensor comprise indium tin oxide. The touch panel display of claim 1, wherein the capping layer comprises an alloy of Cu, Ta, and Cr. 9. The touch panel display of claim 8, wherein the capping layer consists essentially of from 1 wt% to 12 wt% Ta, from 1 wt% to 5 wt% Cr, and a balance of Cu. The touch panel display of claim 8, wherein the capping layer consists essentially of 5 wt% Ta, 2 wt% Cr, and the balance Cu. The touch panel display of claim 8, wherein the capping layer consists essentially of 2 wt% Ta, 1 wt% Cr, and the balance Cu. The touch panel display of claim 1, wherein the capping layer comprises an alloy of Cu, Ta, and Ti. 13. The touch panel display of claim 12, wherein the capping layer consists essentially of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Ti, and the balance Cu. 13. The touch panel display of claim 12, wherein the capping layer consists essentially of 5 wt% Ta, 2 wt% Ti, and the balance Cu. The touch panel display of claim 1, wherein the capping layer comprises an alloy of Cu, Nb and Cr. 16. The touch panel display of claim 15, wherein the capping layer consists essentially of 1wt% to 10wt% Nb, 1wt% to 5wt% Cr, and the balance Cu. 16. The touch panel display of claim 15, wherein the capping layer consists essentially of 5 wt% Nb, 2 wt% Cr, and the balance Cu. 2. The method of claim 1, wherein: (i) the interconnection is between an exposed portion of the capping layer, (b) an exposed portion of the conductor layer, and (c) And (ii) the sidewalls of the electrodes do not have a discontinuity despite the interface. delete (i) a substrate, (ii) a plurality of conductive touch panel row sensors arranged in a line extending along a first direction, (b) a conductive touch panel row sensor disposed on the substrate, and (iii) (B) providing a structure comprising a plurality of conductive touch panel column sensors disposed on a substrate, the array being arranged in a line intersecting a line of the row sensor;
Depositing an insulator layer at least at the intersection between the line of the row sensor and the line of the column sensor;
Depositing a conductor layer comprising at least one of Cu, Ag, Al or Au on the insulator layer;
Depositing on the conductor layer a capping layer comprising Cu and an alloy of one or more refractory metal elements selected from the group consisting of Ta, Nb, Zr, Hf, Re, Os, Ru, Rh, Ti, V and Cr;
Forming a mask layer over the capping layer;
Patterning the mask layer to expose a portion of the capping layer and at least partially defining the shape of the interconnects with the remaining portion of the mask layer; And
The etchant is then applied to remove portions of the capping layer and portions of the conductor layer that are not masked by the patterned mask layer,
(i) an exposed portion of the capping layer, (ii) an exposed portion of the conductor layer, and (iii) an interface between the exposed portion of the capping layer and the exposed portion of the conductor layer,
Having no discontinuity in spite of the interface
Forming a side wall of the interconnecting portion
A method of forming interconnections of a touch panel display comprising:
(i) the capping layer comprises a plurality of crystal grains separated by grain boundaries, (ii) at least one of the grain boundaries comprises fine grains therein, (iii) the fine grains comprise at least one agglomeration of refractory metal elements, Wherein the method comprises the steps of: 21. The method of claim 20, wherein the mask layer comprises a photoresist. 21. The method of claim 20, wherein the etchant comprises a mixture of phosphoric acid, acetic acid, nitric acid, and water. 21. The touch panel display of claim 20, wherein the etchant consists essentially of 50 to 60 wt.% Phosphoric acid, 15 to 25 wt.% Acetic acid, 3 to 5 wt.% Nitric acid, / RTI &gt; 21. The method of claim 20, wherein the etchant consists essentially of 50 wt.% Phosphoric acid, 25 wt.% Acetic acid, 3 wt.% Nitric acid, and the balance water. 21. The method of claim 20, further comprising removing a remaining portion of the patterned mask layer. 21. The method of claim 20, wherein the capping layer comprises a plurality of crystal grains separated by grain boundaries. 27. The method of claim 26, further comprising annealing the interconnect at a temperature sufficient to form microparticles in at least one of the grain boundaries, wherein the microparticles comprise at least one agglomerate of refractory metal elements To form interconnections. 21. The method of claim 20, wherein the substrate comprises an insulating material. 21. The method of claim 20, wherein the substrate comprises glass. 21. The method of claim 20, wherein the row sensor and the column sensor comprise a transparent conductive material. 21. The method of claim 20, wherein the row sensor and the column sensor comprise indium tin oxide. 21. The method of claim 20, wherein the capping layer comprises an alloy of Cu, Ta and Cr. 33. The method of claim 32, wherein the capping layer consists essentially of 1 wt% to 12 wt% Ta, 1 wt% to 5 wt% Cr, and the balance Cu. 36. The method of claim 32, wherein the capping layer consists essentially of 5 wt% Ta, 2 wt% Cr, and the balance Cu. 33. The method of claim 32, wherein the capping layer consists essentially of 2 wt% Ta, 1 wt% Cr, and the balance Cu. 21. The method of claim 20, wherein the capping layer comprises an alloy of Cu, Ta, and Ti. 37. The method of claim 36, wherein the capping layer consists essentially of from 1 wt% to 12 wt% Ta, from 1 wt% to 5 wt% Ti, and a balance of Cu. 37. The method of claim 36, wherein the capping layer consists essentially of 5 wt% Ta, 2 wt% Ti, and the balance Cu. 21. The method of claim 20, wherein the capping layer comprises an alloy of Cu, Nb and Cr. 40. The method of claim 39, wherein the capping layer consists essentially of from 1 wt% to 10 wt% Nb, from 1 wt% to 5 wt% Cr, and a balance of Cu. 40. The method of claim 39, wherein the capping layer consists essentially of 5 wt% Nb, 2 wt% Cr, and the balance Cu. The touch panel display of claim 1, wherein the conductor layer consists essentially of at least one of Cu, Ag, or Au. The touch panel display of claim 1, wherein the capping layer comprises Cu and an alloy of one or more refractory metal elements selected from the list consisting of Hf, Re, Os, Ru and Rh. 21. The method of claim 20, wherein the conductor layer consists essentially of at least one of Cu, Ag, or Au. 21. The method of claim 20, wherein the capping layer comprises Cu and an alloy of one or more refractory metal elements selected from the list consisting of Hf, Re, Os, Ru and Rh. delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete delete

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