KR101790578B1 - Device and method for pulse-width modulation of multi-level inverter for generating sinusoidal output voltage with unbalanced dc input voltages - Google Patents

Abstract

The present invention relates to a pulse width modulation apparatus for controlling a switch of a multi-level (N-level) inverter, comprising: N-1 input side DC voltages of the multi-level A waveform generator for outputting N-1 different carrier waveforms having amplitudes corresponding to the magnitudes of the carriers; A comparator for receiving the carrier waveform and a reference voltage of the multi-level (N-level) inverter and comparing the reference voltage with the carrier waveform; And a gating signal generator for outputting a gating signal for controlling the switch at the output of the comparator.
According to the present invention, it is possible to generate a distortionless sinusoidal output voltage even if the DC input power is not necessarily balanced in a multi-level inverter having an unbalanced DC power supply.

Description

TECHNICAL FIELD [0001] The present invention relates to a pulse width modulation apparatus and a switch control method for a multi-level inverter that outputs a sine wave voltage regardless of unbalance of an input side DC voltage in a multi-level inverter. WITH UNBALANCED DC INPUT VOLTAGES}

The present invention relates to a pulse width modulation apparatus for a multilevel inverter and a switch control method for a multilevel inverter. More particularly, the present invention relates to a pulse width modulation apparatus and a multi-level inverter apparatus capable of generating an output voltage of a sine wave irrespective of an unbalanced input- Level inverter.

Figure 1 below shows a conceptual diagram of a multilevel inverter that outputs an AC voltage waveform from a series-connected DC input power supply and an exemplary AC voltage waveform that is output.

[Figure 1]

[Figure 1] is a conceptual diagram showing a phase of a 5-level inverter in which 5 voltage sources are connected in series as an example of a multi-level inverter. As shown in Figure 1, the multilevel inverter has a circuit configuration that can output one of several stages of DC input voltage (V1, V2, V3, V4, V5) to the output like a multiplexer used in signal processing . The multi-level inverter operates like a single-pole multiple-through switch (SPMT) and can be understood as generating an output voltage of an alternating current waveform in a predetermined cycle by changing contact points in a predetermined order .

Several types of multi-level inverters conceptually expressed in [Figure 1] have been proposed depending on the circuit configuration method. N-level multilevel inverters with a common arbitrary N level have a Neutral Point Clamped (NPC) scheme, which was first proposed in the early 1990s, and thereafter various types of multi-level inverter configurations that have improved the disadvantages of the NPC scheme. T-type Neutral Point Clamped (MNPC), Mixed Voltage Neutral Point Clamped (ANPC), Advanced Neutral Point Clamped (ANPC), and Cascade.

Figure 2 below shows the circuit configuration of an NPC multi-level inverter and shows the half bridge configuration of a 5-level inverter.

[Figure 2]

In the 5-level NPC inverter of Fig. 2, the control table of the IGBT switch for obtaining the desired output voltage is shown in Table 1 below.

[Table 1]

)In Table 1, 0 means that the IGBT switch is turned off, and 1 means that the IGBT switch is turned on. For example, when Q1, Q2, Q3 and Q4 are turned on and Q5, Q6, Q7 and Q8 are turned off, the output point P _o is connected to P ₁ , and the output voltage V _o becomes V1. Looking at the switching logic in Table 1, there are always four IGBT switches on, Q1 is complementary to Q5, Q2 is complementary to Q6, Q3 is complementary to Q7, Q4 is complementary to Q8 Relationship. (

)

In the multilevel inverter of Fig. 2, the AC voltage (V _o ) waveform on the output side is obtained by appropriately selecting a large number of DC voltages (V 1, V 2, V 3, V 4, V 5) connected in series to the input side. The following [Figure 3] shows an example of the AC output voltage when the pulse width modulation (PWM) method is used to reduce the magnitude of the harmonic component of the output voltage.

[Figure 3]

In Fig. 3, V _o represents the output voltage waveform, and V _{o (avg)} represents the moving average waveform obtained by averaging the output voltage (V _o ) at every switching period. In this case, V _{o (avg)} becomes equal to the fundamental wave component of the output voltage waveform as the switching frequency increases.

Note that in Figure 3, the four DC power supplies connected in series on the input side have the same DC voltage (V _dc / 4). It is very important that the magnitude of the DC voltage connected in series to the input side when the multi-level inverter is operating should be the same. This is because the pulse width modulation control method of most multi-level inverters normally operates only when the magnitudes of the input side DC voltages are all the same. It is said that voltage balancing is done when the magnitude of DC voltage connected in series to the input side of the multilevel inverter is equal to each other.

In multilevel inverters with a single DC voltage source, it is often the case that no voltage balancing occurs on the input side. When the input side of the multi-level inverter is a single DC power source, the voltage of the DC power source is usually divided into a plurality of series-connected capacitors as shown in [Figure 4] to obtain the input voltage.

[Figure 4]

In this case, there are actually cases where the DC side capacitor voltage is not equal to the allowable range for various reasons. The unbalanced capacitor voltage can be found in three main ways. First, unbalance of voltage may occur due to unbalance of device parameter values in terms of hardware. For example, each of the capacitors C1, C2, C3, and C4 may be designed to have the same value but may actually have different values within the tolerance. Furthermore, in phase 3, unbalanced voltages can occur as all three phase parameters are not exactly balanced. Second, even if the hardware is exactly symmetrical and balancing is done, balancing of the dc capacitor voltage may be broken if the switching operation of the three-phase inverter is asymmetrically done in terms of software. Finally, voltage unbalance occurs in the transient state such as when the power is first applied or when the load is turned on or off, so that it is maintained without being removed. For example, the following [Figure 5] shows the output voltage waveform when PWM switching operation is the same as [Figure 3] without balancing input DC voltage.

[Figure 5]

In Figure 5, the four DC power supplies have two states of DC power supply value (V _dc / 6, V _dc / 3), indicating unbalanced voltage. As shown in [Figure 5], the moving average voltage of the output voltage shows the sinusoidal distorted waveform.

All conventional multi-level inverter pulse width modulation control methods have been developed under the assumption of balancing the input side DC voltage. As a result, when a voltage unbalance state in which the magnitudes of the input side DC voltages are different from each other (voltage unbalance) is applied, the waveform of the output voltage is distorted when the developed pulse width modulation control operation is applied assuming voltage balancing. Therefore, when voltage unbalance occurs, distortion of the output voltage waveform causes problems such as reduction of the output voltage fundamental wave, distortion of output current, system static and dynamic performance degradation.

Korean Patent No. 10-1462750 discloses a multilevel inverter capable of easily performing voltage balancing. There is a conventional technique for performing voltage balancing as described above, but a circuit diagram for generating a sinusoidal output even though the voltage is unbalanced regardless of whether the voltage is balanced or not has not been proposed yet.

The present applicant has devised a pulse width modulation apparatus and a switch control method of a new multilevel inverter which generates an output voltage equal to a command value which is a reference voltage even when the input side voltage of the multilevel inverter is unbalanced .

Korean Patent No. 10-1462750

Accordingly, it is an object of the present invention to provide a pulse width modulation apparatus and a switch control method capable of generating an output voltage of a sine wave irrespective of an unbalanced input side DC voltage of a multi-level inverter.

In order to achieve the above object, the present invention provides a pulse width modulation apparatus for controlling a switch of a multi-level (N-level) inverter, comprising: N-1 input side DC voltages of the multi- A waveform generator for outputting carrier waveforms of N-1 different triangular waveforms having amplitudes corresponding to the magnitudes of the DC voltages; A comparator for receiving the carrier waveform and a reference voltage of the multi-level (N-level) inverter and comparing the carrier waveform and the reference voltage; And a gating signal generator for outputting a gating signal for controlling an IGBT switch of the multilevel (N-level) inverter as an output of the comparator unit.

Preferably, the waveform generator may output N-1 carrier waves of different triangular waveforms by making at least one of a frequency, a phase, and a duty ratio different from each other.

Preferably, the comparator unit includes N-1 comparators for comparing the carrier waveform and the reference voltage to compare the reference voltage with each of the N-1 carrier waveforms.

Preferably, the comparator may receive the reference voltage at a non-inverting terminal and the carrier waveform at an inverting terminal.

Preferably, the gating signal generator may include N-1 controllers for outputting a gating signal for controlling two switches as outputs of a single comparator.

Preferably, the controller has two branched output lines electrically connected to the two IGBT switches, and one of the output lines may have a NOT gate to output two complementary gating signals.

According to another aspect of the present invention, there is provided a method of controlling a switch of a multi-level (N-level) inverter, the method comprising: (a) receiving N-1 input-side DC voltages of the multi-level (N-level) (B) outputting carrier waveforms of N-1 different triangular waveforms having amplitudes corresponding to the magnitude of the DC voltage; (C) comparing the carrier waveform with a reference voltage of the multi-level (N-level) inverter; And (d) outputting a gating signal for controlling the switch as a result of the comparison in the step (c).

The step (c) may compare the reference voltage with the carrier waveform, amplify and output the result, and compare the reference voltage and the (N-1) carrier waveforms, respectively, for output.

Preferably, the step (d) includes receiving N-1 outputs in step (c), outputting 2 (N-1) gating signals, and outputting two complementary gating signals per single input .

According to the present invention, it is possible to generate a sinusoidal output voltage without distortion even when the DC input power is not necessarily balanced in a multi-level inverter having an unbalanced DC power supply. Effects obtained by applying the pulse width modulation apparatus according to the present invention to a multilevel inverter are summarized as follows.

Distortion of the output voltage waveform can be eliminated regardless of the DC power source condition. Further, by removing the distortion of the output voltage waveform, it is possible to obtain an output current of an improved sinusoidal wave. In addition, the harmonic components of the output voltage and the output current waveform can be reduced. In addition, the harmonic of the output AC component decreases, thereby reducing the size of the output filter. In addition, the control performance can be improved by increasing the linearity of the inverter. In addition, the reliability of the inverter can be improved. In addition, the life of the inverter can be improved.

1 shows a pulse width modulation apparatus applied to a three-level inverter according to an embodiment of the present invention.
FIG. 2 shows a configuration diagram of a pulse width modulation apparatus according to the embodiment of FIG.
3 is a waveform diagram for explaining a process of synthesizing the output voltage according to the magnitude of the reference voltage in the pulse width modulation apparatus according to the embodiment of FIG.
4 illustrates an exemplary operation waveform of the pulse width modulation apparatus according to the embodiment of the present invention when the reference wave voltage changes to a sinusoidal wave.
5 shows a pulse width modulation apparatus applied to an N-level inverter.
6 shows a circuit configuration of one phase of an NPC type N-level inverter according to the embodiment of FIG.
7 shows a waveform of a triangular wave carrier outputted from the waveform generator in the pulse width modulation apparatus of FIG.
Figure 8 shows a three-phase three-level inverter with an unbalanced DC voltage input.
Fig. 9 shows the operating waveforms of the three-phase three-level inverter with the unbalanced DC voltage of Fig.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to or limited by the exemplary embodiments. Like reference numerals in the drawings denote members performing substantially the same function.

The objects and effects of the present invention can be understood or clarified naturally by the following description, and the purpose and effect of the present invention are not limited by the following description. In the following description, well-known functions or constructions are not described in detail since they would obscure the invention in unnecessary detail.

1 shows a pulse width modulation apparatus 1 according to an embodiment of the present invention. Referring to FIG. 1, a pulse width modulation apparatus 1 connected when the inverter is three-level in consideration of a complexity of a design is illustrated. A pulse width modulator (1) as shown in Figure 1 is applied to the command value (command value) of the reference voltage input DC voltage (V _dc1, V _dc2) of (V _oref) and the inverter (3) of the inverter 3, inverter (3).

Prior to the description of the present invention, for the sake of understanding, the case of an NPC-type three-level inverter will be described with reference to FIG. 1 as an example. [Figure 6] shows the circuit configuration of one phase of NPC type 3-level inverter.

[Figure 6]

Where V _NP is the NP voltage of the 3-level inverter. Table 2 below shows the switching table of the 3-level inverter in [Figure 6].

[Table 2]

In Table 2, the output voltage is based on the voltage at point N. For example, when Q _1a and Q _2a are turned on and Q _1a and Q _2a are turned off, the output voltage V _o becomes the voltage at the point P, that is, V _dc . (In the following specification, the stage to the top of the phase relationship of the document editing tools Q _1a, Q _2a - can not represent a subscript, "'' - 'and given the subscript in the lower Q _1a and Q _2a complementary relationship with the switch Are represented by Q _1a and Q _2a .

In FIG. 1, the 3-level inverter pole 3 means the circuit of FIG. 6, and the pulse width modulation apparatus 1 has two input side DC voltages V _dc1 and V _dc2 of the 3-level inverter 1, V _oref to generate the PWM signal of the IGBT every switching cycle and supply it to the pole 3 of the 3-level inverter. V _oref is a reference voltage or a command wave of the output voltage as described above.

Fig. 2 shows a block diagram of the pulse width modulation apparatus 1 according to the embodiment of Fig. Referring to FIG. 2, the pulse width modulation apparatus 1 may include a waveform generator 10, a comparator 30, and a gating signal generator 50.

The waveform generating unit 10 receives the two input side DC voltages V _dc1 and V _dc2 of the three-level inverter, receives the carrier waveform V _tri1 having the amplitude corresponding to the magnitude of V _dc1 , the amplitude V _tri1 corresponding to the magnitude of V _{dc2 Lt} ; / RTI > can be output. In the present embodiment, the case where the carrier waveform is a triangular wave is exemplified. At this time, the two carrier waveforms V _tri1 and V _tri2 can be set to different waveforms. That is, the waveform generator 10 may output at least two different carrier waveforms V _tri1 and V _tri2 , which may differ in at least one of frequency, phase, and duty ratio.

More specifically, the waveform generating unit 10 forms a carrier waveform using the size information of the sensed input side DC voltages V _dc1 and V _dc2 . In this case, the information on the magnitudes of the input voltages V _dc1 and V _dc2 is used only for determining the amplitudes of the carrier waveforms V _tri1 and V _tri2 , and the two triangular waves may have different frequencies, phases, and duty ratios . Hereinafter, for simplicity of description and for convenience of explanation, two triangular wave carrier waveforms V _tri1 and V _tri2 are set to have the same frequency, phase, and duty ratio and different amplitudes only.

2, the comparator section 30 receives a carrier waveform and a reference voltage _Voref of the 3-level inverter 3, and receives a comparison _signal from the comparator 301 for comparing the carrier waveforms V _tri1 , V _tri2 with the reference voltage V _oref . . In the comparator 301, the reference voltage is input to the non-inverting terminal (+) and the carrier waveforms V _tri1 and V _tri2 are input to the inverting terminal (-).

In Figure 2, the gating signal generation section 50 has two controllers 501 is provided, and the gating signal Q _1a for controlling the IGBT switch with the output of the comparison base 30 a, Q _1a, Q _2a, Q _2a Can be output. The controller 501 has two branched output lines electrically connected to two IGBT switches and has two NOT gates on any one output line to output two complementary gating signals Q _1a , Q _1a or Q _2a , Q _2a .

In the circuit example of FIG. 2, the operation principle in which the output voltage of the sinusoidal wave is generated despite the unbalance of the voltage will be described as follows.

The output voltage (V _o ) of one pole of the 3-level inverter (3) can be synthesized using three input voltage levels, V _dc , V _NP , However, if the reference value V _oref of the output voltage is V _NP ≤V _oref ≤V _dc , the output voltage can be synthesized by using only two input voltages of the three-level inverter (3), ie, V _NP and V _dc . Further, when the reference value V _oref of the output voltage is 0? _Voref ? V _NP , the output voltage can be synthesized by using only the other two input voltages of the 3-level inverter 3, that is, V _NP and 0.

3 is a waveform diagram for explaining a process of synthesizing the output voltage according to the magnitude of the reference voltage in the pulse width modulation apparatus according to the embodiment of FIG. Referring to FIG. 3A, when V _NP ≤V _oref ≤V _dc , the comparator 30 compares the reference value V _oref of the output voltage with the triangular wave carrier waveform V _tri1 which reciprocates between V _NP and V _dc do. The output voltage V _o of the 3-level inverter 3 is determined according to the following [Relation 1].

[Relation 1]

Here, the slope of the triangular wave carrier waveform V _tri1 is V _dc1 / T _s and, according to the geometric proportional relationship, the following relation (2) is established.

[Relation 2]

로 표현될 수 있고, T_sT₁+T₂ 조건과 [관계식 2]를 대입하여 정리하면, 하기의 [관계식 3]과 같이 출력 전압의 평균값이 출력 전압의 기준값과 같음이 증명된다.When the average value of the output voltages is obtained,

And T _s T ₁ + T ₂ and [Equation 2] are substituted, it is proved that the mean value of the output voltage is equal to the reference value of the output voltage as shown in the following [Relation Equation 3].

[Relation 3]

If V _NP < V oref _> V _dc , the switch gating signal of the 3-level inverter 3 is determined according to [Equation 1]. That is, in order to form an output voltage of V _dc gating signal generation section 50 is the _{(Q 1a 1, Q 2a =} 1) should be applied to the gating signal, the output of the V _NP turn-on signal to the Q _1a and Q _2a gating signal generating section 50 to form a voltage Q _1a is turned off, Q _2a and applies a turn-on signal is the _{(Q 1a = 0, Q 2a} = 1) as a gating signal. Therefore, the gating signal generating unit 50 can set a gating signal generation rule as shown in the following [Relation 4].

[Relation 4]

Referring to FIG. 3 (b), when 0 _? Voref _? V _NP , the comparator 30 compares the reference value _Voref of the output voltage with the triangular carrier waveform V _tri2 which reciprocates between 0 and V _dc . The output voltage V _o of the 3-level inverter 3 is determined according to the following [Expression 5].

[Equation 5]

Here, the slope of the triangular wave carrier waveform is V _dc2 / T _s , and the following relation (6) is established by the geometric proportional relationship.

[Relation 6]

로 표현될 수 있고, T_sT₁+T₂ 조건과 [관계식 6]을 대입하여 정리하면, [관계식 3]과 같이 출력 전압의 평균값이 출력 전압의 기준값과 같음이 증명된다.When the average value of the output voltages is obtained,

And T _s T ₁ + T ₂ and [Equation 6] are substituted, it is proved that the average value of the output voltage is equal to the reference value of the output voltage as shown in [Equation 3].

If the 0≤V _oref ≤V _NP, switch gating signal of the three-level inverter 3 is determined in accordance with [Expression 5]. That is, in order to form an output voltage of V _NP gating signal generation section 50, and Q _1a is turned off, Q _2a is a turn-on signal is the _{(Q 1a 0, Q 2a =} 1) should be applied to the gating signal, the 0 In order to form the output voltage, the gating signal generator 50 applies a signal (Q _1a = 0, Q _2a = 0), which is a signal to turn off Q _1a and Q _2a , as a gating signal. Accordingly, the gating signal generator 50 may set a gating signal generation rule as in the following [Expression 7].

[Relation 7]

However, since V _tri2 <V _tri1 in FIG. 3, the gating signal generator 50 can finally set the switching rule as shown in [Equation 8] in consideration of [Equation 4] and [Equation 7].

[Relational expression 8]

4 illustrates an exemplary operation waveform of the pulse width modulation apparatus 1 according to the embodiment of the present invention when the reference wave voltage changes to a sinusoidal wave. Referring to FIG. 4, the reference voltage waveform of the sinusoidal wave is arranged such that the center line thereof is V _dc / 2. This is to enable the swing of the maximum amplitude. Also, note that the output voltage waveform has an offset of V _dc / 2 since it represents the potential of the N point as a reference. In FIG. 4, it can be seen that the dc input voltages V _dc1 and V _dc2 are asymmetric, but the switching period moving average of the output voltage or the fundamental wave component is the same as the sinusoidal reference wave. In the above description, the operation principle of the pulse width modulation apparatus 1 according to the embodiment of the present invention will be fully understood.

5 shows a configuration diagram of a pulse width modulation apparatus 1 applied to an N-level inverter according to an embodiment of the present invention. 6 shows a circuit configuration of one phase of an NPC type N-level inverter according to the embodiment of FIG.

Referring to FIG. 6, in an N-level inverter of an arbitrary level, one phase is supplied with an N-level DC voltage as input from N-1 DC power supplies serially connected to the input terminal. Also, since the N-level inverter includes 2 (N-1) power semiconductor switches (e.g., IGBTs) on one phase, 2 (N-1) gating signals for driving the respective power semiconductor switches are required .

5, a reference wave generator (not shown) for generating a reference voltage V _oref outputs one reference wave signal when the N-level inverter is single-phase, and three reference wave signals when the N- Output. The output of the reference wave generator is input to the comparator 30. At this time, the reference voltage V _{oref, which} is the output of the reference wave generator, always satisfies the following relational expression (9).

[Relational expression 9]

On the other hand, the waveform generator 10 receives N-1 input side DC voltages of the N-level inverter and outputs N-1 different carrier waveforms having amplitudes corresponding to the magnitude of the DC voltage. In the present embodiment, the carrier waveform may be a triangular wave, and V _tri1 , V _tri2 , ... , And V _{tri (N-1)} . At this time, the waveform generating unit 10 can generate a carrier waveform by making at least one of frequency, phase, and duty ratio different. The waveform generator 10 outputs N-1 different carrier waveforms, which can be understood through the above-described operation principle. 7 shows different N-1 triangular wave carrier waveforms outputted from the waveform generator 10 in the pulse width modulation apparatus 1 of Fig.

The comparator unit 30 includes N-1 comparators 301 for receiving the carrier waveform and the reference voltage of the N-level inverter and comparing the carrier waveform with the reference voltage _Voref , so that the reference voltage _Voref is _divided into N-1 carriers And waveforms, respectively. In the comparator 301, the reference voltage V _oref may be input to the non-inverting terminal (+) and the carrier waveform V _tri may be input to the inverting terminal (-).

The gating signal generating unit 50 outputs a gating signal for controlling 2 (N-1) switches to the output of the comparator unit 30. [ At this time, the gating signal generator 50 includes N-1 controllers 501 for outputting a gating signal for controlling the two power semiconductor switches at the output of the single comparator 301.

The controller 501 has two branched output lines electrically connected to the two switches and has a NOT gate on one output line to output two complementary gating signals Q _1a , Q _1a or Q _2a , Q _2a Etc.).

Figure 8 shows a three-phase three-level inverter with an unbalanced DC voltage input. In order to confirm the effect of the pulse width modulation apparatus 1 according to the present embodiment, the operation of the three-phase three-level inverter having different DC voltages illustrated in FIG. 8 will be described below. In this embodiment, the circuit constants for FIG. 8 are V _dc1 = 200 V, V _dc2 = 300 V, R = 10?, And L = _{1.5 mH} . In addition, the frequency of the output voltage is 50 Hz, the switching frequency is 10 kHz, and the amplitude modulation index is 0.9.

9 shows a simulation result when the pulse width modulation apparatus 1 according to the embodiment of the present invention is applied to the 3-level inverter of FIG. 8 having an unbalanced DC voltage. In FIG. 9, VAN is the output voltage based on point N, and VAN (avg) is a moving average waveform obtained by averaging the waveform of the VAN every switching cycle. VAB means VAB = VAN-VBN and represents the line-to-line voltage between A and B phases. ia, ib, ic mean the three-phase output current. As shown in FIG. 9, both the output phase voltage and the output phase voltage have a fundamental wave of sinusoidal wave, and as a result, it can be confirmed that the output current has a complete sinusoidal waveform without distortion.

In another embodiment of the present invention, a method of controlling the switch of the N-level inverter performed in the pulse width modulation device 1 will be summarized as follows. The method for controlling the switch of the N-level inverter includes the steps of: (a) receiving the N-1 input side DC voltages of the N-level inverter of the waveform generator 10; (B) the waveform generator 10 outputs N-1 different carrier waveforms having a magnitude corresponding to each amplitude of the DC voltage; (C) comparing the carrier waveform with a reference voltage of the multi-level (N-level) inverter; And (d) the gating signal generator 50 outputs a gating signal for controlling the switch as a result of the comparison in the step (c).

In the step (c), the reference voltage and the carrier waveform are compared with each other, and the reference voltage and the N-1 carrier waveforms are compared with each other and output. In step (d), N-1 outputs are received and 2 (N-1) gating signals are output in step (c), and two gating signals complementary to each single input may be output. The steps (a) through (d) above are performed by the waveform generating unit 10, the comparator unit 30 and the gating signal generating unit 50. In the embodiments of FIGS. 1 through 9, .

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments. will be. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be determined by all changes or modifications derived from the scope of the appended claims and equivalents of the following claims.

1: pulse width modulation device
3: Three-level inverter
10: Waveform generator
30: Comparative donation
301: comparator
50: Gating signal generator
501: Controller

Claims (10)

A pulse width modulation apparatus for controlling a plurality of switches of a multi-level (N-level) inverter,
(N-1) inverters having different magnitudes of the DC levels of the multi-level (N-level) inverters, A waveform generator for outputting a plurality of carrier waves having different amplitudes;
A plurality of carrier waves having different amplitudes and a reference voltage of a corresponding phase of the multi-level (N-level) inverter, and comparing the reference voltage with each of a plurality of carrier waves having different amplitudes, A comparator section having a plurality of comparators for outputting comparison results; And
And a gating signal generator for outputting a plurality of gating signals for controlling the plurality of switches of the multi-level (N-level) inverter using the plurality of comparison results,
The pulse width modulation apparatus includes:
And generates an output voltage of a sinusoidal wave irrespective of unbalance of the DC levels of the plurality of input side DC voltages.
delete The method according to claim 1,
Wherein the waveform generator comprises:
And outputs a plurality of triangular waves having N-1 different amplitudes having the same amplitude as the magnitude of each of the plurality of input side DC voltages to the carrier waveform.
The method according to claim 1,
Wherein the comparator comprises:
And N-1 plurality of comparators.
5. The method of claim 4,
Wherein each of the plurality of comparators comprises:
Wherein the reference voltage is input to each non-inverting terminal and each of the plurality of carrier waveforms is input to each inverting terminal.
5. The method of claim 4,
The gating signal generator includes:
And a controller for outputting two gating signals for controlling two switches belonging to the same phase of the multi-level (N-level) inverter by using the comparison result of the single comparator. Pulse width modulating device.
The method according to claim 6,
The controller comprising:
Off signal to two switches belonging to the same phase of the multi-level (N-level) inverter and having a NOT gate on any one output line to output two complementary gating signals And outputs the pulse width modulation signal.
A method for controlling a plurality of switches of a multi-level (N-level) inverter,
Sensing a plurality of N-1 input side DC voltages having different magnitudes of DC levels of the multi-level (N-level) inverters;
Outputting a plurality of carrier waveforms having N-1 different amplitudes each having an amplitude equal to the magnitude of each of the plurality of input-side DC voltages;
Comparing a reference voltage of a corresponding phase of the multi-level (N-level) inverter with each of a plurality of carrier waveforms having different amplitudes to output a plurality of comparison results;
Outputting a plurality of gating signals for controlling a plurality of switches of the multi-level (N-level) inverter using the plurality of comparison results; And
And generating an output voltage of a sinusoidal wave irrespective of unbalance of the DC levels of the plurality of input side DC voltages.
9. The method of claim 8,
Wherein the outputting of the plurality of comparison results comprises:
And comparing the reference voltage with a plurality of carrier waveforms having different amplitudes, and outputting the comparison result.
9. The method of claim 8,
Wherein the outputting of the plurality of gating signals comprises:
(N-1) number of gating signals, and outputting two complementary gating signals per single input, receiving the N-1 number of comparison results and outputting 2 (N-1) ) A method of controlling a switch of an inverter.

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