KR101787751B1 - Resistive RAM of having Ohmic Contact Layer - Google Patents

Abstract

There is provided a resistance change memory that simultaneously includes a resistance change characteristic and a diode selection characteristic. The resistance-variable diode constituting the resistance-change memory is composed of oxide semiconductors and is achieved by joining the p-type resistance-variable semiconductor layer and the n-type resistance-variable semiconductor layer. In the p-type resistance-variable semiconductor layer, charge transfer is performed by the dominant behavior of holes according to the metal vacancies, and charge transfer is performed in the n-type resistance-variable semiconductor layer by movement of electrons by oxygen vacancies. An ohmic contact layer is formed on the resistance-variable diode in order to achieve ohmic contact with the resistance-variable semiconductor layer and suppress formation of a Schottky barrier. This makes it possible for each memory cell to read information without misreading even under a low reading voltage and to reduce the driving power of the memory structure to realize a large capacity and high density memory and to avoid the complexity and high cost of the manufacturing process .

Description

Resistive RAM of having ohmic contact layer < RTI ID = 0.0 >

The present invention relates to a nonvolatile memory, and more particularly, to a resistive random access memory having a diode structure.

Nonvolatile memory is an essential element used in the field of digital information communication. This has the characteristic that the stored information is retained even if the power supply is removed. In particular, flash memory, which is a typical non-volatile memory, exhibits a behavior based on charge control. Conventional nonvolatile memories based on charge control are expected to reach a critical point due to reduced design rules and difficult usage conditions in various applications.

In order to overcome these limitations, new memory devices using phase change and magnetic field change are being studied. The information storage method of new memory devices under study uses the principle of changing the resistance of the material itself by inducing the state change of the material.

In a flash memory, which is a typical non-volatile memory device, a high operating voltage is required for programming and erasing data. Therefore, when scaling down to 45 nm or less, it is exposed to certain limits due to interference between neighboring cells, and slow operation speed and large power consumption are still a problem. MRAM (Magnetic RAM), a newly studied nonvolatile memory, has a limitation in that it has a complicated manufacturing process, a multi-layer structure, and a small margin of read / write operation.

The resistance change memory element has a structure including a resistance change layer composed of an oxide between an upper electrode and a lower electrode. The resistance of the resistance variable layer is changed according to the applied voltage, and the operation of the memory is realized by using the resistance. The resistance change memory is advantageous in that it can theoretically record and reproduce at an infinite time, and there is no deterioration of characteristics due to repeated operation, and high temperature operation is possible. In addition, it has non-volatile characteristics and data stability. Particularly, when the input pulse is applied, a high-speed operation of about 10 to 20 ns is possible with a change in resistance of 1000 times or more.

The resistance-variable layer of the resistance-change memory has a single-layer or multi-layer structure, which enables high integration and high-speed operation. In addition, since the process technology similar to the conventional CMOS process is applied, there is an advantage that the manufacturing process is easy.

The material of the resistance variable layer is binary oxide or perovskite. When a predetermined voltage is initially applied ('forming'), a conductive filament is formed in the resistance variable layer. In addition, the voltage regulation of the conductive filament causes the conductive filament to be reset and set. By doing so, the operation of the nonvolatile memory is achieved by controlling the current flowing through the resistance variable layer.

Also, for the highly integrated ideal memory device, it is important to develop an orthogonal bar cell array having a memory cell size of 4F ^2. Due to the inherent characteristics of the orthogonal bar cell array, an interference phenomenon occurs between adjacent cells. This causes an error in the reading operation of the data stored in the memory. To solve this problem, a selection device such as a diode or a transistor capable of selectively reading each cell is additionally provided for each cell. However, the smaller the size of the transistor, the more difficult it is to fabricate and characterize it, and it is advantageous to use a diode having a relatively simple structure as a selection device.

As described above, when a resistance change memory element having a pn diode structure is fabricated in an orthogonal bar cell array, there is a fear of information misreading due to the influence of peripheral elements in reading information. However, the schottky barrier formed between the oxide and the electrode material There arises a problem that the read voltage becomes large at the time of reading information.

It is an object of the present invention to solve the above-described problems and to provide a resistance change memory which can eliminate the influence of peripheral elements in a rectangular bar cell array structure and eliminate the possibility of information misreading through a simple structure.

According to an aspect of the present invention, there is provided a plasma display panel comprising: a lower electrode formed on a substrate; A resistance variable diode formed on the lower electrode; And a top electrode layer formed on the resistance-changing diode, the top-electrode layer achieving ohmic contact with the resistance-changing diode.

The above object of the present invention can also be achieved by a plasma display panel comprising: a lower electrode formed on a substrate; A resistance change diode formed on the lower electrode and having a resistance change according to an applied voltage and a diode characteristic at the same time; And an ohmic contact layer formed on the resistance-variable diode and achieving ohmic contact with the resistance-change diode.

According to the present invention described above, the resistance change operation and the diode characteristic operation, which is a selection operation of the element, are performed simultaneously in one structure. In addition, an ohmic junction is achieved over the resistance-varying diode that does this. Therefore, it is possible to suppress the schottky barrier to obtain a high forward current even at a low forward bias while maintaining forward and reverse rectification characteristics. Improvement of the characteristics of the resistance variable diode memory device through application of the Ohmic junction layer enables each memory cell to read information without misreading the information even under a low read voltage. The improvement of these characteristics can finally realize a memory of a large capacity and a high density by reducing the driving power of the entire memory structure, and it is possible to avoid the complication and the high cost in the manufacturing process.

1 is a cross-sectional view illustrating a resistance change memory according to a preferred embodiment of the present invention.
FIGS. 2 to 4 are cross-sectional views illustrating a method for fabricating a resistance change memory according to a preferred embodiment of the present invention.
5 is a graph showing voltage-current characteristics of a resistance-change memory including an Ohmic junction layer according to a preferred embodiment of the present invention.
6 is another graph showing voltage-current characteristics for confirming the resistance change switching characteristic of the diode of the resistance change memory according to the preferred embodiment of the present invention.

The present invention is capable of various modifications and various forms, and specific embodiments are illustrated in the drawings and described in detail in the text. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for like elements in describing each drawing.

Unless defined otherwise, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

Example

1 is a cross-sectional view illustrating a resistance change memory according to a preferred embodiment of the present invention.

Referring to FIG. 1, a lower electrode 110, a resistance-variable diode 120, and an upper electrode layer 130 are provided on a substrate 100. The resistance-variable diode 120 includes a p-type resistance-variable semiconductor layer 121 and an n-type resistance-variable semiconductor layer 122. The upper electrode layer 130 includes an ohmic contact layer 131 and an upper electrode 132.

The substrate 100 can be used as long as it is applied to an ordinary semiconductor memory device. Therefore, there is no particular limitation on the material, and Si, SiO ₂ , Si / SiO ₂ multilayer substrate, polysilicon substrate, or the like can be used.

In addition, the substrate 100 may be a specific film quality rather than a physical substrate. That is, it may be a film formed on the substrate 100 to have a predetermined laminated structure and physically supporting the lower electrode 110.

A lower electrode 110 is formed on the substrate 100. The lower electrode 110 may be selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or may be a nitride electrode containing TiN or WN. The lower electrode 110 may have a thickness of 20 nm to 200 nm, depending on the selected material.

A resistance-variable diode 120 is provided on the lower electrode 110. The resistance-variable diode 120 has a p-type resistance-change semiconductor layer 121 and an n-type resistance-variable semiconductor layer 122.

First, a p-type resistance-variable semiconductor layer 121 is formed on the lower electrode 110. The p-type resistance-variable semiconductor layer 121 is formed of CoO _x (1? X? 1.5, x is a real number), MgO _x (1? X <2, x is a real number), CuAlO _x real _{number), MnO x (1≤ x ≤} 1.5, x is a real _{number), SnO x (1.2≤ x <} 2, x is a real _{number), FeO x (1≤ x ≤} 1.5, x is a real number), WO _x (1.8≤ x <3, x is a real _{number), PbO x (1.2≤ x <} 2, x is a real _{number), Pr 1 -x Ca x MnO} 3 (0.6≤ x <1, x is a real number), La _{1 -x} Ca _x MnO ₃ (0.6≤ x <1, x is a real _{number), La 1 -x Sr x MnO} 3 (0.6≤ x <1, x is a real number) or _{PbZr 1 -x Ti x O 3 (} 0.6≤ x <1, x is Mistakes).

That is, the p-type resistance-variable semiconductor layer 121 is made of an oxide semiconductor, and the p-type resistance-variable semiconductor layer 121 is mainly driven by charge transfer through holes. In particular, the material constituting the p-type resistance-variable semiconductor layer 121 preferably has a non-stoichiometric structure. Particularly, the movement of holes using vacancies of metal atoms is dominant.

The n-type resistance-variable semiconductor layer 122 is formed on the p-type resistance-variable semiconductor layer 121. The n-type semiconductor resistance change layer 122 is _{TiO x (1.2≤ x ≤ 1.89,} x is a real _{number), CeO x (1.5≤ x <} 2, x is a real _{number), ZnO x (1.2≤ x <} 2, x is real number), TaO _{x (x} is 1.2 ≤ x <2.5, x is a real _{number), AlO x (1.2≤ x <} 2, x is a real _{number), LaO x (1.2≤ x <} 2, x is a real number), NbO _x ( (Where x is a real number), Sn-doped InO _x (1 < _x ? 1.5, x is a real number), In _x Zn _{1 -x} O _{2 x Nb 1 -x O 3 (0} <x≤ 0.5, x is a real _{number), Sr x Ti 1 -x O} 3 (0 <x≤ 0.5, x is a real _{number), Ba x Sr 1 -x TiO} 3 (0 < x≤ 0.5, x is a real number), Nb- doped _{Sr x Ti 1 -x O 3 (} 0 <x≤ 0.5, x is a real number), Cr- doped _{Sr x Ti 1-x O 3} (0 <x≤ 0.5, x is a real number), Sr _x Zr _{1 -x} O ₃ (0 <x? 0.5, x is a real number) or Cr-doped Sr _x Zr _{1 -x} O ₃ .

The n-type resistance-variable semiconductor layer 122 is made of an oxide semiconductor, and charge transfer through electrons is predominantly caused. Therefore, it is desirable to have a non-stoichiometric configuration depending on the vacancy of the oxygen atom.

The upper electrode layer 130 is formed on the n-type resistance-variable semiconductor layer 122.

In particular, an ohmic contact layer 131 for suppressing formation of a schottky barrier is disposed on the n-type resistance-variable semiconductor layer 122. The ohmic contact layer 131 is made of a conductive material and forms an ohmic contact with the n-type resistance-variable semiconductor layer 122. Ohmic contact layer 131 has a relatively low work or a metal material such as Al, In, Ti or Mn has a function, WN, nitride material such as TiN, TiOx (0.5 <x < 1.4), (In, Sn) 2 O ₃ , RuO ₂ or SrRuO _3, and the like. The thickness of the Ohmic bonding layer 131 is preferably 3 nm to 250 nm. If the thickness of the ohmic contact layer 131 is less than 3 nm, the effect of suppressing the Schottky barrier is reduced. If the thickness exceeds 250 nm, the diode characteristics of the device are affected or the overall size of the device is increased. Particularly, when the n-type resistance variable semiconductor layer 122 is made of TiOx (1.2? X? 1.89 and x is a real number), it is preferable to use the same kind of TiOx (0.5 <x <1.4) as the ohmic contact layer 131 Do.

An upper electrode 132 is formed on the ohmic contact layer 131. The upper electrode 132 may be selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or may be a nitride electrode including TiN or WN. The upper electrode 132 may be formed to have a thickness of 20 nm to 200 nm and may be formed of a micro orthogonal rod array through a method such as a shadow mask, patterning through a normal photolithography process, nanoimprinting or e-beam lithography . That is, the lower electrode 110 and the upper electrode 132 may be formed such that the extending directions thereof cross each other.

1, the arrangement of the p-type resistance-variable semiconductor layer 121 and the n-type resistance-variable semiconductor layer 122 may be changed. That is, the n-type resistance-variable semiconductor layer 122 is formed first on the ohmic contact layer 131 formed on the lower electrode 110, and the p-type resistance-variable semiconductor layer 121 may be disposed.

The resistance change of the resistance-variable semiconductor layers 121 and 122 is achieved by the formation and disappearance of the conductive filament by the applied voltage. That is, the resistance changes due to the formation and disappearance of the conductive filament in which the path of the charge in the material is formed by the applied high voltage or bias.

The junction of the p-type resistance-change semiconductor layer 121 and the n-type resistance-variable semiconductor layer 122 has a diode characteristic. That is, even when the conductive filament is formed, the p-type resistance-variable semiconductor layer 121 and the n-type resistance-variable semiconductor layer 122 form the resistance-variable diode 120 that functions as a resistance-variable layer while maintaining diode characteristics.

FIGS. 2 to 4 are cross-sectional views illustrating a method for fabricating a resistance change memory according to a preferred embodiment of the present invention.

Referring to FIG. 2, a lower electrode 110 is formed on a substrate 100. The substrate 100 may be a physical substrate and may be a specific film supporting the lower electrode 110. The lower electrode 110 may be selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or may be a nitride electrode including TiN or WN.

In addition, the lower electrode 110 may be formed by a conventional deposition method. That is, a physical vapor deposition method, a chemical vapor deposition method, a sputtering method, a pulse laser deposition method, an evaporation method, an electron beam deposition method, an atomic layer deposition method or a molecular beam epitaxy deposition method can be used. Preferably, a Pt material using sputtering is used as a lower electrode .

Referring to FIG. 3, a resistance-variable diode 120 is formed on the lower electrode 110. The resistance-variable diode 120 has a difference between the amount of current when a positive bias is applied and the amount of current when a reverse bias is applied. It also has a characteristic in which the resistance changes in accordance with an applied voltage. Accordingly, the resistance-variable diode 120 can perform a set / reset operation in which a conductive filament is formed or destroyed according to a bias applied thereto, and can cause a selective operation of the cell according to characteristics inherent to the diode.

The resistance-variable diode 120 has a p-type resistance-change semiconductor layer 121 and an n-type resistance-variable semiconductor layer 122.

For example, the p-type resistance-variable semiconductor layer 121 is formed on the lower electrode 110. The p-type resistance-variable semiconductor layer 121 includes the material shown in FIG. In addition, the formation of the p-type resistance-variable semiconductor layer 121 can be accomplished through various deposition methods known to those skilled in the art.

For example, a physical vapor deposition method, a chemical vapor deposition method, a sputtering method, a pulse laser deposition method, an evaporation method, an electron beam deposition method, an atomic layer deposition method or a molecular beam epitaxy deposition method may be used. Preferably, the CoO _x material is a p- Is used.

The n-type resistance-variable semiconductor layer 122 is formed on the p-type resistance-variable semiconductor layer 121. The n-type resistance-variable semiconductor layer 122 includes the material shown in FIG. Further, the n-type resistance-variable semiconductor layer 122 can be formed through various deposition methods as mentioned in the formation of the p-type resistance-variable semiconductor layer 121. Preferably, the n-type resistance-variable semiconductor layer 122 may be formed through the same method as the method for forming the p-type resistance-variable semiconductor layer 121. In addition, the n-type resistance-variable semiconductor layer 122 preferably includes TiO _x (1.2? X? 1.89, where x is a real number).

Referring to FIG. 4, an upper electrode layer 130 is formed on the resistance-variable diode 120. The upper electrode layer 130 has an ohmic contact layer 131 and an upper electrode 132. In particular, the ohmic contact layer 131 is formed on the resistance-variable diode 120 first. Ohmic contact layer 131 is a nitride material, TiOx (0.5 <x <1.4 ) , such as a metallic material or, WN or TiN, such as Al, In, Ti or Mn having a low work _{function, (In, Sn) 2 O} 3 , RuO ₂ Or an oxide electrode material such as SrRuO ₃ or the like. The thickness of the Ohmic bonding layer 131 is preferably 3 nm to 250 nm. At this time, if the thickness of the ohmic contact layer 131 is less than 3 nm, the effect of suppressing the Schottky barrier is decreased. If the thickness exceeds 250 nm, it affects the diode characteristics of the device or affects the overall size of the device.

In addition, the ohmic contact layer 131 may have a patterned shape through a shadow mask or conventional photolithography and e-beam lithography. For example, an ohmic contact layer 131 may be formed through patterning according to a conventional photolithography, by forming a conductive film as a pre-stage of the ohmic contact layer 131 through deposition of a metal material. Alternatively, the patterned ohmic contact layer 131 may be formed simultaneously with the deposition using a shadow mask in the deposition process. In particular, when the n-type resistance-variable semiconductor layer 122 is made of TiOx (1.2? X? 1.89, x is a real number), TiOx is preferably used as the ohmic contact layer 131.

An upper electrode 132 is formed on the ohmic contact layer 131. The upper electrode 132 may be selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or may be a nitride electrode including TiN or WN. In addition, the upper electrode 132 may have a patterned shape through a shadow mask or conventional photolithography. For example, the upper electrode 132 may be formed through the deposition of metal to form a conductive film, which is a pre-stage of the upper electrode 132, and patterning according to conventional photolithography. Alternatively, a patterned top electrode 132 may be formed at the same time as deposition using a shadow mask during the deposition process.

After the upper electrode 132 is formed, a post-heat treatment for the manufactured resistance change memory may be performed.

5 is a graph showing voltage-current characteristics of a resistance-change memory including an Ohmic junction layer according to a preferred embodiment of the present invention.

Referring to FIG. 5, when polysilicon is used as a substrate, a lower electrode is directly formed on a substrate. The material of the lower electrode is Pt, and the thickness is set to 100 nm.

A resistance-variable diode is provided on the upper portion of the lower electrode, and a p-type resistance-variable semiconductor layer is formed on the lower electrode. The material of the p-type resistance-variable semiconductor layer includes CoO, and its thickness is set to 30 nm. Further, an n-type resistance-variable semiconductor layer is formed on the p-type resistance-variable semiconductor layer. The material of the n-type resistance variable semiconductor layer includes TiO _x (1.2? x? 1.89, x is a real number) and its thickness is 10 nm.

On the resistance variable diode, an ohmic contact layer is formed of TiO x (0.5 <x <1.4) having a thickness of 5 nm, and the upper electrode formed on the upper part includes Pt. The thickness of the upper electrode is set to 100 nm.

The voltage difference is applied to the upper and lower electrodes of the resistance change memory having the above-described structure to measure the current flowing. The direction in which the negative voltage is applied is the positive direction, and the direction in which the positive voltage is applied is the reverse direction. The resistance change memory shown in FIG. 5 is in a state before the forming is performed.

In the case of a resistance-variable diode element with an ohmic junction layer inserted, the resistance-changing diode forms a high positive current due to the application of positive voltage (expressed in units of -). For example, a positive current of 1 mA or more flows due to a voltage difference of 2V. On the other hand, when the reverse voltage is applied (expressed in units of +), a low amount of reverse current flows due to the rectifying characteristic. For example, a reverse current of 1 uA or less flows due to a voltage difference of 2V. As described above, the resistance change memory causes a difference in the amount of current to be about 1000 times or more when the forward bias and the reverse bias are applied by the resistance-change diode composed of resistance-changing semiconductors. As a result, it can be seen that the rectifying action is performed with respect to the directionality of the bias to which the resistance variable diode is applied. In particular, when comparing the amount of forward current in the low voltage region such as 0.5 V or less, It can be seen that the current amount of the device is much larger than that of the resistance-variable diode device not including the ohmic junction layer. This is due to the presence or absence of a schottky barrier between the electrode material and the resistance-changing material. The ohmic junction layer suppresses the formation of a Schottky barrier and forms an ohmic contact so that a high forward current can flow at a low voltage during forward bias Because.

6 is another graph showing voltage-current characteristics for confirming the resistance change switching characteristic of the diode of the resistance change memory according to the preferred embodiment of the present invention.

Referring to FIG. 6, a forming process is performed on the resistance change memory shown in FIG. 5, and the diode characteristics of the resistance change memory in which the forming is performed are measured. Foaming is performed by application of reverse bias and occurs at about 4.6V. Thereafter, the reset process is performed according to the application of the forward bias of 1.5V. The conductive filament formed by the foaming is partially broken through the reset process.

The resistance change memory after the reset process is performed can be repeatedly reset and reset. The forwarding is performed, and the forward and reverse characteristics of the resistance change memory in which the reset is performed are measured. It can be seen that the amount of current when a forward bias is applied (indicated by a unit) has a higher value than the amount of reverse bias applied (expressed in units of +). In particular, the amount of current in the HRS state in the forward low voltage region (< 0.5 V) for reading the information of the resistance change memory is 10 times or more larger when the case where the ohmic junction layer is inserted is not inserted. This indicates that the operation of the resistance change memory element is useful for reading information of the memory cell even at a low read voltage.

As described above, according to the present invention, a schottky barrier is suppressed through the use of an ohmic contact layer in a resistance-variable memory device that simultaneously realizes both diode characteristics and resistance change characteristics, so that forward current and reverse current rectification characteristics are maintained, Can be obtained. Improvement of the characteristics of the resistance variable diode memory device through application of the Ohmic junction layer enables each memory cell to read information without misreading the information even under a low read voltage. The improvement of these characteristics can finally realize a memory of a large capacity and a high density by reducing the driving power of the entire memory structure, and it is possible to avoid the complication and the high cost in the manufacturing process.

100: substrate 110: lower electrode
120: resistance-variable diode 130: upper electrode layer

Claims (14)

A lower electrode formed on a substrate;
A p-type resistance-variable semiconductor layer formed on the lower electrode, the p-type resistance-variable semiconductor layer being composed of an oxide semiconductor in which charge transfer through holes is dominant;
An n-type resistance-variable semiconductor layer formed on the p-type resistance-variable semiconductor layer, the n-type resistance-variable semiconductor layer being composed of an oxide semiconductor in which charge transfer through electrons is predominantly generated;
An ohmic contact layer formed on the n-type resistance-variable semiconductor layer and suppressing formation of a resistance-variable diode and a Schottky barrier; And
And an upper electrode formed on the ohmic contact layer,
The ohmic contact layer may be formed of a metal material having Al, In, Ti or Mn, a nitride material having WN or TiN or an oxide electrode material having TiOx (0.5 <x <1.4), (In, Sn) 2O3, RuO2 or SrRuO3 / RTI &gt;
Wherein the p-type resistance variable semiconductor layer is made of CoO _x (1? X? 1.5 and x is a real number), MgO _x (1? X <2, x is a real number), CuAlO _{x , MnO x (1≤ x ≤ 1.5} , x is a real _{number), SnO x (1.2≤ x <} 2, x is a real _{number), FeO x (1≤ x ≤} 1.5, x is a real number), WO _x (1.8≤ _x < 3, x is a real _{number), PbO x (1.2≤ x <} 2, x is a real _{number), Pr 1-x Ca x} MnO 3 (0.6≤ x <1, x is a real _{number), La 1-x Ca x} MnO 3 ( (Where x is a real number), La _1-x Sr _x MnO ₃ (0.6 x <1, x is a real number), or PbZr _1-x Ti _x O ₃ / RTI &gt;
The n-type semiconductor layer has a resistance _{change, TiO x (1.2≤ x ≤ 1.89} , x is a real _{number), CeO x (1.5≤ x <} 2, x is a real _{number), ZnO x (1.2≤ x <} 2, x is a real number) , TaO _x (x is 1.2 ≤ x <2.5, x is a real _{number), AlO x (1.2≤ x <} 2, x is a real _{number), LaO x (1.2≤ x <} 2, x is a real number), NbO _x (1.2≤ x ≤ 2, x is a real number), Sn- doped _{InO x (1 <x≤ 1.5,} x is a real _{number), In x Zn 1-x} O 2 (0 <x≤ 0.5, x is a real number), Li _x Nb _{1-x O 3 (0 <} x≤ 0.5, x is a real _{number), Sr x Ti 1-x} O 3 (0 <x≤ 0.5, x is a real _{number), Ba x Sr 1-x} TiO 3 (0 <x≤ 0.5, x is a real number), Nb-doped Sr _x Ti _1-x O ₃ (0 <x? 0.5, x is a real number), Cr-doped Sr _x Ti _1-x O ₃ x is a real number), Sr _x Zr _1-x O ₃ (0 < x 0.5, x is a real number) or Cr-doped Sr _x Zr _1-x O ₃ And the resistance change memory. delete The resistance change memory according to claim 1, wherein the p-type resistance-variable semiconductor layer has a non-stoichiometric configuration and has a pore of a metal atom. delete The resistance change memory according to claim 1, wherein the n-type resistance-variable semiconductor layer has a non-stoichiometric configuration and has a vacancy of oxygen atoms. delete The resistance change memory according to claim 1, wherein the lower electrode is a nitride electrode selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or TiN or WN. delete delete The resistance change memory according to claim 1, wherein the upper electrode is a nitride electrode selected from the group consisting of Pt, Au, Al, Cu, Ti, and alloys thereof, or TiN or WN. delete delete delete delete

Images