KR101782201B1 - System for Controlling Multilevel Inverter for Transmitting Voltage Signal of Cell Inverter - Google Patents

Abstract

A multi-level inverter control system for voltage signal transmission of a cell inverter according to an aspect of the present invention capable of reducing a DC voltage of a cell inverter received by a cell controller and an error component of an IGBT module stack temperature voltage comprises: A first interface board for generating a first transmission signal by compressing a first voltage signal including one of a voltage and an IGBT stack temperature voltage of the cell inverter and a first clock signal for performing serial communication in synchronization; A second interface circuit for receiving the first transmission signal from the first interface board to extract the first voltage signal, parallelizing the first voltage signal according to a second clock signal synchronized with the first clock signal, A second interface board for generating a second interface board; And generating the first and second gating signals for controlling the cell inverter by receiving the parallelized first voltage signal from the second interface board to generate a PWM carrier and comparing the PWM carrier with a preset voltage command value, And a cell controller for controlling the cell.

Description

[0001] The present invention relates to a multilevel inverter control system for voltage signal transmission of a cell inverter,

The present invention relates to an inverter control system, and more particularly to voltage signal transmission in a multilevel inverter.

As the electric equipment becomes larger in the general industry, multilevel inverters have been developed and applied to the high voltage large capacity power conversion system. These multilevel inverters can easily generate large AC voltages with low distortion by synthesizing a large number of capacitor DC voltages and outputting them close to a sinusoidal waveform. In addition, by increasing the number of voltage levels, the total harmonic distortion (THD) can be reduced, and the rated voltage and switch loss of the switch can be reduced to obtain a superior output voltage. In addition, the multi-level inverter is characterized in that the higher the number of levels of the output voltage, the lower the harmonic component is, and thus the size of the filter can be reduced.

Due to these advantages, recently, multi-level inverters have also been applied to reactive power compensation systems in order to improve the power quality for system stabilization and to apply the reactive power compensation device to keep the supply voltage constant.

The structure of the multilevel inverter includes a diode-clamp structure as shown in FIG. 1A, a flying capacitor structure as shown in FIG. 1B, and an H-bridge as shown in FIG. 1C. (H-bridge) structure.

The multilevel inverter of the diode clamp structure as shown in FIG. 1A has a merit that the harmonic components are lowered and the control is simple as the number of levels increases. However, in order to solve the problem that a large number of clamping diodes are required and a capacitor voltage imbalance occurs A complicated switching algorithm is required.

The multilevel inverter of the flying capacitor structure as shown in FIG. 1B uses a plurality of capacitors in place of the clamping diode, and has a margin for the internal voltage level so that stable power supply and effective / reactive power control are possible. There is a problem that it is difficult to group large-capacity power capacitors and control becomes complicated.

The multilevel inverter of the H bridge structure as shown in FIG. 1C is formed by connecting a plurality of H-bridge inverter modules in series, eliminating the need for a conventional clamping diode or a large number of capacitors, Level inverter can be configured. In addition, H-bridge inverter modules can be grouped, making them easy to expand and control, and free from DC link imbalance problems. A multi-level inverter having such an H-bridge structure is disclosed in Korean Patent Registration No. 10-0970666.

The multi-level inverter control system for controlling the multi-level inverter as described above can be roughly divided into a centralized control system and a distributed control system. In the centralized control system, only each cell inverter gating amplifier and some protection circuits are built in, and all control operations are performed in the main controller. Such a centralized control system concentrates control and monitoring of the entire system, so that it is easy to perform batch control and simple processing of data processing and sequence processing. However, since the load of the main controller becomes large and a lot of signal lines between the main controller and the cell are required .

In the case of the distributed control system 100 shown in FIG. 2, in addition to the main controller 110 for calculating the voltage command value for controlling the acceleration and the shift of the electric motor, the main control unit 110 controls the PWM Cell controllers 120a to 120n and 130a to 130n and 140a to 140n for performing voltage control and phase control are installed for each cell inverter and cell controllers 120a to 120n and 130a to 130n and 140a to 140n generate gating signals Or performs a cell-by-cell protection operation.

The cell controllers 120a to 120n, 130a to 130n, 140a to 140n receive the DC voltage of each cell inverter and the stack temperature voltage of the IGBT module constituting each cell inverter from the cell inverter to generate a gating signal. At this time, the DC voltage of the cell inverter and the stack temperature voltage of the IGBT module are converted into a frequency signal by using a VF converter (Voltage-Frequency Converter) and then transmitted to the cell controller. The cell controller converts the received frequency signal into an FV -Voltage Converter) to restore the voltage signal.

However, the DC voltage (or the IGBT module stack temperature voltage) received through the VF converter and the FV converter, because the VF converter and the FV converter always output ripple with a predetermined size (e.g., 0.08 Vp) There is a problem that the gating signal according to the DC voltage (or the IGBT module stack temperature voltage) can not be accurately generated because the error component is included in comparison with the original signal.

The present invention has been made to solve the above problems and it is an object of the present invention to provide a multilevel inverter control system for transmitting a voltage signal of a cell inverter capable of reducing a DC voltage of a cell inverter received by a cell controller and an error component of an IGBT module stack temperature voltage The technical problem is to provide.

The present invention also provides a multi-level inverter control system for voltage signal transmission of a cell inverter capable of reducing the number of communication lines for transmitting the DC voltage of the cell inverter and the IGBT module stack temperature voltage to the cell controller, We will do it.

It is another object of the present invention to provide a multi-level inverter control system for voltage signal transmission of a cell inverter for transmitting a DC voltage of a cell inverter and a temperature voltage of an IGBT module stack to a cell controller without delay.

According to an aspect of the present invention, there is provided a multi-level inverter control system for transmitting a voltage signal of a cell inverter, the multi-level inverter control system comprising: A first interface board for generating a first transmission signal by compressing a first clock signal for performing serial communication in accordance with one voltage signal and synchronization; A second interface circuit for receiving the first transmission signal from the first interface board to extract the first voltage signal, parallelizing the first voltage signal according to a second clock signal synchronized with the first clock signal, A second interface board for generating a second interface board; And generating the first and second gating signals for controlling the cell inverter by receiving the parallelized first voltage signal from the second interface board to generate a PWM carrier and comparing the PWM carrier with a preset voltage command value, And a cell controller for controlling the cell.

According to the present invention, the DC voltage of the cell inverter and the IGBT module stack temperature voltage can be converted and transmitted through an analog-to-digital converter (ADC) to reduce the error component in the DC voltage of the cell inverter and the IGBT module stack temperature voltage, This has the effect that the cell controller can generate a more accurate gating signal.

According to the present invention, since the DC voltage of the cell inverter, the IGBT module stack temperature voltage, and the clock signal are compressed and transmitted as a single signal, the DC voltage of the cell inverter and the IGBT module stack temperature voltage are supplied to the cell controller It is possible to reduce the manufacturing cost of the multi-level inverter control system.

According to the present invention, the DC voltage of the cell inverter and the IGBT module stack temperature voltage are transferred to the cell controller without being converted into analog data, thereby converting the DC voltage of the cell inverter and the IGBT module stack temperature voltage into analog data There is an effect that the delay can be reduced.

FIG. 1A is a schematic view showing a multi-level inverter configuration of a diode-clamp structure. FIG.
1B schematically shows a multilevel inverter configuration of a flying capacitor structure;
1C schematically shows a multilevel inverter configuration of an H-bridge structure;
2 is a diagram showing a configuration of a general multilevel inverter control system;
3 is a graph showing a comparison between the DC voltage waveform of the sensed cell inverter and the DC voltage waveform received by the cell controller.
4 is a diagram illustrating a configuration of a multi-level inverter control system according to an embodiment of the present invention.
FIG. 5 is a block diagram illustrating a configuration of a first interface board according to an embodiment of the present invention; FIG.
6A shows waveforms of a first voltage signal and a first clock signal;
6B is a view showing a waveform of a first transmission signal;
FIG. 7 is a block diagram schematically illustrating a configuration of a second interface board according to an embodiment of the present invention; FIG.
FIG. 8 is a block diagram illustrating a configuration of a signal extracting unit according to an embodiment of the present invention; FIG.

The meaning of the terms described herein should be understood as follows.

The word " first, "" second," and the like, used to distinguish one element from another, are to be understood to include plural representations unless the context clearly dictates otherwise. The scope of the right should not be limited by these terms.

It should be understood that the terms "comprises" or "having" does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or combinations thereof.

It should be understood that the term "at least one" includes all possible combinations from one or more related items. For example, the meaning of "at least one of the first item, the second item and the third item" means not only the first item, the second item or the third item, but also the second item and the second item among the first item, Means any combination of items that can be presented from more than one.

Prior to the description of the multilevel inverter control system according to an embodiment of the present invention, a description will be given of a multilevel inverter.

When the multi-level inverter according to the embodiment of the present invention is implemented as a static synchronous compensator (STACOM), the multi-level inverter can be connected to the system in parallel to compensate the reactive power of the system.

Each of the A-phase, B-phase, and C-phase includes a plurality of cell inverters connected in series, and a plurality of cell inverters are connected in series to obtain a high voltage . In this case, since each cell inverter has an independent DC power source, a constant voltage can be applied to the power device included in the cell inverter without a separate clamping circuit, and the output voltage of the relatively low- High voltage output of several kV can be obtained.

Also, the output voltage and the voltage level can be easily adjusted according to the number of cell inverters, and a voltage waveform close to a sine wave can be obtained as the number of cell inverters increases.

On the other hand, the cell inverter has an independent DC power supply and includes a capacitor charged or discharged according to the phase of the output voltage.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

4 is a schematic diagram illustrating a multi-level inverter control system according to an embodiment of the present invention.

4, the multi-level inverter control system 400 according to an embodiment of the present invention includes cell inverters 410a to 410n, first interface boards 420a to 420n, a second interface board 430a To 430m, cell controllers 440a to 440m, and main controller 450. [

In the multilevel inverter control system 400 shown in FIG. 4, twelve cell inverters, twelve first interface boards, two second interface boards, and two cell controllers are provided for each phase A, B, However, the number of the cell inverter, the first interface board, the second interface board, and the cell controller may be changed according to the topology of the multi-level inverter to be implemented.

According to the multi-level inverter topology shown in FIG. 4, one cell controller is connected to one second interface board, one second interface board is connected to six first interface boards, It can be seen that the board is connected to one cell inverter.

That is, the cell controller and the second interface board are in a 1: 1 relationship, the second interface board and the first interface board are in a 1: n relationship, and the first interface board and the cell inverter are in a relationship of n: n .

Hereinafter, for convenience of explanation, a cell inverter 410a included in the phase A, one first interface board 420a, one second interface board 430a, and one cell controller 410a, The multi-level inverter control system according to the present invention will be described with reference to the multi-level inverter control system 440a.

First, the cell inverter 410a constitutes a unit cell, and a plurality of cell inverters included in each phase are connected to each other in series. That is, the multi-level inverter obtains a high voltage by serially connecting a plurality of cell inverters 410a to 410n for each phase.

In one embodiment, the plurality of cell inverters 410a may be implemented as a single-phase H-bridge inverter configured as an IGBT (Insulated Gate Bipolar Mode Transistor) module. Specifically, one IGBT module is mounted on the top and bottom of the first leg of the cell inverter 410a, and one IGBT module is mounted on the top and bottom of the second leg, respectively. So that one cell inverter 410a is composed of four IGBT modules. The IGBT modules disposed at the top and bottom of the first leg are IGBT modules connected to the top and bottom of the IGBT modules serially connected to one branch of the H-Bridge inverter, and the IGBT modules disposed at the top and bottom of the second leg IGBT modules are connected to the upper and lower IGBT modules connected in series to the other branch of the H-Bridge inverter.

The cell inverter 410a outputs the sensed DC voltage and the IGBT stack temperature voltage from the cell inverter 410a to the first interface board 420a. At this time, the DC voltage sensed by the cell inverter 410a means a voltage across the capacitor connected in parallel to the cell inverter 410a.

In one embodiment, the cell inverter 410a may be equipped with a temperature measurement module consisting of a NTC resistor (not shown) and a test resistor (not shown) connected in series to the NTC resistor to sense the IGBT stack temperature voltage . Here, the NTC resistance is a resistor having a property that a resistance value changes according to temperature. When the temperature rises, the resistance value decreases. When the temperature rises, the resistance value rises.

Such a temperature measuring module can output a voltage value distributed to the test resistor to the IGBT stack temperature voltage by applying a predetermined voltage to the NTC resistance and the test resistance. Therefore, when the temperature of the IGBT stack rises, the voltage value distributed to the NTC resistance decreases due to the decrease of the NTC resistance value, and the voltage value distributed to the test resistance increases. Also, as the temperature of the IGBT stack decreases, the voltage value distributed to the NTC resistance increases due to the rise of the NTC resistance value, and the voltage value distributed to the test resistance decreases.

The first interface board 420a is connected to the cell inverter 410a and converts the DC voltage sensed by the cell inverter 410a and the IGBT stack temperature voltage into an optical signal and transmits the optical signal to the second interface board 430a.

The first interface board 420a is connected to the first inverter board 410a for driving the IGBT module disposed in the first leg tower of the cell inverter 410a using the first gating signal generated by the cell controller 440a And generates a second inverter drive signal for driving the IGBT module disposed in the bottom of the first leg by inverting the first gating signal.

In addition, the first interface board 420a may include a third inverter drive signal for driving the IGBT module disposed in the second leg tower of the cell inverter 410a using the second gating signal generated by the cell controller 440a, And inverts the second gating signal to generate a fourth inverter drive signal for driving the IGBT module disposed in the second leg bottom.

At this time, the first interface board 420a uses the gating on / off control signal for whether the cell inverter 410a generated by the cell controller 440a is driven and the overcurrent signal inputted from the cell inverter 410a, And outputs the first to fourth inverter driving signals to the cell inverter 410a when the output is determined.

In the present invention, converting the DC voltage and the IGBT stack temperature voltage into optical signals using the first interface board 420a and transferring the optical signals to the second interface board 430a is performed by electrically connecting the cell inverter 410a and the cell controller 440a For isolation. Since the cell inverter 410a is in a floating state, the reference potential must be different from that of the cell controller 440a. Therefore, the cell controller 440a is protected from the cell inverter 410a to which a relatively high voltage is applied. .

Hereinafter, the configuration of the first interface board 420a will be described in more detail with reference to FIG.

5 is a block diagram illustrating a configuration of a first interface board according to an embodiment of the present invention.

5, the first interface board 420a according to an embodiment of the present invention includes a signal compressing unit 510 and a first signal converting unit 520. [

First, the signal compressing unit 510 operates as a master. The signal compressing unit 510 generates either a DC voltage or an IGBT stack temperature voltage as a first voltage signal, and outputs the generated first voltage signal and the first clock signal as one Compresses the signal into a single signal, and outputs it in a serial communication manner.

5, the signal compressing unit 510 includes a signal selector 512, a first analog-to-digital converter 514, a first clock generator 516, and an OR gate 518 do.

First, the signal selector 512 receives the voltage selection signal generated by the cell controller 440a through the second interface board 430a. The voltage selection signal is a signal for selecting the DC voltage to be sensed by the cell inverter 410a and the output voltage of the IGBT stack temperature voltage.

For example, when the voltage selection signal having a high level is received, the signal selection unit 512 selects and outputs the sensed DC voltage. When the voltage selection signal having the low level is received, the signal selection unit 512 selects and outputs the sensed IGBT stack temperature voltage . As another example, the signal selector 512 selects and outputs the sensed IGBT stack temperature voltage when a voltage selection signal having a high level is received. When the voltage selection signal having a low level is received, the signal selector 512 selects the sensed DC voltage, can do.

A first analog-to-digital converter (ADC) 514 converts the first voltage signal output from the signal selection unit 512 into a digital form. That is, in the conventional multi-level inverter control system, since the DC voltage or the IGBT stack temperature voltage is converted into a frequency signal through the VF converter and transmitted, the DC voltage or IGBT stack temperature voltage received by the cell controller 440a The present invention is not limited to the DC voltage received at the cell controller 440a or the IGBT stack temperature voltage < RTI ID = 0.0 > (IGBT) < / RTI > voltage due to the conversion of the first voltage signal to digital form via the first analog to digital converter 514 instead of the VF converter. Can be prevented from occurring in advance.

The first clock generator 516 generates a first clock signal for enabling the signal compressor 510 operating as a master to synchronize with the slave to enable serial communication. In one embodiment, the first clock signal has a waveform in which the high level (1) and the low level (0) are alternately repeated in units of 1 bps (bit per second).

The OR gate 518 performs an "OR" operation on the first voltage signal of digital form output from the first analog-to-digital converter 514 and the first clock signal output from the first clock generator 516, Signal. That is, the OR gate 518 compresses the digital first voltage signal and the first clock signal into a single signal. In the present invention, the first voltage signal and the first clock signal of the digital form are "OR" operated through the OR gate 518 because the first voltage signal and the first clock signal are ORed in the order of outputting the low level To input the first voltage signal.

Specifically, the first clock signal alternates between high level and low level every 1 bps, but the first voltage signal of the digital form is held at 1 during 2 spb when the data is "1 ", so that the first clock signal and the digital form Quot; OR "operation of the first voltage signal. Accordingly, the first transmission signal output from the OR gate 518 can be determined as a signal in which the clock signal and the digital first voltage signal are repeatedly output.

For example, when the waveforms of the first clock signal and the first voltage signal in digital form are as shown in Fig. 6A, the OR gate 518 performs an "OR" operation of the first clock signal and the first voltage signal in digital form And outputs a first transmission signal having a waveform as shown in FIG. 6B.

As described above, according to the present invention, since the first voltage signal and the first clock signal are compressed and output as a single transmission signal through the signal compressing unit 510, the one for outputting the first transmission signal, The number of communication lines for signal transmission can be reduced.

5, the first signal converter 520 converts the first transmission signal output from the signal compressor 510 in a serial communication manner to an optical signal (Optic Signal) Lt; / RTI >

As described above, in the present invention, the first signal converter 520 converts the first transmission signal including the DC voltage and the IGBT stack temperature voltage into an optical signal and transmits the optical signal to the second interface board 430a The cell inverter 410a and the cell controller 440a can be electrically isolated from each other.

Referring again to FIG. 4, the second interface board 430a is connected to the first interface board 420a, and receives the first transmission signal converted into the optical signal from the first interface board 420a. The second interface board 430a extracts a first voltage signal including one of the DC voltage and the IGBT stack temperature voltage from the first transmission signal and transmits the first voltage signal to the cell controller 440a.

In one embodiment, the second interface board 430a is connected to the six first interface boards 420a as shown in FIG. 4, and the first interface board 420a is connected to six first interface boards 420a, 1 transmission signal.

Hereinafter, the second interface board 430a according to the present invention will be described in detail with reference to FIG. 7 and FIG.

FIG. 7 is a block diagram illustrating a configuration of a second interface board 430a according to an embodiment of the present invention.

As shown in FIG. 7, the second interface board 430a includes a plurality of second signal converters 710a through 710n, a plurality of signal extractors 720a through 720n, and a decoder 730.

7, since the second interface board 430a is connected to the plurality of (e.g., n) first interface boards 420a, the second interface board 430a is connected to the second signal converter < RTI ID = 710a to 710n and signal extraction units 720a to 720n. Accordingly, the number of the second signal converters 710a to 710n and the signal extractors 720a to 720n may be changed according to the number of the first interface boards 420a connected to the second interface board 430a.

Since the functions of the second signal converters 710a through 710n are identical to each other and the functions of the signal extractors 720a through 720n are the same as each other, And one signal extracting unit 720a will be described with reference to the configuration of the second interface board 430a.

First, the second signal converter 710a is connected to the first signal converter 520 included in the first interface board 420a, and the first signal converter 520a converts the first signal converted by the first signal converter 520 into an optical signal And receives a transmission signal. The second signal converter 710a converts the received optical signal to obtain a first transmission signal in digital form, and outputs the obtained first transmission signal to the signal extractor 720a.

The signal extracting unit 720a operates as a slave with respect to the signal compressing unit 510 operating as a master. The signal extracting unit 720a generates a second clock signal and transmits the second clock signal from the signal compressing unit 510, And outputs the synchronized second clock signal by synchronizing with the first clock signal. In addition, the signal extracting unit 720a extracts the first voltage signal from the first transmission signal obtained by the second signal converting unit 710a.

Hereinafter, the configuration of the signal extracting unit 720a will be described more specifically with reference to FIG.

8 is a block diagram illustrating a configuration of a signal extracting unit according to an embodiment of the present invention. 8, a signal extracting unit 720a according to an embodiment of the present invention includes a rising edge detecting unit 810, an AND gate 830, a signal delay unit 840, a clock synchronizing unit 850, A data parallelization unit 860, a data holding unit 870, and a data output unit 880. [

First, the rising edge detector 810 detects the first pulse in the first transmission signal by detecting the first rising edge of the first transmission signal obtained by the second signal converter 710a. The rising edge detector 810 notifies the AND gate 830 and the clock synchronizer 850 of the detection of the first rising edge when the first rising edge of the first transmission signal is detected.

In one embodiment, when the first rising edge of the first transmission signal is detected, the rising edge detector 810 generates an enable signal EN for enabling the output of the data holding unit 870, (870). For example, the rising edge detector 810 may generate an enable signal to output a low level in accordance with the first rising edge of the first transmission signal, and the data holding unit 870 may apply an enable signal of a low level The data parallelization unit 860 can transmit the first voltage signal to the data output unit 880.

When the first rising edge of the first transmission signal is detected by the rising edge detector 810, the AND gate 830 outputs n-th bit data and n-1 (n-1) bits for signals after the first rising edge of the first transmission signal, Th bit data to recover the n-th bit data of the first voltage signal and to recover the first voltage signal from the first transmission signal by repeating it for all the bits of the first transmission signal.

That is, the AND gate 830 performs an AND operation on the data of the current bit and the data of the previous bit based on the current bit in the first transmission signal, thereby restoring the data of the current bit of the first voltage signal.

In another embodiment, when the first rising edge of the first transmission signal is detected by the rising edge detector 810, the AND gate 830 performs an AND operation on the synchronized second clock signal and the first transmission signal, So that the first voltage signal can be restored by calculating the voltage data for each bit.

The signal delay unit 840 delays the first voltage signal restored by the AND gate 830 by a predetermined time and outputs the delayed signal. In one embodiment, the signal delay unit 840 delays the first voltage signal restored by the AND gate 830 by a unit sample (e.g. This is to solve the error caused by using the data one bit before the restoration of the first voltage signal through the AND gate 830. [

The clock synchronization unit 850 generates a second clock signal. When the first rising edge of the first transmission signal is detected by the rising edge detection unit 810, the clock synchronization unit 850 synchronizes the second clock signal to the first rising edge, Synchronizes the clock signal to the first clock signal. The clock synchronization unit 850 outputs the second clock signal synchronized with the first clock signal to the data parallelization unit 860.

The data parallelization unit 860 parallelizes the first voltage signal output from the signal delay unit 840 according to a second clock signal input from the clock synchronization unit 850 and outputs the parallelized signal. That is, the data parallelizing unit 860 generates the parallelized first voltage signal by arranging the bits of the first voltage signal of the serial format outputted from the signal delay unit 840 in parallel according to the second clock signal.

In one embodiment, the data parallelizer 860 may be implemented as a shift register.

The data holding unit 870 holds the first voltage signal of the parallel format being output in accordance with the enable signal output from the corresponding edge detector 810 or the first voltage signal of the first parallel type that is newly input from the data parallelizing unit 860 And outputs a voltage signal. For example, when the low-level enable signal is input from the rising edge detector 810, the data holding unit 870 outputs the first voltage signal of the parallel format output from the data parallelizer 860, and the rising edge detector 810 may input a high-level enable signal, the first voltage signal of the parallel format being output may be maintained.

In one embodiment, the data storage unit 870 may be implemented as a D-Flip Flop.

The data output unit 880 receives the enable signal EN from the decoder 730 shown in FIG. 7 and outputs the parallelized first voltage signal input from the data holding unit 870 to the cell controller 440). That is, the data output unit 880 does not output the parallelized first voltage signal unless the enable signal is input from the decoder 730, and when the enable signal is input, And outputs the first voltage signal.

7, when the address information of the specific first interface board 420a is input from the cell controller 440, the decoder 730 extracts a signal that matches the address of the input first interface board 420 The signal extracting unit 720 generates the enable signal for the unit 720 and provides the generated enable signal to the corresponding signal extracting unit 720 so that the signal extracting unit 720 outputs the parallelized first voltage signal to the cell controller 440a .

The cell controller 440a according to the present invention generates address information of the first interface boards 420a to 420n to be extracted from the first interface boards 420a to 420n and outputs the address information to the decoder 730 ). At this time, the cell controller 440a and the decoder may share the address information of the first interface boards 420a to 420n in advance.

As described above, according to the present invention, the second interface board 430a directly processes the first voltage signal generated by the first interface board 420a into a digital form without converting it into an analog form, and provides the digital signal to the cell controller 440a Therefore, the accuracy of the first voltage signal is improved, and the time delay due to the analog-to-digital conversion of the first voltage signal can be prevented.

4, the cell controllers 440a to 440m are provided for each phase, and the plurality of cell inverters 410a to 410n are arranged so that a voltage corresponding to the voltage command value received from the main controller 450 can be output. .

The cell controllers 440a to 440m included in each phase (A phase, B phase, and C phase) have the same or similar characteristics. Therefore, for convenience of explanation, the cell controllers 440a through 440m .

The cell controller 440a controls the operation of the cell inverters 410a included on the A-

More specifically, the cell controller 440a receives the voltage command value from the main controller 450, and uses the DC voltage of the cell inverters 410a and the IGBT stack temperature voltage and the voltage command value received from the main controller 450 And outputs the PWM control signal to the cell inverters 410a. At this time, the PWM control signal may be a gating signal for driving the IGBT module, which is power devices included in the cell inverters 410a.

In one embodiment, the cell controller 440a includes a first gating signal for controlling the IGBT modules disposed in the first leg of the cell inverter 410a and IGBT modules disposed in the second leg of the cell inverter 410a And generate a second gating signal for controlling.

The main controller 450 calculates a voltage command value for outputting a target current value to the system, and outputs the voltage command value to the cell controllers 440a to 410n. The main controller 450 can transmit and receive the voltage command values to the plurality of cell controllers 440a to 440m through a CAN (Controller Area Network) communication in synchronization with each phase, and can include a CAN driver for this purpose .

The main controller 450 also transmits a PWM synchronization command to each of the cell controllers 440a to 440m for synchronizing PWM (Pulse Width Modulation) control signals between the plurality of cell inverters 410a to 410n for each phase .

It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof.

It is therefore to be understood that the above-described embodiments are illustrative in all aspects and not restrictive. The scope of the present invention is defined by the appended claims rather than the detailed description and all changes or modifications derived from the meaning and scope of the claims and their equivalents are to be construed as being included within the scope of the present invention do.

400: Multi-level inverter control system 410a ~ 410n: Cell inverter
420a to 420n: first interface boards 430a to 430m: second interface boards
440a to 440m: a cell controller 450: a main controller
510: signal compressing unit 520: first signal converting unit
710a to 710n: second signal conversion units 720a to 720n:
730: decoder

Claims (13)

A first voltage signal including one of a DC voltage of the cell inverter and an IGBT stack temperature voltage of the cell inverter and a first clock signal for performing serial communication in synchronization with the first clock signal to generate a first transmission signal, Interface board;
A second interface circuit for receiving the first transmission signal from the first interface board to extract the first voltage signal, parallelizing the first voltage signal according to a second clock signal synchronized with the first clock signal, A second interface board for generating a second interface board; And
Receiving the parallelized first voltage signal from the second interface board to generate a PWM carrier, and comparing the PWM carrier with a preset voltage command value to generate first and second gating signals for controlling the cell inverter A cell controller,
Wherein the first interface board comprises:
A first analog-to-digital converter (ADC) for converting the first voltage signal into a digital form; And
OR operation of the first voltage signal converted to the digital form so that the first voltage signal converted into the digital form is arranged in order of outputting a low level of the waveform of the first clock signal, And an OR gate for generating a first transmission signal. The method according to claim 1,
Wherein the number of the first interface boards is n,
Wherein the second interface board comprises:
A plurality of signal extractors matching the n first interface boards in a 1: 1 manner to generate the parallelized first voltage signal from the first transmission signal received from each first interface board; And
And a decoder for receiving the address information of the first interface board from the cell controller and generating a first enable signal for activating the signal extracting unit matched with the first interface board corresponding to the received address information,
Wherein the signal extractor outputs the parallelized first voltage signal to the cell controller when the first enable signal is received from the decoder. 3. The method of claim 2,
Wherein the signal extracting unit comprises:
A rising edge detector for detecting a first rising edge of the first transmission signal and generating a second enable signal when a first rising edge of the first transmission signal is detected; And
And an AND gate for ANDing the n-th bit and the (n-1) -th bit in the first transmission signal to restore the first voltage signal when the first rising edge of the first transmission signal is detected by the rising edge detector Level inverter control system for a voltage signal transmission of a cell inverter. The method of claim 3,
Wherein the signal extracting unit comprises:
A data parallelizer for generating the parallelized first voltage signal by arranging each bit of the first voltage signal output from the AND gate in parallel with the second clock signal;
A data holding unit for outputting the parallelized first voltage signal input from the data parallelizing unit when the second enable signal is input; And
And a data output unit for outputting the parallelized first voltage signal input from the data holding unit to the cell controller when the first enable signal is input from the decoder. Multi-level inverter control system 5. The method of claim 4,
Wherein the data parallelization unit is implemented as a shift register and the data storage unit is implemented as a D flip-flop. The method of claim 3,
Wherein the signal extracting unit comprises:
Further comprising a signal delay unit delaying the first voltage signal output from the AND gate by a predetermined time period. 5. The method of claim 4,
Wherein the signal extracting unit comprises:
Wherein the first rising edge detecting unit detects the first rising edge of the first transmission signal and extracts the first clock signal from the first transmission signal and outputs the second clock signal synchronized with the first clock signal to the data And a clock synchronization unit for outputting the voltage signal to the parallelization unit. 3. The method of claim 2,
Wherein the signal extracting unit comprises:
A rising edge detector for detecting a first rising edge of the first transmission signal; And
And an AND gate for performing an AND operation on the second clock signal and the first transmission signal to recover the first voltage signal when the first rising edge of the first transmission signal is detected by the rising edge detection unit A multi-level inverter control system for voltage signal transmission of a cell inverter. delete The method according to claim 1,
Wherein the first interface board comprises:
And a signal selector for receiving the voltage selection signal from the cell controller and selecting either the DC voltage or the IGBT stack temperature voltage according to the voltage selection signal to generate the first voltage signal. A multilevel inverter control system for inverter voltage signal transmission. The method according to claim 1,
Wherein the first interface board and the second interface board are connected by n: 1,
And the second interface board and the cell controller are connected in a 1: 1 ratio. The method according to claim 1,
Further comprising a temperature measuring module configured with a NTC resistor and a test resistor connected in series with the NTC resistor to output the IGBT stack temperature voltage,
Wherein the temperature measuring module applies a predetermined voltage to the NTC resistor and the test resistor and outputs a voltage value distributed to the test resistor to the IGBT stack temperature voltage. Level inverter control system. The method according to claim 1,
Wherein the cell inverter includes a plurality of IGBT modules,
Wherein the first interface board comprises:
Generating a first inverter drive signal for driving an IGBT module disposed in a first leg of a cell inverter using the first gating signal generated by the cell controller, Inverts the gating signal to generate a second inverter drive signal for driving the IGBT module disposed in the first leg bottom,
Generating a third inverter drive signal for driving an IGBT module disposed in a second leg tower of the cell inverter using the second gating signal, inverting the second gating signal, Generates a fourth inverter drive signal for driving the IGBT module,
Wherein the control unit determines whether to output the first to fourth inverter driving signals by using a gating on / off control signal indicating whether or not the cell inverter is driven and an overcurrent signal inputted from the cell inverter. Multi - level inverter control system for.

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